Gate drive circuit, display device, and gate drive method

Abstract

A display device is provided, the display device including: a display panel including one or more sub-pixels; and a gate drive circuit to provide gate signals to the sub-pixels through gate lines, the gate drive circuit including: a gate output buffer circuit including a pull-up transistor to control a connection between a control clock input node and a gate output node and a pull-down transistor to control a connection between a low level voltage node and the gate output node; a control circuit able to control the gate output buffer circuit; and a dummy pull-down transistor, a gate node of the dummy pull-down transistor being shared with a gate node of the pull-down transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0187255, filed on December 30, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to touch driver circuits and touch display devices. Background Technology

[0004] With the advent of the information society, the demand for display devices for displaying images is growing. To meet this demand, various types of display devices have been developed and widely used recently, such as liquid crystal displays (LCDs), electroluminescent displays (ELDs) including quantum dot light-emitting displays, and organic light-emitting displays (e.g., OLEDs).

[0005] In typical display devices, reducing the size of the non-display area of ​​the display panel increases design freedom and improves design quality. However, since various lines and circuit components are arranged in the non-display area of ​​the display panel, it is practically difficult to reduce the size of this area. Summary of the Invention

[0006] Embodiments of this disclosure provide a gate drive circuit capable of reducing the number of transistors included in the gate drive circuit and reducing the complexity of the circuit system or circuit elements configured in the gate drive circuit, as well as a display device including the gate drive circuit.

[0007] Embodiments of this disclosure provide gate drive circuits that can reduce the defect rate of gate drive circuits and allow for narrow bezel implementations, as well as display devices including such gate drive circuits.

[0008] Embodiments of this disclosure provide a gate drive circuit capable of maximizing or increasing the lifetime of transistors included in the gate drive circuit, and a display device including the gate drive circuit.

[0009] According to an aspect of this disclosure, a display device is provided, the display device comprising: a display panel including at least one sub-pixel; and a gate driving circuit that provides a gate signal to at least one sub-pixel via at least one gate line.

[0010] The gate drive circuit includes: a gate output buffer circuit, which includes a pull-up transistor that controls the connection between the clock input node and the gate output node and a pull-down transistor that controls the connection between the low-level voltage node and the gate output node; a control circuit that controls the gate output buffer circuit; and a dummy pull-down transistor, the gate node of which is shared with the gate node of the pull-down transistor.

[0011] According to embodiments of the present disclosure, a gate drive circuit and a display device including the gate drive circuit can be provided, which can reduce the number of transistors included in the gate drive circuit and reduce the complexity of the circuit system or circuit elements configured in the gate drive circuit.

[0012] Therefore, a gate drive circuit that can reduce the defect rate of the gate drive circuit and allow for the realization of a narrow bezel, and a display device including the gate drive circuit can be provided.

[0013] Furthermore, according to embodiments of the present disclosure, a gate drive circuit capable of maximizing or increasing the lifetime of transistors included in the gate drive circuit by adjusting the stress of the transistors, and a display device including the gate drive circuit, can be provided. Attached Figure Description

[0014] The accompanying drawings illustrate aspects of this disclosure and, together with the specification, serve to illustrate the principles of this disclosure. The drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure. In the drawings:

[0015] Figure 1 The system configuration of the display device according to aspects of this disclosure is shown;

[0016] Figure 2 An example system implementation of a display device according to aspects of this disclosure is shown;

[0017] Figure 3 Aspects of this disclosure are shown. Figure 2 The circuit configuration of the display device shown;

[0018] Figure 4 It shows the application to Figure 3 The power supply voltage of the control circuit varies according to the driving time;

[0019] Figure 5 It shows the use Figure 1 controller implementation Figure 3 A block diagram of an example control device for a compensation circuit;

[0020] Figure 6AIt is shown that the sensing processing circuit is included in a source driver integrated circuit of the data driving circuit adjacent to the gate driving circuit;

[0021] Figure 6B It is shown that Figure 3 The control device of the compensation circuit uses Figure 1 The controller of the compensation circuit is implemented and Figure 3 The sensing processing circuit of the compensation circuit is included in Figure 1 The circuit configuration of the data driving circuit of the source driver integrated circuit of

[0022] Figure 7 It is shown that the connection state between the power management integrated circuit and the control circuit of the gate driving circuit located on the control printed circuit board;

[0023] Figure 8 It is shown that the system configuration of the display device according to aspects of the disclosure; and

[0024] Figure 9 It is shown that Figure 8 The circuit configuration of the display device shown in DETAILED DESCRIPTION

[0025] In the following description of examples or embodiments of the disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in which the same reference numerals can be used to denote the same or similar components even if they are shown in different figures from each other. Further, in the following description of examples or embodiments of the disclosure, when it is determined that the description of well-known functions and components incorporated herein can make the subject matter in some embodiments of the disclosure unclear, detailed description thereof will be omitted. The terms such as "include", "have", "contain", "consist of", "comprise", and "form" used herein are generally intended to allow the addition of other components unless the terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0026] Terms such as "first", "second", "A", "B", "(A)", or "(B)" can be used to describe elements of the disclosure herein. Each of these terms is not intended to limit the nature, order, sequence, or number of elements, etc., but is only used to distinguish the corresponding element from other elements.

[0027] When it is referred to that a first element is "connected or coupled" or "contacted or overlapped" with a second element, etc., it should be interpreted that not only the first element can be "directly connected or coupled" or "directly contacted or overlapped" with the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or coupled" or "contacted or overlapped" with each other via a fourth element, etc. Here, the second element can be included in at least one of two or more elements which are "connected or coupled" or "contacted or overlapped" with each other, etc.

[0028] When a time-related term (e.g., "after", "subsequently", "next", "before", etc.) is used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, unless used together with the term "directly" or "immediately", the above term can be used to describe a non-continuous or non-sequential process or operation.

[0029] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value or the corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance or error range that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if not described in relation thereto. In addition, the term "may" completely covers all meanings of the term "can".

[0030] Figure 1 A system configuration of a display device 100 according to an aspect of the disclosure is illustrated.

[0031] Referring to Figure 1 The display device 100 according to an aspect of the disclosure can include a display panel 110 and a driving circuit (120, 130, and 140) for driving the display panel 110.

[0032] The driving circuit can include a data driving circuit 120, a gate driving circuit 130, etc., and can further include a controller 140 which controls the data driving circuit 120 and the gate driving circuit 130.

[0033] The display panel 110 can include a substrate SUB, and a signal line, e.g., a plurality of data lines DL, a plurality of gate lines GL, etc., disposed on the substrate SUB. The display panel 110 can include a plurality of sub-pixels SP connected to the plurality of gate lines GL and the plurality of data lines DL.

[0034] The display panel 110 can include a display area DA that displays an image and a non-display area NDA that does not display an image. A plurality of sub-pixels SP for displaying an image can be disposed in the display area DA of the display panel 110, and driving circuits (120, 130, and 140) can be electrically connected to or mounted in the non-display area NDA of the display panel 110. In addition, a pad portion to which an integrated circuit, a printed circuit, and / or the like is connected can be disposed in the non-display area NDA.

[0035] The data driving circuit 120 is a circuit for driving a plurality of data lines DL and can supply a data signal to the plurality of data lines DL.

[0036] The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL and can supply a gate signal to the plurality of gate lines GL.

[0037] The controller 140 can supply a data control signal DCS to the data driving circuit 120 in order to control the operation timing of the data driving circuit 120. The controller 140 can supply a gate control signal GCS to the gate driving circuit 130 in order to control the operation timing of the gate driving circuit 130.

[0038] The controller 140 starts a scan operation according to a predetermined timing in each frame, converts image data input from other devices or other image supply sources into a data signal form used in the data driving circuit 120, and then supplies the converted image data Data to the data driving circuit 120 and controls the loading of data to at least one pixel according to a scan timing at a pre-configured time.

[0039] In addition to input image data, the controller 140 can receive several types of timing signals, including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, a clock signal CLK, etc., from other devices, a network, or a system (e.g., a host system 150).

[0040] In order to control the data driving circuit 120 and the gate driving circuit 130, the controller 140 can receive one or more of the timing signals such as the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the input data enable signal DE, the clock signal CLK, etc., generate several types of control signals DCS and GCS, and output the generated signals to the data driving circuit 120 and the gate driving circuit 130.

[0041] For example, in order to control the gate driving circuit 130, the controller 140 can output several types of gate control signals GCS, including a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, etc.

[0042] Further, to control the data driving circuit 120, the controller 140 can output several types of data control signals DCS, including a source start pulse SSP, a source sampling clock SSC, a source output enable (SOE) signal, and the like.

[0043] The controller 140 can be implemented in a component separate from the data driving circuit 120, or integrated with the data driving circuit 120 and implemented in an integrated circuit.

[0044] The data driving circuit 120 can drive the plurality of data lines DL by receiving image data Data from the controller 140 and providing data voltages to the plurality of data lines DL. Here, the data driving circuit 120 can also be referred to as a source driving circuit.

[0045] The data driving circuit 120 can include one or more source driver integrated circuits SDIC.

[0046] Each source driver integrated circuit SDIC can include a shift register, a latch circuit, a digital-to-analog converter DAC, an output buffer, and the like. In some examples, each source driver integrated circuit SDIC can also include an analog-to-digital converter ADC.

[0047] In some embodiments, each source driver integrated circuit SDIC can be connected to the display panel 110 in a tape automated bonding (TAB) type, or to a conductive pad, e.g., a bonding pad, of the display panel 110 in a chip on glass (COG) type or a chip on panel (COP) type, or to the display panel 110 in a chip on film (COF) type.

[0048] Under the control of the controller 140, the gate driving circuit 130 can output a gate signal of an on-level voltage or a gate signal of an off-level voltage. The gate driving circuit 130 can sequentially drive the plurality of gate lines GL by sequentially providing the gate signal of the on-level voltage to the plurality of gate lines GL.

[0049] In some embodiments, the gate driving circuit 130 can be connected to the display panel 110 in a tape automated bonding (TAB) type, or connected to conductive pads, e.g., bonding pads, of the display panel 110 in a chip on glass (COG) type or a chip on panel (COP) type, or connected to the display panel 110 in a chip on film (COF) type. In another embodiment, the gate driving circuit 130 can be disposed in the non-display area NDA of the display panel 110 in a gate in panel (GIP) type. The gate driving circuit 130 can be disposed on or above the substrate SUB, or connected to the substrate SUB. That is, in the case of the GIP type, the gate driving circuit 130 can be disposed in the non-display area NDA of the substrate SUB. In the case of the chip on glass (COG) type, the chip on film (COF) type, or the like, the gate driving circuit 130 can be connected to the substrate SUB.

[0050] When a particular gate line is driven by the gate driving circuit 130, the data driving circuit 120 can convert image data Data received from the controller 140 into a data voltage in an analog form, and supply the converted data voltage to the plurality of data lines DL.

[0051] The data driving circuit 120 can be located on, but not limited to, only one portion (e.g., an upper portion or a lower portion) of the display panel 110. In some embodiments, the data driving circuit 120 can be located on, but not limited to, two portions (e.g., an upper portion and a lower portion) of the panel 110, or on, but not limited to, at least two of four portions (e.g., an upper portion, a lower portion, a left side, and a right side) of the panel 110, according to a driving scheme, a panel design scheme, or the like.

[0052] The gate driving circuit 130 can be located on, but not limited to, only one portion (e.g., a left side or a right side) of the display panel 110. In some embodiments, the gate driving circuit 130 can be located on, but not limited to, two portions (e.g., a left side and a right side) of the panel 110, or on, but not limited to, at least two of four portions (e.g., an upper portion, a lower portion, a left side, and a right side) of the panel 110, according to a driving scheme, a panel design scheme, or the like.

[0053] The controller 140 can be a timing controller used in typical display technology, or a control device / apparatus capable of additionally performing other control functions in addition to the typical functions of the timing controller. In some embodiments, the controller 140 can be one or more other control circuits different from the timing controller, or a circuit or component in the control device / apparatus. The controller 140 can be implemented using various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a processor, and / or the like.

[0054] The controller 140 can be mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, etc.

[0055] The controller 140 can transmit and receive signals to and from the data driving circuit 120 via one or more predetermined interfaces. In some embodiments, such interfaces can include a low-voltage differential signaling (LVDS) interface, an EPI interface, a serial peripheral interface (SPI), etc.

[0056] The controller 140 can include a storage medium, such as one or more registers.

[0057] The display apparatus 100 according to aspects of the present disclosure can be a display including a backlight unit, such as a liquid crystal display apparatus, or can be a self-emissive display, such as an organic light-emitting diode (OLED) display, a quantum dot (QD) display, a micro light-emitting diode (M-LED) display, etc.

[0058] In a case where the display apparatus 100 according to aspects of the present disclosure is an OLED display, each sub-pixel SP can include an OLED, in which the OLED itself emits light as a light-emitting element. In a case where the display apparatus 100 according to aspects of the present disclosure is a QD display, each sub-pixel SP can include a light-emitting element including a quantum dot, which is a self-emissive semiconductor crystal. In a case where the display apparatus 100 according to aspects of the present disclosure is a micro LED display, each sub-pixel SP can include a micro LED, in which the micro OLED itself emits light, and the micro LED is based on an inorganic material as a light-emitting element.

[0059] Figure 2 An example system implementation of a display apparatus according to aspects of the present disclosure is illustrated.

[0060] Referring to Figure 2 The display panel 110 can include a display area DA that displays an image and a non-display area NDA that does not display an image.

[0061] When the data driving circuit 120 includes one or more source driver integrated circuits SDIC and is implemented in a chip on film (COF) type, each source driver integrated circuit SDIC can be mounted on a circuit film SF connected to the non-display area NDA of the display panel 110.

[0062] The gate driving circuit 130 can be implemented in a gate-in-panel (GIP) type. In this embodiment, the gate driving circuit 130 can be disposed in the non-display area NDA of the display panel 110. In another embodiment, the gate driving circuit 130 can be implemented in a gate-on-array (GOA) type. In this embodiment, the gate driving circuit 130 can be disposed in the display area DA of the display panel 110.Figure 2 The gate driving circuit 130 can be implemented in a chip on film (COF) type, as illustrated in FIG. 1B.

[0063] The display device 100 can include at least one source printed circuit board (SPCB) for circuit connection between one or more source driver integrated circuits (SDICs) and other devices, components, etc., and a control printed circuit board (CPCB) on which control components and various types of electrical devices or components are mounted.

[0064] The circuit film (SF) on which the source driver integrated circuits (SDICs) are mounted can be connected to the at least one source printed circuit board (SPCB). That is, one side of the circuit film (SF) on which the source driver integrated circuits (SDICs) are mounted can be electrically connected to the display panel 110, and the other side thereof can be electrically connected to the source printed circuit board (SPCB).

[0065] The controller 140 and the power management integrated circuit 310 can be mounted on the control printed circuit board (CPCB). The controller 140 can perform an overall control function related to driving of the display panel 110 and control operations of the data driving circuit 120 and the gate driving circuit 130. The power management integrated circuit 310 can supply various types of voltage or current to the data driving circuit 120 and the gate driving circuit 130, or control various types of voltage or current to be supplied.

[0066] Circuit connection between the at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be made through at least one connection cable (CBL). The connection cable (CBL) can be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like.

[0067] The at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be integrated and implemented in one printed circuit board.

[0068] The display device 100 according to aspects of the disclosure can further include a level shifter 300 for adjusting a voltage level. In an embodiment, the level shifter 300 can be disposed on the control printed circuit board (CPCB) or the source printed circuit board (SPCB).

[0069] Figure 3 A circuit configuration of a display device according to aspects of the disclosure is illustrated in FIG. 1C. Figure 2 A circuit configuration of a display device according to aspects of the disclosure is illustrated in FIG. 1C.

[0070] Referring to FIG. 1C, Figure 3The gate driving circuit 130 of the display apparatus 100 can generate and output a gate signal Vgout based on a clock signal CLK. The gate signal Vgout can be provided to gate lines GL disposed in the display panel 110.

[0071] The gate driving circuit 130 can include a gate output buffer circuit GBUF that outputs the gate signal Vgout based on the clock signal CLK, a control circuit 500 that controls the gate output buffer circuit GBUF, and / or the like.

[0072] The gate output buffer circuit GBUF can include a pull-up transistor Tu that controls connection between a clock input node Nc to which the clock signal CLK is input and a gate output node Ng from which the gate signal Vgout is output, and a pull-down transistor Td that controls connection between the gate output node Ng and a low-level voltage node Ns to which a low-level voltage VGL is input.

[0073] The control circuit 500 can receive a start signal VST, a reset signal RST, and / or the like, and thereby control operation of the gate output buffer circuit GBUF. To this end, the control circuit 500 can control a voltage of a node Q and a voltage VQB of a node QB. The control circuit 500 can control the voltage VQB of the node QB through a DC power supply voltage GVDD.

[0074] The gate driving circuit 130 can further include a transistor susceptible to reliability, for example, a dummy pull-down transistor Dd on which the same stress as the pull-down transistor Td is applied.

[0075] A gate node of the dummy pull-down transistor Dd can be electrically connected to a gate node of the pull-down transistor Td. That is, the respective gate nodes of the pull-down transistor Td and the dummy pull-down transistor Dd can both be electrically connected to one node, i.e., the node QB.

[0076] The structure, material, type, and / or the like of the dummy pull-down transistor Dd can be the same as or substantially the same as those of the pull-down transistor Td; however, embodiments of the disclosure are not limited thereto.

[0077] When a first power voltage V1 is applied to a drain node Ndd of the dummy pull-down transistor Dd, a current flowing through a source node Nds of the dummy pull-down transistor Dd or a voltage related to the current can be sensed. The drain node Ndd and the source node Nds of the dummy pull-down transistor Dd can be positioned opposite to each other according to the type of the transistor.

[0078] The display device 100 according to the aspect of the present disclosure can further include a compensation circuit 400 capable of sensing a current Isen flowing through the source node Nds of the dummy pull-down transistor Dd or a voltage Vsen through the current Isen to compensate for the power supply voltage, and compensating for the power supply voltage according to the sensed current Isen or voltage Vsen.

[0079] The compensation circuit 400 can include a sensing processing circuit 405 capable of sensing a current Isen flowing through the source node Nds of the dummy pull-down transistor Dd or a voltage Vsen through the current to compensate for the power supply voltage, and a control device 420 capable of compensating for the power supply voltage according to the sensed current Isen or voltage Vsen.

[0080] For example, as shown in FIG. 4, the sensing processing circuit 405 can include a sampling switch SAM, an analog-to-digital converter 410, and a sensing capacitor Csen. Figure 3

[0081] The sampling switch SAM can be disposed between the analog-to-digital converter 410 and the source node Nds of the dummy pull-down transistor Dd. The sampling switch SAM can control electrical connection between the analog-to-digital converter 410 and the source node Nds of the dummy pull-down transistor Dd.

[0082] The analog-to-digital converter 410 can sense the sensing voltage Vsen stored in the sensing capacitor Csen through the sensing current Isen flowing through the source node Nds of the dummy pull-down transistor Dd electrically connected through the sampling switch SAM.

[0083] For example, the sensing capacitor Csen can be connected between the source node Nds of the dummy pull-down transistor Dd and a ground voltage GND. The sensing capacitor Csen can store a voltage of the sensing current Isen as the sensing voltage Vsen. When the sensing capacitor Csen is electrically connected to the analog-to-digital converter 410 through the sampling switch SAM, the analog-to-digital converter 410 can sense the sensing voltage Vsen.

[0084] The analog-to-digital converter 410 can convert the sensing voltage Vsen into sensing data in a digital form, and output the converted sensing data to the control device 420.

[0085] The control device 420 can determine a voltage value of the power supply voltage GVDD of the gate driving circuit 130 according to the life dissipation or the expected life of the pull-down transistor Td of the gate driving circuit 130 based on the sensing data.

[0086] For example, as shown in FIG. 4, the sensing processing circuit 405 can include a sampling switch SAM, an analog-to-digital converter 410, and a sensing capacitor Csen. Figure 4 ​As shown, the power supply voltage GVDD of the control circuit 500 applied to the gate driving circuit 130 can be controlled to gradually increase from a low voltage to a high voltage according to a driving time.

[0087] For example, in an example typical display panel, the gate driving circuit is controlled based on alternating current (AC), and has two output buffer circuits GBUF for each control circuit 500. In this case, when a direct current (DC) power supply voltage GVDD of the gate driving circuit 130 corresponding to a relatively high voltage is continuously applied to the control circuit 500, since the lifespan of the pull-down transistor Td can be rapidly shortened, the control circuit 500 is alternately driven based on AC.

[0088] In this case, in order to allow the control circuit 500 to be alternately driven based on AC, since two output buffer circuits GBUF are configured for each control circuit 500, the number of transistors included in the gate driving circuit 130 increases, and the complexity of the corresponding circuitry or circuit elements configured in the gate driving circuit increases. Due to the increase in the number of transistors included in the gate driving circuit 130 and the increase in the complexity of the corresponding circuitry or circuit elements, the defect rate of the gate driving circuit 130 increases, and it becomes difficult to implement a narrow bezel.

[0089] The gate driving circuit 130 included in the display apparatus 100 can apply a DC voltage as a power supply voltage GVDD to the control circuit 500, and in order to maximize the lifespan of the pull-down transistor Td, the power supply voltage GVDD of the control circuit 500 is compensated using a voltage value ranging from a low voltage (e.g., 5 V) to a high voltage (e.g., 12 V or 20 V) according to a driving time as shown in FIG. 1B. Figure 4 The stress applied to the pull-down transistor Td is considered. Thus, since the power supply voltage GVDD of the control circuit 500 is compensated using a voltage value ranging from a low voltage (e.g., 5 V) to a high voltage (e.g., 12 V or 20 V) according to a driving time as shown in FIG. 1B, the stress of the pull-down transistor Td can be adjusted, which increases or maximizes the lifespan of the pull-down transistor Td. Figure 4 The stress applied to the pull-down transistor Td is considered. Thus, since the power supply voltage GVDD of the control circuit 500 is compensated using a voltage value ranging from a low voltage (e.g., 5 V) to a high voltage (e.g., 12 V or 20 V) according to a driving time as shown in FIG. 1B, the stress of the pull-down transistor Td can be adjusted, which increases or maximizes the lifespan of the pull-down transistor Td.

[0090] More specifically, in the display apparatus 100 according to aspects of the disclosure, by adding a dummy pull-down transistor Dd in the gate driving circuit 130 and configuring the dummy pull-down transistor Dd such that the same stress as the pull-down transistor Td of the output buffer circuit GBUF is applied to the dummy pull-down transistor Dd, the sensing current Isen or the sensing voltage Vsen can be sensed by the dummy pull-down transistor Dd.

[0091] The display apparatus 100 can calculate the life dissipation and the expected life of the pull-down transistor Td of the output buffer circuit GBUF based on the sensed current Isen or the sensed voltage Vsen obtained by sensing by the control apparatus 420, and thereby compensate for the power voltage GVDD applied to the control circuit 500 of the gate driving circuit 130. According to embodiments of the present disclosure, when the power voltage GVDD applied to the control circuit 500 of the gate driving circuit 130 gradually increases from a low voltage to a high voltage, the life of the pull-down transistor Td can be improved.

[0092] In the display apparatus 100 according to aspects of the present disclosure, the number of transistors included in the gate driving circuit 130 can be reduced, and the complexity of the corresponding circuitry or circuit elements configured in the gate driving circuit can be lowered. Accordingly, in the display apparatus 100 according to aspects of the present disclosure, the defect rate of the gate driving circuit 130 can be lowered, and a narrow bezel can be implemented.

[0093] In the above description according to embodiments of the present disclosure, although a discussion has been made regarding the display apparatus 100 in which a DC voltage is applied as the power voltage GVDD to the control circuit 500 of the gate driving circuit 130, and the DC power voltage GVDD applied to the control circuit 500 is compensated according to the driving time, embodiments of the present disclosure are not limited thereto. For example, in the display apparatus 100 according to aspects of the present disclosure, the power voltage GVDD applied to the control circuit 500 of the gate driving circuit 130 can be an AC voltage in which a low voltage and a high voltage are alternated, and the low voltage or the high voltage of the AC power voltage GVDD applied to the control circuit 500 can be compensated according to the driving time.

[0094] In the above description according to embodiments of the present disclosure, although a discussion has been made regarding the display apparatus 100 in which the analog-digital converter 410 can sense the sensing voltage Vsen stored in the sensing capacitor Csen by the sensing current Isen flowing through the source node Nds of the dummy pull-down transistor Dd, embodiments of the present disclosure are not limited thereto. For example, in the display apparatus 100 according to aspects of the present disclosure, an impedance circuit such as a sensing resistor can be configured instead of the sensing capacitor Csen, and then the analog-digital converter 410 can sense a voltage formed by the impedance circuit.

[0095] Further, the analog-digital converter 410 can directly sense the sensing current Isen flowing through the source node Nds of the dummy pull-down transistor Dd, and can convert the sensing current Isen into sensing data in a digital form.

[0096] In some embodiments, the control apparatus 420 of the compensation circuit 400 can be implemented in a separate component, or can be implemented byFigure 1 by the controller 140 of FIG. 1, as described below with reference to FIG. 4. Figure 5 That is, the compensation circuit 400 can include a sensing processing circuit 405 capable of sensing a current flowing through a source node Nds of the dummy pull-down transistor Dd or sensing a voltage by the current, and the controller 140 capable of compensating the power supply voltage according to the sensed current or voltage.

[0097] Figure 5 is a block diagram illustrating a control device of a compensation circuit implemented using Figure 1 the controller of FIG. 1. Figure 3

[0098] Referring to Figure 5 , the controller 140 can perform various computing functions and control functions based on the sensed data output from the analog-to-digital converter 410.

[0099] The controller 140 can calculate the life dissipation and the expected life of the pull-down transistor Td based on the sensed data output from the analog-to-digital converter 410. The controller 140 can determine the power supply voltage GVDD based on the calculated life dissipation and the expected life of the pull-down transistor Td.

[0100] The controller 140 can store the sensed data output from the analog-to-digital converter 410, or store various types of control information in the memory 142. The controller 140 can store control information related to compensation of the power supply voltage in the form of a lookup table LUT in the memory 142.

[0101] The controller 140 can output a power control signal PCS for compensation of the power supply voltage to the power management integrated circuit 310.

[0102] The power management integrated circuit 310 can provide the power supply voltage GVDD to the control circuit 500 of the gate driving circuit 130 according to the power control signal PCS for compensating the power supply voltage, or cause the power supply circuitry (not shown) to provide the power supply voltage GVDD.

[0103] In some embodiments, the sensing processing circuit 405 can be implemented in a separate component, or can be included in the data driving circuit 120 of FIG. 1. For example, the sensing processing circuit 405 can be included in a source driver integrated circuit SDIC of the data driving circuit 120 of FIG. 1. Figure 1 Figure 1 As shown in FIG. 4, the sensing processing circuit 405 can be included in a source driver integrated circuit SDIC of the data driving circuit 120 adjacent to the gate driving circuit 130.

[0104] As shown in FIG. 4, the sensing processing circuit 405 can be included in a source driver integrated circuit SDIC of the data driving circuit 120 adjacent to the gate driving circuit 130. Figure 6A

[0105] ​​​As described above, the gate driving circuit 130 can be located on at least two of the four portions (e.g., the upper portion, the lower portion, the left side, and the right side) of the panel 110, but is not limited thereto. In this embodiment, the sensing processing circuit 405 can be included in the source driver integrated circuit SDIC located on each of the two portions (the left side and the right side) of the display panel 110.

[0106] When the gate driving circuit 130 is located on one portion (the left side or the right side) of the display panel 110, the sensing processing circuit 405 can be included in the source driver integrated circuit SDIC of the data driving circuit 120 disposed adjacent to the one portion (the left side or the right side) of the gate driving circuit 130.

[0107] Figure 6B The control device of the compensation circuit of Figure 3 is implemented by the controller of Figure 1 and the sensing processing circuit of the compensation circuit of Figure 3 is included in the circuit configuration of the source driver integrated circuit of the data driving circuit of Figure 1 .

[0108] Referring to Figure 6B , the display device 100 can include the data driving circuit 120 described with reference to Figure 1 , the gate driving circuit 130 described with reference to Figure 3 , the controller 140 described with reference to Figure 5 , and a plurality of sub-pixels SP.

[0109] The source driver integrated circuit SDIC of the data driving circuit 120 can include at least one selection switch SW, at least one sample and hold device S / H, a sample switch SAM, and an analog-to-digital converter 410.

[0110] Each of the plurality of sub-pixels SP disposed in the display panel 110 of the display device 100 can include an emission element ED, a driving transistor DRT, and a sensing transistor SEN.

[0111] The first node N1 of the driving transistor DRT can be a gate node of the driving transistor DRT. The second node N2 of the driving transistor DRT can be a source node or a drain node of the driving transistor DRT. The second node N2 can also be electrically connected to a source node or a drain node of the sensing transistor SEN, and electrically connected to the emission element ED. The third node N3 of the driving transistor DRT can be electrically connected to a driving voltage line DVL for providing a driving voltage EVDD.

[0112] The sensing transistor SEN can be turned on by the sensing signal SENSE and transfer one of the reference voltages VpreS and VpreR transmitted through the reference voltage line RVL to the second node N2 of the driving transistor DRT. The reference voltages VpreS and VpreR can be selected by two switches SPRE and RPRE.

[0113] In addition, the sensing transistor SEN can be turned on by the sensing signal SENSE and transmit the voltage at the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0114] In this case, the voltage at the second node N2 of the driving transistor DRT transmitted to the reference voltage line RVL can be a voltage for calculating at least one characteristic value of the sub-pixel SP or a voltage reflecting at least one characteristic value of the sub-pixel SP. For example, the at least one characteristic value of the sub-pixel SP can be at least one characteristic value of the driving transistor DRT or the light emitting element ED. The at least one characteristic value of the driving transistor DRT can include a threshold voltage and / or mobility of the driving transistor DRT. The characteristic value of the light emitting element ED can include a threshold voltage of the light emitting element ED.

[0115] The reference voltage line RVL can be electrically connected to the selection switch SW, the two or more sample and hold devices S / H, the sampling switch SAM, and the analog-digital converter 410 through data pads (SIO#k, here, k denotes the number of the reference voltage lines RVL corresponding to the sub-pixel SP).

[0116] The dummy line DuL extending from the source node Nds of the dummy pull-down transistor Dd of the gate driving circuit 130 as described above can be electrically connected to at least one selection switch SW, at least one sample and hold device S / H, the sampling switch SAM, and the analog-digital converter 410 through a dummy pad Du SIO.

[0117] The selection switch SW can select one of the dummy pad Du SIO and the two or more data pads SIO#k. For example, the selection switch SW can select the two or more data pads SIO#k during a display driving period and can select the dummy pad Du SIO during a blank period.

[0118] The sample and hold S / H can temporarily store the voltage at the second node N2 of the driving transistor DRT transmitted through the reference voltage line RVL (connected through the data pad SIO#k) and the sensing voltage Vsen of the dummy pull-down transistor Dd sensed through the dummy line DuL, respectively.

[0119] The sampling switch SAM can sequentially connect the sample and hold devices S / H to the analog-digital converter 410.

[0120] That is, in addition to the data pad SIO#k, the selection switch SW, and the sample-and-hold device S / H required for sensing the voltage at the second node N2 of the drive transistor DRT, the source driver integrated circuit SDIC of the data driving circuit 120 can further include the dummy pad Du SIO, the selection switch Du SW, and the sample-and-hold device Du S / H required for sensing the sensing voltage Vsen of the dummy pull-down transistor Dd.

[0121] The dummy pad Du SIO, the selection switch Du SW, the sample-and-hold device Du S / H, and the analog-to-digital converter 410 can correspond to the sensing processing circuit 405 described with reference to Figure 3

[0122] The analog-to-digital converter 410 can sense the voltage at the second node N2 of the drive transistor DRT and the sensing voltage Vsen of the dummy pull-down transistor Dd according to the selection of the sampling switch SAM.

[0123] The respective times at which the analog-to-digital converter 410 senses the voltage at the second node N2 of the at least one drive transistor DRT and the sensing voltage Vsen of the dummy pull-down transistor Dd can be the same or different.

[0124] In one embodiment, the analog-to-digital converter 410 can sense the voltage at the second node N2 of the at least one drive transistor DRT during a display driving period, and can sense the sensing voltage Vsen of the dummy pull-down transistor Dd during a blank period. In another embodiment, the analog-to-digital converter 410 can sense the voltage at the second node N2 of the drive transistor DRT and the sensing voltage Vsen of the dummy pull-down transistor Dd during respective sub-blank periods generated by dividing the blank period.

[0125] The source driver integrated circuit SDIC of the data driving circuit 120 can transmit respective sensing data corresponding to the voltage at the second node N2 of the drive transistor DRT and the sensing voltage Vsen of the dummy pull-down transistor Dd to the controller 140.

[0126] The controller 140 can determine the voltage value of the power supply voltage GVDD of the gate driving circuit 130 based on the sensing data corresponding to the sensing voltage Vsen of the dummy pull-down transistor Dd in the form of a lookup table as shown in Figure 5

[0127] The controller 140 can control the voltage to be output from the power management integrated circuit 310, and thereafter, the power supply voltage GVDD output from the power management integrated circuit 310 can gradually increase from a low voltage to a high voltage according to the driving time.

[0128] ​​like Figure 7 As shown, the power management integrated circuit 310 located on the control printed circuit board CPCB can transmit the power supply voltage GVDD to the control circuit 500 of the gate drive circuit 130 through the circuit film SF and power line PL located in the non-display area NDA of the display panel 110.

[0129] In the above description of embodiments according to this disclosure, although the following discussion has been made regarding the display device 100: the sensing processing circuit 405 of the compensation circuit 400 is included in the data driving circuit 120 (e.g., included in the source driver integrated circuit SDIC), and the control device 420 of the compensation circuit 400 is... Figure 1 The controller 140 is implemented, but the implementation of this disclosure is not limited thereto.

[0130] Figure 8 The system configuration of the display device according to aspects of this disclosure is shown. Figure 9 It shows Figure 8 The circuit configuration of the display device is shown.

[0131] Reference Figure 8 The display device 200 according to an aspect of this disclosure may include a gate drive circuit 130, which includes a compensation circuit 400. The compensation circuit 400 is capable of sensing the stress level, i.e., the degree to which stress is applied to the dummy pull-down transistor Dd, through a dummy pull-down transistor Dd.

[0132] Reference Figure 9 The compensation circuit 400 may have a differential amplifier structure, which includes an operational amplifier OP-AMP, sensing resistors Rset1 and Rset2 for enabling the sensing voltage Vsen to be applied to the non-inverting input terminal (+) of the operational amplifier OP-AMP, and input resistors Rop1 and Rop2 for enabling the reference voltage Vr to be applied to the inverting input terminal (-) of the operational amplifier OP-AMP.

[0133] The sensing resistor Rset1 in Rset1 and Rset2 can be set between the set voltage Vset and the non-inverting input terminal (+). The other sensing resistor Rset2 can be set between the base voltage VSS and the non-inverting input terminal (+). For example, the set voltage Vset can be 15V and the base voltage VSS can be 0V.

[0134] Input resistor Rop2 can be set between the reference voltage Vr and the inverting input terminal (-), and input resistor Rop1 can be set between the inverting input terminal (-) and the output terminal.

[0135] The operational amplifier OP-AMP can receive a difference (variation) of the sensed voltage Vsen obtained by sensing with respect to the initial reference voltage Vr via the input terminal, and can generate a power voltage GVDD due to the further increase of the output voltage Vop as the difference (variation) increases.

[0136] As described above, according to the embodiments described herein, the gate driving circuit 130 and the display apparatuses 100 and 200 including the gate driving circuit 130 can be provided, in which the number of transistors included in the gate driving circuit 130 can be reduced, and the complexity of the circuit system or circuit elements configured in the gate driving circuit 130 can be reduced.

[0137] According to the embodiments described herein, the gate driving circuit 130 and the display apparatuses 100 and 200 including the gate driving circuit 130 can be provided, in which the defect rate of the gate driving circuit can be reduced and a narrow bezel can be implemented.

[0138] According to the embodiments described herein, the gate driving circuit 130 and the display apparatuses 100 and 200 including the gate driving circuit 130 can be provided, in which the lifespan of the transistors such as the pull-down transistor Td included in the gate driving circuit can be maximized or increased by adjusting the stress of the transistors.

[0139] The above description has been given to enable any person skilled in the art to implement and use the technical idea of the present application, and has been provided in the context of a specific application and its requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. The above description and drawings provide examples of the technical idea of the present application for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical idea of the present application. Therefore, the scope of the present application is not limited to the illustrated embodiments, but is consistent with the widest scope consistent with the claims. The scope of protection of the present application should be interpreted based on the appended claims, and all technical ideas within the equivalent scope thereof should be interpreted as included in the scope of the present application.

Claims

1. A display device comprising: a display panel including at least one sub-pixel; and a gate driver circuit configured to supply a gate signal to the at least one sub-pixel through at least one gate line; wherein the gate driver circuit includes: a gate output buffer circuit including a pull-up transistor controlling a connection between a clock input node and a gate output node from which the gate signal is output, and a pull-down transistor controlling a connection between a low voltage node and the gate output node from which the gate signal is output; a control circuit capable of controlling the gate output buffer circuit; and a dummy pull-down transistor whose gate node is shared with that of the pull-down transistor, the pull-down transistor being electrically connected to the gate output node for outputting the gate signal through the at least one gate line, wherein the display device further includes a data driver circuit including one or more source driver integrated circuits each configured to output at least one data signal to at least one data line, wherein the at least one sub-pixel includes at least one drive transistor, and at least one reference voltage line electrically connected to a certain node of the at least one drive transistor, and wherein the one or more source driver integrated circuits include at least one selection switch selecting the at least one reference voltage line and a dummy line electrically connected with the dummy pull-down transistor.

2. The display device according to claim 1, wherein A power voltage applied to the control circuit is direct current, and the direct current power voltage applied to the control circuit is compensated according to a driving time. 3.The display device of claim 1, further comprising a compensation circuit capable of sensing a current flowing through a source node of the dummy pull-down transistor or sensing the voltage through the current, and compensating a power voltage according to the sensed current or voltage.

4. The display device according to claim 3, wherein The compensation circuit includes: a sensing processing circuit capable of sensing the current flowing through the source node of the dummy pull-down transistor or sensing the voltage through the current; and a control means capable of compensating the power voltage according to the sensed current or voltage.

5. The display device of claim 4, wherein, The sensing processing circuit includes: a sensing capacitor storing a sensing voltage according to the current flowing through the source node of the dummy pull-down transistor; an analog-to-digital converter configured to convert the sensing voltage stored in the sensing capacitor into sensing data in digital form; and a sampling switch configured to control electrical connection between the sensing capacitor and the analog-to-digital converter.

6. The display device of claim 4, further comprising: a controller for controlling the gate driver circuit, wherein the control means is implemented through the controller. 7.The display device of claim 3, wherein The compensation circuit includes: a sensing processing circuit capable of sensing the current flowing through the source node of the dummy pull-down transistor or sensing the voltage through the current; and a control device capable of compensating the power supply voltage according to the sensed current or voltage, and wherein the sensing processing circuit is included in at least one of the one or more source driver integrated circuits.

8. The display device of claim 7, wherein, wherein at least one source driver integrated circuit including the sensing processing circuit is positioned adjacent to a side of the display panel on which the gate drive circuit is located.

9. The display device according to claim 3, wherein the one or more source driver integrated circuits further include: a sample and hold device electrically connected to the selection switch, respectively, and configured to store a voltage at the specific node of the at least one drive transistor transmitted through the at least one reference voltage line and a sensing voltage of the dummy pull-down transistor sensed through the dummy line; an analog-to-digital converter configured to convert the voltage at the specific node of the at least one drive transistor transmitted through the at least one reference voltage line and the sensing voltage of the dummy pull-down transistor sensed through the dummy line stored in the sample and hold device into digital form sensing data; and a sampling switch configured to electrically connect the sample and hold device and the analog-to-digital converter.

10. The display device according to claim 3, wherein the compensation circuit is included in the gate drive circuit.

11. A gate drive circuit, comprising: a gate output buffer circuit including a pull-up transistor of a connection between a control clock input node and a gate output node from which a gate signal is output, and a pull-down transistor of a connection between a control low voltage node and the gate output node from which the gate signal is output; a control circuit capable of controlling the gate output buffer circuit; and a dummy pull-down transistor having a gate node shared with a gate node of the pull-down transistor, the pull-down transistor being electrically connected to the gate output node for outputting the gate signal through at least one gate line, wherein a display device having the gate drive circuit includes: a display panel including at least one sub-pixel; and a data drive circuit including one or more source driver integrated circuits, each source driver integrated circuit being configured to output at least one data signal to at least one data line, wherein the at least one sub-pixel includes at least one drive transistor, and at least one reference voltage line electrically connected to a specific node of the at least one drive transistor, and wherein the one or more source driver integrated circuits include at least one selection switch selecting the at least one reference voltage line and a dummy line electrically connected to the dummy pull-down transistor.

12. The gate drive circuit of claim 11, wherein, a power supply voltage applied to the control circuit is direct current, and the direct current power supply voltage applied to the control circuit is compensated according to a driving time.

13. The gate drive circuit according to claim 11, further comprising a compensation circuit capable of sensing a current flowing through a source node of the dummy pull-down transistor or a voltage across the current, and compensating a power supply voltage according to the sensed current or voltage.

14. The gate drive circuit of claim 13, wherein, The compensation circuit includes: a sensing processing circuit capable of sensing a current flowing through the source node of the dummy pull-down transistor or the voltage across the current; and a control device capable of compensating the power supply voltage according to the sensed current or voltage.

15. The gate drive circuit of claim 14, wherein, The sensing processing circuit includes: a sensing capacitor storing a sensing voltage according to a current flowing through the source node of the dummy pull-down transistor; an analog-to-digital converter configured to convert the sensing voltage stored in the sensing capacitor into sensing data in digital form; and a sampling switch configured to control an electrical connection between the sensing capacitor and the analog-to-digital converter.

16. The gate drive circuit of claim 13, wherein, The compensation circuit is included in the gate drive circuit.

14. The gate drive circuit according to claim 13, wherein the compensation circuit is included in the gate drive circuit.

15. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

16. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

17. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

18. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

19. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

20. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

21. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

22. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

23. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

24. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

25. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

26. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

27. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

28. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power supply circuit of the gate drive circuit.

29. The gate drive circuit according to claim 13, wherein the compensation circuit is included in a power

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