Method and system for memory control

Abstract

Methods and systems for improved memory control are disclosed. One memory architecture of the present application includes a plurality of memory units and an interface. A respective memory unit of the plurality of memory units is configured as a PIM architecture. The interface includes a plurality of lines. The interface is coupled between the plurality of memory units and a host. The interface is to receive one or more signals from the host via the plurality of lines. A respective memory unit of the plurality of memory units is coupled to a respective line of the plurality of lines, and the respective memory unit also receives a respective signal of the one or more signals through the interface to facilitate being individually selected by the host.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically to methods and systems for memory control. Background Technology

[0002] In the field of memory technology, designers and manufacturers aim to improve memory architecture in terms of speed, capacity, cost, power efficiency, and control efficiency, and to develop and upgrade memory interfaces to facilitate these improvements. For example, Peripheral Component Interconnect (PCIe or PCI-e) is a high-speed serial computer expansion bus standard that standardizes the common motherboard interface for personal computer graphics cards, hard drives, memory, network hardware connections, etc. Another example is Compute ExpressLink (CXL), a new high-speed CPU-to-Device and CPU-to-Memory interconnect protocol designed to accelerate next-generation data computing performance. However, traditional Dynamic Random Access Memory (DRAM) technology has limitations such as manufacturing processes and cost control, making it difficult to implement high-performance interfaces in DRAM architectures.

[0003] Dual Data Rate (DDR) interfaces are feasible in DRAM architectures. Typically, existing DDR-based memory module designs use two or more chipsets, and only one chipset can be selected at a time. Therefore, all chips within the same chipset are always selected simultaneously and operate in sync. However, the DDR protocol does not support data access to individual chips; different chips within the same chipset cannot be selected individually. Therefore, it is necessary to improve DDR-based memory control so that individual chips can be selected, controlled, and accessed (read / write) precisely and flexibly to adapt to various application scenarios. Summary of the Invention

[0004] This application provides methods and systems for memory control to address the problem of how to improve DDR interface-based memory control in the prior art.

[0005] In a first aspect, this application provides a memory architecture coupled to a host outside the memory architecture. The memory architecture includes: a plurality of memory cells, each of which is configured as a PIM architecture; and an interface coupled between the plurality of memory cells and the host. The interface includes multiple lines for receiving one or more signals from the host via the multiple lines. Each memory cell is coupled to a corresponding line of the multiple lines, and the corresponding memory cell is also configured to receive a corresponding signal from the one or more signals via the interface for individual selection by the host. The one or more signals received by the interface include one or more unit I / O enable signals. Each memory cell includes a corresponding unit I / O enable register for enabling / disabling the I / O function of the corresponding memory cell.

[0006] Secondly, this application also provides a memory method, comprising: individually selecting one or more memory cells from a plurality of memory cells of a storage system by sending one or more signals to the storage system, wherein a corresponding memory cell among the plurality of memory cells is configured as a PIM architecture, wherein the one or more signals include one or more cell I / O enable signals, and a corresponding memory cell among the plurality of memory cells includes a corresponding cell I / O enable register for enabling / disabling the I / O function of the corresponding memory cell; and accessing the one or more memory cells.

[0007] Thirdly, this application also provides a memory system, comprising: a memory architecture coupled to a host external to the memory architecture, the memory architecture comprising: a plurality of memory cells, a corresponding memory cell among the plurality of memory cells being configured as a PIM architecture; and an interface coupled between the plurality of memory cells and the host, the interface comprising a plurality of lines, the interface being used to receive one or more signals from the host via the plurality of lines; wherein a corresponding memory cell among the plurality of memory cells is coupled to a corresponding line among the plurality of lines, and the corresponding memory cell is further used to receive a corresponding signal among the one or more signals via the interface for individual selection by the host, wherein the one or more signals received by the interface include one or more unit I / O enable signals, the corresponding memory cell among the plurality of memory cells includes a corresponding unit I / O enable register, the corresponding unit I / O enable register being used to enable / disable the I / O function of the corresponding memory cell; the host being used to send the one or more signals to the memory architecture through the interface and to access the corresponding memory cells.

[0008] Fourthly, this application also provides a memory architecture coupled to a host external to the memory architecture, the memory architecture comprising: a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells, and a corresponding memory cell among the plurality of memory cells being configured as a PIM architecture; and an interface coupled between the memory architecture and the host, the interface comprising a plurality of lines, the interface being configured to receive one or more first-type signals and one or more second-type signals from the host via the plurality of lines; wherein a corresponding memory cell group among the plurality of memory cell groups is selected by the host using a corresponding first-type signal among the one or more first-type signals; wherein a corresponding memory cell among the plurality of memory cell groups is coupled to a corresponding line among the plurality of lines, and the corresponding memory cell among the plurality of memory cell groups is further configured to receive a corresponding second-type signal among the one or more second-type signals via the interface, so as to be individually selected by the host.

[0009] Fifthly, this application also provides a memory system, comprising: a memory architecture coupled to a host external to the memory architecture, the memory architecture comprising: multiple memory cell groups, each memory cell group comprising multiple memory cells, each memory cell being configured as a PIM architecture; and an interface coupled between the memory architecture and the host, the interface comprising multiple lines, the interface being configured to receive one or more first-type signals and one or more second-type signals from the host via the multiple lines, wherein a corresponding group of the multiple memory cell groups is selected by the host using a corresponding first-type signal from the one or more first-type signals, a corresponding memory cell of the multiple memory cells is coupled to a corresponding line from the multiple lines, and a corresponding memory cell of the multiple memory cells is further configured to receive a corresponding second-type signal from the one or more second-type signals via the interface for individual selection by the host; the host being configured to send the one or more signals to the memory architecture via the interface and access the corresponding memory cells.

[0010] In a sixth aspect, this application also provides a memory method, comprising: individually selecting a corresponding memory cell group among a plurality of memory cell groups of a storage system by sending one or more signals of a first type to the storage system, the corresponding memory cell group comprising a plurality of memory cells; individually selecting a corresponding memory cell among the plurality of memory cells of the corresponding memory cell group by sending one or more signals of a second type to the corresponding memory cell group, wherein the corresponding memory cell among the plurality of memory cells is configured as a PIM architecture; and accessing the corresponding memory cell.

[0011] Compared with the prior art, this application has the following advantages:

[0012] The memory architecture provided in this application is coupled to a host outside the memory architecture. The memory architecture includes: multiple memory cells, each of which is configured as a PIM architecture; and an interface coupled between the multiple memory cells and the host. The interface includes multiple lines for receiving one or more signals from the host via the multiple lines. Each memory cell is coupled to a corresponding line among the multiple lines, and the corresponding memory cell is also used to receive a corresponding signal from the one or more signals via the interface for individual selection by the host. The one or more signals received by the interface include one or more unit I / O enable signals. Each memory cell includes a corresponding unit I / O enable register for enabling / disabling the I / O function of the corresponding memory cell. Because this application provides a complete method and system for memory control, it improves memory control based on the DDR interface, allowing individual chips to be selected, controlled, and accessed (read / write) individually with precision and flexibility to adapt to various application scenarios. Attached Figure Description

[0013] Detailed explanations are provided with reference to the accompanying drawings. In these drawings, the leftmost digit of the reference value indicates the drawing in which the reference value first appears. The same reference value is used in different drawings to represent similar or identical items or features.

[0014] Figure 1A This is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0015] Figure 1B This is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0016] Figure 2AThis is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0017] Figure 2B This is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0018] Figure 3A This is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0019] Figure 3B This is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0020] Figure 4 An example table showing the correspondence between data mask signals and unit interfaces is provided.

[0021] Figure 5A This is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0022] Figure 5B This is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0023] Figure 6 Example tables of features for Example Option 1, Example Option 2, and Example Option 3 are provided.

[0024] Figure 7 This is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0025] Figure 8 This is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0026] Figure 9 This is a schematic diagram illustrating communication between an exemplary memory system and a host.

[0027] Figure 10 This is a schematic diagram illustrating an exemplary memory control process.

[0028] Figure 11 This is a schematic diagram illustrating an exemplary memory control process. Detailed Implementation

[0029] The systems and methods discussed in this paper aim to improve memory control, and more specifically, to improve methods and systems for memory control.

[0030] Typically, memory cannot keep up with the speed of the processor. Moving data from memory is more expensive than computation in terms of bandwidth, energy, and latency. The growing gap between the processor and memory is known as the "memory wall."

[0031] Some research aims to bring computation closer to data storage to address the memory wall crisis. The Processing-in-Memory (PIM) architecture is rapidly emerging as an attractive solution. Based on the PIM architecture, certain algorithms are processed by a Data Processing Unit (DPU) within memory. Although the concept of PIM has been studied for decades, attempts to implement the PIM architecture have encountered difficulties in terms of practicality. For example, designers of PIM architecture cannot achieve the same high memory capacity on a single chip as they would on multiple chips. Communication between memory chips becomes a bottleneck based on traditional memory architectures. Furthermore, PIM may be at a disadvantage in the memory market. For instance, 128MB memory modules with PIM architecture from different manufacturers are not interchangeable, which impairs interoperability and drives up prices.

[0032] With advancements in emerging memory technologies in recent years, practicality issues have been alleviated. For example, one approach is to integrate the Data Processing Unit (DPU) into DRAM. The short distance between the DPU and the memory cells in DRAM results in minimal energy expenditure for moving data back and forth, leading to very low latency. This means computations can be performed quickly within memory, freeing up the processor to perform other complex tasks. In other words, the PIM architecture accelerates computation and reduces the overhead of data movement.

[0033] Traditional computers are often affected by the von Neumann bottleneck, meaning that newly emerging data-intensive workloads / applications are no longer actually handled by traditional computers. The idea behind the von Neumann bottleneck is that the throughput of a computer system is affected by the relative power of the processor compared to the maximum data transfer rate of the memory.

[0034] While accessing memory, the processor remains idle for a certain period. However, next-generation data-intensive workloads / applications, such as machine learning tasks, can benefit from PIM technology. PIM acceleration solutions position the processing core next to the data, addressing the bottleneck of big data computing. PIM solutions have reportedly accelerated data-intensive workloads / applications by up to 20 times with virtually no additional energy costs. The evolving PIM solutions are opening new horizons for the big data era in terms of performance and cost efficiency.

[0035] However, seamless integration of PIM architecture with traditional computing systems remains challenging due to the need for non-traditional control technologies. Many current approaches fail to adequately address the diverse control requirements of PIM.

[0036] Figure 1AThis is a schematic diagram 100 illustrating communication between an exemplary memory system 102 and a host 104. In embodiments, the memory system 102 can be any suitable type of memory architecture, such as a DDR-based memory architecture. In embodiments, the host can be, but is not limited to, a central processing unit (CPU), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), field-programmable gate arrays (FPGAs), a digital signal processor (DSP), or any combination thereof.

[0037] refer to Figure 1A In the memory system 102, there are a controller 106 and n memory cells, which include memory cells 1_108, ..., m_110, (m+1)_112, ..., n_114, where m and n are positive integers. As an example, but not limited to, the total number of memory cells n in the memory system 102 is a power of 2.

[0038] Controller 106 is used to receive command and address signals from host 104. Controller 106 is also used to control the corresponding memory units of memory units 1_108, ..., memory unit m_110, memory unit (m+1)_112, ..., memory unit n_114. Controller 106 is also used to receive command and address signals from host 104 via command and address lines 116.

[0039] The respective memory cells of memory cells 1_108, ..., m_110, (m+1)_112, ..., n_114 are used to transmit data / signals to / from host 104 via data bus 118. In an embodiment, data bus 118 may include independent bidirectional data paths / channels for the respective memory cells to communicate with host 104 to transmit data / signals, and these data paths / channels are referred to as cell interfaces 1_120, 2_122, 3_124, ..., n_126. In an embodiment, cell interface 1_120 is used to transmit data / signals between memory cell 1_108 and host 104. Cell interface 2_122 is used to transmit data / signals between memory cell m_110 and host 104. Cell interface 3_124 is used to transmit data / signals between memory cell (m+1)_112 and host 104. Unit interface n_126 is used to transfer data / signals between memory unit n_114 and host 104. In an embodiment, the corresponding memory units in memory units 1_108, ..., memory units m_110, memory units (m+1)_112, ..., memory units n_114 can be memory chips / units of "×4", "×8", "×16", etc., where "×4", "×8", and "×16" are the data widths of the chip / unit in bits. As an example, memory units 1_108, ..., memory units m_110, memory units (m+1)_112, ..., memory units n_114 are used to transfer data / signals with a data width of 16 bits.

[0040] In this embodiment, the corresponding memory cells in memory cells 1_108, ..., m_110, (m+1)_112, ..., n_114 can be configured as an accelerator architecture. In this embodiment, the accelerator architecture is designed to provide powerful computing capabilities and large memory capacity / bandwidth. An exemplary accelerator architecture may be based on a PIM architecture using DRAM technology, which integrates memory and computing resources into the same memory chip / cell.

[0041] Many computational operations can be performed while data resides in DRAM. This saves time, power, and effective memory bandwidth. Further examples of accelerator architectures include, but are not limited to, intelligent random access memory (IRAM) architectures, DRAM-based reconfigurable in-situ accelerator (DRISA) architectures, and so on.

[0042] Command and address lines 116 and data bus 118 are collectively referred to as interface 128. In other words, interface 128 includes command and address lines 116 and data bus 118. Interface 128 is coupled between host 104 and memory system 102 / each memory cell. In embodiments, interface 128 can be any suitable memory interface, such as a DDR interface. In embodiments, interface 128 may further include other lines such as clock lines, response signal lines, control signal lines, etc.

[0043] Host 104 includes memory controller 130. Host 104 is used to exchange data / signals with memory system 102 via data bus 118 using memory controller 130. In embodiments, the data width of data bus 118 can be any suitable width, for example, 64 bits. As an example, but not limited to, the data width of data bus 118 is a power of 2. Host 104 is also used to send command and address signals to controller 106 of memory system 102 via command and address lines 116 using memory controller 130.

[0044] Under the DDR protocol, DDR-based memory modules are designed to have two or more chipsets. A chipset is a group of memory chips / cells connected to the same chipset select signal, and only one chipset can be selected at a given time. Taking the exemplary schematic diagram 100 above as an example, memory cells 1_108, ..., m_110 can be in the first chipset 132, and memory cells (m+1)_112, ..., n_114 can be in the second chipset 134. Although Figure 1A Two chipsets are shown in memory system 102, but memory system 102 may include other numbers of chipsets. Therefore, all memory chips / cells within the same chipset are always selected simultaneously and operate synchronously. For example, memory cells 1_108, ..., m_110 in the first chipset 132 are always selected together. Similarly, memory cells (m+1)_112, ..., n_114 in the second chipset 134 are always selected together. However, different chips / cells within the same chipset cannot be selected individually. For example, memory cells 1_108, ..., m_110 in the first chipset 132 cannot be selected individually. Likewise, memory cells (m+1)_112, ..., n_114 in the second chipset 134 cannot be selected individually.

[0045] Figure 1BThis is a schematic diagram 100' illustrating communication between an exemplary memory system 102' and a host 104'. In embodiments, the memory system 102' can be any suitable type of memory architecture, such as a DDR-based memory architecture. In embodiments, the host can be, but is not limited to, a CPU, ASIC, GPU, FPGA, DSP, or any combination thereof.

[0046] refer to Figure 1B The memory system 102' includes a controller 106' and n memory units, which include memory units 1_108', ..., m_110' and (m+1)_112', ..., n_114', where m and n are positive integers. As an example, but not limited to, the total number of memory units n in the memory system 102' is a power of 2.

[0047] Controller 106' is used to receive command and address signals from host 104'. Controller 106' is also used to control the corresponding memory cells in memory cells 1_108', ..., m_110' and (m+1)_112', ..., n_114'. Controller 106' is also used to receive command and address signals from host 104' via command and address lines 116'.

[0048] The corresponding memory cells in memory cells 1_108', ..., m_110' and (m+1)_112', ..., n_114' are used to transmit data / signals to / from host 104' via data bus 118'. In an embodiment, data bus 118' may include independent bidirectional data paths / channels for the respective memory cells to communicate with host 104 to transmit data / signals, and these data paths / channels are referred to as cell interface 1_120', cell interface 2_122', cell interface 3_124', ..., cell interface n_126'. In an embodiment, cell interface 1_120' is used to transmit data / signals between memory cell 1_108' and host 104'. Cell interface 2_122' is used to transmit data / signals between memory cell m_110' and host 104'. Cell interface 3_124' is used to transmit data / signals between memory cell (m+1)_112' and host 104'. Unit interface n_126' is used to transmit data / signals between memory unit n_114' and host 104'. In an embodiment, the corresponding memory units in memory units 1_108', ..., memory units m_110', memory units (m+1)_112', ..., memory units n_114' can be memory chips / units of "×4", "×8", "×16", etc., where "×4", "×8", and "×16" are the data widths of the chip / unit in bits. As an example, memory units 1_108', ..., memory units m_110', memory units (m+1)_112', ..., memory units n_114' are used to transmit data / signals with a data width of 16 bits.

[0049] Command + address line 116' and data bus 118' can be collectively referred to as interface 128'. In other words, interface 128' may include command + address line 116' and data bus 118'. Interface 128' is coupled between host 104' and memory system 102' / each memory cell. In embodiments, interface 128' can be any suitable memory interface, such as a DDR interface. In embodiments, interface 128' may further include other lines such as clock lines, response signal lines, control signal lines, etc.

[0050] Host 104' includes memory controller 130'. Host 104' is used to exchange data / signals with memory system 102' via data bus 118' using memory controller 130'. In embodiments, the data width of data bus 118' can be any suitable width, for example, 64 bits. Host 104' is also used to send command and address signals to controller 106' of memory system 102' via command + address lines 116 using memory controller 130'.

[0051] Under the DDR protocol, DDR-based memory modules are designed to have two or more chipsets. A chipset is a group of memory chips / cells connected to the same chipset select signal, and only one chipset can be selected at a given time. Taking the exemplary schematic diagram 100' above as an example, memory cells 1_108', ..., m_110' can be in the first chipset 132', and memory cells (m+1)_112', ..., n_114' can be in the second chipset 134'. Although Figure 1B Two chipsets in memory system 102 are shown, but this disclosure is not limited thereto, and memory system 102 may include other numbers of chipsets. Therefore, all memory chips / cells within the same chipset are always selected simultaneously and operate synchronously. For example, memory cells 1_108', ..., m_110' in the first chipset 132' are always selected together. Similarly, memory cells (m+1)_112', ..., n_114' in the second chipset 134 are always selected together. However, different chips / cells within the same chipset cannot be selected individually. For example, memory cells 1_108', ..., m_110' in the first chipset 132 cannot be selected individually. Likewise, memory cells (m+1)_112', ..., n_114' in the second chipset 134 cannot be selected individually.

[0052] In this embodiment, the corresponding memory units of memory units 1_108', ..., m_110' and (m+1)_112', ..., n_114' can be accelerator architectures, such as PIM architectures. In this embodiment, memory unit 1_108' includes a data area 136' for storing data, a computation block (COMPT) 138' for performing computations, and a computation block 140' for performing computations. The data area 136' is also used to communicate / interact with computation blocks 138' and 140'. Memory unit m_110' includes a data area 142' for storing data, a computation block 144' for performing computations, and a computation block 146' for performing computations. The data area 142' is also used to communicate / interact with computation blocks 144' and 146'. Memory unit (m+1)_112' includes a data area 148' for storing data, a computation block 150' for performing computations, and a computation block 152' for performing computations. The data area 148' is also used for communication / interaction with computation blocks 150' and 152'. Memory unit n_114' includes a data area 154' for storing data, a computation block 156' for performing computations, and a computation block 158' for performing computations. The data area 154' is also used for communication / interaction with computation blocks 156' and 158'. Although... Figure 1B The illustration shows a corresponding memory unit comprising one data region and two computation blocks, but this disclosure is not limited thereto, and the corresponding memory unit may include other numbers of data regions and computation blocks. Additionally or optionally, the computation blocks may include a data processing unit (DPU). Using the PIM architecture described above, specific types of algorithms are processed by the computation blocks / data processing units within the memory unit, thereby eliminating some costly data movements and significantly improving the overall efficiency of the computation blocks.

[0053] As mentioned above, even when memory cells are located within the same chipset of the memory system, it is necessary to improve memory control in terms of the precision and flexibility of individually selecting and controlling memory cells. More details will be described below.

[0054] Figure 2A This is a schematic diagram 200 illustrating communication between an exemplary memory system 202 and a host 204. In embodiments, the memory system 202 can be any suitable type of memory architecture, such as a DDR-based multichannel memory architecture. In embodiments, the memory system 202 can include volatile memory, such as RAM, DRAM, cache, etc., and non-volatile memory, such as ROM, flash memory, micro hard disk drives, etc., or any combination thereof. In embodiments, the host can be, but is not limited to, a CPU, ASIC, GPU, FPGA, DSP, or any combination thereof.

[0055] refer to Figure 2A The memory system 202 includes n memory cells, including a first memory cell 206, a second memory cell 208, a third memory cell 210, ..., an nth memory cell 212. As an example, but not limited to, the total number of memory cells n in the memory system 202 is a power of 2. In embodiments, the corresponding memory cells of the first memory cell 206, the second memory cell 208, the third memory cell 210, ..., the nth memory cell 212 can be accelerator architectures, such as PIM architectures. Accelerator architectures have been described above and will not be repeated here.

[0056] The corresponding memory units of the first memory unit 206, the second memory unit 208, the third memory unit 210, ..., the nth memory unit 212 are used to transmit data / signals to / from the host 204 via the data bus 214.

[0057] In this embodiment, the data width of the data bus 214 can be any suitable width, for example, 64 bits. In this embodiment, the data bus 214 may include independent bidirectional data paths / channels for communication between the respective memory cells and the host 204 to transmit data / signals, and the data paths / channels are referred to as cell interface 1_216, cell interface 2_218, cell interface 3_220, ..., cell interface n_222. In this embodiment, cell interface 1_216 is used to transmit data / signals between the first memory cell 206 and the host 204. Cell interface 2_218 is used to transmit data / signals between the memory cell 208 and the host 204. Cell interface 3_220 is used to transmit data / signals between the third memory cell 210 and the host 204. Cell interface n_222 is used to transmit data / signals between the memory cell n_212 and the host 204.

[0058] The corresponding memory units of the first memory unit 206, the second memory unit 208, the third memory unit 210, ..., the nth memory unit 212 are also used to receive command / address signals from the host 204 via the command / address signal line 216.

[0059] The first memory unit 206, the second memory unit 208, the third memory unit 210, ..., the nth memory unit 212 are also used to receive chipset selection signals from the host 204. For example, the first memory unit 206 is also used to receive a first chipset selection signal from the host 204 via a first chipset selection line 226. The second memory unit 208 is also used to receive a second chipset selection signal from the host 204 via a second chipset selection line 228. The third memory unit 210 is also used to receive a third chipset selection signal from the host 204 via a third chipset selection line 230. The nth memory unit 212 is also used to receive an nth chipset selection signal from the host 204 via an nth chipset selection line 232.

[0060] The host 204 is used to transmit data / signals to / from the corresponding memory units in the first memory unit 206, the second memory unit 208, the third memory unit 210, ..., the nth memory unit 212 via the data bus 214 / the corresponding unit interface 216, 218, 220 or 222.

[0061] The host 204 is also used to send command / address signals to the corresponding memory cells in the first memory cell 206, the second memory cell 208, the third memory cell 210, ..., the nth memory cell 212 via command / address line 224.

[0062] The host 204 is also configured to send chipset selection signals to corresponding memory cells in the first memory cell 206, the second memory cell 208, the third memory cell 210, ..., the nth memory cell 212 to select / deselect the corresponding memory cell. For example, the host 204 is also configured to send a first chipset selection signal to the first memory cell 206 via the first chipset selection line 226 to select / deselect the first memory cell 206. The host 204 is also configured to send a second chipset selection signal to the second memory cell 208 via the second chipset selection line 228 to select / deselect the second memory cell 208. The host 204 is also configured to send a third chipset selection signal to the third memory cell 210 via the third chipset selection line 230 to select / deselect the third memory cell 210. The host 204 is also configured to send an nth chipset selection signal to the nth memory cell 212 via the nth chipset selection line 232 to select / deselect the nth memory cell 212.

[0063] In summary, the data bus 214, command / address line 224, first chipset select line 226, second chipset select line 228, third chipset select line 230, ..., nth chipset select line 232 can be collectively referred to as interface 234. In other words, interface 234 may include the data bus 214, command / address line 224, first chipset select line 226, second chipset select line 228, third chipset select line 230, ..., nth chipset select line 232. Interface 234 is coupled between host 204 and memory system 202 / each memory cell. In embodiments, interface 234 can be any suitable memory interface, such as a DDR interface. In embodiments, interface 234 may further include other lines such as clock lines, response signal lines, control signal lines, etc.

[0064] As mentioned above, traditional DDR interface-based memory modules are designed with two or more chipsets, and only one chipset can be selected at a time. Therefore, all memory chips / cells within the same chipset are always selected simultaneously and operate in sync. However, different chips / cells within the same chipset cannot be selected, controlled, or accessed (read / write) individually.

[0065] However, in the exemplary schematic diagram 200, each memory cell in the first memory cell 206, the second memory cell 208, the third memory cell 210, ..., the nth memory cell 212 is considered as a chipset and is individually selected by the host 204 using chipset selection signals 218, 220, 222, ..., 224. In this embodiment, only one memory cell can be selected at a given time.

[0066] The host 204 is also used to individually access the corresponding memory cells in the first memory cell 206, the second memory cell 208, the third memory cell 210, ..., the nth memory cell 212 via the data bus 214 / cell interfaces 216, 218, 220 and 222. The functions of the data bus 214 and the cell interfaces 216, 218, 220 and 222 are as described above and will not be repeated here.

[0067] For example, host 204 is also used to access the first memory cell 206 via data bus 214 / cell interface 1_216 when the first memory cell 206 is selected to perform a read and / or write operation. In the embodiment, although data bus 214 is shared among n memory cells, the entire data width of data bus 214 is available during the read and / or write operation of host 204 and the first memory cell 206 because only the first memory cell 206 is selected at a given time.

[0068] For example, host 204 is also used to access second memory cell 208 via data bus 214 / cell interface 2_218 when second memory cell 208 is selected to perform read and / or write operations. In an embodiment, although data bus 214 is shared among n memory cells, the entire data width of data bus 214 is available during read and / or write operations of host 204 and second memory cell 208 because only second memory cell 208 is selected at a given time.

[0069] For example, host 204 is also used to access the third memory cell 210 via data bus 214 / cell interface 3_220 when the third memory cell 210 is selected to perform a read and / or write operation. In the embodiment, although data bus 214 is shared among n memory cells, the entire data width of data bus 214 is available during read and / or write operations of host 204 and the third memory cell 210 because only the third memory cell 210 is selected at a given time.

[0070] For example, host 204 is also used to access the nth memory cell 212 via data bus 214 / cell interface n_222 when the nth memory cell 212 is selected to perform a read and / or write operation. In the embodiment, although data bus 214 is shared among the n memory cells because only the nth memory cell 212 is selected at a given time, the entire data width of data bus 214 is available during the read and / or write operation of host 204 and the nth memory cell 212.

[0071] Using the exemplary schematic diagram 200 described above, each memory cell in the memory system 202 can be individually selected, controlled, and accessed (read / write) by the host 204. This overcomes the problem that chips / cells in traditional DDR-based memories must operate in synchronized mode. Therefore, memory control is improved.

[0072] Although Figure 2A The illustration shows n memory cells in memory system 202, but this disclosure is not limited thereto. In embodiments, memory system 202 may include other components. For example, other components may include, but are not limited to, computing units, memory cells, accelerator units, control units, or any combination thereof. In embodiments, exemplary schematic diagram 200 can be extended to control other components in memory system 202.

[0073] Figure 2BThis is a schematic diagram 200' illustrating communication between an exemplary memory system 202' and a host 204'. In embodiments, the memory system 202' can be any suitable type of memory architecture, such as a DDR-based multichannel memory architecture. In embodiments, the memory system 202' can include volatile memory, such as RAM, DRAM, cache, etc., and non-volatile memory, such as ROM, flash memory, micro hard disk drive, etc., or any combination thereof. In embodiments, the host can be, but is not limited to, a CPU, ASIC, GPU, FPGA, DSP, or any combination thereof.

[0074] refer to Figure 2B The memory system 202' includes n memory cells, which include a first memory cell 206', a second memory cell 208', a third memory cell 210', ..., an nth memory cell 212'. As an example, but not limited to, the total number of memory cells n in the memory system 202' is a power of 2.

[0075] The corresponding memory units in the first memory unit 206', the second memory unit 208', the third memory unit 210', ..., the nth memory unit 212' are used to transmit data / signals to / from the host 204' via the data bus 214'.

[0076] In this embodiment, the data width of data bus 214' can be any suitable width, for example, 64 bits. In this embodiment, data bus 214' may include bidirectional data paths / channels for communication between corresponding memory units and host 104 to transmit data / signals, and the data paths / channels are referred to as unit interface 1_216', unit interface 2_218', unit interface 3_220', ..., unit interface n_222'. In this embodiment, unit interface 1_216' is used to transmit data / signals between the first memory unit 206' and host 204'. Unit interface 2_218' is used to transmit data / signals between the second memory unit 208' and host 204'. Unit interface 3_220' is used to transmit data / signals between the third memory unit 210' and host 204'. Unit interface n_222' is used to transmit data / signals between memory unit n_212' and host 204'.

[0077] The corresponding memory units in the first memory unit 206', the second memory unit 208', the third memory unit 210', ..., the nth memory unit 212' are also used to receive command / address signals from the host 204' via the command / address signal line 216'.

[0078] The first memory unit 206', the second memory unit 208', the third memory unit 210', ..., the nth memory unit 212' are also used to receive a chipset selection signal from the host 204'. For example, the first memory unit 206' is also used to receive a first chipset selection signal from the host 204' via a first chipset selection line 226'. The second memory unit 208' is also used to receive a second chipset selection signal from the host 204' via a second chipset selection line 228'. The third memory unit 210' is also used to receive a third chipset selection signal from the host 204' via a third chipset selection line 230'. The nth memory unit 212' is also used to receive an nth chipset selection signal from the host 204' via an nth chipset selection line 232'.

[0079] The host 204' is used to transmit data / signals to / from the corresponding memory units in the first memory unit 206', the second memory unit 208', the third memory unit 210', ..., the nth memory unit 212' via the data bus 214'.

[0080] The host 204' is also used to send command / address signals to the corresponding memory cells in the first memory cell 206', the second memory cell 208', the third memory cell 210', ..., the nth memory cell 212' via command / address line 224'.

[0081] The host 204' is also configured to send chipset selection signals to corresponding memory cells in the first memory cell 206', second memory cell 208', third memory cell 210', ..., nth memory cell 212' to select / deselect the corresponding 16 memory cells. For example, the host 204' is also configured to send a first chipset selection signal to the first memory cell 206' via the first chipset selection line 226' to select / deselect the first memory cell 206'. The host 204' is also configured to send a second chipset selection signal 220' to the second memory cell 208' to select / deselect the second memory cell 208'. The host 204' is also configured to send a third chipset selection signal to the third memory cell 210' via the third chipset selection line 230' to select / deselect the third memory cell 210'. The host 204' is also used to send the nth chipset select signal to the nth memory cell 212' via the nth chipset select line 232' to select / deselect the nth memory cell 212'.

[0082] In the embodiments, the corresponding memory units in the first memory unit 206', second memory unit 208', third memory unit 210', ..., nth memory unit 212' can be used in an accelerator architecture, such as a PIM architecture, which will be described in more detail below. In the embodiments, firstly, memory unit 206' includes a data area 234' for storing data, a computation block 236' for performing computations, and a computation block 238' for performing computations. The data area 234' is also used to communicate / interact with computation blocks 236' and 238'. The second memory unit 208' includes a data area 240' for storing data, a computation block 242' for performing computations, and a computation block 244' for performing computations. The data area 240' is also used to communicate / interact with computation blocks 242' and 244'. The third memory unit 210' includes a data area 246' for storing data, a computation block 248' for performing computations, and a computation block 250' for performing computations. Data area 246' is also used for communication / interaction with computation blocks 248' and 250'. The nth memory unit 212' includes a data area 252' for storing data, a computation block 254' for performing computations, and a computation block 256' for performing computations. Data area 252' is also used for communication / interaction with computation blocks 254' and 256'. Although... Figure 2B The illustration shows a corresponding memory unit comprising a data area and two compute blocks; however, this disclosure is not limited thereto, and the corresponding memory unit may include other numbers of data areas and compute blocks. Additionally or optionally, the compute blocks include data processing units (DPUs). Utilizing the PIM structure, certain algorithms are processed by the compute blocks / DPUs within the memory unit, thereby eliminating some costly data movements and significantly improving the overall efficiency of the compute blocks.

[0083] In general, the data bus 214', command / address line 224', first chipset select line 226', second chipset select line 228', third chipset select line 230', ..., nth chipset select line 232' can be collectively referred to as interface 258'. In other words, interface 258' includes the data bus 214', command / address line 224', first chipset select line 226', second chipset select line 228', third chipset select line 230', ..., nth chipset select line 232'. Interface 258' is coupled between host 204' and memory system 202' / each memory cell. In embodiments, interface 258' can be any suitable memory interface, such as a DDR interface. In embodiments, interface 258' may further include other lines such as clock lines, response signal lines, control signal lines, etc.

[0084] As described above, traditional DDR interface-based memory modules are designed with two or more chipsets, and only one chipset can be selected at a given time. Therefore, all memory chips / cells within the same chipset are always selected simultaneously and operate in sync. However, different chips / cells within the same chipset cannot be selected, controlled, or accessed (read / write) individually. In the exemplary schematic 200' described above, each memory cell in the first memory cell 206', second memory cell 208', third memory cell 210', ..., nth memory cell 212' is a chipset and can be individually selected by the host 204' using chipset selection signals 218', 220', 222', and 224'. In this embodiment, only one memory cell can be selected at a given time.

[0085] The host 204' is also used to individually access corresponding memory cells in the first memory cell 206', the second memory cell 208', the third memory cell 210', ..., the nth memory cell 212' via the data bus 214 and the cell interfaces 216', 218', 220', ..., 222'. The functions of the data bus 214' and the cell interfaces 216', 218', 220', and 222' are as described above and will not be repeated here.

[0086] For example, host 204' is also used to access the first memory cell 206' via data bus 214' / cell interface 1_216' when the first memory cell 206' is selected to perform a read and / or write operation. In the embodiment, although data bus 214' is shared among n memory cells, the entire data width of data bus 214' is available during read and / or write operations of host 204' and the first memory cell 206' because only the first memory cell 206' is selected at a given time.

[0087] For example, host 204' is also used to access the second memory cell 208' via data bus 214' / cell interface 2_218' when the second memory cell 208' is selected to perform read and / or write operations. In the embodiment, although data bus 214' is shared among n memory cells, the entire data width of data bus 214' is available during read and / or write operations of host 204' and the second memory cell 208' because only the second memory cell 208' is selected at a given time.

[0088] For example, host 204' is also used to access the third memory cell 210' via data bus 214' / cell interface 3_220' when the third memory cell 210' is selected to perform read and / or write operations. In the embodiment, although data bus 214' is shared among n memory cells, the entire data width of data bus 214' is available during read and / or write operations of host 204' and the third memory cell 210' because only the third memory cell 210' is selected at a given time.

[0089] For example, host 204' is also used to access the nth memory cell 212' via data bus 214' / cell interface n_222' when the nth memory cell 212' is selected to perform a read and / or write operation. In the embodiment, although data bus 214' is shared among the n memory cells, the entire data width of data bus 214' is available during the read and / or write operation of host 204' and the nth memory cell 212' because only the nth memory cell 212' is selected at a given time.

[0090] Using the exemplary schematic diagram 200' above, each memory cell in the memory system 202' can be individually selected, controlled, and accessed (read / write) by the host 204'. This overcomes the problem in conventional DDR memory where chips / cells always operate in synchronized mode. Therefore, memory control is improved.

[0091] Although Figure 2B The illustration shows n memory cells in memory system 202', but this disclosure is not limited thereto. In embodiments, memory system 202' may include other components. For example, other components may include, but are not limited to, computing units, memory cells, accelerator units, control units, or any combination thereof. In embodiments, the exemplary schematic diagram 200' may be extended to control other components in memory system 202'.

[0092] Some features of the exemplary schematic diagrams 200 / 200' may include the following. In the embodiment, the number of cells in each memory system n of memory systems 202 and 202' is less than or equal to the number of chipsets in memory systems 202 / 202'. The number of chipset select signals is the same as the number of chipsets in memory systems 202 / 202'. If the memory system has m chipsets, where m is a positive integer, then there are m chipset select signals. Using the m chipset select signals, the host 204 / 204' can select at most m memory cells individually. Therefore, the number of cells n in each memory system n is less than or equal to the number of chipsets m.

[0093] In this embodiment, the maximum system bandwidth of memory system 202 / 202' is x GB / s, where x is a positive value. For example, for a DDR4-2400 memory system, x might be 19.2.

[0094] In this embodiment, the maximum cell bandwidth (BW) of a corresponding memory cell in memory system 202 / 202' is x GB / s. For example, if only one memory cell is selected at a given time, then the entire bandwidth of memory system 204 / 204' is available for the selected memory cell during the given time period. Therefore, the maximum cell bandwidth is x GB / s, which is the same as the maximum system bandwidth.

[0095] In an embodiment, in the exemplary schematic 200 / 200', the control of a single unit is based on a chipset selection signal.

[0096] In this embodiment, the exemplary schematic diagram 200 / 200' can be adapted to situations where individual memory cells require high peak bandwidth.

[0097] The above features of the exemplary schematic diagram 200 / 200' are for illustrative purposes and not for limiting the scope of this disclosure.

[0098] Figure 3A This is a schematic diagram 300 illustrating communication between an exemplary memory system 302 and a host 304. In embodiments, the memory system 302 can be any suitable type of memory architecture, such as a DDR-based multichannel memory architecture. In embodiments, the memory system 302 can include volatile memory, such as RAM, DRAM, cache, etc., and non-volatile memory, such as ROM, flash memory, micro hard disk drives, etc., or any combination thereof. In embodiments, the host can be, but is not limited to, a CPU, ASIC, GPU, FPGA, DSP, or any combination thereof.

[0099] refer to Figure 3A In this embodiment, memory system 302 includes n memory cells, which include first memory cell 306, second memory cell 308, third memory cell 310, ..., nth memory cell 312. As an example, but not a limitation, the total number of memory cells n in memory system 302 is a power of 2. In embodiments, the corresponding memory cells in first memory cell 306, second memory cell 308, third memory cell 310, ..., nth memory cell 312 can be configured as accelerator architectures, such as PIM architectures. Accelerator architectures are described above and will not be repeated here.

[0100] Data bus 314 includes bidirectional data channels for communication between each memory cell and host 304 to transmit data / signals, and the data channels / channels are referred to as cell interface 1_316, cell interface 2_318, cell interface 3_320, ..., cell interface n_322. In embodiments, the data width of data bus 314 can be any suitable width, for example, 64 bits. In embodiments, the data width of the corresponding cell interface in cell interface 1_316, cell interface 2_318, cell interface 3_320, ..., cell interface n_322 can be any suitable width, for example, 16 bits or similar. In embodiments, cell interface 1_316 is used to transmit data / signals between the first memory cell 306 and host 304. Cell interface 2_318 is used to transmit data / signals between the second memory cell 308 and host 304. Cell interface 3_320 is used to transmit data / signals between the third memory cell 310 and host 304. Unit interface n_322 is used to transfer data / signals between memory unit n_312 and host 304.

[0101] The corresponding memory units of the first memory unit 306, the second memory unit 308, the third memory unit 310, ..., the nth memory unit 312 are used to transmit data / signals to / from the host 304 via the data bus 314 and various unit interfaces 316, 318, 320, or 322. For example, the first memory unit 306 is used to transmit data / signals to / from the host 304 via unit interface 1_316. The second memory unit 308 is used to transmit data / signals to / from the host 304 via unit interface 2_318. The third memory unit 310 is used to transmit data / signals to / from the host 304 via unit interface 3_320. The nth memory unit 312 is used to transmit data / signals to / from the host 304 via unit interface n_322.

[0102] The corresponding memory units in the first memory unit 306, the second memory unit 308, the third memory unit 310, ..., the nth memory unit 312 are also used to receive command and address signals from the host 304 via the command / address line 324.

[0103] The first memory unit 306, the second memory unit 308, the third memory unit 310, ..., the nth memory unit 312 are also used to receive data mask (DM) signals from the host 304 via data mask signal lines 326. The data mask lines 326 include n lines, namely DM_1 320, DM_2 322, DM_3 324, ..., DM_n 326. For example, the first memory unit 306 is also used to receive a first data mask signal from the host 304 via DM_1 328. The second memory unit 308 is also used to receive a second data mask signal from the host 304 via DM_2 330. The third memory unit 310 is also used to receive a third data mask signal from the host 304 via DM_3 332. The nth memory unit 312 is also used to receive the nth data mask signal from the host 304 via DM_n 334.

[0104] The host 304 is used to transmit data / signals to / from corresponding memory cells in the first memory cell 306, the second memory cell 308, the third memory cell 310, ..., the nth memory cell 312. For example, the host 304 is also used to transmit data / signals to / from the first memory cell 306 via cell interface 1_316. The host is also used to transmit data / signals to / from the second memory cell 308 via cell interface 2_318. The host is also used to transmit data / signals to / from the third memory cell 310 via cell interface 3_320. The host is also used to transmit data / signals to / from the nth memory cell 312 via cell interface n_322.

[0105] The host 304 is also used to send command / address signals to the corresponding memory cells in the first memory cell 306, the second memory cell 308, the third memory cell 310, ..., the nth memory cell 312 via the command / address line 324.

[0106] The host 304 is also used to send data mask signals via data mask lines 326 to the first memory unit 306, the second memory unit 308, the third memory unit 310, ..., the nth memory unit 312 to select / deselect the corresponding memory unit. In embodiments, the host 304 is designed / customized to send multiple data mask signals via multiple data mask lines.

[0107] For example, host 304 is also used to send a first data mask signal to first memory unit 306 via DM_1 328 to select / deselect the first memory unit 306. The first data mask signal is used to mask / demask data bits transmitted on unit interface 1_316. When data bits transmitted through unit interface 1_316 are masked, data bits transmitted through unit interface 1_316 and received by the first memory unit 306 are ignored. In other words, the first memory unit 306 is not selected. When data bits transmitted through unit interface 1_316 are demasked, data bits transmitted through unit interface 1_316 are received by the first memory unit 306. In other words, the first memory unit 306 is selected.

[0108] For example, host 304 is also used to send a second data mask signal to second memory unit 308 via DM_2 330 to select / deselect second memory unit 308. The second data mask signal is used to mask / demask data bits transmitted on unit interface 2_318. When data bits transmitted through unit interface 2_318 are masked, data bits received by second memory unit 308 that are transmitted through unit interface 2_318 are ignored. In other words, second memory unit 308 is not selected. When data bits transmitted through unit interface 2_318 are demasked, data bits transmitted through unit interface 2_318 are received by second memory unit 308. In other words, second memory unit 308 is selected.

[0109] For example, host 304 is also used to send a third data mask signal to third memory unit 310 via DM_3 332 to select / deselect third memory unit 310. The third data mask signal is used to mask / demask data bits transmitted through unit interface 3_320. When data bits transmitted through unit interface 3_320 are masked, data bits received by third memory unit 310 that are transmitted through unit interface 3_320 are ignored. In other words, third memory unit 310 is not selected. When data bits transmitted through unit interface 3_320 are demasked, data bits transmitted through unit interface 3_320 and received by third memory unit 310 are ignored. In other words, third memory unit 310 is not selected.

[0110] For example, host 304 is also used to send the nth data mask signal to the nth memory cell 312 via DM_n 334 to select / deselect the nth memory cell 312. The nth data mask signal is used to mask / demask data bits transmitted through cell interface n_322. When data bits transmitted through cell interface n_322 are masked, data bits transmitted through cell interface n_322 and received by the nth memory cell 312 are ignored. In other words, the nth memory cell 312 is not selected. When data bits transmitted through cell interface n_322 are demasked, data bits transmitted through cell interface n_322 are received by the nth memory cell 312. In other words, the nth memory cell 312 is selected.

[0111] For more details on the correspondence between data mask signals and unit interfaces, please refer to [link / reference]. Figure 4 .

[0112] The host 304 is also used to access corresponding memory cells in the first memory cell 306, the second memory cell 308, the third memory cell 310, ..., the nth memory cell 312 to perform read and / or write operations. In this embodiment, a data mask signal is sent from the host 304 to the memory cells only during write operations to select / deselect one or more memory cells. During read operations, the host 304 does not need to send a data mask signal to select / deselect the corresponding memory cells because the host 304 discards unwanted portions of the data from the memory cells but retains the desired portions.

[0113] In general, the data bus 314, command / address line 324, and data mask line 326 can be referred to as interface 336. In other words, interface 336 includes command / address line 324 and data mask line 326. Interface 336 is coupled between host 304 and memory system 302 / each memory cell. In embodiments, interface 336 can be any suitable memory interface, such as a DDR interface. In embodiments, interface 336 may further include other lines such as clock lines, response signal lines, control signal lines, etc.

[0114] As mentioned above, in traditional DDR interface-based memory modules, all memory chips / cells within the same chipset are always selected simultaneously and operate in sync. However, different chips / cells cannot be selected, controlled, or accessed (read / write) individually.

[0115] Using the exemplary schematic diagram 300 described above, each memory cell in the memory system 302 can be individually selected, controlled, and accessed (read / write) by the host 304. Furthermore, more than one memory cell in the memory system 302 can be selected, controlled, and accessed (read / write) simultaneously. Therefore, the problem that chips / cells in conventional DDR memory always need to operate in synchronized mode is overcome. Thus, memory control is improved.

[0116] Although Figure 3A The illustration shows n memory cells in memory system 302, but this disclosure is not limited thereto. In embodiments, memory system 302 may include other components. For example, other components may include, but are not limited to, computing units, memory cells, accelerator units, control units, or any combination thereof. In embodiments, the exemplary schematic diagram 300 can be extended to control other components in memory system 302.

[0117] Figure 3B A schematic diagram 300' illustrates communication between an exemplary memory system 302' and a host 304'. In embodiments, the memory system 302' can be any suitable type of memory architecture, such as a DDR-based multichannel memory architecture. In embodiments, the memory system 302' can include volatile memory, such as RAM, DRAM, cache, etc., and non-volatile memory, such as ROM, flash memory, micro hard disk drive, etc., or any combination thereof. In embodiments, the host can be, but is not limited to, a CPU, ASIC, GPU, FPGA, DSP, or any combination thereof.

[0118] refer to Figure 3B The memory system 302' includes n memory cells, namely the first memory cell 306', the second memory cell 308', the third memory cell 310', ..., the nth memory cell 312'. As an example, but not limited to, the total number of memory cells n in the memory system 302' is a power of 2.

[0119] Data bus 314' may include bidirectional data paths / channels for communication between corresponding memory units and host 304' to transmit data / signals, and the data paths / channels refer to unit interfaces 1_316', 2_318', 3_320', ..., n_322'. In embodiments, the data width of data bus 314' can be any suitable width, for example, 64 bits. In embodiments, the data width of the corresponding unit interfaces of unit interfaces 1_316', 2_318', 3_320', ..., n_322' can be any suitable width, for example, 16 bits. In embodiments, unit interface 1'_316' is used to transmit data / signals between the first memory unit 306' and host 304'. Unit interface 2'_318' is used to transmit data / signals between the second memory unit 308' and host 304'. Unit interface 3'_320' is used to transfer data / signals between the third memory unit 310' and the host 304'. Unit interface n_322' is used to transfer data / signals between memory unit 312' and the host 304'.

[0120] The corresponding memory units of the first memory unit 306', the second memory unit 308', the third memory unit 310', ..., the nth memory unit 312' are used to transmit data / signals to / from the host 304' via the data bus 314' and unit interfaces 316, 318, 320, or 322. For example, the first memory unit 306' is used to transmit data / signals to / from the host 304' via unit interface 1_316'. The second memory unit 308' is used to transmit data / signals to / from the host 304' via unit interface 2_318'. The third memory unit 310' is used to transmit data / signals to / from the host 304' via unit interface 3_320'. The nth memory unit 312' is used to transmit data / signals to / from the host 304' via unit interface n_322'.

[0121] The corresponding memory units in the first memory unit 306', the second memory unit 308', the third memory unit 310', ..., the nth memory unit 312' are also used to receive command / address signals from the host 304' via the command / address line 324'.

[0122] The first memory unit 306', the second memory unit 308', the third memory unit 310', ..., the nth memory unit 312' are also used to receive data mask signals from the host 304' via data mask signal lines 326'. The data mask lines 326' may include n lines, namely DM_1 320', DM_2 322', DM_3 324', ..., DM_n 326'. For example, the first memory unit 306' is also used to receive a first data mask signal from the host 304' via DM_1 328'. The second memory unit 308' is also used to receive a second data mask signal from the host 304' via DM_2 330'. The third memory unit 310' is also used to receive a third data mask signal from the host 304' via DM_3 332'. The nth memory unit 312' is also used to receive the nth data mask signal from the host 304' via DM_n 334'.

[0123] The host 304' is used to transmit data / signals to / from corresponding memory cells in the first memory cell 306', second memory cell 308', third memory cell 310', ..., nth memory cell 312'. For example, the host 304' is also used to transmit data / signals to / from the first memory cell 306' via cell interface 1_316'. The host is also used to transmit data / signals to / from the second memory cell 308' via cell interface 2_318'. The host is also used to transmit data / signals to / from the third memory cell 310' via cell interface 3_320'. The host is also used to transmit data / signals to / from the nth memory cell 312' via cell interface n_322'.

[0124] The host 304' is also used to send command / address signals to the corresponding memory units in the first memory unit 306', the second memory unit 308', the third memory unit 310', ..., the nth memory unit 312' via command / address line 324'.

[0125] The host 304' is also used to send data mask signals via data mask lines 326' to the first memory unit 306', the second memory unit 308', the third memory unit 310', ..., the nth memory unit 312' to select / deselect the corresponding memory unit. In embodiments, the host 304' may be designed / customized to send multiple data mask signals via multiple data mask lines.

[0126] For example, host 304' is also used to send a first data mask signal to first memory unit 306' via DM_1 328' to select / deselect the first memory unit 306'. The first data mask signal is used to mask / demask data bits transmitted on unit interface 1_316'. When data bits transmitted through unit interface 1_316' are masked, data bits transmitted through unit interface 1_316' and received by first memory unit 306' are ignored. In other words, first memory unit 306' is not selected. When data bits transmitted through unit interface 1_316' are demasked, data bits transmitted through unit interface 1_316' can be received by first memory unit 306'. In other words, first memory unit 306' is selected.

[0127] For example, host 304' is also used to send a second data mask signal to second memory unit 308' via DM_2 330' to select / deselect second memory unit 308'. The second data mask signal is used to mask / demask data bits transmitted through unit interface 2_318'. When data bits transmitted through unit interface 2_318' are masked, data bits transmitted through unit interface 2_318' and received by second memory unit 308' are ignored. In other words, second memory unit 308' is not selected. When data bits transmitted through unit interface 2_318' are not masked, data bits transmitted through unit interface 2_318' are received by second memory unit 308'. In other words, second memory unit 308' is selected.

[0128] For example, host 304' is also used to send a third data mask signal to third memory unit 310' via DM_3 332' to select / deselect third memory unit 310'. The third data mask signal is used to mask / demask data bits transmitted through unit interface 3_320'. When data bits transmitted through unit interface 3_320' are masked, data bits transmitted through unit interface 3_320' and received by third memory unit 310' are ignored. In other words, third memory unit 310' is not selected. When data bits transmitted through unit interface 3_320' are demasked, data bits transmitted through unit interface 3_320' can be received by third memory unit 310'. In other words, third memory unit 310' is selected.

[0129] For example, host 304' is also used to send an nth data mask signal to the nth memory cell 312' via DM_n 334' to select / deselect the nth memory cell 312'. When data bits transmitted through cell interface n_322' are masked, data bits transmitted through cell interface n_322' and received by the nth memory cell 312' are ignored. In other words, the nth memory cell 312' is not selected. When data bits transmitted through cell interface n_322' are demasked, data bits transmitted through cell interface n_322' can be received by the nth memory cell 312'. In other words, the nth memory cell 312' is selected.

[0130] For more details on the correspondence between data mask signals and unit interfaces, please refer to [link / reference]. Figure 4 As shown.

[0131] The host 304' is also used to access corresponding memory cells in the first memory cell 306', second memory cell 308', third memory cell 310', ..., nth memory cell 312' to perform read and / or write operations. In an embodiment, a data mask signal is sent from the host 304' to the memory cells only during write operations to select / deselect one or more memory cells. During read operations, the host 304' does not need to send a data mask signal to select / deselect the corresponding memory cells because the host 304' can discard unwanted portions of the data read from the memory cells and retain the desired portions. Alternatively or additionally, the host 304' may send a data mask signal to select / deselect one or more memory cells during read and write operations.

[0132] In an embodiment, the corresponding memory units in the first memory unit 306', second memory unit 308', third memory unit 310', ..., nth memory unit 312' can be configured as an accelerator architecture, such as a PIM architecture. In an embodiment, the first memory unit 306' includes a data area 328' for storing data, a computation block 330' for performing computations, and a computation block 332' for performing computations. The data area 328' can communicate / interact with the computation blocks 330' and 332'. The second memory unit 308' includes a data area 334' for storing data, a computation block 336' for performing computations, and a computation block 338' for performing computations. The data area 334' can communicate / interact with the computation blocks 336' and 338'. The third memory unit 310' includes a data area 340' for storing data, a computation block 342' for performing computations, and a computation block 344' for performing computations. Data region 340' can communicate / interact with computation blocks 342' and 344'. The nth memory unit 312' includes a data region 346' for storing data, a computation block 348' for performing computations, and a computation block 350' for performing computations. Data region 346' can communicate / interact with computation blocks 348' and 350'. Although... Figure 3B The illustration shows a corresponding memory unit comprising one data area and two computation blocks, but this disclosure is not limited thereto, and the corresponding memory unit may include other numbers of data areas and computation blocks. Additionally or optionally, the computation blocks may include data processing units. Utilizing the PIM architecture, certain types of algorithms will be processed by the computation blocks / DPUs within the memory unit, rather than within the CPU, thereby eliminating some costly data movements and significantly improving the overall efficiency of computation.

[0133] In general, the data bus 314', command / address line 324', and data mask line 326' can be referred to as interface 352'. In other words, interface 352' may include the data bus 314', command / address line 324', and data mask line 326'. Interface 352' is coupled between host 304' and memory system 302' / each memory cell. In embodiments, interface 352' can be any suitable memory interface, such as a DDR interface. In embodiments, interface 352' may further include other lines, such as clock lines, response signal lines, control signal lines, etc.

[0134] As mentioned above, in traditional DDR interface-based memory modules, all memory chips / cells within the same chipset are always selected simultaneously and operate in sync. However, different chips / cells cannot be selected, controlled, or accessed (read / write) individually.

[0135] Using the exemplary schematic diagram 300' above, each memory cell in the memory system 302' can be individually selected, controlled, and accessed (read / write) by the host 304'. Furthermore, more than one memory cell in the memory system 302' can be selected, controlled, and accessed (read / write) simultaneously. Therefore, the problem of chips / cells always operating in synchronized mode, as in traditional DDR-based memories, is overcome. Thus, memory control is improved.

[0136] Although Figure 3B The illustration shows n memory cells in memory system 302', but this disclosure is not limited thereto. In embodiments, memory system 302' may include other components. For example, other components may include, but are not limited to, computing units, memory cells, accelerator units, control units, or any combination thereof. In embodiments, the exemplary schematic diagram 300' may be extended to control other components in memory system 302'.

[0137] Some features of the exemplary schematic diagram 300 / 300' may include the following. In an embodiment, the number of cells in each memory system n of the memory system 304 / 304' is less than or equal to the number of data mask signals. For example, the number of data mask signals is k, where k is a positive integer. Because the host 304 / 304' sends corresponding data mask signals to select / deselect corresponding memory cells, the host 304 / 304' can control at most k memory cells. The number of data mask signals can be calculated based on the smallest granularity of the data mask signals.

[0138] In this embodiment, the maximum system bandwidth of the memory system 302 / 302' is x GB / s, where x is a positive value. For example, for a DDR4-2400 memory system, x is 19.2.

[0139] In this embodiment, the maximum unit size (BW) of a corresponding memory cell in the memory system 302 / 302' is x / n GB / s. Because the entire data bus 314 is divided into n channels, the maximum unit size (BW) of each memory cell is x / n GB / s.

[0140] In this embodiment, the control of a single unit of the exemplary schematic diagram 300 / 300' is based on a data mask signal.

[0141] In an embodiment, the exemplary schematic diagram 300 / 300' can be adapted to situations where one or more memory cells to be selected and accessed change frequently, because the data mask signal can be generated dynamically and flexibly.

[0142] The above features of the exemplary schematic diagram 300 / 300' are for illustrative purposes and not for limiting the scope of this disclosure.

[0143] Figure 4 An example table showing the correspondence between data mask signals and unit interfaces is provided.

[0144] refer to Figure 4 Line 402 shows the data mask signal, and line 404 shows the cell interface.

[0145] refer to Figure 4 Row 406 shows the first data mask signal for data bits transmitted via unit interface_1 for masking / demasking. Row 408 shows the second data mask signal for data bits transmitted via unit interface_2 for masking / demasking. Column 410 shows the third data mask signal for data bits transmitted via unit interface_3 for masking / demasking. Column 412 shows the nth data mask signal for data bits transmitted via unit interface_n for masking / demasking.

[0146] Figure 5A A schematic diagram 500 illustrates communication between an exemplary memory system 502 and a host 504. In embodiments, the memory system 502 can be any suitable type of memory architecture, such as a DDR-based multichannel memory architecture. In embodiments, the memory system 502 can include volatile memory, such as RAM, DRAM, cache, etc., and non-volatile memory, such as ROM, flash memory, micro hard disk drives, etc., or any combination thereof. In embodiments, the host can be, but is not limited to, a CPU, ASIC, GPU, FPGA, DSP, or any combination thereof.

[0147] refer to Figure 5A In this system, memory system 502 includes n memory cells, namely, first memory cell 506, second memory cell 508, third memory cell 510, ..., nth memory cell 512. As an example, but not limited to, the total number of memory cells n in memory system 502 is a power of 2. In embodiments, the corresponding memory cells in the first memory cell 506, second memory cell 508, third memory cell 510, ..., nth memory cell 512 can be configured as an accelerator architecture, such as a PIM architecture. Accelerator architectures have been described above and will not be repeated here.

[0148] Data bus 522 may include bidirectional data paths / channels for communication between corresponding memory units and host 504 to transmit data / signals. These data paths / channels are referred to as unit interface 1_524, unit interface 2_526, unit interface 3_528, ..., unit interface n_530. In embodiments, the data width of data bus 522 can be any suitable width, for example, 64 bits. In embodiments, the data width of the corresponding unit interface among unit interfaces 1_524, unit interface 2_526, unit interface 3_528, ..., unit interface n_530 can be any suitable width, for example, 16 bits. In embodiments, unit interface 1_524 is used to transmit data / signals between the first memory unit 506 and host 504. Unit interface 2_526 is used to transmit data / signals between the second memory unit 508 and host 504. Unit interface 3_528 is used to transmit data / signals between the third memory unit 510 and host 504. The unit interface n_530 is used to transfer data / signals between the memory unit n_512 and the host 504.

[0149] The corresponding memory cells in the first memory cell 506, the second memory cell 508, the third memory cell 510, ..., the nth memory cell 512 may include independent cell I / O enable registers. For example, the first memory cell 506 includes a first cell I / O enable register 514. The second memory cell 508 includes a second cell I / O enable register 516. The third memory cell 510 includes a third cell I / O enable register 518. The nth memory cell 512 includes an nth cell I / O enable register 520.

[0150] The corresponding memory units in the first memory unit 506, second memory unit 508, third memory unit 510, ..., nth memory unit 512 are used to transmit data / signals to / from the host 504 via the data bus 522 / each unit interface 524, 526, 528 or 530. For example, the first memory unit 506 is used to transmit data / signals to the host 504 via unit interface 1_524. The second memory unit 508 is used to transmit data / signals to / from the host 504 via unit interface 2_526. The third memory unit 510 is used to transmit data / signals to / from the host 504 via unit interface 3_528. The nth memory unit 512 is used to transmit data / signals to / from the host 504 via unit interface n_530.

[0151] The corresponding memory units in the first memory unit 506, the second memory unit 508, the third memory unit 510, ..., the nth memory unit 512 are also used to receive command / address signals from the host 504 via the command / address line 532.

[0152] The respective storage units of the first storage unit 506, the second storage unit 508, the third storage unit 510, ..., and the nth storage unit 512 are also configured to receive command / address signals from the host 504 via command / address line 532.

[0153] The host 504 is used to transmit data / signals to / from the corresponding memory cells of the first memory cell 506, the second memory cell 508, the third memory cell 510, ..., the nth memory cell 512. For example, the host 504 is also used to transmit data / signals to / from the first memory cell 506 via cell interface 1_524. The host is also used to transmit data / signals to / from the second memory cell 508 via cell interface 2_526. The host is also used to transmit data / signals to / from the third memory cell 510 via cell interface 3_528. The host is also used to transmit data / signals to / from the nth memory cell 512 via cell interface n_530.

[0154] The host 504 is also used to send command / address signals to the corresponding memory cells in the first memory cell 506, the second memory cell 508, the third memory cell 510, ..., the nth memory cell 512 via the command / address line 532.

[0155] The host 504 is also configured to send unit I / O enable signals to corresponding memory cells in the first memory cell 506, the second memory cell 508, the third memory cell 510, ..., the nth memory cell 512 via the data bus 522 / each unit interface 524, 526, 528 and 530, so as to select / deselect the corresponding memory cell by setting the corresponding unit I / O enable register. For example, the host 504 is also configured to send a first unit I / O enable signal to the first memory cell 506 via unit interface 1_524, so as to select / deselect the first memory cell 506 by setting the first unit I / O enable register 514. The host 504 is also configured to send a second unit I / O enable signal to the second memory cell 508 via unit interface 2_526, so as to select / deselect the second memory cell 508 by setting the second unit I / O enable register 516. The host 504 is also configured to send a third unit I / O enable signal to the third memory unit 510 via unit interface 2_528, so as to select / deselect the second memory unit 510 by setting the second unit I / O enable register 518. The host 504 is also configured to send an nth unit I / O enable signal to the nth memory unit 512 via unit interface n_530, so as to select / deselect the nth memory unit 512 by setting the nth unit I / O enable register 520.

[0156] The host 504 is also used to access corresponding memory cells in the first memory cell 506, the second memory cell 508, the third memory cell 510, ..., the nth memory cell 512 to perform read and / or write operations when the corresponding memory cell is selected.

[0157] Each of the unit I / O enable registers 514 (first unit), 516 (second unit), 518 (third unit), ..., 520 (nth unit I / O enable register) temporarily enables / disables the I / O function of the corresponding memory unit in the first memory unit 506, second memory unit 508, third memory unit 510, ..., nth memory unit 512 in response to receiving the corresponding unit I / O enable signal. For example, the first unit I / O enable register 514 temporarily enables / disables the I / O function of the first memory unit 506 in response to receiving the first unit I / O enable signal. The second unit I / O enable register 516 temporarily enables / disables the I / O function of the second memory unit 508 in response to receiving the second unit I / O enable signal. The third unit I / O enable register 518 temporarily enables / disables the I / O function of the third memory unit 510 in response to receiving the third unit I / O enable signal. The nth unit I / O enable register 520 is used to temporarily enable / disable the I / O function of the nth memory unit 512 in response to receiving the nth unit I / O enable signal.

[0158] In an embodiment, if a memory cell in the memory system 502 is idle for a period of time, the host 504 may send a corresponding cell I / O enable signal to set the corresponding cell I / O enable register to disable the memory cell during that period. In an embodiment, setting the cell I / O enable register may result in additional overhead compared to not setting the corresponding cell I / O enable register, as setting the cell I / O enable register may cause latency, power consumption, etc.

[0159] In general, the data bus 522 and command / address lines 532 are collectively referred to as interface 534. In other words, interface 534 includes the data bus 522 and the command / address lines 532. Interface 534 is coupled between host 504 and memory system 502 / each memory cell. In embodiments, interface 534 can be any suitable memory interface, such as a DDR interface. In embodiments, interface 534 may further include other lines such as clock lines, response signal lines, control signal lines, etc.

[0160] As mentioned above, in traditional DDR interface-based memory modules, all memory chips / cells within the same chipset are always selected simultaneously and operate in sync. However, different chips / cells cannot be selected, controlled, or accessed (read / write) individually.

[0161] Using the exemplary schematic 500 described above, each memory cell in the memory system 504 can be individually selected, controlled, and accessed (read / write) by the host 504. Furthermore, more than one memory cell in the memory system 502 can be selected, controlled, and accessed (read / write) simultaneously. Therefore, the problem of chips / cells always operating in synchronized mode in conventional DDR memory is overcome. Thus, memory control is improved.

[0162] Although Figure 5A The present disclosure illustrates n memory cells in memory system 502, but is not limited thereto. In embodiments, memory system 502 may include other components. For example, other components may include, but are not limited to, computing units, memory cells, accelerator units, control units, or any combination thereof. In embodiments, exemplary schematic diagram 500 can be extended to control other components in memory system 502.

[0163] Figure 5B This is a schematic diagram 500' illustrating communication between an exemplary memory system 502' and a host 504'. In embodiments, the memory system 502' can be any suitable type of memory architecture, such as a DDR-based multichannel memory architecture. In embodiments, the memory system 502' can include volatile memory, such as RAM, DRAM, cache, etc., and non-volatile memory, such as ROM, flash memory, micro hard disk drive, etc., or any combination thereof. In embodiments, the host can be, but is not limited to, a CPU, ASIC, GPU, FPGA, DSP, or any combination thereof.

[0164] refer to Figure 5B The memory system 502' includes n memory cells, namely the first memory cell 506', the second memory cell 508', the third memory cell 510', ..., the nth memory cell 512'. As an example, but not limited to, the total number of memory cells n in the memory system 502' is a power of 2.

[0165] Data bus 522' may include bidirectional data paths / channels for communication between corresponding memory units and host 504' to transmit data / signals, and these data paths / channels are referred to as unit interface 1_524', unit interface 2_526', unit interface 3_528', ..., unit interface n_530'. In embodiments, the data width of data bus 522' can be any suitable width, for example, 64 bits. In embodiments, the data width of the corresponding unit interface among unit interface 1_524', unit interface 2_526', unit interface 3_528', ..., unit interface n_530' can be any suitable width, for example, 16 bits. In embodiments, unit interface 1_524' is used to transmit data / signals between first memory unit 506' and host 504'. Unit interface 2_526' is used to transmit data / signals between second memory unit 508' and host 504'. Unit interface 3_528' is used to transmit data / signals between third memory unit 510' and host 504'. The unit interface n_530' is used to transfer data / signals between the memory unit n_512' and the host 504'.

[0166] The corresponding memory cells in the first memory cell 506', second memory cell 508', third memory cell 510', ..., nth memory cell 512' may include corresponding cell I / O enable registers. For example, the first memory cell 506' includes a first cell I / O enable register 514'. The second memory cell 508' includes a second cell I / O enable register 516'. The third memory cell 510' includes a third cell I / O enable register 518'. The nth memory cell 512' includes an nth cell I / O enable register 520'.

[0167] The corresponding memory units in the first memory unit 506', second memory unit 508', third memory unit 510', ..., nth memory unit 512' are used to transmit data / signals to / from the host 504' via the data bus 522' / corresponding unit interfaces 524', 526', 528', or 530'. For example, the first memory unit 506' is used to transmit data / signals to / from the host 504' via unit interface 1_524'. The second memory unit 508' is used to transmit data / signals to / from the host 504' via unit interface 2_526'. The third memory unit 510' is used to transmit data / signals to / from the host 504' via unit interface 3_528'. The nth memory unit 512' is used to transmit data / signals to / from the host 504' via unit interface n_530'.

[0168] The corresponding memory units in the first memory unit 506', the second memory unit 508', the third memory unit 510', ..., the nth memory unit 512' are also used to receive command / address signals from the host 504' via the command / address line 532'.

[0169] The host 504' is used to transmit data / signals to / from corresponding memory units in the first memory unit 506', second memory unit 508', third memory unit 510', ..., nth memory unit 512'. For example, the host 504' is also used to transmit data / signals to / from the first memory unit 506' via unit interface 1_524'. The host 504' is also used to transmit data / signals to / from the second memory unit 508' via unit interface 2_526'. The host 504' is also used to transmit data / signals to / from the third memory unit 510' via unit interface 3_528'. The host 504' is also used to transmit data / signals to / from the nth memory unit 512' via unit interface n_530'.

[0170] The host 504' is also used to send command / address signals to the corresponding memory units in the first memory unit 506', the second memory unit 508', the third memory unit 510', ..., the nth memory unit 512' via command / address line 532'.

[0171] The host 504' is also used to send unit I / O enable signals to each memory cell in the first memory cell 506', second memory cell 508', third memory cell 510', ..., nth memory cell 512' via the data bus 522' / each unit interface 524', 526', 528' and 530', so as to select / deselect each memory cell by setting each unit I / O enable register. For example, the host 504' is also used to send a first unit I / O enable signal to the first memory cell 506' via unit interface 1_524', so as to select / deselect the first memory cell 506' by setting the first unit I / O enable register 514'. The host 504' is also used to send a second unit I / O enable signal to the second memory cell 508' via unit interface 2_526', so as to select / deselect the second memory cell 508' by setting the second unit I / O enable register 516'. The host 504' is also configured to send a third unit I / O enable signal to the third memory unit 510' via unit interface 3_528', so as to select / deselect the third memory unit 510' by setting the third unit I / O enable register 518'. The host 504' is also configured to send an nth unit I / O enable signal to the nth memory unit 512' via unit interface n_530', so as to select / deselect the nth memory unit 512' by setting the nth unit I / O enable register 520'.

[0172] The host 504' is also used to access the corresponding memory cells in the first memory cell 506', the second memory cell 508', the third memory cell 510', ..., the nth memory cell 512', to perform read and / or write operations when the corresponding memory cell is selected.

[0173] The I / O enable registers of the first unit I / O enable register 514', the second unit I / O enable register 516', the third unit I / O enable register 518', ..., the nth unit I / O enable register 520' are used to temporarily enable / disable the first memory unit 506', the second memory unit 508', the third memory unit 510', ..., the nth memory unit 512' in response to receiving the respective unit I / O enable signal.

[0174] For example, the first unit I / O enable register 514' is used to temporarily enable / disable the I / O function of the first memory unit 506' in response to receiving the first unit I / O enable signal. The second unit I / O enable register 516' is used to temporarily enable / disable the I / O function of the second memory unit 508' in response to receiving the second unit I / O enable signal. The third unit I / O enable register 518' is used to temporarily enable / disable the I / O function of the third memory unit 510' in response to receiving the third unit I / O enable signal. The nth unit I / O enable register 520' is used to temporarily enable / disable the I / O function of the nth memory unit 512' in response to receiving the nth unit I / O enable signal.

[0175] In an embodiment, if a memory cell in the memory system 502' is idle for a period of time, the host 504' may send a corresponding cell I / O enable signal to set the corresponding cell I / O enable register to disable the memory cell during that period. In an embodiment, setting the cell I / O enable register may result in additional overhead compared to not setting it, as setting the cell I / O enable register may cause latency, power consumption, etc.

[0176] The data bus 522' and command / address line 532' can be collectively referred to as interface 558'. In other words, interface 558' may include data bus 522' and command / address line 532'. Interface 558' is coupled between host 504 and memory system 502 / each memory cell. In embodiments, interface 558' may be any suitable memory interface, such as a DDR interface. In implementations, interface 558' may further include other lines such as clock lines, response signal lines, control signal lines, etc.

[0177] As mentioned above, in traditional DDR interface-based memory modules, all memory chips / cells within the same chipset are always selected simultaneously and operate in sync. However, different chips / cells cannot be selected, controlled, or accessed (read / write) individually.

[0178] Using the exemplary schematic diagram 500' described above, each memory cell in the memory system 502' can be individually selected, controlled, and accessed (read / write) by the host 504'. Furthermore, more than one memory cell in the memory system 502' can be selected, controlled, and accessed (read / write) simultaneously. Therefore, the problem of chips / cells always operating in synchronized mode in conventional DDR memory is overcome. Thus, memory control is improved.

[0179] Although Figure 5BThe illustration shows n memory cells in memory system 502', but this disclosure is not limited thereto. In embodiments, memory system 502' may include other components. For example, other components may include, but are not limited to, computing units, memory cells, accelerator units, control units, or any combination thereof. In embodiments, example schematic 500' may be extended to control other components in memory system 502'.

[0180] Some features of the exemplary schematic diagram 500 / 500' may include the following.

[0181] In this embodiment, the number of cells in each memory system n of memory system 502 / 502' is less than or equal to the data width of data bus 522 / 522'. For example, if the data width of data bus 522 / 522' is 64 bits, then data bus 522 / 522' may include a maximum of 64 channels. In this case, host 504 / 504' can send 64 cell enable signals to 64 memory cells via 64 channels respectively. Therefore, the number of cells in each memory system n is less than or equal to the data width of data bus 522 / 522'.

[0182] In this embodiment, the maximum system bandwidth of memory system 502 / 502' is x GB / s. For example, for a DDR4-2400 memory system, x is 19.2.

[0183] In this embodiment, the maximum cell size (BW) of the corresponding memory cell in the memory system 502 / 502' is x / n GB / s. Because the entire data bus 522 / 522' is divided into n channels, the maximum cell size (BW) of each memory cell is x / n GB / s.

[0184] In an embodiment, in an exemplary schematic 500 / 500', a single cell is controlled based on a cell I / O enable signal and a cell I / O enable register.

[0185] In the embodiments, the exemplary schematic diagram 500 / 500' can be applied to situations where one or more memory cells can be idle for a period of time.

[0186] The above features of the exemplary schematic diagram 500 / 500' are for illustrative purposes and not for limiting the scope of this disclosure.

[0187] Figure 6 Example table 600 provides the features of example option 1, example option 2, and example option 3. In an embodiment, example option 1 may include the features referenced above. Figure 2A and Figure 2B The described system 200 / 200', example option 2 may include the above reference. Figure 3Aand Figure 3B The described system 300 / 300', example option 3 may include the above reference. Figure 5A and Figure 5B The system described is 500 / 500'.

[0188] Line 602 shows the number of cells in each memory system in Example Option 1, Example Option 2, and Example Option 3.

[0189] Line 604 shows the maximum system bandwidth for example option 1, example option 2, and example option 3.

[0190] Line 606 shows the maximum unit BW for example option 1, example option 2, and example option 3.

[0191] Line 608 shows how to control individual units in Example Option 1, Example Option 2, and Example Option 3.

[0192] Line 610 shows the PCB routing / signal integrity for Example Option 1, Example Option 2, and Example Option 3.

[0193] Line 612 shows the additional overhead of example option 1, example option 2, and example option 3.

[0194] Line 614 explains the considerations for example option 1, example option 2, and example option 3.

[0195] Line 616 shows the application of example option 1, example option 2, and example option 3.

[0196] Column 618 illustrates the features of Example Option 1. For example, the number of cells per memory system n in Example Option 1 is less than or equal to the number of chipsets. The maximum system bandwidth of Example Option 1 is x GB / s, where x is a positive value. The maximum cell bandwidth of Example Option 1 is x GB / s. The method of controlling individual cells in Example Option 1 is based on chipset select signals. In embodiments, the methods of controlling individual cells in Example Option 1 include cell selection and row address. Taking Option 1 as an example, PCB routing / signal integrity is relatively difficult to design, but Option 1 has no additional overhead. Considerations for implementing Example Option 1 include routableness. Regarding applications, Example Option 1 can be suitable for situations where individual memory cells require high peak bandwidth.

[0197] Column 620 illustrates the characteristics of Example Option 2. For example, the number of cells per memory system n in Example Option 2 is less than or equal to the number of data mask signals. The calculation of the number of data mask signals can be as described above and will not be repeated here. The maximum system bandwidth of Example Option 2 is x GB / s. The maximum cell BW of Example Option 2 is x / n GB / s. Individual cells in Example Option 2 are controlled based on data mask signals. PCB routing / signal integrity is relatively straightforward for Example Option 2. Example Option 2 has no additional overhead. Considerations for implementing Example Option 2 include applying data mask signals only during write operations, and the smallest granularity of the data mask being adjusted by the DDR protocol. Regarding applications, Example Option 2 can be suitable for situations where one or more memory cells to be selected and accessed change frequently.

[0198] Column 622 illustrates the characteristics of Example Option 3. For example, the number of cells per memory system n in Example Option 3 is less than or equal to the data width of the data bus. The maximum system bandwidth of Example Option 3 is x GB / s. The maximum cell BW of Example Option 3 is x / n GB / s. Individual cells in Example Option 3 are controlled based on cell I / O enable signals and cell I / O enable resistors. PCB routing / signal integrity is relatively straightforward for Example Option 3. Example Option 3 described above incurs additional overhead. Considerations for implementing Example Option 3 include this additional overhead. Regarding applications, Example Option 3 may be suitable for situations where one or more memory cells are idle for a period of time.

[0199] The features described above in Exemplary Options 1, 2 and 3 are for illustrative purposes and not for limiting the scope of this disclosure.

[0200] In embodiments, different types of signals can be combined to control a memory system comprising multiple memory cells, enabling more complex control to adapt to different usage scenarios. For example, chipset select signals and data mask signals can be combined to form a hybrid control method. Chipset select signals and cell I / O enable register signals can be combined to form another hybrid control method. Data mask signals and cell I / O enable register signals can be combined to form yet another hybrid control method. The hybrid control methods described herein are for illustrative purposes and not for limitation. Furthermore, chipset select signals, data mask signals, and cell I / O enable register signals can be combined to form other hybrid control methods. Referring below to Figure 5… Figure 7 , Figure 8 and Figure 9 Describe more details.

[0201] Figure 7This is a schematic diagram 700 illustrating communication between an exemplary memory system 702 and a host 704. In the diagram, different types of signals, namely chipset select signals and data mask signals, are combined to form a hybrid control approach. In embodiments, the memory system 702 can be any suitable type of memory architecture, such as a DDR-based multichannel memory architecture. In embodiments, the memory system 702 can include volatile memory, such as RAM, DRAM, cache, etc., and non-volatile memory, such as ROM, flash memory, micro hard disk drives, etc., or any combination thereof. In embodiments, the host 704 can be, but is not limited to, a CPU, ASIC, GPU, FPGA, DSP, or any combination thereof.

[0202] refer to Figure 7 The memory system 702 includes a first memory cell group 706 and a second memory cell group 708. The first memory cell group 706 includes n memory cells, namely, first memory cell 710, second memory cell 712, third memory cell 714, ..., nth memory cell 716. The second memory cell group 708 includes m memory cells, namely, (n+1)th memory cell 718, (n+2)th memory cell 720, ..., (n+m)th memory cell 724. As an example and not a limitation, n and m are powers of 2. Although... Figure 7 Two groups of memory cells are shown, but this disclosure is not limited thereto. Memory system 702 may include more than two groups of memory cells.

[0203] In the embodiments, the corresponding memory units of the first memory unit 710, the second memory unit 712, the third memory unit 714, ..., the nth memory unit 716, the (n+1)th memory unit 718, the (n+2)th memory unit 720, ..., the (n+m)th memory unit 724 can be configured as accelerator architectures, such as PIM architectures. Accelerator architectures and PIM architectures have been described above and will not be repeated here.

[0204] The corresponding memory units in the first memory unit 710, the second memory unit 712, the third memory unit 714, ..., the nth memory unit 716, the (n+1)th memory unit 718, the (n+2)th memory unit 720, ..., the (n+m)th memory unit 724 are used to receive command / address signals from the host 704 via the command / address signal line 726.

[0205] The corresponding memory units in the first memory unit 710, the second memory unit 712, the third memory unit 714, ..., the nth memory unit 716, the (n+1)th memory unit 718, the (n+2)th memory unit 720, ..., the (n+m)th memory unit 724 are also used to transmit data / signals to / from the host 704 via the data bus 728.

[0206] In this embodiment, the data width of the data bus 714 can be any suitable width, for example, 64 bits. In this embodiment, the data bus 714 may include bidirectional data paths / channels for communication between the various memory cells and the host 704 to transmit data / signals, and these paths / channels are referred to as cell interface 1_730, cell interface 2_732, cell interface 3_734, ..., cell interface n_736, cell interface (n+1)_738, cell interface (n+2)_740, cell interface (n+3)_742, ..., cell interface (n+m)_744. The data width of each cell interface can be any suitable width, for example, 16 bits.

[0207] In this embodiment, unit interface 1_730 is used to transmit data / signals 10 between the first memory unit 710 and the host 704. Unit interface 2_712 is used to transmit data / signals between the first memory unit 714 and the host 704. Unit interface 3_734 is used to transmit data / signals between the first memory unit 714 and the host 704. Unit interface n_736 is used to transmit data / signals between the first memory unit 716 and the host 704. Unit interface (n+1)_738 is used to transmit data / signals between the first memory unit 718 and the host 704. Unit interface (n+2)_740 is used to transmit data / signals between the first memory unit 720 and the host 704. Unit interface (n+3)_742 is used to transmit data / signals between the first memory unit 722 and the host 704. Unit interface (n+m)_744 is used to transmit data / signals between the first memory unit 724 and the host 704.

[0208] In the first memory cell group 706, the corresponding memory cells of the first memory cell 710, the second memory cell 712, the third memory cell 714, ..., the nth memory cell 716 are also used to receive a first chipset selection signal from the host 704 via the first chipset selection line 746. In an embodiment, the first memory cell group is selected / not selected together by the first chipset selection signal.

[0209] In the second memory cell group 708, each memory cell of the (n+1)th memory cell 718, the (n+2)th memory cell 720, ..., the (n+m)th memory cell 724 is also used to receive a second chipset selection signal from the host 704 via the second chipset selection line 748. In an embodiment, the second memory cell group is selected / unselected together via the second chipset selection signal.

[0210] In the first memory cell group 706, each memory cell of the first memory cell 710, the second memory cell 712, the third memory cell 714, ... and the nth memory cell 716 is also used to receive a data mask signal from the host 704 via a first set of data mask lines 750. The first set of data mask lines 750 includes n lines, namely DM_1 752, DM_2 754, DM_3 756, ..., DM_n 758. For example, the first memory cell 710 is also used to receive a first data mask signal from the host 704 via DM_1 752. The second memory cell 712 is also used to receive a second data mask signal from the host 704 via DM_2 754. The third memory cell 714 is also used to receive a third data mask signal from the host 704 via DM_3 756. The nth memory cell 716 is also used to receive an nth data mask signal from the host 704 via DM_n 758.

[0211] In the second group 708, each memory cell of the (n+1)th memory cell 718, the (n+2)th memory cell 720, ..., the (n+m)th memory cell 724 is also used to receive a data mask signal from the host 704 via the second group of data mask lines 750. The second group of data mask lines 752 includes n lines, namely DM_(n+1) 762, DM_(n+2) 764, DM_(n+3) 766, ..., DM_(n+m) 768. For example, the (n+1)th memory cell 718 is also used to receive the (n+1)th data mask signal from the host 704 via DM_(n+1) 762. The (n+2)th memory cell 720 is also used to receive the (n+2)th data mask signal from the host 704 via DM_(n+2) 764. The (n+3)th memory unit 722 is also used to receive the (n+3)th data mask signal from the host 704 via DM_(n+3) 766. The (n+m)th memory unit 724 is also used to receive the (n+m)th data mask signal from the host 704 via DM_(n+m) 768.

[0212] The host 704 is used to transfer data / signals to / from the corresponding memory cell via the data bus 728 / the corresponding unit interface 730, 732, 734, 736, 738, 740, 742, or 744. The functions of the data bus 728 and the unit interfaces 730, 732, 734, 736, 738, 740, 742, and 744 have been described above and will not be repeated here.

[0213] The host 704 is also used to send command / address signals via command / address lines 726 to the corresponding memory units in the first memory unit 710, the second memory unit 712, the third memory unit 714, ..., the nth memory unit 716, the (n+1)th memory unit 718, the (n+2)th memory unit 720, ... and the (n+m)th memory unit 724.

[0214] The host 704 is also configured to send a first chipset select signal to each memory cell in the first memory cell group 706 via a first chipset select line 746. The host 704 is also configured to send a second chipset select signal to each memory cell in the second memory cell group 708 via a second chipset select line 748. Therefore, n memory cells in the first memory cell group 706 are selected together by the first chipset select signal, and m memory cells in the second memory cell group 708 are selected together by the second chipset select signal.

[0215] The host 704 is also used to send data mask signals to the first memory cell group 706 via a first set of data mask lines 750, and to send data mask signals to the second memory cell group 708 via a second set of data mask lines 760. In embodiments, the host 704 may be designed / customized to send multiple data mask signals via multiple data mask lines.

[0216] For example, host 704 is also used to send a first data mask signal to first memory unit 710 via DM_1 752. The first data mask signal is used to select / deselect the first memory unit 710. The first data mask signal is used to mask / demask data bits transmitted through unit interface 1_730. When data bits transmitted through unit interface 1_730 are masked, data bits received by first memory unit 710 and transmitted through unit interface 1_730 are ignored. In other words, first memory unit 710 is not selected. When data bits transmitted through unit interface 1_730 are demasked, data bits transmitted through unit interface 1_730 are received by first memory unit 710. In other words, first memory unit 710 is selected.

[0217] For example, host 704 is also used to send a second data mask signal to second memory unit 712 via DM_2 754 to select / deselect the second memory unit 712. The second data mask signal is used to mask / demask data bits transmitted through unit interface 2_732. When data bits transmitted through unit interface 2_732 are masked, data bits received by second memory unit 712 and transmitted through unit interface 2_732 are ignored. In other words, second memory unit 712 is not selected. When data bits transmitted through unit interface 2_732 are demasked, data bits transmitted through unit interface 2_732 are received by second memory unit 712. In other words, second memory unit 712 is selected.

[0218] For example, host 704 is also used to send a third data mask signal to third memory unit 714 via DM_3 756 to select / deselect third memory unit 714. The third data mask signal is used to mask / demask data bits transmitted through unit interface 3_734. When data bits transmitted through unit interface 3_734 are masked, data bits transmitted through unit interface 3_734 and received by third memory unit 714 are ignored. In other words, third memory unit 714 is not selected. When data bits transmitted through unit interface 3_734 are demasked, data bits transmitted through unit interface 3_734 are received by third memory unit 714. In other words, third memory unit 714 is selected.

[0219] For example, host 704 is also used to send an nth data mask signal to nth memory cell 716 via DM_n 758 to select / deselect the nth memory cell 716. The nth data mask signal is used to mask / demask the data bits transmitted on cell interface n_736. When data bits transmitted through cell interface n_736 are masked, data bits transmitted through cell interface n_736 and received by the nth memory cell 716 are ignored. In other words, the nth memory cell 716 is not selected. When data bits transmitted through cell interface n_736 are demasked, data bits transmitted through cell interface n_736 are received by the nth memory cell 716. In other words, the nth memory cell 716 is selected.

[0220] For example, host 704 is also used to send a (n+1)th data mask signal to the (n+1)th memory cell 718 via DM_(n+1) 762 to select / deselect the (n+1)th memory cell. The (n+1)th data mask signal is used to mask / demask the data bits transmitted through cell interface (n+1)_738. When the data bits transmitted through cell interface (n+1)_738 are masked, the data bits transmitted through cell interface (n+1)_738 and received by the (n+1)th memory cell 718 are ignored. In other words, the (n+1)th memory cell 718 is not selected. When the data bits transmitted through cell interface (n+1)_738 are demasked, the data bits transmitted through cell interface (n+1)_738 are received by the (n+1)th memory cell 718. In other words, the (n+1)th memory cell 718 is selected.

[0221] For example, host 704 is also used to send the (n+2)th data mask signal to the (n+2)th memory cell 720 via DM_(n+2) 764 to select / deselect the (n+2)th memory cell 720. The (n+2)th data mask signal is used to mask / demask the data bits transmitted through cell interface (n+2)_740. When the data bits transmitted through cell interface (n+2)_740 are masked, the data bits transmitted through cell interface (n+2)_740 and received by the (n+2)th memory cell 720 are ignored. In other words, the (n+2)th memory cell 720 is not selected. When the data bits transmitted through cell interface (n+2)_740 are demasked, the data bits transmitted through cell interface (n+2)_740 are received by the (n+2)th memory cell 720. In other words, the (n+2)th memory cell 720 is selected.

[0222] For example, host 704 is also used to send a (n+3)th data mask signal to the (n+3)th memory cell 722 via DM_(n+3) 766 to select / deselect the (n+3)th memory cell 722. The (n+3)th data mask signal is used to mask / demask data bits transmitted through cell interface (n+3)_742. When data bits transmitted through cell interface (n+3)_742 are masked, data bits received by the (n+3)th memory cell 722 and transmitted through cell interface (n+3)_742 are ignored. In other words, the (n+3)th memory cell 722 is not selected. When data bits transmitted through cell interface (n+3)_742 are demasked, data bits transmitted through cell interface (n+3)_742 are received by the (n+3)th memory cell 722. In other words, the (n+3)th memory cell 722 is selected.

[0223] For example, host 704 is also used to send the (n+m)th data mask signal to the (n+m)th memory cell 724 via DM_(n+m) 768 to select / deselect the (n+m)th memory cell 724. The (n+m)th data mask signal is used to mask / demask the data bits transmitted through cell interface (n+m)_744. When the data bits transmitted through cell interface (n+m)_744 are masked, the data bits transmitted through cell interface (n+m)_744 and received by the (n+m)th memory cell 724 are ignored. In other words, the (n+m)th memory cell 724 is not selected. When the data bits transmitted through cell interface (n+m)_744 are demasked, the data bits transmitted through cell interface (n+m)_744 are received by the (n+m)th memory cell 724. In other words, the (n+m)th memory cell 724 is selected.

[0224] The host 704 is also used to access each memory cell in the first memory cell 710, the second memory cell 712, the third memory cell 714, ..., the nth memory cell 716, the (n+1)th memory cell 718, the (n+2)th memory cell 720, ..., the (n+m)th memory cell 724 via the data bus 728 / each cell interface to perform read and / or write operations. The functions of the data bus 728 and the cell interfaces 730, 732, 734, 736, 738, 740, 742 and 744 are as described above and will not be repeated here.

[0225] In general, the data bus 728, command / address line 726, first chipset select line 746, second chipset select line 748, first data mask line 750, and second data mask line 760 are collectively referred to as interface 770. In other words, the interface includes the data bus 728, command / address line 726, first chipset select line 746, second chipset select line 748, first data mask line 750, and second data mask line 760. Interface 770 is coupled between host 704 and memory system 702 / each memory cell. In embodiments, interface 770 can be any suitable memory interface, such as a DDR interface. In embodiments, interface 770 may further include other lines such as clock lines, response signal lines, control signal lines, etc.

[0226] As mentioned above, in traditional DDR interface-based memory modules, all memory chips / cells within the same chipset are always selected simultaneously and operate in sync. However, different chips / cells cannot be selected, controlled, or accessed (read / write) individually.

[0227] For the exemplary schematic 700 described above, a group of memory cells can be selected via chipset signals, and one or more memory cells within the selected group can be further selected via data mask signals. Therefore, even if memory cells are arranged in groups, the host can precisely and flexibly select, control, and access (read / write) individual memory cells in the storage system 702. This overcomes the problem that traditional DDR-based memory chips / cells always operate in synchronized mode. Therefore, memory control is improved.

[0228] Figure 8 This is a schematic diagram 800 illustrating communication between an exemplary memory system 802 and a host 804. In the diagram, different types of signals, namely chipset select signals and cell I / O enable register signals, are combined to form a hybrid control approach. In embodiments, the memory system 802 can be any suitable type of memory architecture, such as a DDR-based multichannel memory architecture. In embodiments, the memory system 802 can include volatile memory, such as RAM, DRAM, cache, etc., and non-volatile memory, such as ROM, flash memory, micro hard disk drives, etc., or any combination thereof. In embodiments, the host 804 can be, but is not limited to, a CPU, ASIC, GPU, FPGA, DSP, or any combination thereof.

[0229] refer to Figure 8 The memory system 802 includes a first memory cell group 806 and a second memory cell group 808. The first memory cell group 806 includes n memory cells, namely, first memory cell 810, second memory cell 812, third memory cell 814, ..., nth memory cell 816. The second memory cell group 808 includes m memory cells, namely, (n+1)th memory cell 818, (n+2)th memory cell 820, ..., (n+m)th memory cell 824. As an example and not a limitation, n and m are powers of 2. Although... Figure 8 Two groups of memory cells are shown, but this disclosure is not limited thereto. Memory system 802 may include more than two groups of memory cells.

[0230] In the embodiments, the corresponding memory units of the first memory unit 810, the second memory unit 812, the third memory unit 814, ..., the nth memory unit 816, the (n+1)th memory unit 818, the (n+2)th memory unit 820, ..., the (n+m)th memory unit 824 can be configured as accelerator architectures, such as PIM architectures. Accelerator architectures and PIM architectures have been described above and will not be repeated here.

[0231] The corresponding memory units in the first memory unit 810, the second memory unit 812, the third memory unit 814, ..., the nth memory unit 816, the (n+1)th memory unit 818, the (n+2)th memory unit 820, ..., the (n+m)th memory unit 824 are used to receive command / address signals from the host 804 via the command / address signal line 826.

[0232] The corresponding memory units of the first memory unit 810, the second memory unit 812, the third memory unit 814, ..., the nth memory unit 816, the (n+1)th memory unit 818, the (n+2)th memory unit 820, ..., the (n+m)th memory unit 824 are also used to transmit data / signals from / to the host 804 via the data bus 828.

[0233] In this embodiment, the data width of the data bus 814 can be any suitable width, for example, 64 bits. In this embodiment, the data bus 814 can include bidirectional data paths / channels for communication between the various memory cells and the host 804 to transmit data / signals, and these paths / channels are referred to as cell interface 1_830, cell interface 2_832, cell interface 3_834, ..., cell interface n_836, cell interface (n+1)_838, cell interface (n+2)_840, cell interface (n+3)_842, ..., cell interface (n+m)_844. The data width of each cell interface can be any suitable width, for example, 16 bits.

[0234] In this embodiment, unit interface 1_830 is used to transmit data / signals 10 between the first memory unit 810 and the host 804. Unit interface 2_812 is used to transmit data / signals between the first memory unit 814 and the host 804. Unit interface 3_834 is used to transmit data / signals between the first memory unit 814 and the host 804. Unit interface n_836 is used to transmit data / signals between the first memory unit 816 and the host 804. Unit interface (n+1)_838 is used to transmit data / signals between the first memory unit 818 and the host 804. Unit interface (n+2)_840 is used to transmit data / signals between the first memory unit 820 and the host 804. Unit interface (n+3)_842 is used to transmit data / signals between the first memory unit 822 and the host 804. Unit interface (n+m)_844 is used to transmit data / signals between the first memory unit 824 and the host 804.

[0235] In the first memory cell group 806, the corresponding memory cells of the first memory cell 810, the second memory cell 812, the third memory cell 814, ..., the nth memory cell 816 are also used to receive a first chipset selection signal from the host 804 via the first chipset selection line 846. In an embodiment, the first memory cell group is selected / not selected together by the first chipset selection signal.

[0236] In the second memory cell group 808, each memory cell of the (n+1)th memory cell 818, the (n+2)th memory cell 820, ..., the (n+m)th memory cell 824 is also used to receive a second chipset selection signal from the host 804 via the second chipset selection line 848. In an embodiment, the second memory cell group is selected / unselected together via the second chipset selection signal.

[0237] The corresponding memory units of the first memory unit 810, the second memory unit 812, the third memory unit 814, ..., the nth memory unit 816, the (n+1)th memory unit 818, the (n+2)th memory unit 820, ..., the (n+m)th memory unit 824 may include corresponding unit I / O enable registers. For example, the first memory unit 810 includes a first unit I / O enable register 850. The second memory unit 812 includes a second unit I / O enable register 852. The third memory unit 814 includes a third unit I / O enable register 854. The nth memory unit 816 includes an nth unit I / O enable register 856. The (n+1)th memory unit 818 includes an (n+1)th unit I / O enable register 818. The (n+2)th memory unit 820 includes an (n+3)th unit I / O enable register 820. The (n+m)th memory cell 824 includes the (n+m)th cell I / O enable register 864.

[0238] The host 804 is used to transfer data / signals to / from various memory units via the data bus 828 / each unit interface 830, 832, 834, 836, 838, 840, 842, or 844. The functions of the data bus 828 and the respective unit interfaces 830, 832, 834, 836, 838, 840, 842, and 844 have been described above and will not be repeated here.

[0239] The host 804 is also used to send command / address signals via command / address lines 826 to the corresponding storage units in the first storage unit 810, the second storage unit 812, the third storage unit 814, ..., the nth storage unit 816, the (n+1)th storage unit 818, the (n+2)th storage unit 820, ..., the (n+m)th storage unit 824.

[0240] The host 804 is also configured to send a first chipset select signal to a corresponding memory cell in the first memory cell group 806 via a first chipset select line 846. The host 804 is also configured to send a second chipset select signal to a corresponding memory cell in the second memory cell group 808 via a second chipset select line 848. Therefore, n memory cells in the first memory cell group 806 are selected together by the first chipset select signal, and m memory cells in the second memory cell group 808 are selected together by the second chipset select signal.

[0241] The host 804 is also used to send unit I / O enable signals to the corresponding memory cells of the first memory cell 810, the second memory cell 812, the third memory cell 814, ..., the nth memory cell 816, the (n+1)th memory cell 818, the (n+2)th memory cell 820, ..., the (n+m)th memory cell 824 via the data bus 822 / the corresponding unit interface. The unit I / O enable signal selects / does not select the corresponding memory cell by setting the corresponding unit I / O enable register.

[0242] For example, host 804 is also configured to send a first unit I / O enable signal to the first memory unit 810 via unit interface 1_830, so as to select / deselect the first memory unit 810 by setting the first unit I / O enable register 850. Host 804 is also configured to send a second unit I / O enable signal to the second memory unit 812 via unit interface 2_832, so as to select / deselect the second memory unit 812 by setting the second unit I / O enable register 852. Host 804 is also configured to send a third unit I / O enable signal to the third memory unit 814 via unit interface 3_834, so as to select / deselect the third memory unit 814 by setting the third unit I / O enable register 854. Host 804 is also configured to send an nth unit I / O enable signal to the nth memory unit 816 via unit interface n_836, so as to select / deselect the nth memory unit 816 by setting the nth unit I / O enable register 856.

[0243] For example, host 804 is also configured to send a (n+1)th unit I / O enable signal to (n+1)th memory unit 818 via unit interface (n+1)_838, so as to select / deselect the (n+1)th memory unit 818 by setting the (n+1)th unit I / O enable register 858. Host 804 is also configured to send a (n+2)th unit I / O enable signal to (n+2)th memory unit 820 via unit interface (n+2)_840, so as to select / deselect the (n+2)th memory unit 820 by setting the (n+2)th unit I / O enable register 860. Host 804 is also configured to send a (n+3)th unit I / O enable signal to (n+3)th memory unit 822 via unit interface 3_842, so as to select / deselect the (n+3)th memory unit 822 by setting the (n+3)th unit I / O enable register 862. The host 804 is also used to send the (n+m)th unit I / O enable signal to the (n+m)th memory unit 824 via the unit interface (n+m)_836, so as to select / deselect the (n+m)th memory unit 824 by setting the (n+m)th unit I / O enable register 864.

[0244] The host 804 is also used to access the corresponding memory cells of the first memory cell 810, the second memory cell 812, the third memory cell 814, ..., the nth memory cell 816, the (n+1)th memory cell 818, the (n+2)th memory cell 820, ..., the (N+M)th memory cell 824 via the data bus 828 / the corresponding cell interface to perform read and / or write operations. The functions of the data bus 828 and the cell interfaces 830, 832, 834, 836, 838, 840, 842 and 844 are as described above and will not be repeated here.

[0245] In general, the data bus 828, command / address line 826, first chipset select line 846, and second chipset select line 848 are collectively referred to as interface 866. In other words, interface 866 includes the data bus 828, command / address line 826, first chipset select line 846, and second chipset select line 848. Interface 866 is coupled between host 804 and memory system 802 / each memory cell. In embodiments, interface 866 can be any suitable memory interface, such as a DDR interface. In embodiments, interface 866 may further include other lines such as clock lines, response signal lines, control signal lines, etc.

[0246] As mentioned above, in traditional DDR interface-based memory modules, all memory chips / cells within the same level are always selected simultaneously and operate synchronously. However, different chips / cells cannot be selected, controlled, or accessed (read / write) individually.

[0247] For the exemplary schematic 800 described above, a group of memory cells can be selected via chipset signals, and one or more memory cells within the selected group can be further selected via cell I / O enable signals. Therefore, even if memory cells are arranged in groups, the host 804 can precisely and flexibly select, control, and access (read / write) individual memory cells in the memory system 802. This overcomes the problem of chips / cells always operating in synchronized mode in conventional DDR memory. Therefore, memory control is improved.

[0248] Figure 9 This is a schematic diagram 900 illustrating communication between an exemplary memory system and a host. In the diagram, different types of signals, namely data mask signals and cell I / O enable register signals, are combined to form a hybrid control approach. In an embodiment, the memory system 902 can be any suitable type of memory architecture, such as a DDR-based multichannel memory architecture. In an embodiment, the memory system 902 can include volatile memory, such as RAM, DRAM, cache, etc., and non-volatile memory, such as ROM, flash memory, micro hard disk drives, etc., or any combination thereof. In an implementation, the host 904 can be, but is not limited to, a CPU, ASIC, GPU, FPGA, DSP, or any combination thereof.

[0249] refer to Figure 9 The memory system 902 includes a first memory cell group 906, a second memory cell group 908, a third memory cell group 910, and a fourth memory cell group 912. Although Figure 9 Four memory cell groups are shown, but this disclosure is not limited thereto. The memory system 902 may include other numbers of memory cell groups.

[0250] In an embodiment, the first memory cell group 906 includes a first memory cell 914 and a second memory cell 916. The second memory cell group 908 includes a third memory cell 918 and a fourth memory cell 920. The third memory cell group 910 includes a fifth memory cell 922 and a sixth memory cell 924. The fourth memory cell group 912 includes a seventh memory cell 926 and an eighth memory cell 928. Although Figure 9 The illustration shows that each group includes two memory cells, but this disclosure is not limited thereto. Each group may include more than two memory cells.

[0251] In the embodiments, the corresponding memory units in the first memory unit 914, the second memory unit 916, the third memory unit 918, the fourth memory unit 920, the fifth memory unit 922, the sixth memory unit 924, the seventh memory unit 926, and the eighth memory unit 928 can be configured as accelerator architectures, such as PIM architectures. Accelerator architectures and PIM architectures have been described above and will not be repeated here.

[0252] Each of the memory units 914, 916, 918, 920, 922, 924, 926, and 928 is used to transmit data / signals to / from the host 904 via the data bus 930.

[0253] In this embodiment, the data width of the data bus 930 can be any suitable width, for example, 64 bits. In this embodiment, the data bus 930 may include bidirectional data paths / channels for communication between the various memory cells and the host 904 to transmit data / signals, and these data paths / channels are referred to as cell interface 1_932, cell interface 2_934, cell interface 3_936, ..., cell interface 4_938, cell interface 5_940, cell interface 6_942, cell interface 7_944, and cell interface 8_946. The data width of each cell interface can be any suitable width, for example, 8 bits.

[0254] In this embodiment, unit interface 1_932 is used to transmit data / signals between the first memory unit 914 and the host 904. Unit interface 2_934 is used to transmit data / signals between the second memory unit 916 and the host 904. Unit interface 3_936 is used to transmit data / signals between the third memory unit 918 and the host 904. Unit interface 4_938 is used to transmit data / signals between the fourth memory unit 920 and the host 904. Unit interface 5_940 is used to transmit data / signals between the fifth memory unit 922 and the host 904. Unit interface 6_942 is used to transmit data / signals between the sixth memory unit 926 and the host 904. Unit interface 7_944 is used to transmit data / signals between the seventh memory unit 928 and the host 904. Unit interface 8_946 is used to transmit data / signals between the eighth memory unit 930 and the host 904.

[0255] Each of the memory units in the first memory unit 914, the second memory unit 916, the third memory unit 918, the fourth memory unit 920, the fifth memory unit 922, the sixth memory unit 924, the seventh memory unit 926, and the eighth memory unit 928 is also used to receive command / address signals from the host 904 via command / address signal line 948.

[0256] In the first memory cell group 906, each memory cell in the first memory cell 914 and the second memory cell 916 is also used to receive the first data mask signal via the data mask line DM_1 950.

[0257] In the second memory cell group 908, each memory cell in the third memory cell 918 and the fourth memory cell 920 is also used to receive the second data mask signal via the data mask line DM_2 952.

[0258] In the third memory cell group 910, each memory cell in the fifth memory cell 922 and the sixth memory cell 924 is also used to receive the third data mask signal via the data mask line DM_3 954.

[0259] In the fourth memory cell group 912, each memory cell in the seventh memory cell 926 and the eighth memory cell 928 is also used to receive the fourth data mask signal via the data mask line DM_4 956.

[0260] The corresponding memory units in the first memory unit 914, second memory unit 916, third memory unit 918, fourth memory unit 920, fifth memory unit 922, sixth memory unit 924, seventh memory unit 926, and eighth memory unit 928 may include corresponding unit I / O enable registers. For example, the first memory unit 914 includes a first unit I / O enable register 958. The second memory unit 916 includes a second unit I / O enable register 960. The third memory unit 918 includes a third unit I / O enable register 962. The fourth memory unit 920 includes a fourth unit I / O enable register 964. The fifth memory unit 922 includes a fifth unit I / O enable register 966. The sixth memory unit 924 includes a sixth unit I / O enable register 968. The seventh memory unit 926 includes a seventh unit I / O enable register 970. The eighth memory unit 928 includes an eighth unit I / O enable register 972.

[0261] The host 904 is used to transfer data / signals to / from the corresponding memory cells via the data bus 930 / the corresponding unit interfaces 932, 934, 936, 939, 940, 942, 944 or 946. The functions of the data bus 930 and the unit interfaces 932, 934, 936, 939, 940, 942, 944 and 946 have been described above and will not be repeated here.

[0262] The host 904 is also used to send command / address signals via command / address lines 948 to corresponding memory cells in the first memory cell 914, the second memory cell 916, the third memory cell 918, the fourth memory cell 920, the fifth memory cell 922, the sixth memory cell 924, the seventh memory cell 926 and the eighth memory cell 928.

[0263] In an embodiment, host 904 may be designed / customized to send multiple data mask signals via multiple data mask lines.

[0264] For example, host 904 is also used to send a first data mask signal to first memory cell group 906 via data mask line DM_1 950. Therefore, the first memory cell 914 and the second memory cell 916 are selected together by the first data mask signal. In an embodiment, the first data mask signal is used to mask / demask data bits transmitted through cell interface 1_932 and cell interface 2_934. When data bits transmitted through cell interface 1_932 and cell interface 2_934 are masked, data bits received by first memory cell 914 and second memory cell 916 and transmitted through cell interface 1_932 and cell interface 2_934 are ignored. In other words, first memory cell 914 and second memory cell 916 are not selected. When data bits transmitted through cell interface 1_932 and cell interface 2_934 are demasked, data bits transmitted through cell interface 1932 and cell interface 2_934 are received by first memory cell 914 and second memory cell 916. In other words, the first memory cell 914 and the second memory cell 916 are selected.

[0265] For example, host 904 is also used to send a second data mask signal to the second memory cell group 908 via data mask line DM_2 952. Therefore, the third memory cell 918 and the fourth memory cell 920 are selected together by the second data mask signal. In an embodiment, the second data mask signal is used to mask / demask data bits transmitted through unit interfaces 3_936 and 4_938. When data bits transmitted through unit interfaces 3_936 and 4_938 are masked, data bits transmitted through unit interfaces 3_936 and 4_938 and received by the third memory cell 918 and the fourth memory cell 920 are ignored. In other words, the third memory cell 918 and the fourth memory cell 920 are not selected. When data bits transmitted through unit interfaces 3_936 and 4_938 are demasked, data bits transmitted through unit interfaces 3_936 and 4_938 are received by the third memory cell 918 and the fourth memory cell 920. In other words, the third memory cell 918 and the fourth memory cell 920 are selected.

[0266] For example, host 904 is also used to send a third data mask signal to the third memory cell group 910 via data mask line DM_3 954. Therefore, the fifth memory cell 922 and the sixth memory cell 924 are selected together by the third data mask signal. In an embodiment, the third data mask signal is used to mask / demask data bits transmitted through cell interfaces 5_940 and 6_942. When data bits transmitted through cell interfaces 5_940 and 6_942 are masked, data bits transmitted through cell interfaces 5_940 and 6_942 and received by the fifth memory cell 922 and the sixth memory cell 924 are ignored. In other words, the fifth memory cell 922 and the sixth memory cell 924 are not selected. When data bits transmitted through cell interfaces 5_940 and 6_942 are demasked, data bits transmitted through cell interfaces 5_940 and 6_942 are received by the fifth memory cell 922 and the sixth memory cell 924. In other words, the fifth memory unit 922 and the sixth memory unit 924 were selected.

[0267] For example, host 904 is also used to send a fourth data mask signal to the fourth memory cell group 912 via data mask line DM_4 956. Therefore, the seventh memory cell 926 and the eighth memory cell 928 are selected together by the fourth data mask signal. In this embodiment, the fourth data mask signal is used to mask / demask data bits transmitted through cell interfaces 7_944 and 8_946. When data bits transmitted through cell interfaces 7_944 and 8_946 are masked, data bits transmitted through cell interfaces 7_944 and 8_946 and received by the seventh memory cell 926 and the eighth memory cell 928 are ignored. In other words, the seventh memory cell 926 and the eighth memory cell 928 are not selected. When data bits transmitted through cell interfaces 7_944 and 8_946 are demasked, data bits transmitted through cell interfaces 7_944 and 8_946 are received by the seventh memory cell 926 and the eighth memory cell 928. In other words, the seventh memory cell 926 and the eighth memory cell 928 are selected.

[0268] For example, the host 904 is also used to send cell I / O enable signals to each memory cell via the data bus 930 / each cell interface, so as to individually select / deselect each memory cell by setting the each cell I / O enable register.

[0269] For example, host 904 is also configured to send a first unit I / O enable signal to first memory unit 914 via unit interface 1_932, so as to select / deselect the first memory unit 914 by setting the first unit I / O enable register 958. Host 904 is also configured to send a second unit I / O enable signal to second memory unit 916 via unit interface 2_934, so as to select / deselect the second memory unit 916 by setting the second unit I / O enable register 960.

[0270] The host 904 is also configured to send a third unit I / O enable signal to the third memory unit 918 via unit interface 3_936, so as to select / deselect the third memory unit 918 by setting the third unit I / O enable register 962. The host 904 is also configured to send a fourth unit I / O enable signal to the fourth memory unit 920 via unit interface 4_938, so as to select / deselect the fourth memory unit 920 by setting the fourth unit I / O enable register 964. The host 904 is also configured to send a fifth unit I / O enable signal to the fifth memory unit 922 via unit interface 5_940, so as to select / deselect the fifth memory unit 922 by setting the fifth unit I / O enable register 966. The host 904 is also configured to send a sixth unit I / O enable signal to the sixth memory unit 924 via unit interface 6_942, so as to select / deselect the sixth memory unit 924 by setting the sixth unit I / O enable register 968. The host 904 is also configured to send a seventh unit I / O enable signal to the seventh memory unit 926 via unit interface 7_944, so as to select / deselect the seventh memory unit 926 by setting the seventh unit I / O enable register 970. The host 904 is also configured to send an eighth unit I / O enable signal to the eighth memory unit 928 via unit interface 8_946, so as to select / deselect the eighth memory unit 928 by setting the eighth unit I / O enable register 972.

[0271] The host 904 is also used to access the memory cells of the first memory cell 914, the second memory cell 916, the third memory cell 918, the fourth memory cell 920, the fifth memory cell 922, the sixth memory cell 924, the seventh memory cell 926, and the eighth memory cell 928 via the data bus 930 / each cell interface to perform read and / or write operations. The functions of the data bus 930 and the cell interfaces 932, 934, 936, 939, 940, 942, 944, and 946 have been described above and will not be repeated here.

[0272] In general, the data bus 930, command / address line 948, and data mask lines DM_1 950, DM_2 952, DM_3 954, and DM_4 956 are referred to as interface 974. In other words, interface 974 includes the data bus 930, command / address line 948, and data mask lines DM_1 950, DM_2 952, DM_3 954, and DM_4 956. Interface 974 is coupled between host 904 and memory system 902 / each memory cell. In embodiments, interface 974 can be any suitable memory interface, such as a DDR interface. In implementations, interface 974 may also include other lines such as clock lines, response signal lines, control signal lines, etc.

[0273] As mentioned above, traditional DDR interface-based memory modules are designed with two or more chipsets, and only one chipset can be selected at a time. Therefore, all memory chips / cells within the same chipset are always selected simultaneously and operate in sync. However, different chips / cells within the same chipset cannot be selected individually.

[0274] For the exemplary schematic 900 described above, one or more memory cell groups can be selected via a data mask signal, and one or more memory cells within the selected group can be further selected via a cell I / O enable signal. Therefore, even if memory cells are arranged in groups, the host 904 can precisely and flexibly select, control, and access (read / write) individual memory cells in the memory system 902. This overcomes the problem of chips / cells always operating in synchronized mode in conventional DDR memory. Therefore, memory control is improved.

[0275] refer to Figure 7 , Figure 8 and Figure 9 As shown, different types of signals can be combined to control memory systems, enabling more complex control to adapt to different application scenarios. However, Figure 7 , Figure 8 and Figure 9 The arrangement shown is for illustration and not limitation. Other elements can be added, and other types of signals can be combined with chipset select signals, data mask signals, and cell I / O enable register signals. Other combinations can be derived based on the teachings of this disclosure.

[0276] Figure 10 An exemplary process 1000 for memory control is shown.

[0277] refer to Figure 10 In block 1002, the host selects one or more memory cells from a plurality of memory cells in the storage system by sending one or more signals to the storage system. In an embodiment, the respective memory cells among the plurality of memory cells are configured as an accelerator architecture, such as a PIM architecture. Exemplary accelerator architectures have been described above and will not be repeated here.

[0278] In an embodiment, the host may send one or more signals, including one or more chipset select signals. In this embodiment, a corresponding memory cell among a plurality of memory cells is selected each time by a corresponding chipset select signal among the one or more chipset select signals. Details of the one or more chipset select signals have been described above and will not be repeated here.

[0279] In one embodiment, the host may send one or more signals, including one or more data mask signals. In another embodiment, the one or more data mask signals are sent by the host during a write operation. In yet another embodiment, the host may send the one or more data mask signals to multiple memory cells. Details of the one or more data mask signals are as described above and will not be repeated here.

[0280] In an embodiment, the host may send one or more signals, including one or more unit I / O enable signals. In an embodiment, each memory cell among the plurality of memory cells includes a corresponding unit I / O enable register. In an embodiment, each unit I / O enable register is used to enable / disable the I / O function of the respective memory cell. Details of the one or more unit I / O enable signals are as described above and will not be repeated here.

[0281] In block 1004, the host accesses one or more memory cells.

[0282] As mentioned above, in traditional DDR interface-based memory modules, all memory chips / cells within the same chipset are always selected simultaneously and operate in sync. However, different chips / cells cannot be selected, controlled, or accessed (read / write) individually.

[0283] Through the example process 1000 described above, the host can use one or more signals to individually select, control, and access (read / write) the corresponding memory cell. Therefore, the problem of chips / cells always operating synchronously in traditional DDR-based memories can be overcome. This improves memory control.

[0284] In the exemplary process 1000 described above, the host can use one or more signals to individually select, control, and access (read / write) the corresponding memory cell. This overcomes the problem that traditional DDR-based memory chips / cells always operate in synchronized mode. Therefore, memory control is improved.

[0285] The example procedure 1000 is for illustrative purposes, but this disclosure is not limited thereto. The individual blocks in the example procedure 1000 may be omitted, combined, or executed once, twice, or more. Furthermore, additional blocks may be added to the example procedure 1000.

[0286] Figure 11 An example procedure 1100 for memory control is shown.

[0287] refer to Figure 11In block 1102, the host selects a corresponding memory cell group from a plurality of memory cell groups in the memory system by sending one or more signals of the first type to the memory system. The corresponding group comprises a plurality of memory cells. In an embodiment, the corresponding memory cell is configured as an accelerator architecture, such as a PIM architecture. Examples of accelerator architectures have been described above and will not be repeated here.

[0288] In one embodiment, the host may send one or more chipset select signals as one or more signals of the first type. In another embodiment, the host may send one or more data mask signals as one or more signals of the first type. The details of the chipset select signals and data mask signals are as described above and will not be repeated here.

[0289] In block 1104, the host selects one memory cell from a plurality of memory cells in a respective cell group by sending one or more signals of the second type to the respective cell group.

[0290] In one embodiment, the host may send one or more data mask signals as one or more second-type signals. In another embodiment, the host may send one or more unit I / O enable signals as one or more second-type signals. The details of the data mask signals and unit I / O enable signals are as described above and will not be repeated here.

[0291] In block 1106, the host accesses the corresponding memory unit.

[0292] As mentioned above, traditional DDR interface-based memory modules are designed with two or more chipsets, and only one chipset can be selected at a time. Therefore, all memory chips / cells within the same chipset are always selected simultaneously and operate in sync. However, different chips / cells within the same chipset cannot be selected, controlled, or accessed (read / write) independently.

[0293] For the exemplary process 1100 described above, different types of signals can be combined to control the memory system, enabling more complex control to adapt to different usage scenarios. For example, chipset select signals and data mask signals can be combined to form a hybrid control method. The host selects a group of memory cells using chipset signals, and the host individually selects each memory cell within the selected group using cell I / O enable signals. For example, chipset select signals and cell I / O enable register signals can be combined to form another hybrid control method. The host selects a group of memory cells using chipset signals, and the host individually selects each memory cell within the selected group using cell I / O enable signals. As another example, data mask signals and cell I / O enable register signals can be combined to form another hybrid control method. The host selects a group of memory cells using data mask signals, and the host individually selects each memory cell within the selected group using cell I / O enable signals. (See above reference) Figure 7 , Figure 8 and Figure 9 More details have been described. Therefore, even if memory cells are arranged in groups, the host can accurately and flexibly select, control, and access (read / write) individual memory cells in the memory system. This overcomes the problem of chips / cells always operating in synchronized mode in traditional DDR memory. Therefore, memory control is improved.

[0294] Example procedure 1100 is for illustrative purposes, but this disclosure is not limited thereto. Blocks in example procedure 1100 may be omitted, combined, or executed once, twice, or more. In addition, additional blocks may be added to example procedure 1100.

[0295] As defined below, some or all of the operations of the methods described above can be performed by executing computer-readable instructions stored on a computer-readable storage medium. The term "computer-readable instructions" as used in the description and claims includes routines, applications, application modules, program modules, programs, components, data structures, algorithms, etc. Computer-readable instructions can be implemented on various system configurations, including single-processor or multi-processor systems, minicomputers, mainframe computers, personal computers, handheld computing devices, microprocessor-based programmable consumer electronics devices, combinations thereof, etc.

[0296] Computer-readable storage media may include volatile memory (e.g., random access memory (RAM)) and / or non-volatile memory (e.g., read-only memory (ROM), flash memory, etc.). Computer-readable storage media may also include additional removable and / or non-removable storage, including but not limited to flash memory, magnetic storage, optical storage, and / or magnetic tape storage, which can provide non-volatile storage of computer-readable instructions, data structures, program modules, etc.

[0297] Non-transient computer-readable storage media are examples of computer-readable media. Computer-readable media include at least two types of computer-readable media: computer-readable storage media and communication media. Computer-readable storage media include volatile and non-volatile, removable and non-removable media for storing information such as computer-readable instructions, data structures, program modules, or other data, using any process or technological implementation. Computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), other types of random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, optical disc read-only memory (CDROM), digital versatile disc (DVD) or other optical storage, cassette tape, magnetic tape, disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible to computing devices. Conversely, communication media may embody computer-readable instructions, data structures, program modules, or other data in modulated data signals (e.g., carrier waves) or other transmission mechanisms. As defined herein, computer-readable storage media do not include communication media.

[0298] Computer-readable instructions stored on one or more non-transitory computer-readable storage media, when executed by one or more processors, can perform the operations described above with reference to the accompanying drawings. Typically, computer-readable instructions include routines, programs, objects, components, data structures, etc., that perform a specific function or implement a specific abstract data type. The order in which the operations are described should not be construed as limiting, and any number of described operations can be implemented in any order and / or in parallel.

[0299] Sample

[0300] 1. A memory architecture coupled to a host external to the memory architecture, the memory architecture comprising:

[0301] Multiple memory units, wherein corresponding memory units among the multiple memory units are configured as a PIM architecture; and

[0302] An interface, coupled between the plurality of memory units and the host, the interface including multiple lines, the interface being used to receive one or more signals from the host via the multiple lines;

[0303] The respective memory unit among the plurality of memory units is coupled to the respective line among the plurality of lines, and the respective memory unit is also used to receive the respective signal among the one or more signals via the interface so that it can be individually selected by the host.

[0304] 2. The memory architecture according to claim 1, wherein the one or more signals received by the interface include one or more chipset selection signals.

[0305] 3. The memory architecture according to claim 2, wherein a corresponding memory unit among the plurality of memory units is further configured to receive a corresponding chipset selection signal among the one or more chipset selection signals via a corresponding line among the plurality of lines of the interface.

[0306] 4. The memory architecture according to claim 1, wherein the one or more signals received by the interface include one or more data mask signals.

[0307] 5. The memory architecture according to claim 4, wherein a corresponding memory cell among the plurality of memory cells is further configured to receive a corresponding data mask signal among the one or more data mask signals via a corresponding line among the plurality of lines of the interface.

[0308] 6. The memory architecture according to claim 1, wherein the one or more signals received by the interface include one or more cell I / O enable signals.

[0309] 7. The memory architecture according to claim 6, wherein each memory cell in the plurality of memory cells includes a corresponding cell I / O enable register, the corresponding cell I / O enable register being used to enable / disable the I / O function of the corresponding memory cell.

[0310] 8. The memory architecture according to claim 6, wherein a corresponding memory cell among the plurality of memory cells is further configured to receive a corresponding cell I / O enable signal via the interface.

[0311] 9. The memory architecture according to claim 1, wherein the PIM architecture comprises:

[0312] Data area, used to store data; and

[0313] A computation block is used to perform computations.

[0314] 10. A method comprising:

[0315] One or more memory cells from a plurality of memory cells in a storage system are individually selected by sending one or more signals to the storage system, wherein the respective memory cells among the plurality of memory cells are configured in a PIM architecture; and

[0316] Access the one or more memory units.

[0317] 11. The method of claim 10, wherein sending the one or more signals includes sending one or more chipset select signals.

[0318] 12. The method of claim 11, wherein selecting a specific memory cell individually comprises selecting a specific memory cell individually using a specific chipset selection signal among the one or more chipset selection signals.

[0319] 13. The method of claim 10, wherein sending the one or more signals includes sending one or more data mask signals.

[0320] 14. The method of claim 13, wherein selecting a corresponding memory cell individually comprises selecting the corresponding memory cell individually using a corresponding data mask signal from the one or more data mask signals.

[0321] 15. The method of claim 10, wherein sending the one or more signals includes sending one or more unit I / O enable signals.

[0322] 16. The method according to claim 15, wherein each of the plurality of memory cells includes a corresponding cell I / O enable register, the corresponding cell I / O enable register being used to enable / disable the I / O function of the corresponding memory cell.

[0323] 17. The method of claim 15, wherein individually selecting a corresponding memory cell comprises individually selecting the corresponding memory cell using a corresponding cell I / O enable signal among the one or more cell I / O enable signals.

[0324] 18. A system comprising:

[0325] A memory architecture coupled to a host external to the memory architecture, the memory architecture comprising:

[0326] Multiple memory units, wherein corresponding memory units among the multiple memory units are configured as a PIM architecture; and

[0327] An interface, coupled between the plurality of memory units and the host, the interface including multiple lines, the interface being used to receive one or more signals from the host via the multiple lines;

[0328] The respective memory unit among the plurality of memory units is coupled to the respective line among the plurality of lines, and the respective memory unit is also used to receive the respective signal among the one or more signals via the interface so that it can be individually selected by the host.

[0329] The host is configured to send one or more signals to the memory architecture via the interface and access the corresponding memory cells.

[0330] 19. The system of claim 18, wherein the one or more signals received by the interface include one or more chipset selection signals.

[0331] 20. The system according to claim 19, wherein a corresponding memory unit among the plurality of memory units is further configured to receive a corresponding chipset selection signal among the one or more chipset selection signals via a corresponding line among the plurality of lines of the interface.

[0332] 21. The system of claim 18, wherein the one or more signals received by the interface include one or more data mask signals.

[0333] 22. The system according to claim 21, wherein a corresponding memory unit among the plurality of memory units is further configured to receive a corresponding data mask signal among the one or more data mask signals via a corresponding line among the plurality of lines of the interface.

[0334] 23. The system of claim 18, wherein the one or more signals received by the interface include one or more unit I / O enable signals.

[0335] 24. The system according to claim 23, wherein each of the plurality of memory cells includes a corresponding unit I / O enable register, the corresponding unit I / O enable register being used to enable / disable the I / O function of the corresponding memory cell.

[0336] 25. The system according to claim 23, wherein a corresponding memory unit among the plurality of memory units is further configured to receive a corresponding unit I / O enable signal via the interface.

[0337] 26. The system according to claim 18, wherein the PIM architecture comprises:

[0338] Data area, used to store data; and

[0339] A computation block is used to perform computations.

[0340] 27. A memory architecture coupled to a host external to the memory architecture, the memory architecture comprising:

[0341] Multiple memory cell groups, each memory cell group comprising multiple memory cells, and each memory cell among the multiple memory cells being configured as a PIM architecture; and

[0342] An interface, coupled between the memory architecture and the host, the interface comprising multiple lines, the interface being used to receive one or more signals of a first type and one or more signals of a second type from the host via the multiple lines;

[0343] The corresponding memory cell group among the plurality of memory cell groups is selected by the host using a signal of the corresponding first type among the one or more first type signals;

[0344] The respective memory unit among the plurality of memory units is coupled to the respective line among the plurality of lines, and the respective memory unit among the plurality of memory units is also used to receive the respective second type of signal among the one or more second type signals via the interface, so that it can be individually selected by the host.

[0345] 28. The memory architecture of claim 27, wherein the one or more signals of the first type received by the interface include one or more chipset select signals.

[0346] 29. The memory architecture of claim 28, wherein the one or more second-type signals received by the interface include one or more data mask signals.

[0347] 30. The memory architecture according to claim 29, wherein a corresponding memory cell among the plurality of memory cells is further configured to receive a corresponding data mask signal among the one or more data mask signals via a corresponding line among the plurality of lines of the interface.

[0348] 31. The memory architecture of claim 28, wherein the one or more second-type signals received by the interface include one or more cell I / O enable signals.

[0349] 32. The memory architecture according to claim 31, wherein a corresponding memory cell among the plurality of memory cells is further configured to receive a corresponding cell I / O enable signal among the one or more cell I / O enable signals via the interface.

[0350] 33. The memory architecture according to claim 32, wherein each memory cell in the plurality of memory cells includes a corresponding cell I / O enable register, the corresponding cell I / O enable register being used to enable / disable the I / O function of the corresponding memory cell.

[0351] 34. The memory architecture of claim 27, wherein the one or more signals of the first type received by the interface include one or more data mask signals.

[0352] 35. A system comprising:

[0353] The memory architecture is coupled to a host outside the memory architecture.

[0354] The memory architecture includes:

[0355] A multi-memory unit group, wherein the corresponding memory unit group includes multiple memory units, and the corresponding memory units among the multiple memory units are configured as a PIM architecture;

[0356] and an interface coupled between the memory architecture and the host, the interface comprising multiple lines for receiving one or more first-type signals and one or more second-type signals from the host via the multiple lines.

[0357] Wherein, a corresponding group among the plurality of memory cell groups is used by the host to select a corresponding first type of signal from one or more first type signals.

[0358] A corresponding memory unit among the plurality of memory units is coupled to a corresponding line among the plurality of lines, and the corresponding memory unit among the plurality of memory units is also configured to receive a corresponding second type signal among the one or more second type signals via the interface, so that it can be individually selected by the host.

[0359] The host is configured to send one or more signals to the memory architecture via the interface and access the corresponding memory cells.

[0360] 36. The system of claim 35, wherein the one or more signals of the first type received by the interface include one or more chipset selection signals.

[0361] 37. The system of claim 36, wherein the one or more second-type signals received by the interface include one or more data mask signals.

[0362] 38. The system according to claim 37, wherein a corresponding memory unit among the plurality of memory units is further configured to receive a corresponding data mask signal among the one or more data mask signals via a corresponding line among the plurality of lines of the interface.

[0363] 39. The system of claim 37, wherein the one or more second-type signals received by the interface include one or more unit I / O enable signals.

[0364] 40. The system of claim 39, wherein a corresponding memory unit among the plurality of memory units is further configured to receive a corresponding unit I / O enable signal among the one or more unit I / O enable signals via the interface.

[0365] 41. The system according to claim 40, wherein each of the plurality of memory cells includes a corresponding cell I / O enable register, the corresponding cell I / O enable register being used to enable / disable the I / O function of the corresponding memory cell.

[0366] 42. The system of claim 35, wherein the one or more signals of the first type received by the interface include one or more data mask signals.

[0367] 43. A method comprising:

[0368] A corresponding memory cell group in a plurality of memory cell groups of the storage system is selected individually by sending one or more signals of the first type to the storage system, wherein the corresponding memory cell group in the plurality of memory cell groups includes a plurality of memory cells;

[0369] Individual memory cells within a plurality of memory cells in a respective memory cell group are selected by sending one or more signals of the second type to the respective memory cell group, wherein the respective memory cell is configured in a PIM architecture; and

[0370] Access the corresponding memory unit.

[0371] 44. The method of claim 43, wherein sending the first type of signal includes sending a chipset selection signal.

[0372] 45. The method of claim 43, wherein sending the signal of the first type includes sending a data mask signal.

[0373] 46. ​​The method of claim 43, wherein sending the one or more signals of the second type includes sending one or more data mask signals.

[0374] 47. The method of claim 43, wherein sending the one or more signals of the second type includes sending one or more unit I / O enable signals.

[0375] Although the subject matter has been described in language specific to structural features and / or methodological behavior, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or behaviors described. Rather, the specific features and actions are disclosed as exemplary forms for implementing the claims.

Claims

1. A memory architecture coupled to a host external to the memory architecture, the memory architecture comprising: Multiple memory units, wherein a corresponding memory unit among the multiple memory units is configured as a PIM architecture; as well as An interface, coupled between the plurality of memory cells and the host, includes multiple lines for receiving one or more signals from the host via the multiple lines; wherein a corresponding memory cell among the plurality of memory cells is coupled to a corresponding line among the multiple lines, and the corresponding memory cell is also configured to receive a corresponding signal among the one or more signals via the interface for individual selection by the host; wherein the one or more signals received by the interface include one or more unit I / O enable signals, and a corresponding memory cell among the plurality of memory cells includes a corresponding unit I / O enable register for enabling / disabling the I / O function of the corresponding memory cell.

2. The memory architecture according to claim 1, wherein, The one or more signals received by the interface also include one or more chipset selection signals.

3. The memory architecture according to claim 2, wherein, The respective memory unit among the plurality of memory units is also used to receive the corresponding chipset selection signal from the one or more chipset selection signals via the corresponding line among the plurality of lines of the interface.

4. The memory architecture according to claim 1, wherein, The one or more signals received by the interface also include one or more data mask signals.

5. The memory architecture according to claim 4, wherein, The respective memory unit among the plurality of memory units is also used to receive the corresponding data mask signal among the one or more data mask signals via the corresponding line among the plurality of lines of the interface.

6. The memory architecture according to claim 1, wherein, The respective memory cells among the plurality of memory cells are also used to receive the corresponding cell I / O enable signal via the interface.

7. The memory architecture according to claim 1, wherein, The PIM architecture includes: Data area, used to store data; and A computation block is used to perform computations.

8. A method for accessing memory, comprising: One or more memory cells from a plurality of memory cells in a storage system are individually selected by sending one or more signals to the storage system, wherein the respective memory cells among the plurality of memory cells are configured in a PIM architecture, and An interface is coupled between the plurality of memory cells and a host, the interface comprising multiple lines for receiving one or more signals from the host via the multiple lines; wherein a corresponding memory cell among the plurality of memory cells is coupled to a corresponding line among the multiple lines, and the corresponding memory cell is also configured to receive a corresponding signal among the one or more signals via the interface for individual selection by the host, wherein the one or more signals include one or more unit I / O enable signals, and the corresponding memory cell among the plurality of memory cells includes a corresponding unit I / O enable register for enabling / disabling the I / O function of the corresponding memory cell; and Access the one or more memory units.

9. The method for accessing memory according to claim 8, wherein, Sending the one or more signals also includes sending one or more chipset select signals.

10. The method for accessing memory according to claim 9, wherein, Selecting a specific memory cell individually includes selecting a specific memory cell individually using the corresponding chipset selection signal among the one or more chipset selection signals.

11. The method for accessing memory according to claim 8, wherein, Sending the one or more signals also includes sending one or more data mask signals.

12. The method for accessing memory according to claim 11, wherein, Selecting a specific memory cell individually includes selecting the specific memory cell using the specific data mask signal from the one or more data mask signals.

13. The method for accessing memory according to claim 8, wherein, Selecting a specific memory cell individually includes using the corresponding cell I / O enable signal among the one or more cell I / O enable signals to select the specific memory cell individually.

14. A memory system, comprising: A memory architecture coupled to a host external to the memory architecture, the memory architecture comprising: Multiple memory units, wherein corresponding memory units among the multiple memory units are configured as a PIM architecture; and An interface, coupled between the plurality of memory units and the host, the interface including multiple lines, the interface being used to receive one or more signals from the host via the multiple lines; The respective memory cells in the plurality of memory cells are coupled to the respective lines in the plurality of lines, and the respective memory cells are also used to receive the respective signals in the one or more signals via the interface so as to be individually selected by the host. The one or more signals received by the interface include one or more unit I / O enable signals, and the respective memory cells in the plurality of memory cells include a corresponding unit I / O enable register, which is used to enable / disable the I / O function of the respective memory cells. The host is configured to send one or more signals to the memory architecture via the interface and access the corresponding memory cells.

15. The memory system according to claim 14, wherein, The one or more signals received by the interface also include one or more chipset selection signals.

16. The memory system of claim 15, wherein a corresponding memory cell of the plurality of memory cells is further configured to receive a corresponding chipset selection signal of the one or more chipset selection signals via a corresponding line of the plurality of lines of the interface.

17. The memory system according to claim 14, wherein, The one or more signals received by the interface also include one or more data mask signals.

18. The memory system according to claim 17, wherein, The respective memory unit among the plurality of memory units is also used to receive the corresponding data mask signal among the one or more data mask signals via the corresponding line among the plurality of lines of the interface.

19. The memory system according to claim 14, wherein, The respective memory cells among the plurality of memory cells are also used to receive the corresponding cell I / O enable signal via the interface.

20. The memory system of claim 14, wherein, The PIM architecture includes: Data area, used to store data; and A computation block is used to perform computations.

21. A memory architecture coupled to a host external to the memory architecture, the memory architecture comprising: Multiple memory cell groups, each memory cell group comprising multiple memory cells, and each memory cell among the multiple memory cells being configured as a PIM architecture; as well as An interface, coupled between the memory architecture and the host, the interface comprising multiple lines, the interface being used to receive one or more signals of a first type and one or more signals of a second type from the host via the multiple lines; The corresponding memory cell group among the plurality of memory cell groups is selected by the host using a signal of the corresponding first type among the one or more first type signals; The respective memory unit among the plurality of memory units is coupled to the respective line among the plurality of lines, and the respective memory unit among the plurality of memory units is also used to receive the respective second type of signal among the one or more second type signals via the interface, so that it can be individually selected by the host.

22. The memory architecture according to claim 21, wherein, The one or more signals of the first type received by the interface include one or more chipset selection signals.

23. The memory architecture according to claim 22, wherein, The one or more second-type signals received by the interface include one or more data mask signals.

24. The memory architecture according to claim 23, wherein, A corresponding memory unit among the plurality of memory units is also used to receive a corresponding data mask signal among the one or more data mask signals via a corresponding line among the plurality of lines of the interface.

25. The memory architecture according to claim 22, wherein, The one or more second-type signals received by the interface include one or more unit I / O enable signals.

26. The memory architecture according to claim 25, wherein, The respective memory cell among the plurality of memory cells is also used to receive the corresponding unit I / O enable signal among the one or more unit I / O enable signals via the interface.

27. The memory architecture according to claim 26, wherein, The corresponding memory cell among the plurality of memory cells includes a corresponding cell I / O enable register, which is used to enable / disable the I / O function of the corresponding memory cell.

28. The memory architecture according to claim 21, wherein, The one or more signals of the first type received by the interface include one or more data mask signals.

29. A memory system, comprising: The memory architecture is coupled to a host outside the memory architecture. The memory architecture includes: A multi-memory unit group, wherein the corresponding memory unit group includes multiple memory units, and the corresponding memory units among the multiple memory units are configured as a PIM architecture; and an interface coupled between the memory architecture and the host, the interface comprising multiple lines for receiving one or more first-type signals and one or more second-type signals from the host via the multiple lines. Wherein, a corresponding group among the plurality of memory cell groups is used by the host to select a corresponding first type of signal from one or more first type signals. A corresponding memory unit among the plurality of memory units is coupled to a corresponding line among the plurality of lines, and the corresponding memory unit among the plurality of memory units is also configured to receive a corresponding second type signal among the one or more second type signals via the interface, so that it can be individually selected by the host. The host is configured to send one or more signals to the memory architecture via the interface and access the corresponding memory cells.

30. The memory system according to claim 29, wherein, The one or more signals of the first type received by the interface include one or more chipset selection signals.

31. The memory system according to claim 30, wherein, The one or more second-type signals received by the interface include one or more data mask signals.

32. The memory system according to claim 31, wherein, A corresponding memory unit among the plurality of memory units is also used to receive a corresponding data mask signal among the one or more data mask signals via a corresponding line among the plurality of lines of the interface.

33. The memory system according to claim 31, wherein, The one or more second-type signals received by the interface include one or more unit I / O enable signals.

34. The memory system according to claim 33, wherein, The respective memory cell among the plurality of memory cells is also used to receive the corresponding unit I / O enable signal among the one or more unit I / O enable signals via the interface.

35. The memory system according to claim 34, wherein, The corresponding memory cell among the plurality of memory cells includes a corresponding cell I / O enable register, which is used to enable / disable the I / O function of the corresponding memory cell.

36. The memory system of claim 29, wherein the one or more signals of the first type received by the interface include one or more data mask signals.

37. A method for accessing memory, comprising: A corresponding memory cell group in a plurality of memory cell groups of the storage system is selected individually by sending one or more signals of the first type to the storage system, wherein the corresponding memory cell group in the plurality of memory cell groups includes a plurality of memory cells; A corresponding memory cell in a plurality of memory cells of a corresponding memory cell group is individually selected by sending one or more signals of the second type to the corresponding memory cell group, wherein the corresponding memory cell in the plurality of memory cells is configured as a PIM architecture, and an interface is coupled between the memory architecture and the host, the interface including multiple lines, the interface being used to receive one or more signals of the first type and one or more signals of the second type from the host via the multiple lines; The corresponding memory cell group among the plurality of memory cell groups is selected by the host using a signal of the corresponding first type among the one or more first type signals; Wherein, a corresponding memory unit among the plurality of memory units is coupled to a corresponding line among the plurality of lines, and the corresponding memory unit among the plurality of memory units is also used to receive a corresponding second-type signal among the one or more second-type signals via the interface, so as to be individually selected by the host; and Access the corresponding memory unit.

38. The method for accessing memory according to claim 37, wherein, Sending the first type of signal includes sending a chipset selection signal.

39. The method for accessing memory according to claim 37, wherein, Sending the first type of signal includes sending a data mask signal.

40. The method for accessing memory according to claim 37, wherein, Sending one or more signals of the second type includes sending one or more data mask signals.

41. The method for accessing memory according to claim 37, wherein, Sending one or more signals of the second type includes sending one or more unit I / O enable signals.

Images