A method, system, storage medium and device for generating a chip pin location map

Abstract

The present invention provides a method, system, storage medium, and device for generating a chip pin location map. The method includes: obtaining pin information and a corresponding location label for each pin from a pin statistics table of a chip, where the location label includes letter information and numeric information; parsing each location label to set the sequence value corresponding to the letter information as the Y-axis value, and the corresponding numeric information as the X-axis value; calibrating the Y-axis value of each pin according to a preset rule so that the calibrated Y-axis value and X-axis value are mapped to corresponding cells of a target table of the chip, and obtaining the location information of each pin based on the calibrated Y-axis value and X-axis value; and filling the corresponding pin information into the corresponding cells according to the location information of each pin to obtain a pin location map of the chip. The present invention improves the efficiency of generating pin location maps for chips with multiple packages and chips with a large number of pins.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a method, system, storage medium and device for generating a chip pin location map. Background Art

[0002] With the continuous development of integrated circuits, the complexity of chips continues to increase. As chips become more and more versatile, the number of pins required increases. During package design, it is necessary to optimize the layout of different signal locations, which is a tedious and complex task.

[0003] Previously, the common practice was to arrange the positions in an Excel spreadsheet, then fill in the corresponding pin information in the column below the corresponding position information. This information was then placed in the target spreadsheet using a reference algorithm. This was very cumbersome and inflexible. A later approach employed a script to import the table containing the signal pin location information, and then used the mapping algorithm within the script to map the pin information to the target spreadsheet. While this approach was relatively simple to use, it did require setting up the appropriate runtime environment and installing the appropriate runtime libraries, placing high demands on the system. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to propose a method, system, storage medium and device for generating a chip pin location map, so as to solve the problem in the prior art that generating a chip pin location map in an Excel spreadsheet is cumbersome and complicated.

[0005] Based on the above purpose, the present invention provides a method for generating a chip pin location map, comprising the following steps:

[0006] Get the pin information and corresponding position number of each pin from the pin statistics table of the chip. The position number contains letter information and number information.

[0007] Parse each position label to set the order value corresponding to the letter information as the Y-axis value, and set the corresponding numerical information as the X-axis value;

[0008] Calibrate the Y-axis value of each pin according to a preset rule so that the calibrated Y-axis value and the X-axis value are mapped to corresponding cells of the target table of the chip, and obtain the position information of each pin based on the calibrated Y-axis value and the X-axis value;

[0009] According to the location information of each pin, the corresponding pin information is filled into the corresponding cells to obtain the pin location map of the chip.

[0010] In some embodiments, calibrating the Y-axis value of each pin according to a preset rule so that the calibrated Y-axis value and the X-axis value are mapped to corresponding cells of a target table of the chip includes:

[0011] In response to the Y-axis value belonging to the n-th letter segment block, subtracting Δy from the Y-axis value to obtain a calibrated Y-axis value, wherein Δy represents the sum of spacing values between all letter segment blocks before the n-th letter segment block;

[0012] Map the calibrated Y-axis values to the column coordinates of the corresponding cells, and map the X-axis values to the horizontal coordinates of the corresponding cells.

[0013] In some embodiments, the letter information includes single letters and combined letters; and the target table of the chip is an Excel table.

[0014] In some embodiments, the method further comprises:

[0015] Fill the cells where each pin information is located with solder ball graphics.

[0016] Another aspect of the present invention further provides a system for generating a chip pin location map, comprising:

[0017] An acquisition module is configured to obtain pin information and a corresponding position number of each pin from a pin statistics table of the chip, where the position number includes letter information and numeric information;

[0018] a parsing module configured to parse each position label to set the order value corresponding to the letter information as the Y-axis value and the corresponding numerical information as the X-axis value;

[0019] a mapping module configured to calibrate the Y-axis value of each pin according to a preset rule so that the calibrated Y-axis value and the X-axis value are mapped to corresponding cells of a target table of the chip, and obtain position information of each pin based on the calibrated Y-axis value and the X-axis value; and

[0020] The pin location map generating module is configured to fill the corresponding pin information into the corresponding cells according to the location information of each pin, so as to obtain the pin location map of the chip.

[0021] In some embodiments, the mapping module includes a cell mapping module configured to, in response to the Y-axis value belonging to the nth letter segment block, subtract Δy from the Y-axis value to obtain a calibrated Y-axis value, wherein Δy represents the sum of the spacing values between all letter segment blocks before the nth letter segment block, and map the calibrated Y-axis value to the column coordinate of the corresponding cell, and map the X-axis value to the horizontal coordinate of the corresponding cell.

[0022] In some embodiments, the letter information includes single letters and combined letters; and the target table of the chip is an Excel table.

[0023] In some embodiments, the system further includes a pattern filling module configured to fill each cell where the pin information is located with a solder ball pattern.

[0024] According to another aspect of the present invention, a computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions implement the above method when executed by a processor.

[0025] In another aspect of the present invention, a computer device is provided, comprising a memory and a processor, wherein a computer program is stored in the memory, and the computer program performs the above method when executed by the processor.

[0026] The present invention has at least the following beneficial technical effects:

[0027] The present invention obtains the position labels of the pins from the pin statistics table of the chip, parses the position labels, and calibrates the parsed position labels according to preset rules, so that the position information obtained after calibration can be directly matched to the row and column information of the cell, thereby directly mapping the pin position information to the corresponding cell of the table, and then quickly and effectively generating the pin location map of the chip in the target table; the present invention is simple to operate, greatly reducing the tedious and complicated process in generating the chip pin location map in the prior art, and improving the generation efficiency of the pin location map of chips with multiple packages and chips with a large number of pins. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A schematic diagram of a method for generating a chip pin location map according to an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of a system for generating a chip pin location map according to an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of a computer-readable storage medium for implementing a method for generating a chip pin location map according to an embodiment of the present invention;

[0032] Figure 4The present invention is a schematic diagram of the hardware structure of a computer device for executing a method for generating a chip pin location map according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0034] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. Therefore, "first" and "second" are used for convenience of expression only and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product, or device that includes a series of steps or units.

[0035] Based on the above objectives, a first aspect of an embodiment of the present invention provides an embodiment of a method for generating a chip pin location map. Figure 1 FIG. 1 is a schematic diagram of an embodiment of a method for generating a chip pin location map provided by the present invention. Figure 1 As shown, the embodiment of the present invention includes the following steps:

[0036] Step S10: Obtain the pin information and corresponding position number of each pin from the pin statistics table of the chip, where the position number includes letter information and number information;

[0037] Step S20: parse each position label to set the order value corresponding to the letter information as the Y-axis value, and set the corresponding numerical information as the X-axis value;

[0038] Step S30: calibrate the Y-axis value of each pin according to a preset rule so that the calibrated Y-axis value and X-axis value are mapped to corresponding cells of the target table of the chip, and obtain the position information of each pin based on the calibrated Y-axis value and X-axis value;

[0039] Step S40: Fill the corresponding cells with the corresponding pin information according to the position information of each pin, so as to obtain a pin location map of the chip.

[0040] The embodiment of the present invention obtains the position labels of the pins from the pin statistics table of the chip, parses the position labels, and calibrates the parsed position labels according to preset rules, so that the position information obtained after calibration can be directly matched to the row and column information of the cell, thereby directly mapping the pin position information to the corresponding cell of the table, and then quickly and effectively generating the pin location map of the chip in the target table; the embodiment of the present invention is simple to operate, greatly reducing the tedious and complicated process of generating the chip pin location map in the prior art, and improving the generation efficiency of the pin location map of chips with multiple packages and chips with a large number of pins.

[0041] In some embodiments, the Y-axis value of each pin is calibrated according to a preset rule so that the calibrated Y-axis value and the X-axis value are mapped to corresponding cells of the target table of the chip, including: in response to the Y-axis value belonging to the nth letter segment block, subtracting Δy from the Y-axis value to obtain a calibrated Y-axis value, where Δy represents the sum of the spacing values between all letter segment blocks before the nth letter segment block; mapping the calibrated Y-axis value to the column coordinate of the corresponding cell, and mapping the X-axis value to the horizontal coordinate of the corresponding cell.

[0042] In some embodiments, the letter information includes single letters and combined letters; and the target table of the chip is an Excel table.

[0043] In some embodiments, the method further includes: filling solder ball patterns in each cell where the pin information is located.

[0044] The following is a specific embodiment of the method for generating a chip pin location map of the present invention:

[0045] This embodiment uses the VBA (Visual Basic for Applications, macro language) environment in Excel to implement different functions by developing different program modules.

[0046] It mainly includes the following contents:

[0047] (1) Coordinate information analysis: By reading the coordinate information columns in the table, the coordinate information is differentially inverted to generate coordinate information that conforms to the position map rules. For the bottom view position map, the coordinate information needs to be further symmetrically analyzed. This is related to the horizontal size of the chip. The specific parameter values used need to be calculated based on the number of horizontal columns of the chip.

[0048] (2) Coordinate mapping: This function is mainly divided into mapping rule calibration, mapping generation, and color identification. For mapping rule calibration, the vertical coordinate information of the pin location map is not all arranged using 26 English letters, but 20 letters are selected for application. Therefore, in the mapping process, it is necessary to obtain the coordinate information from (1) and process it in a step-by-step manner according to the mapping rule calibration algorithm. For color identification, after the mapping rule calibration is completed, the pin information has been mapped to the target table. This function will color-code different types of signals so that the locations of different signals can be distinguished. This function mainly uses a fuzzy contrast algorithm to process the background color of the compared cells. In the coordinate mapping process, it is necessary to traverse the coordinate information of all pins so that the pin information can be mapped to the target table one by one.

[0049] (3) Pin Location Map Generation: This function primarily assigns solder ball shapes to locations containing pin information in the location map. This shape is primarily derived from the octagonal shape provided by the Excel spreadsheet. This module configures shape attributes and then uses a traversal algorithm to assign solder ball shapes to the corresponding locations in the location map.

[0050] The specific implementation is as follows:

[0051] 1) This embodiment first obtains the position label information of the chip, and this information is obtained from the pin statistics table in Table 1 below. The letters in the position label represent row information, and the numbers represent column information. The GPIO (General-purpose input / output) chip in Table 1 below has three packages. When the pin location map is finally generated, one package corresponds to one pin location map. After obtaining the corresponding information from the table, the position label is parsed. The main work is coordinate information disassembly and coordinate inversion. When generating the Bottom View position map, coordinate symmetry analysis is also required.

[0052] Table 1 Pin Statistics

[0053]

[0054]

[0055] When decomposing the position labels, they are broken down into X-axis and Y-axis information in the table. The X-axis and Y-axis information are then swapped to achieve numerical designations on the X-axis and alphabetical designations on the Y-axis. To generate the pin location diagram for the bottom view, the position labels are further symmetrically transformed along the X-axis to achieve an inverted view.

[0056] 2) Next, the parsed position labels are mapped. This function is divided into three main parts: first, mapping rule adjustment, second, mapping generation, and third, color identification. In this module, the three modules mentioned above are polled according to the pin position labels. This allows the signal corresponding to the pin position to be mapped to the corresponding cell.

[0057] Regarding mapping rule calibration, based on the current coordinate rules for the location map, coordinates are processed during the mapping process to ensure compliance. Letters are segmented according to A-H, J-N, P, R, T-W, Y, AA-AH, AJ-AN, AP, AR, AT-AW, AY, etc. Therefore, A-H is a segmented block, J-N is a segmented block, P is also a segmented block, and so on. Therefore, when mapping in the table, the corresponding position labels must be processed according to the rules.

[0058] Upon receiving the position information, the mapping rule calibration module processes the column information within it to calculate the actual position coordinates in the target table. The Y-axis value represents the information after the position label is parsed. Each judgment module corresponds to a rule block, and the number of judgment modules depends on the number of rows in the chip. In the mapping rule module, the column header labels are mapped to the target table based on the coordinate information. The column header information is predefined according to the mapping rules, namely, A-H, J-N, P, R, T-W, Y, AA-AH, AJ-AN, AP, AR, AT-AW, AY, etc. Δy represents the sum of the spacing values between all letter segments before the nth letter segment. If the Y-axis value belongs to the first letter segment A-H, Δy is 0; if the Y-axis value belongs to the third letter segment P, Δy is 2, and so on.

[0059] The generation module will obtain the pin information corresponding to the corresponding cell when traversing the coordinate position information, and then fill the pin information into the target table according to the coordinate position information calibrated by the mapping rules, and traverse the position information column in turn.

[0060] Color identification mainly uses a fuzzy comparison algorithm to perform fuzzy matching on pin information and perform color identification based on the RGB color table information. The color identification module will be traversed as a separate function body.

[0061] 3) The pin location map generation module performs solder ball mapping on the target table after pin information mapping. It mainly uses a traversal method to locate the position information after the mapping rule is calibrated, and then configures the solder ball attributes.

[0062] This embodiment can quickly generate a pin location diagram based on a certain size based on the pin location label, and can realize a location diagram from two perspectives: TopView (top view) and Bottom View (bottom view). This embodiment can quickly process a large number of location labels and is not affected by the number of chip pins. It can quickly realize the pin location diagram of multiple packages for one chip, and the operation is simple and fast, greatly improving work efficiency. In addition, it can achieve rapid reuse. When adding multiple packages, it only needs to copy the corresponding platform module, modify the location label and the mapped target table to support the automatic generation of pin location diagrams for multiple packages.

[0063] This embodiment utilizes the VBA environment built into Excel to create an automated tool for pin location mapping. This eliminates the need for a dedicated runtime environment and is easy to use. The automated generation process is performed separately, minimizing the need for excessive computer resources and increasing efficiency. Furthermore, pin mapping can be implemented for multiple packages and large-scale applications to meet diverse needs.

[0064] A second aspect of an embodiment of the present invention further provides a system for generating a chip pin location map. Figure 2 FIG. 1 is a schematic diagram of an embodiment of a system for generating a chip pin location map provided by the present invention. Figure 2 As shown, a chip pin location map generation system includes: an acquisition module 10, configured to obtain pin information and a corresponding position label of each pin from a pin statistics table of the chip, where the position label includes letter information and numeric information; a parsing module 20, configured to parse each position label to set the sequential sorting value corresponding to the letter information as the Y-axis value, and the corresponding numeric information as the X-axis value; a mapping module 30, configured to calibrate the Y-axis value of each pin according to a preset rule, so that the calibrated Y-axis value and the X-axis value are mapped to the corresponding cells of the target table of the chip, and the position information of each pin is obtained based on the calibrated Y-axis value and the X-axis value; and a pin location map generation module 40, configured to fill the corresponding pin information into the corresponding cells according to the position information of each pin to obtain a pin location map of the chip.

[0065] In some embodiments, the mapping module 30 includes a cell mapping module configured to, in response to the Y-axis value belonging to the nth letter segment block, subtract Δy from the Y-axis value to obtain a calibrated Y-axis value, where Δy represents the sum of the spacing values between all letter segment blocks before the nth letter segment block, and map the calibrated Y-axis value to the column coordinate of the corresponding cell, and map the X-axis value to the horizontal coordinate of the corresponding cell.

[0066] In some embodiments, the letter information includes single letters and combined letters; and the target table of the chip is an Excel table.

[0067] In some embodiments, the system further includes a pattern filling module configured to fill each cell where the pin information is located with a solder ball pattern.

[0068] The embodiment of the present invention obtains the position labels of the pins from the pin statistics table of the chip, parses the position labels, and calibrates the parsed position labels according to preset rules, so that the position information obtained after calibration can be directly matched to the row and column information of the cell, thereby directly mapping the pin position information to the corresponding cell of the table, and then quickly and effectively generating the pin location map of the chip in the target table; the embodiment of the present invention is simple to operate, greatly reducing the tedious and complicated process of generating the chip pin location map in the prior art, and improving the generation efficiency of the pin location map of chips with multiple packages and chips with a large number of pins.

[0069] A third aspect of the embodiments of the present invention further provides a computer-readable storage medium. Figure 3 FIG. 1 is a schematic diagram showing a computer-readable storage medium for implementing a method for generating a chip pin location map according to an embodiment of the present invention. Figure 3 As shown, the computer-readable storage medium 3 stores computer program instructions 31. When the computer program instructions 31 are executed by the processor, the following steps are implemented:

[0070] Get the pin information and corresponding position number of each pin from the pin statistics table of the chip. The position number contains letter information and number information.

[0071] Parse each position label to set the order value corresponding to the letter information as the Y-axis value, and set the corresponding numerical information as the X-axis value;

[0072] Calibrate the Y-axis value of each pin according to a preset rule so that the calibrated Y-axis value and the X-axis value are mapped to corresponding cells of the target table of the chip, and obtain the position information of each pin based on the calibrated Y-axis value and the X-axis value;

[0073] According to the location information of each pin, the corresponding pin information is filled into the corresponding cells to obtain the pin location map of the chip.

[0074] In some embodiments, calibrating the Y-axis value of each pin according to a preset rule so that the calibrated Y-axis value and the X-axis value are mapped to corresponding cells of a target table of the chip includes:

[0075] In response to the Y-axis value belonging to the n-th letter segment block, subtracting Δy from the Y-axis value to obtain a calibrated Y-axis value, wherein Δy represents the sum of spacing values between all letter segment blocks before the n-th letter segment block;

[0076] Map the calibrated Y-axis values to the column coordinates of the corresponding cells, and map the X-axis values to the horizontal coordinates of the corresponding cells.

[0077] In some embodiments, the letter information includes single letters and combined letters; and the target table of the chip is an Excel table.

[0078] In some embodiments, the steps further include: filling solder ball graphics in each cell where the pin information is located.

[0079] It should be understood that, to the extent that there is no conflict between them, all the embodiments, features and advantages described above for the method for generating a chip pin location map according to the present invention are also applicable to the system and storage medium for generating a chip pin location map according to the present invention.

[0080] A fourth aspect of the embodiments of the present invention further provides a computer device, including: Figure 4 The memory 402 and the processor 401 are shown. The memory 402 stores a computer program. When the computer program is executed by the processor 401, the method of any one of the above embodiments is implemented.

[0081] like Figure 4 FIG. 1 is a schematic diagram of the hardware structure of a computer device for executing a method for generating a chip pin location map provided by the present invention. Figure 4 Taking the computer device shown in FIG. 4 as an example, the computer device includes a processor 401 and a memory 402, and may also include: an input device 403 and an output device 404. The processor 401, the memory 402, the input device 403 and the output device 404 may be connected via a bus or other means. Figure 4 The bus connection is used as an example. The input device 403 can receive input digital or character information and generate key signal input related to user settings and function control of the chip pin location map generation system. The output device 404 can include a display device such as a display screen.

[0082] The memory 402 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs, and modules, such as the program instructions / modules corresponding to the chip pin location map generation method in the embodiment of the present application. The memory 402 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created by the use of the chip pin location map generation method, etc. In addition, the memory 402 may include a high-speed random access memory and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 402 may optionally include a memory remotely located relative to the processor 401, and these remote memories may be connected to the local module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0083] The processor 401 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 402, that is, implements the method for generating the chip pin location map of the above method embodiment.

[0084] Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein may be a volatile memory or a non-volatile memory, or may include both a volatile memory and a non-volatile memory. By way of example and not limitation, the non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may include a random access memory (RAM), which may act as an external cache memory. By way of example and not limitation, RAM may be obtained in a variety of forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.

[0085] It will also be appreciated by those skilled in the art that the various exemplary logic blocks, modules, circuits and algorithmic steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given of the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0086] The various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or executed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and / or any other such configuration.

[0087] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless expressly limited to the singular.

[0088] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0089] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples. Within the spirit of the embodiments of the present invention, the technical features of the above embodiments or different embodiments may be combined, and there are many other variations of different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the scope of protection of the embodiments of the present invention.

Claims

1. A method for generating a chip pin location map, characterized in that: The following steps are involved: Obtain pin information and corresponding position number of each pin from the pin statistics table of the chip, wherein the position number includes letter information and number information; Parsing each of the position labels to set the order value corresponding to the letter information therein as the Y-axis value, and setting the corresponding numerical information as the X-axis value; Calibrate the Y-axis value of each pin according to a preset rule so that the calibrated Y-axis value and the X-axis value are mapped to corresponding cells of the target table of the chip, and obtain the position information of each pin based on the calibrated Y-axis value and the X-axis value; Filling corresponding pin information into corresponding cells according to the position information of each pin to obtain a pin location map of the chip; Calibrating the Y-axis value of each pin according to a preset rule so that the calibrated Y-axis value and the X-axis value are mapped to corresponding cells of the target table of the chip includes: In response to the Y-axis value belonging to the n-th letter segment block, subtract Δy from the Y-axis value to obtain the calibrated Y-axis value, wherein Δy represents the sum of spacing values between all letter segment blocks before the n-th letter segment block; The calibrated Y-axis value is mapped to the column coordinate of the corresponding cell, and the X-axis value is mapped to the horizontal coordinate of the corresponding cell.

2. The method according to claim 1, characterized in that The letter information includes single letters and combined letters; the target table of the chip is an Excel table.

3. The method according to claim 1, characterized in that Also includes: Fill the cells where each pin information is located with solder ball graphics.

4. A system for generating a chip pin location map, characterized in that: include: An acquisition module configured to acquire pin information and a corresponding position number of each pin from a pin statistics table of the chip, wherein the position number includes letter information and numeric information; a parsing module configured to parse each of the position labels to set the order value corresponding to the letter information as the Y-axis value and the corresponding digital information as the X-axis value; a mapping module configured to calibrate the Y-axis value of each pin according to a preset rule so that the calibrated Y-axis value and the X-axis value are mapped to corresponding cells of the target table of the chip, and obtain the position information of each pin based on the calibrated Y-axis value and the X-axis value; as well as A pin location map generating module is configured to fill corresponding pin information into corresponding cells according to the location information of each pin, so as to obtain a pin location map of the chip; The mapping module includes a cell mapping module, which is configured to, in response to the Y-axis value belonging to the nth letter segment block, subtract Δy from the Y-axis value to obtain the calibrated Y-axis value, wherein the Δy represents the sum of the spacing values between all letter segment blocks before the nth letter segment block, and map the calibrated Y-axis value to the column coordinate of the corresponding cell, and map the X-axis value to the horizontal coordinate of the corresponding cell.

5. The system according to claim 4, characterized in that The letter information includes single letters and combined letters; the target table of the chip is an Excel table.

6. The system according to claim 4, characterized in that The invention also includes a graphic filling module configured to fill the solder ball graphics in each cell where the pin information is located.

7. A computer-readable storage medium, characterized in that Computer program instructions are stored, and when the computer program instructions are executed by a processor, the method according to any one of claims 1 to 3 is implemented.

8. A computer device comprising a memory and a processor, characterized in that: The memory stores a computer program, which, when executed by the processor, performs the method according to any one of claims 1 to 3.

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