Weight data storage method and device, chip, electronic device, and readable medium

Abstract

The present disclosure provides a weight data storage method, which is applied to a neuromorphic chip. The neuromorphic chip includes an on-chip storage structure and multiple processing cores, each processing core includes multiple neurons, and the method includes: storing the weight data corresponding to each of the neurons in an off-chip storage structure, the off-chip storage structure is located outside the neuromorphic chip; storing the weight index information corresponding to each of the neurons in the corresponding on-chip storage structure; wherein the weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure. The present disclosure also provides a weight data storage device, a neuromorphic chip, an electronic device, and a computer-readable medium.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a method and device for storing weight data, a neuromorphic chip, an electronic device, and a computer-readable medium. Background Art

[0002] High-performance brain-like computing technology and brain simulation technology have become important means of studying brain science. The development of computational neuroscience has had an important impact on the fields of intelligence science, cognitive science, information processing, and artificial intelligence. The basic functions of the human brain require the joint activities of millions of neurons. To simulate brain functions more accurately, a larger-scale brain simulation system is needed.

[0003] In the related art, in a neuromorphic chip, each core (also called a core or a processing core) usually needs to pre-store the weight matrix required by the pulse neural network. The weight matrix contains a large number of connection weights between neurons. The storage accuracy of the connection weights is usually high, such as fp16, which results in excessive occupation of the on-chip storage space of the neuromorphic chip. Summary of the invention

[0004] The present invention provides a weight data storage method and device, a neuromorphic chip, an electronic device, and a computer-readable medium.

[0005] According to the first aspect of the present disclosure, an embodiment of the present disclosure provides a weight data storage method, which is applied to a neuromorphic chip, wherein the neuromorphic chip includes an on-chip storage structure and multiple processing cores, each processing core includes multiple neurons, and the weight data storage method includes: storing the weight data corresponding to each of the neurons in an off-chip storage structure, wherein the off-chip storage structure is located outside the neuromorphic chip; and storing the weight index information corresponding to each of the neurons in the corresponding on-chip storage structure; wherein the weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure.

[0006] In some embodiments, a plurality of the processing cores are provided with a corresponding on-chip storage structure, or each of the processing cores is provided with a corresponding on-chip storage structure.

[0007] In some embodiments, the weight index information includes the starting storage address and length information of the weight data corresponding to the neuron in the off-chip storage structure.

[0008] In some embodiments, the off-chip storage structure includes multiple storage areas, each storage area corresponds to a neuron, each storage area includes at least one weight data configuration area, and each weight data configuration area corresponds to a target processing core connected to the neuron; storing the weight data corresponding to each neuron in the off-chip storage structure includes: for each neuron, storing the corresponding weight data between the neuron and the corresponding target processing core in the corresponding storage area; in the storage area corresponding to the neuron, the corresponding weight data between the neuron and each corresponding target processing core are stored in the corresponding weight data configuration area in sequence; generating the weight index information corresponding to the neuron.

[0009] In some embodiments, storing the weight data corresponding to each of the neurons in an off-chip storage structure includes: generating a weight data packet corresponding to each of the neurons based on the weight data corresponding to each of the neurons; storing the weight data packet corresponding to each of the neurons in the off-chip storage structure, and generating the corresponding weight index information.

[0010] In some embodiments, the weight data includes connection identification information and weight information; the connection identification information includes multiple connection identifications, each of the connection identifications corresponds to a target neuron in a target processing core connected to the neuron, the multiple connection identifications include at least one first connection identification and at least one second connection identification, the first connection identification indicates that there is a connection weight between the neuron and the target neuron in the target processing core, and the second connection identification indicates that there is no connection weight between the neuron and the target neuron in the target processing core; the weight information includes the connection weight corresponding to the first connection identification.

[0011] In some embodiments, when the weight data corresponding to each neuron is stored in the form of a storage area, the weight data configuration area includes a connection identification part and a weight part; the connection identification part is used to configure the connection identification information corresponding to the target processing core connected to the neuron corresponding to the weight data configuration area, and the weight part is used to configure the connection weight corresponding to the first connection identification in the connection identification information.

[0012] In some embodiments, when the weight data corresponding to each neuron is stored in the form of a weight data packet, the weight data packet includes: a header part set in sequence, a weight data configuration part corresponding to each target processing core connected to the neuron, and the weight data configuration part corresponding to each target processing core includes a connection identification part and a weight part; the header part is used to configure the number of target processing cores connected to the neuron, the core identification of each target processing core connected to the neuron, and the length information of the corresponding weight data configuration part; in the weight data configuration part corresponding to each target processing core, the connection identification part is used to configure the connection identification information corresponding to the target processing core connected to the neuron, and the weight part is used to configure the connection weight corresponding to the first connection identification in the connection identification information.

[0013] In some embodiments, the neuromorphic chip is used to run a pulse neural network; for each neuron, the target processing cores connected to the neuron are all the predecessor processing cores of the current processing core where the neuron is located, or, the target processing cores connected to the neuron are all the successor processing cores of the current processing core where the neuron is located; the predecessor processing core is the processing core in the network structure layer before the network structure layer where the current processing core is located; the successor processing core is the network structure layer below the network structure layer where the current processing core is located.

[0014] According to a second aspect of the present disclosure, an embodiment of the present disclosure provides a weight data storage device, which is applied to a neuromorphic chip, wherein the neuromorphic chip includes an on-chip storage structure and multiple processing cores, each processing core includes multiple neurons; the weight data storage device includes:

[0015] A first storage execution module is configured to store the weight data corresponding to each of the neurons into an off-chip storage structure, where the off-chip storage structure is located outside the neuromorphic chip; and

[0016] A second storage execution module is configured to store the weight index information corresponding to each of the neurons into the corresponding on-chip storage structure;

[0017] The weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure.

[0018] According to a third aspect of the present disclosure, an embodiment of the present disclosure provides a neuromorphic chip, which includes multiple processing cores and a weight data storage device, each processing core includes multiple neurons, and the weight data storage device includes the above-mentioned weight data storage device.

[0019] According to the fourth aspect of the present disclosure, an embodiment of the present disclosure provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, and one or more of the computer programs are executed by the at least one processor so that the at least one processor can execute the above-mentioned weight data storage method.

[0020] According to a fifth aspect of the present disclosure, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, wherein the computer program implements the above-mentioned weight data storage method when executed by a processor.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0023] Figure 1 is a schematic diagram of the structure of a neuromorphic chip according to an embodiment of the present disclosure;

[0024] Figure 2 for Figure 1 A schematic diagram of the structure of a processing core;

[0025] Figure 3 A flowchart of a weight data storage method provided by an embodiment of the present disclosure;

[0026] Figure 4 for Figure 3 A flowchart of a specific implementation method of step S1;

[0027] Figure 5 A schematic diagram of the structure of a weight data configuration area in a storage area of ​​an off-chip storage structure;

[0028] Figure 6 A schematic diagram of the connection relationship between the current processing core and a connected target processing core;

[0029] Figure 7 for Figure 3 A flowchart of another specific implementation method of step S1;

[0030] Figure 8 This is a schematic diagram of the format of the weight data packet;

[0031] Fig. 9 A schematic diagram of the connection relationship between the current processing core and multiple connected target processing cores;

[0032] Fig.10 Schematic diagram of the transmission process of neuron weight data;

[0033] Fig.11 A structural diagram of a weight data storage device provided in an embodiment of the present disclosure;

[0034] Fig.12 A block diagram of a composition of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0036] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0037] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0040] Brain-like computing imitates the operating mechanism of the biological brain to build an electronic brain similar to the biological brain, which is used to process data with higher accuracy and processing efficiency. The architecture based on the von Neumann system has limited support for brain-like computing, which limits the application scope of neural networks and has low energy efficiency. Therefore, in order to obtain a new architecture system that better matches neural computing, neuromorphic chips (for example, brain-like computing chips) came into being. Neuromorphic chips are usually multi-core structures.

[0041] Figure 1 is a schematic diagram of the structure of a neuromorphic chip according to an embodiment of the present disclosure, Figure 2 for Figure 1 A schematic diagram of the structure of a processing core in the neuromorphic chip. The neuromorphic chip includes multiple processing cores, each of which usually includes a group (multiple) of neurons, a group of axons, a group of dendrites and a synaptic array, which can simulate the behavior of a biological neuron cluster. Each processing core in the neuromorphic chip can complete the dendrite integral calculation process and cell body calculation process of a corresponding group of neurons. Among them, the dendrite is a structure for receiving external stimuli and generating input current, the axon is a structure for transmitting pulses to the synapse of the subsequent neuron, the synapse is a structure for connecting neurons, and the synaptic array is an array composed of synapses, connecting a group of axons and a group of dendrites.

[0042] For each neuron in the processing core, the dendrite integral calculation process is used to describe the process of integrating the pulse data of all input axons connected to the dendrites of the neuron. The dendrite integral calculation process is also referred to as the membrane potential integral operation in the disclosed embodiment. The cell body operation process is responsible for updating the membrane potential of the neuron and judging the release of pulses. The cell body operation process is also referred to as the release operation in the disclosed embodiment. If the membrane potential of any neuron meets the release condition, the axon of the neuron will release a pulse represented by 1 to the successor neuron connected to the neuron; otherwise, the axon of the neuron will release a pulse represented by 0 to the successor neuron connected to the neuron. This enables the neuromorphic chip, as a very large-scale integrated system of electronic analog circuits, to more accurately simulate the neural biological structure in the nervous system.

[0043] In the related art, synaptic arrays are usually used to simulate the connection relationship between a group of neurons of one processing core and a group of neurons of another processing core, as an array storage structure for storing the connection topology and connection weights (also called synaptic weights) between a group of neurons of one processing core and a group of neurons of another processing core. However, the weight matrix corresponding to the synaptic array usually contains a large number of connection weights between neurons, and the storage accuracy of the connection weights is usually high, for example, fp16, resulting in excessive occupation of the on-chip storage space of the neuromorphic chip. Therefore, how to effectively save the storage resources of the connection weights on the neuromorphic chip, save the on-chip storage space of the neuromorphic chip, and improve the utilization rate of the on-chip storage space has become a technical problem that needs to be solved urgently.

[0044] In order to effectively solve the technical problems existing in the above-mentioned related technologies, the embodiments of the present disclosure provide a weight data storage method and device, a neuromorphic chip, an electronic device, and a computer-readable medium. According to the technical solution provided by the embodiments of the present disclosure, each processing core does not need to store the weight matrix required for the operation of the neuron, and the weight data corresponding to each neuron of each processing core is stored in the off-chip storage structure of the neuromorphic chip, while the on-chip storage structure of the neuromorphic chip stores the weight index information of the weight data, which effectively reduces the occupation of the on-chip storage space of the neuromorphic chip by the weight data of the neuron, saves the on-chip storage space of the neuromorphic chip, and improves the utilization rate of the on-chip storage space of the neuromorphic chip. In some application scenarios, when a processing core issues a pulse to another processing core, it is no longer necessary to pass the relevant weight parameters, and the other processing core can obtain the corresponding weight data from the off-chip storage structure according to the operation needs, thereby effectively reducing the occupation of hardware processing resources and improving the hardware processing performance of the processing core to a certain extent, that is, improving the performance of the neuromorphic chip.

[0045] The technical solution of the embodiment of the present disclosure is described in detail below in conjunction with the relevant drawings.

[0046] Figure 3 A flowchart of a method for storing weight data provided by an embodiment of the present disclosure, referring to Figure 3 The embodiment of the present disclosure provides a weight data storage method, which is applied to a neuromorphic chip. The method can be performed by a weight data storage device, which can be implemented by software and / or hardware. The device can be integrated into the processing core of the neuromorphic chip, or can be independently set outside the neuromorphic chip. The weight data storage method of the embodiment of the present disclosure is implemented by interacting with the neuromorphic chip. The weight data storage method includes:

[0047] Step S1: storing the weight data corresponding to each neuron in an off-chip storage structure, where the off-chip storage structure is located outside the neuromorphic chip.

[0048] Step S2: Store the weight index information corresponding to each neuron into the corresponding on-chip storage structure.

[0049] Among them, the weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure.

[0050] In the disclosed embodiment, the off-chip storage structure may be any type of memory such as a double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR), a non-volatile memory (Non-Volatile Memory, NVM), or a flash memory (Flash).

[0051] In an embodiment of the present disclosure, in a neuromorphic chip, a plurality of processing cores are provided with an on-chip storage structure correspondingly, or an on-chip storage structure is provided correspondingly to each processing core. The embodiment of the present disclosure does not limit the specific implementation form of the on-chip storage structure.

[0052] For each processing core, the on-chip storage structure may store configuration information of each neuron of the processing core, configuration information common to multiple neurons of the processing core, and weight index information corresponding to each neuron.

[0053] The configuration information of each neuron may include: the historical membrane potential, membrane potential threshold and corresponding refractory period of the neuron. If the current time is within the refractory period corresponding to the neuron, then according to the bionic characteristics of the pulse neural network, when the neuron issues output information at the current time, it will not respond to the output information of the neuron, that is, within the refractory period corresponding to the neuron, the neuron's issuing operation will not be processed. Alternatively, the configuration information of each neuron may include: the type identifier (ID) corresponding to the configuration information common to multiple neurons.

[0054] The configuration information common to multiple neurons may include: a function table, and a correspondence between a type ID and a historical membrane potential, a membrane potential threshold, and a refractory period of each neuron. The function table may include an activation function of a neural network, which may be a nonlinear activation function or a linear activation function. Through the correspondence between the type ID and the historical membrane potential, the membrane potential threshold, and the refractory period of each neuron, the historical membrane potential, the membrane potential threshold, and the corresponding refractory period of each neuron may be determined.

[0055] In an embodiment of the present disclosure, the weight index information corresponding to each neuron may include the starting storage address and length information of the weight data corresponding to the neuron in an off-chip storage structure.

[0056] In some embodiments, the weight data corresponding to each neuron is stored in the form of divided storage areas. The off-chip storage structure may include multiple storage areas, each storage area corresponds to a neuron, each storage area includes at least one weight data configuration area, and each weight data configuration area corresponds to a target processing core connected to the neuron. Figure 4 for Figure 3 A flowchart of a specific implementation method of step S1 in FIG. Figure 4 As shown, in some embodiments, step S1 may further include: step S101 to step S102.

[0057] Step S101: For each neuron, the weight data corresponding to the neuron and the corresponding target processing core is stored in the corresponding storage area.

[0058] Among them, in the storage area corresponding to the neuron, the corresponding weight data between the neuron and each corresponding target processing core is stored in the corresponding weight data configuration area in sequence. In the off-chip storage structure, each storage area can correspond to the identifier of the corresponding neuron, and each weight data configuration area can correspond to the core identifier of the corresponding target processing core, so as to perform data retrieval and reading.

[0059] Step S102: Generate weight index information corresponding to the neuron.

[0060] Specifically, based on the storage status of the weight data between the neuron and each target processing core in the off-chip storage structure (such as the storage area, the storage address and length of the weight data configuration area), the weight index information of the corresponding weight data between the neuron and each target processing core in the off-chip storage structure is generated to facilitate reading the corresponding weight data from the corresponding storage area and the corresponding weight data configuration area in the off-chip storage structure.

[0061] In some embodiments, the weight data corresponding to each neuron is stored in compression, which can effectively reduce the storage resources of the off-chip storage structure occupied by the weight data. The weight data may include connection identification information and weight information, the connection identification information includes multiple connection identifications, each connection identification corresponds to a target neuron in the target processing core connected to the neuron, and the multiple connection identifications include at least one first connection identification and at least one second connection identification, the first connection identification indicates that there is a connection weight between the neuron and the target neuron in the target processing core, and the second connection identification indicates that there is no connection weight between the neuron and the target neuron in the target processing core; the weight information includes the connection weight corresponding to the first connection identification. The first connection identification can be represented by the number 1, and the second connection identification can be represented by the number 0.

[0062] The connection weight is the connection weight between the neuron and the neuron in the target processing core, and the connection weight is used to perform the membrane potential integral operation of the corresponding neuron in the target processing core or to perform the membrane potential integral operation of the neuron in the current processing core.

[0063] In some embodiments, the neuromorphic chip is used to run a spiking neural network, and for each neuron, the target processing cores connected to the neuron are all the predecessor processing cores of the current processing core where the neuron is located, or the target processing cores connected to the neuron are all the successor processing cores of the current processing core where the neuron is located. The predecessor processing core is a processing core connected to the current processing core and located in the network structure layer before the network structure layer where the current processing core is located, and the successor processing core is a processing core connected to the current processing core and located in the network structure layer below the network structure layer where the current processing core is located.

[0064] When the target processing core is the predecessor processing core of the current processing core, the connection weights are used to perform membrane potential integral operations on neurons in the current processing core. When the target processing core is the successor processing core of the current processing core, the connection weights are used to perform membrane potential integral operations on corresponding neurons in the target processing core.

[0065] Figure 5 is a schematic diagram of the structure of a weight data configuration area in a storage area of ​​an off-chip storage structure, and correspondingly, Figure 5 As shown, in the case where the weight data corresponding to each of the neurons is stored in the form of a storage area, the weight data configuration area includes a connection identification part and a weight part, the connection identification part is used to configure the connection identification information corresponding to the target processing core connected to the neuron corresponding to the weight data configuration area, and the weight part is used to configure the connection weight corresponding to the first connection identification in the connection identification information.

[0066] Figure 6 is a schematic diagram of the connection relationship between the current processing core and a connected target processing core. For example, when the target processing cores connected to the neuron are all the predecessor processing cores of the current processing core where the neuron is located, Figure 6As shown, taking neuron B1 as the current neuron of the current processing core B, and the target neurons in the target processing core A including 4 target neurons (target neuron A1 to target neuron A4) as an example for explanation, neuron B1 of the current processing core B has a connection relationship with target neurons A1 to target neurons A4, wherein neuron B1 and target neuron A1 have a connection weight and are recorded as weight value 1, neuron B1 and target neuron A4 have a connection weight and are recorded as weight value 2, while neuron B1 and target neuron A2 do not have a connection weight, and neuron B1 and target neuron A3 do not have a connection weight, so the connection identification information of the weight data corresponding to neuron B1 includes "1001", combined with Figure 5 In the off-chip storage structure, in the storage area corresponding to the neuron B1 of the current processing core B, in the weight data configuration area corresponding to the target processing core A connected to the neuron B1, the connection identification part stores "1001" correspondingly, and the weight part stores weight value 1 and weight value 2 correspondingly.

[0067] For example, when the target processing cores connected to the neuron are all the successor processing cores of the current processing core where the neuron is located, Figure 6 As shown, taking neuron A1 as the current neuron of the current processing core A, and the target neurons in the target processing core B including three target neurons (target neuron B1 to target neuron B3) as an example, neuron A1 of the current processing core A has a connection relationship with target neurons B1 to target neurons B3, wherein neuron A1 and target neuron B1 have a connection weight and are recorded as weight value 3, and neuron A1 and target neurons B2 and B3 do not have a connection weight, so the connection identification information of the weight data corresponding to neuron A1 includes "100", combined with Figure 5 In the off-chip storage structure, in the storage area corresponding to the neuron A1 of the current processing core A, in the weight data configuration area corresponding to the target processing core B connected to the neuron A1, the connection identification part stores "100" and the weight part stores the weight value 3.

[0068] In some embodiments, the weight data corresponding to each neuron is stored in the form of a weight data packet. Figure 7 for Figure 3 A flowchart of another specific implementation method of step S1 in FIG. Figure 7 As shown, step S1 may further include: step S111 and step S112.

[0069] Step S111: Generate a weight data packet corresponding to each neuron according to the weight data corresponding to each neuron.

[0070] Figure 8 This is a schematic diagram of the format of the weight data packet, such as Figure 8 As shown, the weight data packet includes: a header part set in sequence, a weight data configuration part corresponding to each target processing core (such as target processing core 1, target processing core 2) connected to the neuron, and the weight data configuration part corresponding to each target processing core includes a connection identification part and a weight part.

[0071] The header part is used to configure the number of target processing cores connected to the neuron, the core identifier of each target processing core connected to the neuron, and the length information of the corresponding weight data configuration part. In the header part, the number of target processing cores connected to the neuron and the core identifier of each target processing core connected to the neuron can be represented by binary numbers. For example, if the number is 1, the corresponding binary number is 0001, and the core identifier is "2", the corresponding binary number is 0010.

[0072] In the weight data configuration part corresponding to each target processing core, the connection identification part is used to configure the connection identification information corresponding to the target processing core connected to the neuron, and the weight part is used to configure the connection weight corresponding to the first connection identification in the connection identification information.

[0073] For example, combined with Figure 6 , taking neuron B1 of the current processing core B as an example, the number of target processing cores connected to neuron B1 is 1, that is, target processing core A, the core identifier of target processing core A is "2", and the connection identifier information corresponding to neuron B1 is "1001", and the corresponding connection weights are weight value 1 and weight value 2 respectively. The weight data packet corresponding to neuron B1 is shown in Table 1.

[0074] Table 1

[0075] 0001, 0010, length 1 1001 Weight value 1, Weight value 2

[0076] Among them, 0001 represents the number of target processing cores connected to neuron B1, that is, 1; 0010 represents the core identifier of the target processing core A connected to neuron B1, that is, "2"; length 1 represents the length information of the weight data configuration part in the weight data packet shown in Table 1. In the connection identifier part, 1001 represents the connection identifier information corresponding to neuron B1, specifically indicating that there is a connection weight between neuron B1 and the target neurons A1 and A4 of the target processing core A, and there is no connection weight between neuron B1 and the target neurons A2 and A3 of the target processing core A. In the weight part, the weight value 1 represents the corresponding connection weight between neuron B1 and the target neuron A1 of the target processing core A, and the weight value 2 represents the corresponding connection weight between neuron B1 and the target neuron A4 of the target processing core A.

[0077] Figure 6The example only shows a situation where a neuron of the current processing core is connected to a target processing core, and the embodiments of the present disclosure include but are not limited to this. In some embodiments, a neuron of the current processing core may also have an interconnection relationship with multiple target processing cores. Fig. 9 It is a schematic diagram of the connection relationship between the current processing core and multiple connected target processing cores, such as Fig. 9 As shown, neuron A1 is interconnected with neurons B1 to B4 and neurons C1 to C3, wherein neuron A1 is located in the current processing core A, neurons C1 to C3 are located in the target processing core C, and neurons B1 to B4 are located in the target processing core B.

[0078] by Fig. 9 Taking neuron A1 of the current processing core A as an example, the number of target processing cores connected to neuron A1 is 2, namely target processing cores B and C. The core identifier of target processing core C is "2", and the core identifier of target processing core B is "3". The corresponding connection identification information between neuron A1 and target processing core C is "100", and the corresponding connection weight is a weight value of 4. The corresponding connection identification information between neuron A1 and target processing core B is "0010", and the corresponding connection weight is a weight value of 5. The weight data packet corresponding to neuron A1 is shown in Table 2.

[0079] Table 2

[0080]

[0081] Among them, from left to right, the first "0010" represents the number of target processing cores connected to neuron A1, that is, 2; the second "0010" represents the core identifier of the target processing core C connected to neuron A1, that is, "2"; "0011" represents the core identifier of the target processing core B connected to neuron A1, that is, "3"; the length 1 represents the length information of the weight data configuration part corresponding to the target processing core C connected to neuron A1. In the connection identifier part of the weight data configuration part corresponding to the target processing core C, 100 represents the connection identifier information corresponding to neuron A1, which specifically indicates that there is a connection weight between neuron A1 and the target neuron C1 of the target processing core C, and there is a connection weight between neuron A1 and the target neurons C2 and C3 of the target processing core C. It has no connection weight. In the weight part, the weight value 4 represents the corresponding connection weight between neuron A1 and the target neuron C1 of the target processing core C; the length 2 represents the length information of the weight data configuration part corresponding to the target processing core B connected to neuron A1. In the connection identification part of the weight data configuration part corresponding to the target processing core B, 0010 represents the connection identification information corresponding to neuron A1, which specifically indicates that there is a connection weight between neuron A1 and the target neuron B3 of the target processing core B, and there is no connection weight between neuron A1 and the target neurons B1, B2, and B4 of the target processing core B. In the weight part, the weight value 5 represents the corresponding connection weight between neuron A1 and the target neuron B3 of the target processing core B.

[0082] Step S112: store the weight data packet corresponding to each neuron into an off-chip storage structure, and generate corresponding weight index information.

[0083] Specifically, based on the storage status of the weight data packet corresponding to the neuron in the off-chip storage structure (such as the storage address and length of the weight data packet corresponding to the neuron), the weight index information of the weight data packet corresponding to the neuron in the off-chip storage structure is generated to facilitate reading the corresponding weight data packet from the off-chip storage structure.

[0084] Fig.10 Schematic diagram of the transmission process of the weight data corresponding to the neuron. In some embodiments, the weight data corresponding to the neuron is stored in the off-chip storage structure in the form of a weight data packet, and the weight data corresponding to the neuron is the weight data corresponding to the neuron and the subsequent processing core. Fig.10As shown, when the current membrane potential of neuron A1 of the current processing core A reaches the membrane potential threshold and needs to be issued to the subsequent processing core B and the subsequent processing core C, the weight data packet corresponding to neuron A1 can be read from the off-chip storage structure according to the weight index information corresponding to neuron A1 stored in the on-chip storage structure. The weight data packet can be cached in the on-chip storage structure. By parsing the weight data packet, the weight data to be issued to the subsequent processing core B and the weight data to be issued to the subsequent processing core C can be determined. For example, the weight data to be issued to the subsequent processing core B includes the connection identification information of "0010" and the weight information of the weight value 5, and the weight data to be issued to the subsequent processing core C includes the connection identification information of "100" and the weight information of the weight value 4.

[0085] Then, the weight data to be issued to the subsequent processing core B and the issuance information (pulse data) of neuron A1 are packaged and transmitted to the subsequent processing core B through the corresponding routing node. The subsequent processing core B can determine the issuance of neuron A1 of the current processing core A based on the received data. Neuron A1 has a connection weight with neuron B3 of the current processing core B, and the connection weight is a weight value of 5, so that the membrane potential integral operation of neuron B3 can be performed subsequently.

[0086] Similarly, the weight data to be issued to the subsequent processing core C and the issuance information (pulse data) of neuron A1 are packaged and transmitted to the subsequent processing core C through the corresponding routing node. The subsequent processing core C can determine the issuance of neuron A1 of the current processing core A based on the received data. Neuron A1 has a connection weight with neuron C1 of the current processing core C, and the connection weight is a weight value of 4, so that the membrane potential integral operation of neuron C1 can be performed subsequently.

[0087] The membrane potential integral operation process may include: weighting and summing the pulse data connected to the neuron according to the corresponding connection weight to obtain the integral potential of the neuron. After the membrane potential integral operation process is performed, it also includes: a discharge calculation process. The discharge calculation process may include: adding the integral potential of the neuron to the corresponding historical membrane potential to update the membrane potential of the neuron, and when the updated membrane potential exceeds the preset membrane potential threshold, it is determined that the neuron discharges pulse data, otherwise it is determined that the neuron does not discharge pulse data.

[0088] Among them, the pulse data emitted by the neuron can be encoded as three-value data, for example, 0, 1 and -1, which can be used to describe the neuron in the state of no action, activation and inhibition respectively. In the embodiment of the present disclosure, neuron firing means that the value of the emitted pulse data is 1 or -1, and 0 means no firing.

[0089] In the case where the weight data corresponding to the neuron is the weight data corresponding to the neuron and the previous processing core, the data packet issued by the previous processing core to the neuron of the current processing core may include but is not limited to issuance information (pulse data) and the core identifier of the current processing core, and the identifier of the neuron of the current processing core. After the current processing core receives and parses the data packet issued by the previous processing core, it can determine the identifier of the neuron in the current core corresponding to this issuance, that is, the identifier of the neuron that needs to perform membrane potential update subsequently, thereby reading the weight index information corresponding to the neuron from the on-chip storage structure, reading the corresponding weight data packet from the off-chip storage structure according to the weight index information, and parsing the weight data packet to obtain the weight data corresponding to the neuron and the previous processing core. Subsequently, the above-mentioned membrane potential integration operation process can be performed on the neuron based on the weight data corresponding to the neuron.

[0090] Fig.11 A structural diagram of a weight data storage device provided in an embodiment of the present disclosure is shown as follows: Fig.11 As shown, an embodiment of the present disclosure provides a weight data storage device 200, which is applied to a neuromorphic chip. The neuromorphic chip includes an on-chip storage structure and multiple processing cores, each processing core includes multiple neurons, and the weight data storage device 200 includes: a first storage execution module 201 and a second storage execution module 202.

[0091] The first storage execution module 201 is configured to store the weight data corresponding to each neuron in an off-chip storage structure, which is located outside the neuromorphic chip; and the second storage execution module 202 is configured to store the weight index information corresponding to each neuron in a corresponding on-chip storage structure. The weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure.

[0092] In addition, the various modules of the weight data storage device 200 provided in the embodiment of the present disclosure are specifically used to implement the weight data storage method provided in the above-mentioned embodiment. For the specific description of the various modules of the weight data storage device 200, please refer to the description of the weight data storage method in the above-mentioned embodiment, which will not be repeated here.

[0093] The disclosed embodiments further provide a neuromorphic chip, which includes a plurality of processing cores and a weight data storage device, each processing core including a plurality of neurons, and the weight data storage device including the above-mentioned weight data storage device.

[0094] Fig.12 A block diagram of a composition of an electronic device provided in an embodiment of the present disclosure.

[0095] Reference Fig.12An embodiment of the present disclosure provides an electronic device, which includes: at least one processor 301; and a memory 302 that is communicatively connected to the at least one processor 301; wherein the memory 302 stores one or more computer programs that can be executed by the at least one processor 301, and the one or more computer programs are executed by the at least one processor 301 so that the at least one processor 301 can execute the above-mentioned weight data storage method.

[0096] In addition, an embodiment of the present disclosure further provides a computer-readable medium on which a computer program is stored, wherein the computer program implements the above-mentioned weight data storage method when executed by a processor.

[0097] The embodiments of the present disclosure also provide a computer program product, which includes a computer program, and the computer program implements the above-mentioned weight data storage method when executed by a processor.

[0098] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0099] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A weight data storage method, applied to a neuromorphic chip, wherein the neuromorphic chip includes an on-chip storage structure and multiple processing cores, each processing core includes multiple neurons, and the weight data storage method includes: The weight data corresponding to each of the neurons is stored in an off-chip storage structure, the off-chip storage structure is located outside the neuromorphic chip, the off-chip storage structure includes a plurality of storage areas, each storage area corresponds to a neuron, each storage area includes at least one weight data configuration area, each weight data configuration area corresponds to a target processing core connected to the neuron; as well as Storing the weight index information corresponding to each of the neurons into the corresponding on-chip storage structure; Wherein, the weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure; In the case where the weight data corresponding to each neuron is stored in the form of a storage area, the weight data configuration area includes a connection identification part and a weight part, the connection identification part is used to configure the connection identification information corresponding to the target processing core connected to the neuron corresponding to the weight data configuration area, and the weight part is used to configure the connection weight corresponding to the first connection identification in the connection identification information.

2. According to the weight data storage method of claim 1, wherein a plurality of the processing cores are correspondingly provided with an on-chip storage structure, or, each of the processing cores is correspondingly provided with an on-chip storage structure.

3. The weight data storage method according to claim 1, wherein the weight index information includes the starting storage address and length information of the weight data corresponding to the neuron in the off-chip storage structure.

4. The weight data storage method according to claim 1, wherein storing the weight data corresponding to each neuron into an off-chip storage structure comprises: For each of the neurons, storing the corresponding weight data between the neuron and the corresponding target processing core in a corresponding storage area; In the storage area corresponding to the neuron, the weight data corresponding to the neuron and each corresponding target processing core are sequentially stored in the corresponding weight data configuration area; Generate the weight index information corresponding to the neuron.

5. The weight data storage method according to claim 1, wherein storing the weight data corresponding to each neuron into an off-chip storage structure comprises: Generate a weight data packet corresponding to each neuron according to the weight data corresponding to each neuron; The weight data packet corresponding to each neuron is stored in the off-chip storage structure, and the corresponding weight index information is generated.

6. The weight data storage method according to claim 4 or 5, wherein the weight data comprises connection identification information and weight information; The connection identification information includes a plurality of connection identifications, each of the connection identifications corresponds to a target neuron in a target processing core connected to the neuron, the plurality of connection identifications include at least one first connection identification and at least one second connection identification, the first connection identification indicates that there is a connection weight between the neuron and the target neuron in the target processing core, and the second connection identification indicates that there is no connection weight between the neuron and the target neuron in the target processing core; The weight information includes a connection weight corresponding to the first connection identifier.

7. The weight data storage method according to claim 6, wherein when the weight data corresponding to each neuron is stored in the form of a weight data packet, The weight data packet includes: A packet header part and a weight data configuration part corresponding to each target processing core connected to the neuron are sequentially arranged, wherein the weight data configuration part corresponding to each target processing core includes a connection identification part and a weight part; The header part is used to configure the number of target processing cores connected to the neuron, the core identifier of each target processing core connected to the neuron, and the length information of the corresponding weight data configuration part; In the weight data configuration part corresponding to each target processing core, the connection identification part is used to configure the connection identification information corresponding to the target processing core connected to the neuron, and the weight part is used to configure the connection weight corresponding to the first connection identification in the connection identification information.

8. The weight data storage method according to claim 6, wherein the neuromorphic chip is used to run a spiking neural network; For each neuron, the target processing cores connected to the neuron are all the predecessor processing cores of the current processing core where the neuron is located, or the target processing cores connected to the neuron are all the successor processing cores of the current processing core where the neuron is located; The predecessor processing core is a processing core connected to the current processing core and located in the network structure layer before the network structure layer where the current processing core is located; the successor processing core is a processing core connected to the current processing core and located in the network structure layer below the network structure layer where the current processing core is located.

9. A weight data storage device, applied to a neuromorphic chip, wherein the neuromorphic chip comprises an on-chip storage structure and a plurality of processing cores, each processing core comprising a plurality of neurons; The weight data storage device comprises: A first storage execution module is configured to store the weight data corresponding to each of the neurons to an off-chip storage structure, the off-chip storage structure is located outside the neuromorphic chip, the off-chip storage structure includes a plurality of storage areas, each storage area corresponds to one of the neurons, each storage area includes at least one weight data configuration area, each weight data configuration area corresponds to a target processing core connected to the neuron; and A second storage execution module is configured to store the weight index information corresponding to each of the neurons into the corresponding on-chip storage structure; Wherein, the weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure; In the case where the weight data corresponding to each neuron is stored in the form of a storage area, the weight data configuration area includes a connection identification part and a weight part, the connection identification part is used to configure the connection identification information corresponding to the target processing core connected to the neuron corresponding to the weight data configuration area, and the weight part is used to configure the connection weight corresponding to the first connection identification in the connection identification information.

10. A neuromorphic chip comprising a plurality of processing cores and a weight data storage device, each processing core comprising a plurality of neurons, and the weight data storage device comprising the weight data storage device of claim 9.

11. An electronic device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor so that the at least one processor can execute the weight data storage method described in any one of claims 1-8.

12. A computer readable medium having a computer program stored thereon, wherein: When the computer program is executed by a processor, the computer program implements the weight data storage method according to any one of claims 1 to 8.

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