Display panel and display device

Abstract

The present application discloses a display panel and a display device. The display panel includes a plurality of pixel circuits, a sampling circuit, a timing controller, and a system-on-chip. Through the sampling circuit and the timing controller, the source potential of the driving transistor in each pixel circuit can be obtained, and according to a new algorithm configured in the timing controller, when a combustion risk is detected, the power-on state of the display panel can be controlled by the system-on-chip. This not only reduces the number and cost of hardware circuits used, but also enables the combustion risk monitoring to be detailed to each pixel circuit, and the parameter adjustment in the algorithm is simpler and more convenient.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the increasing demand for large-sized display screens and the growing requirements of consumers for screen refresh rates and display effects, the drive system of a display screen needs to integrate more functional / algorithm modules, and its power consumption also increases rapidly synchronously. The high power consumption will inevitably bring a larger current. In this case, the risk of overheating and damage of electronic components (including drive chips, etc.) within the above drive system increases accordingly, thereby bringing a risk of combustion.

[0003] However, most of the existing methods for monitoring the combustion of a display screen determine whether there is a combustion risk by monitoring the potential of a power bus through a large number of hardware circuits. In this way, the hardware circuits not only increase the cost but also are inconvenient to adjust their parameters; at the same time, this combustion monitoring method cannot specifically detect the detailed combustion risk of each pixel circuit. Summary of the Invention

[0004] This application provides a display panel and a display device, which are used to alleviate the technical problem that a large number of hardware circuits are required to monitor the combustion risk of each pixel circuit.

[0005] In a first aspect, this application provides a display panel, which includes a plurality of pixel circuits, a sampling circuit, a timing controller, and a system-on-chip. The pixel circuit includes a driving transistor; the sampling circuit is electrically connected to the source electrodes of at least one driving transistor; the timing controller is electrically connected to the sampling circuit and is used to output a corresponding power enable signal according to the abnormal number of the source electrode potentials of the driving transistors; the system-on-chip is electrically connected to the timing controller and is used to control the power-on state of the display panel according to the power enable signal.

[0006] In some embodiments, the power-on state includes a system power-off state. In response to the abnormal number of the source electrode potentials of the driving transistors being greater than or equal to a preset number, the power enable signal enables the system-on-chip to control the display panel to be in the system power-off state.

[0007] In some embodiments, the power-on state further includes a system power supply state. In response to the abnormal number of the source electrode potentials of the driving transistors being less than the preset number, the power enable signal enables the system-on-chip to control the display panel to be in the system power supply state.

[0008] In some embodiments, the timing controller determines whether the source electrode potential of a driving transistor is in an abnormal state according to the difference between the source electrode potential of a driving transistor and the source electrode potentials of at least two other driving transistors, and determines the abnormal number based on the number of driving transistors whose source electrode potentials are in an abnormal state.

[0009] In some of these embodiments, the timing controller determines that the source potential of the driving transistor is in an abnormal state in response to the difference being greater than or equal to a preset potential; and the timing controller determines that the source potential of the driving transistor is in a normal state in response to the difference being less than the preset potential.

[0010] In some of these embodiments, the pixel circuit further includes a switching transistor, a sensing transistor, and a light-emitting device. One of the source / drain of the switching transistor is electrically connected to the data line, and the other of the source / drain of the switching transistor is electrically connected to the gate of the driving transistor. The gate of the switching transistor is electrically connected to the first control line. One of the source / drain of the sensing transistor is electrically connected to the source of the driving transistor, and the other of the source / drain of the sensing transistor is electrically connected to the sampling circuit. The gate of the sensing transistor is electrically connected to the second control line. The anode of the light-emitting device is electrically connected to the source of the driving transistor, and the cathode of the light-emitting device is electrically connected to the negative power supply line. Wherein, the drain of the driving transistor is electrically connected to the positive power supply line.

[0011] In some of these embodiments, the display panel further includes a first trace and a second trace. A first trace is electrically connected to the other of the source / drain of at least three sensing transistors. A second trace is electrically connected to an input terminal of the sampling circuit and at least one first trace. Wherein, the extending direction of the first trace is different from that of the second trace.

[0012] In some of these embodiments, the same first trace is electrically connected to at least three pixel circuits, and the at least three pixel circuits are located in the same row and are adjacent to each other in sequence.

[0013] In some of these embodiments, the system-on-chip includes an external power supply, a power management circuit, and a switching circuit. The power management circuit is configured to provide various power supply voltages for the display panel. The input terminal of the switching circuit is electrically connected to the external power supply, the output terminal of the switching circuit is electrically connected to the power management circuit, and the control terminal of the switching circuit is electrically connected to the timing controller to control the conduction state or the off state of the transmission path between the external power supply and the power management circuit according to the power enable signal.

[0014] In a second aspect, the present application provides a display device, which includes the display panel in at least one of the above embodiments. Wherein, the pixel circuit further includes a storage capacitor, one end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is electrically connected to the source of the driving transistor.

[0015] The display panel and the display device provided by the present application can obtain the source potential of the driving transistor in each pixel circuit through a sampling circuit and a timing controller, and according to the new algorithm configured in the timing controller, the power-on state of the display panel can be controlled by the system-on-chip when a combustion risk is detected. This not only reduces the number and cost of hardware circuits, but also enables the combustion risk monitoring to be detailed to each pixel circuit, and the parameter adjustment in the algorithm is simpler and more convenient. Brief Description of the Drawings

[0016] The technical solutions and other beneficial effects of the present application will become apparent by describing the specific embodiments of the present application in detail with reference to the accompanying drawings.

[0017] Figure 1 It is a schematic structural diagram of a display panel in the related art.

[0018] Figure 2 It is a schematic structural diagram of the display panel provided by an embodiment of the present application.

[0019] Figure 3 It is a schematic structural diagram of the pixel circuit provided by an embodiment of the present application. Detailed Description of the Embodiments

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0021] Most of the above-mentioned combustion monitoring methods for display screens determine whether there is a combustion risk by monitoring the potential of the power bus through a large number of hardware circuits. In this way, the hardware circuits will not only increase the cost but also be inconvenient to adjust their parameters; at the same time, this combustion monitoring method cannot specifically detect the detailed combustion risk of each pixel circuit 90. For example Figure 1As shown, the display screen includes a sensing unit 10, a sampling circuit 20, a timing controller 30, a power management circuit 50, and an external power supply 40. The sensing unit 10 is used to detect the potential of the positive power signal OVDD and / or the potential of the negative power signal OVSS in real time. The output end of the sensing unit 10 is electrically connected to the input end of the sampling circuit 20. The sampling circuit 20 is used to convert an analog signal into a corresponding digital signal. The output end of the sampling circuit 20 is electrically connected to the input end of the timing controller 30. The timing controller 30 is used to determine the combustion risk according to the comparison result between the potential of the positive power signal OVDD and / or the potential of the negative power signal OVSS and a preset potential. The output end of the timing controller 30 is electrically connected to the external power supply 40 to control whether the external power supply 40 provides power to the power management circuit 50. The output end of the external power supply 40 is electrically connected to the input end of the power management circuit 50. The output end of the power management circuit 50 is electrically connected to the sampling circuit 20 and the timing controller 30 to provide corresponding power voltages to the sampling circuit 20 and the timing controller 30.

[0022] It can be seen from this that the display screen requires a large number of hardware circuits such as the sensing unit 10 and the sampling circuit 20 to transmit and process the detected potential of the positive power signal OVDD and / or the potential of the negative power signal OVSS. This not only increases the cost but also has problems such as inconvenient parameter adjustment of the hardware circuit. In addition, it only judges the combustion risk by monitoring the positive power signal OVDD and / or the negative power signal OVSS transmitted in the power bus. Each power bus continuously supplies power to a plurality of pixel circuits 90. Therefore, it can only monitor the combustion risk of the display screen as a whole and is difficult to monitor the combustion risk of each pixel circuit 90. That is, the fineness of the combustion risk monitoring needs to be further improved.

[0023] In view of this, this embodiment provides a display panel. Please refer to Figures 2 to 3 , as Figure 2 shown, the display panel includes a plurality of pixel circuits 90, a sampling circuit 20, a timing controller 30, and a system on chip 100. The pixel circuit 90 includes a driving transistor T1. The sampling circuit 20 is electrically connected to the source electrode of at least one driving transistor T1. The timing controller 30 is electrically connected to the sampling circuit 20 and is used to output a corresponding power enable signal according to the abnormal number of the source electrode potentials of the driving transistors T1. The system on chip 100 is electrically connected to the timing controller 30 and is used to control the power-on state of the display panel according to the power enable signal.

[0024] It can be understood that for the display panel provided in this embodiment, the source potential of the driving transistor T1 in each pixel circuit 90 can be obtained through the sampling circuit 20 and the timing controller 30, and according to the new algorithm configured in the timing controller 30, the power-on state of the display panel can be controlled by the system-on-chip 100 when a combustion risk is detected. This not only reduces the number and cost of hardware circuits used, but also enables the combustion risk monitoring to be detailed to each pixel circuit 90, and the parameter adjustment in the algorithm is simpler and more convenient.

[0025] It should be noted that the above power-on state can include the system power-off state and the system power supply state. Among them, the system power-off state means that the external power supply 40 stops supplying power to the power management circuit 50. At this time, all the electronic components in the display panel are in an uncharged state. The system power supply state means that the external power supply 40 supplies power to the power management circuit 50. At this time, the corresponding electronic components in the display panel are in a charged state.

[0026] Among them, the sampling circuit 20 can be used to convert analog signals into corresponding digital signals to adapt to the signal types that the timing controller 30 can process. The sampling circuit 20 can be integrated into the timing controller 30 to further reduce the area or space occupied by the sampling circuit 20 and the timing controller 30 in the display panel.

[0027] Among them, the power management circuit 50 can also be a power management integrated circuit (PMIC, Power Management IC), which can further reduce the occupied area or space in the display panel.

[0028] In one embodiment, in response to the number of abnormal source potentials of the driving transistor T1 being greater than or equal to a preset number, the power enable signal enables the system-on-chip 100 to control the display panel to be in the system power-off state.

[0029] It should be noted that the preset number can be one or more. As the number of abnormal source potentials of the driving transistor T1 increases, the power consumed by the display panel also increases, and the corresponding current also continuously increases, and the combustion risk of the display panel also increases. Therefore, the preset number can be reasonably set according to needs. A smaller preset number can detect the combustion risk more sensitively, while an overly large preset number will continuously accumulate the combustion risk.

[0030] In one embodiment, in response to the number of abnormal source potentials of the driving transistor T1 being less than the preset number, the power enable signal enables the system-on-chip 100 to control the display panel to be in the system power supply state.

[0031] In one embodiment, the timing controller 30 determines whether the source potential of a driving transistor T1 is in an abnormal state according to the difference between the source potential of the driving transistor T1 and the source potentials of at least two other driving transistors T1, and determines the number of abnormalities based on the number of driving transistors T1 whose source potentials are in an abnormal state.

[0032] It can be understood that the timing controller 30 can also determine whether the source potential of a driving transistor T1 is in an abnormal state according to the difference between the source potential of a driving transistor T1 and the source potential of at least one other driving transistor T1, and determine the number of abnormalities based on the number of driving transistors T1 whose source potentials are in an abnormal state. However, this method will reduce the accuracy of determining the abnormal state. That is to say, the more the number of times the source potential of a driving transistor T1 is compared one by one with the source potentials of other driving transistors T1, the higher the accuracy of whether the source potential of this driving transistor T1 is in an abnormal state.

[0033] Preferably, the above-mentioned at least two other driving transistors T1 are located around the above-mentioned one driving transistor T1 in the planar space of the display panel, or the above-mentioned at least two other driving transistors T1 are adjacent to the above-mentioned one driving transistor T1 in the planar space of the display panel. It can be understood that the source potentials of adjacent driving transistors T1 are closer in the normal state. Therefore, when determining whether it is in an abnormal state and using it as a reference object, the accuracy of determining the abnormal state can be further improved.

[0034] In one embodiment, the timing controller 30 determines that the source potential of the driving transistor T1 is in an abnormal state in response to the difference being greater than or equal to a preset potential; the timing controller 30 determines that the source potential of the driving transistor T1 is in a normal state in response to the difference being less than the preset potential.

[0035] It should be noted that due to the influence of transmission paths, electrical coupling, etc. in the display panel, there will be some differences in the source potentials of different driving transistors T1. Therefore, reasonably setting the preset potential can ignore some influencing factors and further improve the accuracy of determining whether the source potential of the driving transistor T1 is in an abnormal state or a normal state.

[0036] It can be understood that parameters such as the above-mentioned preset quantity and preset potential can be modified or set in the timing controller 30, which is simpler, more convenient and faster compared with adjusting the hardware circuit.

[0037] In one embodiment, as Figure 2As shown, the above pixel circuit 90 further includes a switching transistor T2, a sensing transistor T3, and a light-emitting device D1. One of the source / drain electrodes of the switching transistor T2 is electrically connected to the data line, and the other of the source / drain electrodes of the switching transistor T2 is electrically connected to the gate of the driving transistor T1. The gate of the switching transistor T2 is electrically connected to the first control line; one of the source / drain electrodes of the sensing transistor T3 is electrically connected to the source of the driving transistor T1, and the other of the source / drain electrodes of the sensing transistor T3 is electrically connected to the sampling circuit 20. The gate of the sensing transistor T3 is electrically connected to the second control line; the anode of the light-emitting device D1 is electrically connected to the source of the driving transistor T1, and the cathode of the light-emitting device D1 is electrically connected to the negative power supply line; wherein, the drain of the driving transistor T1 is electrically connected to the positive power supply line.

[0038] It should be noted that the pixel circuit 90 in this embodiment is an externally compensated pixel circuit 90, and the above architectures are all existing structures of the pixel circuit 90. Therefore, the handling of the combustion risk in this application can be achieved without adding new hardware circuits. The pixel circuit 90 in this embodiment can be applied to a backlight module to provide corresponding backlight for a liquid crystal display panel.

[0039] Among them, the data line can be used to transmit a data signal Data. The first control line can be used to transmit a first scan signal WR. The second control line can be used to transmit a second scan signal RD. The negative power supply line can be used to transmit a power negative signal OVSS. The positive power supply line can be used to transmit a power positive signal OVDD.

[0040] Among them, the light-emitting device D1 can be one of an organic light-emitting diode, a micro light-emitting diode, a mini light-emitting diode, or a quantum dot light-emitting diode.

[0041] Among them, the driving transistor T1, the switching transistor T2, and the sensing transistor T3 can each be any one of an N-channel thin-film transistor and a P-channel thin-film transistor.

[0042] In one embodiment, the display panel further includes a first trace 80 and a second trace 70. One first trace 80 is electrically connected to the other of the source / drain electrodes of at least three sensing transistors T3; one second trace 70 is electrically connected to an input terminal of the sampling circuit 20 and at least one first trace 80; wherein, the extending direction of the first trace 80 is different from the extending direction of the second trace 70.

[0043] It can be understood that a first trace 80 is electrically connected to another one of the source / drains of at least three sensing transistors T3, which can save the number of uses of the first trace 80 in the display panel, reduce the occupied area in the display area of the display panel, and is beneficial to improving the aperture ratio. A second trace 70 is electrically connected to at least one first trace 80, which can save the number of uses of the second trace 70 in the display panel, reduce the occupied area in the display area of the display panel, and is beneficial to further improving the aperture ratio.

[0044] In one embodiment, the same first trace 80 is electrically connected to at least three pixel circuits 90, and the at least three pixel circuits 90 are located in the same row and are adjacent in sequence.

[0045] It should be noted that at least three pixel circuits 90 can form a pixel unit. One of the pixel circuits 90 can be configured as a red sub-pixel, another one of the pixel circuits 90 can be configured as a green sub-pixel, and yet another one of the pixel circuits 90 can be configured as a blue sub-pixel. The at least three pixel circuits 90 are located in the same row and are adjacent in sequence, which is beneficial to shortening the trace trajectory or trace path of the first trace 80.

[0046] In one embodiment, the system-on-chip 100 includes an external power supply 40, a power management circuit 50, and a switching circuit 60. The power management circuit 50 is used to provide various power supply voltages for the display panel. The input end of the switching circuit 60 is electrically connected to the external power supply 40, the output end of the switching circuit 60 is electrically connected to the power management circuit 50, and the control end of the switching circuit 60 is electrically connected to the timing controller 30 to control the transmission path between the external power supply 40 and the power management circuit 50 to be in a conducting state or a cut-off state according to a power enable signal.

[0047] It should be noted that the power enable signal can control the transmission path between the external power supply 40 and the power management circuit 50 to be in a conducting state when in a high potential state, and the power enable signal can control the transmission path between the external power supply 40 and the power management circuit 50 to be in a cut-off state when in a low potential state. Or, the power enable signal can control the transmission path between the external power supply 40 and the power management circuit 50 to be in a conducting state when in a low potential state, and the power enable signal can control the transmission path between the external power supply 40 and the power management circuit 50 to be in a cut-off state when in a high potential state.

[0048] In one embodiment, Figure 1 Or Figure 2 the sampling circuit 20 in Figure 3 can be the analog-to-digital converter 21 in

[0049] In one embodiment, asFigure 3 As shown, the above pixel circuit 90 may further include a first switch K1 and a second switch K2. One end of the first switch K1 is electrically connected to the other of the source / drain of the second switch K2 and the sensing transistor T3. The other end of the first switch K1 is electrically connected to the input end of the analog-to-digital converter 21. The other end of the second switch K2 is electrically connected to the reference voltage terminal, which is used to transmit the reference voltage signal Vref. The output end of the analog-to-digital converter 21 is electrically connected to the controller for external compensation.

[0050] It can be understood that when the corresponding control signal controls the control end of the first switch K1 and / or the control end of the second switch K2, the reference voltage signal Vref can be transmitted to the other of the source / drain of the sensing transistor T3 through the second switch K2, and the source potential of the driving transistor T1 can be read through the sensing transistor T3 and the first switch K1. It should be noted that in this embodiment, the source potential of the driving transistor T1 can be used for both the external compensation of the pixel circuit 90 and the determination and protection of the combustion risk.

[0051] As Figure 3 shown, one of the combustion risks is that the driving transistor T1 is short-circuited, that is, the source of the driving transistor T1 is short-circuited to the drain of the driving transistor T1, resulting in the light-emitting device D1 being in a constant-on state. This is only an example of causing the combustion risk, and it does not limit the combustion risk to only this case. It can also be other nodes in the pixel circuit 90.

[0052] In one embodiment, this embodiment provides a display device. As Figure 2 or Figure 3 shown, the display device includes the display panel in the above at least one embodiment. Among them, the pixel circuit 90 further includes a storage capacitor Cst. One end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and the other end of the storage capacitor Cst is electrically connected to the source of the driving transistor T1.

[0053] It can be understood that for the display device provided in this embodiment, the source potential of the driving transistor T1 in each pixel circuit 90 can be obtained through the sampling circuit 20 and the timing controller 30, and according to the new algorithm configured in the timing controller 30, the power-on state of the display panel can be controlled by the system-on-chip 100 when the combustion risk is detected. This not only reduces the number and cost of the hardware circuits used, but also the combustion risk monitoring can be detailed to each pixel circuit 90, and the parameter adjustment in the algorithm is simpler and more convenient.

[0054] It should be noted that the pixel circuit 90 provided in this embodiment can be applied as a sub-pixel for displaying an image in the display panel.

[0055] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0056] The display panel and the display device provided by the embodiments of the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, Comprising: A plurality of pixel circuits, the pixel circuits including driving transistors; A sampling circuit electrically connected to the source of at least one of the driving transistors; A timing controller electrically connected to the sampling circuit for outputting a corresponding power enable signal according to the number of anomalies in the source potential of the driving transistors; And A system-on-chip electrically connected to the timing controller for controlling the power-on state of the display panel according to the power enable signal; wherein the power-on state includes a system power-off state and a system power supply state.

2. The display panel according to claim 1, wherein In response to the number of anomalies in the source potential of the driving transistors being greater than or equal to a preset number, the power enable signal enables the system-on-chip to control the display panel to be in the system power-off state.

3. The display panel according to claim 2, wherein In response to the number of anomalies in the source potential of the driving transistors being less than the preset number, the power enable signal enables the system-on-chip to control the display panel to be in the system power supply state.

4. The display panel according to claim 1, wherein The timing controller determines whether the source potential of a driving transistor is in an abnormal state according to the difference between the source potential of one driving transistor and the source potentials of at least two other driving transistors, and determines the number of anomalies based on the number of driving transistors whose source potentials are in an abnormal state.

5. The display panel according to claim 4, wherein, The timing controller determines that the source potential of the driving transistor is in an abnormal state in response to the difference being greater than or equal to a preset potential; The timing controller determines that the source potential of the driving transistor is in a normal state in response to the difference being less than the preset potential.

6. The display panel according to claim 1, wherein The pixel circuit further includes: A switching transistor, one of the source / drain of the switching transistor being electrically connected to a data line, the other of the source / drain of the switching transistor being electrically connected to the gate of the driving transistor, and the gate of the switching transistor being electrically connected to a first control line; A sensing transistor, one of the source / drain of the sensing transistor being electrically connected to the source of the driving transistor, the other of the source / drain of the sensing transistor being electrically connected to the sampling circuit, and the gate of the sensing transistor being electrically connected to a second control line; and A light-emitting device, the anode of the light-emitting device being electrically connected to the source of the driving transistor, and the cathode of the light-emitting device being electrically connected to a negative power supply line; Wherein the drain of the driving transistor is electrically connected to a positive power supply line.

7. The display panel according to claim 6, characterized in that, The display panel further includes: A first trace, one of the first traces being electrically connected to the other of the source / drain of at least three of the sensing transistors; and A second trace, one of the second traces being electrically connected to an input terminal of the sampling circuit and at least one of the first traces; Wherein the extending direction of the first trace is different from the extending direction of the second trace.

8. The display panel according to claim 7, wherein The same first trace is electrically connected to at least three pixel circuits, and the at least three pixel circuits are located in the same row and are adjacent in sequence.

9. The display panel according to claim 1, wherein The system-on-chip includes: An external power supply; A power management circuit for providing various power supply voltages for the display panel; A switching circuit, an input end of the switching circuit is electrically connected to the external power supply, an output end of the switching circuit is electrically connected to the power management circuit, and a control end of the switching circuit is electrically connected to the timing controller to control a transmission path between the external power supply and the power management circuit to be in a conducting state or an off state according to the power enable signal.

10. A display device, characterized in that, Comprising the display panel according to any one of claims 1 to 9, wherein the pixel circuit further comprises a storage capacitor, one end of the storage capacitor is electrically connected to a gate of the driving transistor, and the other end of the storage capacitor is electrically connected to a source of the driving transistor.

Images