Semiconductor device and method of manufacturing the same
By adjusting the growth steps of the oxide layer during semiconductor device manufacturing, the sharp corners at the junction of the semiconductor substrate and the sidewall of the groove are eliminated, thus solving the problem of uneven oxide layer thickness and improving the performance and reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SILERGY SEMICON TECH (HANGZHOU) CO LTD
- Filing Date
- 2022-03-22
- Publication Date
- 2026-06-23
Smart Images
Figure CN114783878B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically, to semiconductor devices and methods for manufacturing the same. Background Technology
[0002] Power switches can be semiconductor devices, including metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs). Laterally diffused metal-oxide-semiconductor (LDMOS) is widely used in switching regulators. In LDMOS power device manufacturing processes, especially in processes using LOCOS (Local Oxidation of Silicon) for the field plate, there are many devices, or designs, at the interface between the high-voltage field oxide and the shallow trench isolation (STI). Due to the special characteristics of the LOCOS process, such as... Figure 1 As shown, a sharp, upward-protruding corner B is easily formed at the junction. After the entire process is completed, the sharp corner at the junction will accumulate charge, reducing the thickness of the oxide layer between it and the polysilicon. This can lead to oxide layer breakdown at the junction, reducing the performance of the LDMOS device and causing GOI (Gate Oxide Integrity) process reliability issues.
[0003] Therefore, how to propose a method to eliminate the sharp corner at the junction of the upper surface of the semiconductor substrate and the sidewall of the STI groove, and improve the performance of semiconductor devices, has become one of the problems that urgently need to be solved by those skilled in the art. Summary of the Invention
[0004] In view of the above problems, the purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which eliminates the sharp corner at the junction of the upper surface of the semiconductor substrate and the sidewall of the groove, thereby improving device performance.
[0005] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising the following steps:
[0006] A semiconductor substrate is provided, and the substrate is etched to form a groove in the substrate;
[0007] By altering the growth steps for forming the oxide layer in the groove, the sharp angle at the junction of the upper surface of the semiconductor substrate and the sidewall of the groove is reduced.
[0008] Optionally, the growth time of the deposited oxide layer in the groove is increased to make the junction between the upper surface of the semiconductor substrate and the sidewall of the groove smooth.
[0009] Optionally, the number of times an oxide layer is deposited in the groove is increased to make the junction between the upper surface of the semiconductor substrate and the sidewall of the groove smooth.
[0010] Optionally, a first oxide layer is deposited in the groove such that the substrate oxide layer covers the bottom and sidewalls of the groove;
[0011] A second oxide layer is deposited on the surface of the first oxide layer, making the junction between the upper surface of the semiconductor substrate and the sidewall of the groove smooth.
[0012] Optionally, the process may include a step of removing the previously deposited oxide layer between two adjacent oxide layer depositions.
[0013] Optionally, a first oxide layer is deposited in the groove such that the first oxide layer covers the bottom of the groove and the sidewalls of the groove;
[0014] Remove the first oxide layer;
[0015] A second oxide layer is deposited at the bottom and on both sidewalls of the groove, making the junction between the upper surface of the semiconductor substrate and the sidewalls of the groove smooth.
[0016] Optionally, the thickness of the first oxide layer is 100 angstroms, and the thickness of the second oxide layer is 300 angstroms.
[0017] Optionally, a wet process can be used to remove the oxide layer described above.
[0018] Optionally, when an oxide layer is deposited at least twice in the groove, the thickness of the last deposited oxide layer is greater than or equal to the thickness of each of the previous deposited oxide layers.
[0019] Optionally, the sidewalls of the groove are inclined toward the substrate at an angle of less than or equal to 90 degrees.
[0020] Optionally, the cross-sectional shape of the groove is an inverted trapezoid, and the inclination angle is 65 to 70 degrees.
[0021] Optionally, the manufacturing method further includes the following steps:
[0022] The groove is filled with an insulating material layer;
[0023] Ion doping implantation to form bulk and drift regions;
[0024] A field oxide layer is formed above the groove;
[0025] A gate structure is formed above the field oxide layer and the semiconductor substrate.
[0026] Optionally, the manufacturing method further includes the following steps: forming a source region in the body region and a drain region in the drift region by ion doping implantation.
[0027] According to another aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising a shallow trench isolation recess structure obtained according to the above-described semiconductor device manufacturing method.
[0028] The semiconductor device manufacturing method provided by the present invention reduces the sharp corners at the junction of the upper surface of the semiconductor substrate and the sidewall of the groove by changing the growth steps of forming the oxide layer in the groove, thereby reducing the impact of the sharp corners caused by the incomplete oxidation of the boundary structure on the thickness of the field oxide layer structure, thus ensuring the thickness uniformity of the field oxide layer structure, ensuring the breakdown protection effect of the field oxide layer structure, and thus improving the performance of the semiconductor device. Attached Figure Description
[0029] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0030] Figure 1 A schematic diagram of the structure of an LDMOS device according to the prior art is shown;
[0031] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;
[0032] Figures 3A to 3H A partial process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;
[0033] Figure 4 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation
[0034] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.
[0035] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0036] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Figures 3A to 3HA partial process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.
[0037] Reference Figure 2 ,as well as Figures 3A to 3H The method for manufacturing a semiconductor device according to embodiments of the present invention mainly includes:
[0038] Step S11: Provide a semiconductor substrate and etch the substrate to form a trench in the substrate. That is, etch the trench at the location of the shallow trench isolation region.
[0039] like Figure 3A As shown, the sidewall of the groove is inclined outward, and the inclination angle A is less than or equal to 90 degrees. Preferably, in this embodiment, the cross-section of the groove is an inverted trapezoid, and the inclination angle of its sidewall is 65 to 70 degrees, because if the angle A is too large, it will reduce the oxidation rate of the sidewall of the groove in the following steps S12 and S13.
[0040] Step S12: Change the growth step of forming the oxide layer in the groove to reduce the sharp angle at the junction of the upper surface of the semiconductor substrate and the sidewall of the groove.
[0041] In the first embodiment, in step S12, referring to Figures 3B-3D Two linear oxide layers, 131 and 132, were deposited, as shown. Figure 3B As shown, a first oxide layer 131 is deposited in the groove. After the first oxide layer 131 is deposited, as... Figure 3C As shown, a wet process is used to remove the first oxide layer 131. After removing the first oxide layer 131, as... Figure 3D As shown, a second oxide layer 132 is deposited in the groove, and the thickness of the second oxide layer 132 is greater than or equal to the thickness of the first oxide layer 131, and as... Figure 3B and 3D As shown, since both the first oxide layer 131 and the second oxide layer 132 cover the sidewalls of the groove, the sharp corner B at the junction of the upper surface of the semiconductor substrate and the sidewall of the groove is oxidized faster and undergoes two oxidations, thus making the sharp corner B smoother and preventing charge accumulation, thereby improving the breakdown voltage of the semiconductor device and the reliability of the gate oxide layer. As an example, the thickness of the first oxide layer 131 is 100 angstroms, the thickness of the second oxide layer 132 is 300 angstroms, and the temperature at which the first oxide layer 131 and the second oxide layer 132 are formed is 1100°C. Because the opening of the groove will become larger after the formation of the first oxide layer 131 and the removal of the first oxide layer 131 by wet process, the thickness of the first oxide layer 131 should not be too large in order to reduce the impact on the opening of the groove, and the thickness of the first oxide layer 131 is less than or equal to the thickness of the second oxide layer 132.
[0042] In the second embodiment, in step S12, only one linear oxidation is performed, but the oxidation time is longer than the time for the first oxidation or the second oxidation in the first embodiment. The oxide layer covers the sidewalls of the groove and the surface of the substrate, so that the deposition thickness of the oxide layer is greater than the thickness of the first oxide layer 131 or the second oxide layer 132 in the first embodiment, and is approximately the sum of the thicknesses of the first oxide layer 131 and the second oxide layer 132 in the first embodiment. Thus, the sharp corner B can be made to be approximately as smooth as in the first embodiment through one linear oxidation.
[0043] It should be noted that in the first embodiment, the number of linear oxidation cycles can be increased, such as three or four cycles. The oxide layer is removed between two adjacent oxide deposition cycles. That is, except for the last linear oxidation, the oxide layer is removed by a wet process after the formation of the first few linear oxide layers, and the thickness of the first few linear oxide layers should not be too thick. Similarly, in the second embodiment, the time of one linear oxidation cycle can be increased, so that the oxidation time is greater than the time of the first or second oxidation in the first embodiment, such as three or four times the time of the first oxidation in the first embodiment. However, at this time, it is necessary to balance the influence of the furnace tube on the ion doping implantation in the subsequent step S14. This is because if there is a high temperature after ion implantation, the ions will undergo a second distribution, forming a concentration distribution different from the expected one, which will affect the performance of the semiconductor device, such as causing a shift in the threshold voltage. The linear oxide layer formed in step S12 can also repair the damage to the semiconductor substrate caused by the etching of the semiconductor substrate when forming the groove in step S11.
[0044] Step S13: Fill the groove with insulating material layer 133.
[0045] In step S13, as Figure 3E As shown, the filling of the insulating material layer 133 has a significant impact on the performance of the transistor, and its goal is to achieve a void-free filling effect without damaging the substrate structure.
[0046] Step S14: Mid-section process.
[0047] In step S14, the intermediate process is, for example, as follows: Figure 3F As shown, the process may include forming a body region 150 and a drift region 120 on a semiconductor substrate through processes such as ion implantation. Taking an N-type LDMOS as an example, the semiconductor substrate may be a silicon substrate or a gallium substrate, or a P-type substrate. The body region 150 is a P-type doped well region, and the drift region 120 is an N-type deep well. This step may also include source and drain region doping implantation to form a source region in the body region 150 and a drain region in the drift region 120.
[0048] Step S15: Fabricate field oxide layer 134 according to the local silicon oxide isolation process.
[0049] In step S15, as Figure 3G As shown, the process of fabricating the field oxide layer 134 includes depositing a silicon nitride layer on the upper surface of the semiconductor substrate 110 (including structures such as source regions, drain regions, drift regions, and body regions formed on the semiconductor substrate 110) and the insulating material layer 133, etching the silicon nitride layer, and the etched window region of the silicon nitride layer corresponding to the field oxide layer region. This window region covers the region of the insulating material layer 133. Then, according to the LOCOS process, using the silicon nitride layer as a mask, such as... Figure 3F As shown, oxidation yields a field oxide layer 134 structure. The thickness of the field oxide layer 134 is adjusted according to the withstand voltage of the semiconductor device, and for example, it can be between 300 Å and 1000 Å. Preferably, the thickness of the field oxide layer 134 is 800 Å.
[0050] It should be noted that, in one embodiment, after the field oxide layer 134 is formed, the insulating material layer and the field oxide layer 134 are seamlessly connected, forming an integral unit, thereby improving the quality of the field oxide layer 134 structure and the trench isolation structure. Simultaneously, in step S15, because angle B is rounded off in step S13, the thickness of the field oxide layer 134 is effectively increased, reducing the risk of breakdown caused by charge accumulation.
[0051] Step S16: Fabricate the gate structure.
[0052] like Figure 3H As shown, a gate structure 140 is fabricated on a semiconductor substrate having a field oxide layer 134 and a shallow trench isolation region. In this embodiment, the height of the gate oxide layer 142 of the gate structure 140 is not higher than the thickness of the field oxide layer 134, and the polysilicon layer 141 also partially covers the field oxide layer 134.
[0053] In step S15, before depositing the silicon nitride layer, a thin oxide layer with the same thickness as the gate oxide layer 142 can be deposited on the semiconductor substrate 110. The etched silicon nitride layer also covers the gate oxide layer 142. Subsequently, using the silicon nitride layer as a mask, the thickness of a portion of the thin oxide layer is increased by oxidation to obtain a field oxide layer 134 of the target thickness. Then, the silicon nitride layer is removed, and the thin oxide layer is etched to expose other areas on the upper surface of the semiconductor substrate 110, such as the source and drain doped regions, so as to subsequently manufacture source and drain electrodes that connect the source and drain doped regions.
[0054] It should be noted that the main inventive point of this invention is that in step S12, the deposition thickness of linear oxide is greater than the preset thickness when linear oxide is deposited at least twice or only once in the groove. This invention does not impose any particular limitation on the manufacturing process of other layer structures in LDMOS devices or other semiconductor devices, and is not limited to high-voltage LDMOS devices. It can also be used for other low-voltage MOS devices. Correspondingly, it can ensure the thickness reliability of field oxide layers of various thicknesses and ensure the design reliability of breakdown voltage. The field oxide layer 134 is not limited to high-thickness high-voltage field oxide layers. It can be applied to field oxide layers or gate oxide layers of any thickness.
[0055] As an example, Figure 4 A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown. The semiconductor device has a body region 150 and a drift region 120 disposed in a semiconductor substrate 110. A doped region 151 is disposed in the body region 150, and a drain region 121 is disposed in the drift region 120. A shallow trench isolation region 130 (i.e., the groove structure mentioned in the previous embodiment) is also disposed in the drift region 120 between the drain region 121 and the body region 150. A field oxide layer 134 is disposed on the upper surface of the shallow trench isolation region 130. A gate structure 140 is disposed from the doped region 151 to the drift region 120. A gate oxide layer 141 is disposed at the bottom of the gate structure 140, and a polysilicon layer 142 is disposed on the top layer, with the polysilicon layer 142 covering the junction of the field oxide layer 134 and the gate oxide layer 141.
[0056] Reference Figure 4 The semiconductor device manufacturing method of the present invention has a smooth structure at the junction of the upper surface of the substrate and the sidewall of the shallow trench isolation region 130. The thickness of the field oxide layer 134 is guaranteed, and the smooth structure of the sharp corner B is not easy to accumulate charge, which can further reduce the breakdown risk of the field oxide layer 134 and improve the breakdown voltage of the semiconductor device.
[0057] Taking an N-type LDMOS device as an example, the semiconductor substrate 110 of the semiconductor device 200 is a P-type substrate, the body region 120 is a P-type well region, the drift region 130 is an N-type doped well region, the base region 121 is P-type doped, the source region 122 is N-type doped, and the drain region 131 is N-type doped.
[0058] The semiconductor device provided by this invention is manufactured according to the semiconductor device manufacturing method provided by this invention. In the groove, at least two oxides are deposited or only one oxide is deposited with a deposition thickness greater than a preset thickness, so as to reduce the oxidation of the sharp corner at the junction of the upper surface of the semiconductor substrate and the sidewall of the groove, making the sharp corner at the junction of the upper surface of the semiconductor substrate and the sidewall of the groove smooth, reducing the influence of the sharp corner caused by the incomplete oxidation of the boundary structure on the thickness of the field oxide layer structure, thereby ensuring the thickness uniformity of the field oxide layer structure, ensuring the breakdown protection effect of the field oxide layer structure, and improving the performance of the semiconductor device.
[0059] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and make modifications based on it. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method includes the following steps: A semiconductor substrate is provided, and the substrate is etched to form a groove in the substrate; A linear oxide layer is formed at least twice at the sharp corner between the sidewall of the groove and the upper surface of the substrate, and the sharp corner at the junction of the upper surface of the semiconductor substrate and the sidewall of the groove is rounded by increasing the time or number of times the linear oxide layer is formed. The process between two consecutive oxide layer depositions also includes a step of removing the previously deposited oxide layer. The groove is filled with an insulating material layer; A field oxide layer is formed above the groove using a local silicon oxide isolation process; The insulating material layer and the field oxide layer are integrally connected. The groove has an inverted trapezoidal cross-sectional shape with an inclination angle of 65 to 70 degrees.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In the groove, a first oxide layer is deposited such that the substrate oxide layer covers the bottom and sidewalls of the groove; A second oxide layer is deposited on the surface of the first oxide layer, making the junction between the upper surface of the semiconductor substrate and the sidewall of the groove smooth.
3. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In the groove, a first oxide layer is deposited such that the first oxide layer covers the bottom of the groove and the sidewalls of the groove; Remove the first oxide layer; A second oxide layer is deposited at the bottom and on both sidewalls of the groove, making the junction between the upper surface of the semiconductor substrate and the sidewalls of the groove smooth.
4. The method for manufacturing a semiconductor device according to claim 3, characterized in that: The thickness of the first oxide layer is 100 angstroms, and the thickness of the second oxide layer is 300 angstroms.
5. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The oxide layer described above was removed using a wet process.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that: When an oxide layer is deposited at least twice in the groove, the thickness of the last deposited oxide layer is greater than or equal to the thickness of each of the previous deposited oxide layers.
7. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The manufacturing method further includes the following steps: Ion doping implantation to form bulk and drift regions; A gate structure is formed above the field oxide layer and the semiconductor substrate.
8. The method for manufacturing a semiconductor device according to claim 7, characterized in that: The manufacturing method further includes the following steps: forming a source region in the body region and a drain region in the drift region by ion doping implantation.
9. A semiconductor device comprising a shallow trench isolation recess structure obtained by the manufacturing method of the semiconductor device according to any one of claims 1 to 8.