Structure for providing polysilicon resistors under shallow trench isolation and over high resistivity polysilicon layer

Abstract

The present disclosure relates to a structure that provides a polysilicon resistor under shallow trench isolation and over a high resistivity polysilicon layer. A structure provides a polysilicon resistor under shallow trench isolation (STI). The structure includes the STI, a resistor in the form of a doped buried polysilicon layer located under the STI, and a high resistivity (HR) polysilicon layer located under the doped buried polysilicon layer. The structure also includes a pair of contacts operatively coupled to the doped buried polysilicon layer in a spaced apart manner. A related method is also disclosed.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to integrated circuits (ICs), and more specifically, to structures that provide a polysilicon resistor under a shallow trench isolation (STI) and over a high resistivity polysilicon layer. BACKGROUND

[0002] Resistors for ICs are typically formed in interlayer dielectric (ILD) layers that are located above transistors. These layers are referred to as middle-of-line (MOL) layers and back-end-of-line (BEOL) layers. The MOL layers are located directly above front-end-of-line (FEOL) layers that include the transistors, and the BEOL layers are located above the MOL layers. The MOL and BEOL layers provide scaled interconnects for the IC. Resistors are typically formed over oxide or STI, which reduces heat dissipation from the resistor into the substrate. For polysilicon resistors placed on the surface of the substrate, such as over STI, resistance variation due to temperature at high currents is also a problem. In addition, the resistors extend horizontally within the layers, which occupies valuable area and potentially blocks access to other functional components below, requiring complex electrical connections to these components, or requiring addition of more components that are not covered by the resistors. SUMMARY

[0003] One aspect of the present disclosure includes a structure comprising: a shallow trench isolation (STI); a doped buried polysilicon layer located below the STI; a high resistivity (HR) polysilicon layer located below the doped buried polysilicon layer; and a contact pair operatively coupled to the doped buried polysilicon layer in a spaced apart manner.

[0004] Another aspect of the present disclosure relates to a structure comprising: a shallow trench isolation (STI); a resistor comprising a doped buried polysilicon layer located below the STI; a high resistivity (HR) polysilicon layer located below the resistor; and a contact pair operatively coupled to the resistor in a spaced apart manner, wherein the HR polysilicon layer comprises an inert dopant, and wherein the doped buried polysilicon layer comprises a boron dopant.

[0005] Another aspect of the present disclosure includes an aspect of the present disclosure relating to a method comprising: forming a shallow trench isolation (STI) in a substrate; doping the substrate with an inert dopant to form a disordered crystalline layer below the STI; converting the disordered crystalline layer into a doped buried polysilicon layer located below the STI and a high resistivity (HR) polysilicon layer located below the doped buried polysilicon layer; and forming a contact pair operatively coupled to the doped buried polysilicon layer in a spaced apart manner.

[0006] The above-described and other features of the present disclosure will become apparent from the following more detailed description of embodiments thereof, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals refer to like elements, and wherein:

[0008] Figure 1 A cross-sectional view of a structure including a polysilicon resistor is shown, according to embodiments of the present disclosure.

[0009] Figure 2 A cross-sectional view of a structure including a polysilicon resistor is shown, according to embodiments of the present disclosure. Figure 1 A plan view of the structure (see view line 1-1).

[0010] Figure 3 A cross-sectional view of a structure including a polysilicon resistor is shown, according to embodiments of the present disclosure.

[0011] Figure 4 A cross-sectional view of a structure including a polysilicon resistor is shown, according to embodiments of the present disclosure.

[0012] Figure 5 A cross-sectional view of an initial structure of a method is shown, according to embodiments of the present disclosure.

[0013] Figure 6 A cross-sectional view of introducing an inert dopant to form a disordered crystalline layer is shown, according to embodiments of the present disclosure.

[0014] Figure 7 A cross-sectional view of converting the disordered crystalline layer of Figure 6 to a doped buried polysilicon layer located under the STI and a high resistivity (HR) polysilicon layer located under the doped buried polysilicon layer is shown, according to embodiments of the present disclosure.

[0015] Figure 8 A cross-sectional view of introducing a first dopant to form a contact for a polysilicon resistor is shown, according to embodiments of the present disclosure.

[0016] Figure 9 A cross-sectional view of introducing a second dopant to form a contact for a polysilicon resistor is shown, according to embodiments of the present disclosure.

[0017] Figure 10 A cross-sectional view of introducing an inert dopant to form a disordered crystalline layer is shown, according to embodiments of the present disclosure.

[0018] Figure 11 A cross-sectional view of converting the disordered crystalline layer of Figure 10 to a doped buried polysilicon layer located under the STI and a HR polysilicon layer located under the doped buried polysilicon layer is shown, according to embodiments of the present disclosure.

[0019] Figure 12 A cross-sectional view showing the introduction of a dopant to form a contact for a polysilicon resistor is shown in accordance with embodiments of the present disclosure.

[0020] Figure 13 A cross-sectional view showing the introduction of an inert dopant to form a disordered crystalline layer is shown in accordance with further embodiments of the present disclosure.

[0021] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like reference numerals indicate like elements among the drawings. DETAILED DESCRIPTION

[0022] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific exemplary embodiments in which the teachings can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the teachings, and it is to be understood that other embodiments can be utilized and that changes can be made without departing from the scope of the present teachings. The following description is, therefore, not to be taken in a limiting sense.

[0023] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0024] References in the specification to “one embodiment” or “an embodiment” of the disclosure, or to “the” embodiment, and other variations thereof, mean that a particular feature, structure, characteristic, and so forth being described is included in at least one embodiment of the disclosure. Therefore, the phrase “in one embodiment” or “in an embodiment,” as well as any other variations thereof, are not necessarily referring to the same embodiment. It is appreciated that, with respect to the use of any of the following terms in this Specification (including the claims), including the indefinite articles “a” and “an,” and the verb “comprising,” these terms should be construed to cover a singular as well as the plural, unless otherwise indicated herein or inferred from context. The terms “a” (or “an”), “the” (and “the

[0025] Embodiments of the present disclosure provide a structure to provide a poly-resistor under a shallow trench isolation (STI). The structure includes the STI, a resistor in the form of a doped buried poly layer located under the STI, and a high resistivity (HR) poly layer located under the doped buried poly layer. The structure also includes a pair of contacts operably coupled to the doped buried poly layer in a spaced apart manner. A related method is also disclosed. The structure eliminates the oxide / STI under the resistor, thereby improving heat dissipation of the resistor to the substrate. The structure also allows for improved resistor density (with reduced area) by allowing stacked poly resistors under the STI and over the STI. The HR poly layer provides an isolation region under the poly resistor, reducing parasitic leakage of the active device to the substrate. The HR poly layer also provides thermal conductivity from the poly resistor with reduced substrate coupling and improved frequency response in this setup.

[0026] Figure 1A cross-sectional view of structure 100 according to an embodiment of the present disclosure is shown. Structure 100 is formed over substrate 102. As shown, embodiments of the present disclosure can be implemented on a bulk semiconductor substrate 104. However, the teachings of the present disclosure can also be implemented on other substrates such as semiconductor-on-insulator (SOI) substrates (not shown). SOI substrates comprise layered semiconductor-insulator-semiconductor substrates instead of more conventional bulk semiconductor substrates. SOI substrates include a semiconductor-on-insulator (SOI) layer over a buried insulator layer located above a substrate semiconductor layer. Semiconductor substrate 104 may include, but is not limited to, silicon, germanium, silicon-germanium, silicon carbide, and materials substantially composed of materials having the chemical formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 Those comprising one or more III-V compound semiconductors with defined compositions, wherein X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero, and X1+X2+X3+Y1+Y2+Y3+Y4=1 (where 1 is the total relative molar amount). Other suitable substrates include those having the composition Zn. A1 Cd A2 Se B1 Te B2 The semiconductor is a group II-VI compound semiconductor, wherein A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). In the case of an SOI substrate, the SOI layer and the substrate semiconductor layer may comprise any of the aforementioned semiconductor materials. Furthermore, the entire substrate 102 or a portion thereof may be strained. In either case, the semiconductor substrate 104 may be provided as an amorphous semiconductor material (e.g., without a well).

[0027] The structure 100 also includes a shallow trench isolation (STI) 110. The STI 110 includes a trench 112 etched into the substrate 102 and filled with an insulating material 114. In certain embodiments, the STI 110 can isolate one region of the substrate from a region in an adjacent substrate. For example, the STI 110 can electrically isolate one active region 120 from another active region 122. One or more transistors (not shown) having a given polarity can be disposed within the region isolated by the STI 110. The insulating material 114 can include any now known or later developed substance for providing electrical insulation, for example, can include silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated carbon oxide silicon (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides including silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H) atoms (i.e., organosilicates), thermoset polyarylene ether, spin-on silicon-containing carbon polymer material, near frictionless carbon (NFC), or layers constructed therefrom.

[0028] As noted, a typical polysilicon resistor (not shown) can be formed over the STI 110 in an interlayer dielectric (ILD) layer 124 over the STI 110. In this case, the STI 110 limits heat dissipation to the substrate 102. Suitable dielectric materials for the ILD layer 124 can include, but are not limited to: carbon doped silicon oxide materials; fluorinated silicate glass (FSG); organic polymeric thermoset materials; carbon oxide silicon; SiCOH dielectrics; fluorine doped silicon oxide; spin-on glass; silsesquioxane, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB) based polymeric dielectrics; and any silicon-containing low-k dielectrics. Examples of spin-on low-k films with SiCOH type composition using silsesquioxane chemistry include HOSP TM (available from Honeywell), JSR 5109 and 5108 (available from Japan Synthetic Rubber), Zirkon TM (available from Rohm and Haas division Shipley Microelectronics), and porous low-k (ELk) materials (available from Applied Materials). Examples of carbon doped silicon dioxide materials or organosilanes include Black Diamond TM (available from Applied Materials) and Coral TM(Available from Lam Research). An example of HSQ material is FOX. TM (Available from Dow Corning).

[0029] Structure 100 includes a resistor 130 (also referred to herein as "polysilicon resistor 130"), which includes a doped buried polysilicon layer 132 located beneath STI 110. The doped buried polysilicon layer 132 is referred to as "buried" because its location is on the upper surface 134 of the substrate 102 (within...). Figure 1 The upper surface of STI 110 is located below the same plane. The doped buried polysilicon layer 132 may include any dopant capable of controlling the resistivity of the layer. In a non-limiting example, the doped buried polysilicon layer 132 located below STI 110 may include a boron (B) dopant. However, it may be doped with other p-type or n-type dopant, depending on the doping in the substrate 102 or below the high resistivity (HR) polysilicon layer 140 (described herein) below the doped buried polysilicon layer 132. Alternative dopant may include, but is not limited to, other p-type dopant, such as indium (In), aluminum (Al) and / or gallium (Ga), or n-type dopant, such as phosphorus (P), arsenic (As) and / or antimony (Sb). The dopant concentration in the doped buried polysilicon layer 132 can be controlled to determine the resistivity of the polysilicon layer 132.

[0030] Structure 100 also includes a high resistivity (HR) polysilicon layer 140 located beneath the doped buried polysilicon layer 132. The HR polysilicon layer 140 may include an inert dopant capable of altering the crystal structure of the HR polysilicon layer 140 from that of the substrate 102, thereby generating a resistivity greater than that of the substrate 102 and potentially higher than that of the doped buried polysilicon layer 132. Inert dopant may include, for example, argon (Ar), neon (Ne), krypton (Kr), xenon (Xe), helium (He), or combinations thereof. In one particular embodiment, argon (Ar) is used.

[0031] Structure 100 also includes pairs of contacts 144, 146 operably coupled to the doped buried polysilicon layer 132 in a spaced-apart manner. Contacts 144, 146 provide conductive paths to resistor 130. Figure 1 In this context, each contact 144, 146 includes a doped single-crystal semiconductor material 150 extending adjacent to the STI 110. That is, the doped single-crystal semiconductor material 150 is located in the substrate 102 and extends vertically along the lateral side 151 of the STI 100. For example... Figure 1As shown, each contact 144, 146 is operatively coupled to a lateral end 152 of the doped buried polysilicon layer 132. Also, each contact 144, 146 is in contact with an upper surface 154 of the HR polysilicon layer 140. The doped single crystalline semiconductor material 150 can include p-type or n-type dopants, depending on, for example, the type of active device formed elsewhere in the active regions 120, 122. N-type dopants can include, but are not limited to: phosphorus (P), arsenic (As), antimony (Sb). N-type is any element that is introduced into a semiconductor to generate free electrons (by "donating" an electron to the semiconductor) and must have one more valence electron than the host semiconductor. P-type dopants can include, but are not limited to: boron (B), indium (In), and gallium (Ga). P-type is any element that is introduced into a semiconductor to generate free holes (by "accepting" an electron from a semiconductor atom and simultaneously "releasing" a hole); the acceptor atom must have one less valence electron than the host semiconductor. The upper layer 158 of the contacts 144, 146 can have a higher dopant concentration than the doped single crystalline semiconductor material 150. Any now known or later developed form of metal contact or wire 160 through the ILD layer 124 can be formed to complete the contacts 144, 146.

[0032] Figure 2 A plan view of the structure 100 is shown. As shown, the structure 100 includes a substrate 102, a shallow trench isolation (STI) 110, an active region 120, a doped buried polysilicon layer 132, a high resistance (HR) polysilicon layer 140, and a doped single crystalline semiconductor material 150. The substrate 102 can include any now known or later developed form of semiconductor substrate. For example, the substrate 102 can include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a silicon-on-sapphire (SOS) substrate. The STI 110 can include any now known or later developed form of electrically isolating structure. For example, the STI 110 can include a trench isolation or a doped well. In the case of a doped well, it will have a different polarity than the contacts 144, 146, for example, an n-well doped with p-type dopants. In the case of a trench isolation, it can include an STI, a deep trench isolation (DTI, as shown), or a double STI. When in the form of a trench isolation, the STI 110 can be formed similarly to the STI 110. Figure 1 and 2 As shown, the structure 100 can also include an isolation ring 170 that bounds the doped buried polysilicon layer 132. The isolation ring 170 can include any now known or later developed electrically isolating structure. For example, the isolation ring 170 can include a trench isolation or a doped well. In the case of a doped well, it will have a different polarity than the contacts 144, 146, for example, an n-well doped with p-type dopants. In the case of a trench isolation, it can include an STI, a deep trench isolation (DTI, as shown), or a double STI. When in the form of a trench isolation, the isolation ring 170 can be formed similarly to the STI 110.

[0033] For the purposes of the methods described herein, the structure 100 can also optionally include a retardant implant region 174 (dashed line) within and / or below the HR polysilicon layer 140 (i.e., below the HR polysilicon layer 140, within the HR polysilicon layer 140, or within and below the HR polysilicon layer 140). The retardant implant region 174 can include any dopant capable of retarding the exhaustion of, for example, boron (B) in the resistor 130 beyond the HR polysilicon layer 140 into the substrate 102. In one non-limiting example, the dopant can include carbon (C).

[0034] Figure 3A cross-sectional view of a structure 100 according to another embodiment of the present disclosure is shown. Figure 3 Structure 100 and Figure 1 and 2 The structures shown are basically similar, except for the doped buried polysilicon layer 132 and the contacts 144 and 146. Figure 3 In the STI 110, the doped buried polysilicon layer 132 includes a pair of vertical portions 180, 182 extending vertically along the side 151 of the STI 110. That is, the material and dopants in the vertical portions 180, 182 are matched with the material and dopants of the doped buried polysilicon layer 132, while those in the STI 110 include other dopants. Figure 1 and Figure 2 The materials in 150 are different. In this way, such as... Figure 3 As shown, resistor 130 and doped buried polysilicon layer 132 can have a U-shaped cross-section. Figure 3 Each contact 144, 146 may include a doped semiconductor material 184 operatively coupled to the upper surface 186 of the corresponding vertical portion 180, 182 of the doped buried polysilicon layer 132. The dopant in the doped semiconductor material 184 may be the same as that in other regions (in-page or out-page) of the active regions 120, 122. Any form of metal contact or wiring 160, now known or later developed, may be formed through the ILD layer 124 to complete the contacts 144, 146, i.e., the doped semiconductor material 184.

[0035] Figure 4 A cross-sectional view of structure 100 according to another embodiment is shown. Figure 4 Structure 100 and Figure 1 and 2 The basic structure is similar to that shown, except that the doped buried polysilicon layer 132 and contacts 144 and 146 are similar to those shown. Figure 1 and 3 The differences are shown. In Figure 4 In this configuration, each contact 144, 146 extends through the STI 110 to the upper surface 188 of the doped buried polysilicon layer 132. Here, contacts 144, 146 may comprise any form of metal contact or wiring known now or developed later (similar to 160 in other embodiments) and may be formed by the ILD layer 124 and the STI 110 to lie directly on the doped buried polysilicon layer 132 (i.e., resistor 130).

[0036] As will be recognized, in the case where STI 110 forms spaced-apart active regions 120 and 122, Figures 1-4 The distance between the active regions 120 and 122 can control the spacing between contacts 144 and 146. In this way, the length of resistor 130 and the resistance provided by resistor 130 can be further controlled.

[0037] Reference is made to Figures 5-13 A method of forming structure 100 according to various embodiments will be described. Figure 5 An initial structure 200 is shown, along with the formation of STI 110 in substrate 102. As noted above, STI 110 can isolate pairs of spaced apart active regions 120, 122. STI 110 can be formed using any now known or later developed process, such as, for example, patterning a mask (not shown), etching an opening into substrate 102, filling the opening with insulating material 114 (as listed herein), and then performing a planarization. Etching generally refers to the removal of material from a substrate (or structure formed on a substrate), and is typically performed with a mask in place so as to selectively remove material from specific areas of the substrate while leaving material in other areas of the substrate unaffected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed with a solvent (e.g., an acid) that can be selected for its ability to selectively dissolve a given material (e.g., an oxide) while leaving another material (e.g., polysilicon) relatively intact. This ability to selectively etch a given material is the basis for many semiconductor manufacturing processes. Wet etching generally etches a homogeneous material (e.g., an oxide) isotropically, but wet etching can also etch a single crystalline material (e.g., a silicon wafer) anisotropically. Dry etching can be performed with a plasma. Plasma systems can be operated in several modes by adjusting the plasma parameters. A normal plasma etch produces neutral, charged high-energy radicals that react at the wafer surface. Since the neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputter etching bombards the wafer with high-energy ions of a noble gas that approach the wafer from roughly one direction, so the process is highly anisotropic. Reactive ion etching (RIE) operates under conditions intermediate between sputtering and plasma etching, and can be used to produce deep, narrow features, such as STI 110 openings / trenches. Initial structure 200 also includes a liner nitride layer 202 over a liner oxide layer 204 in active regions 120, 122, each of which can be formed using any now known or later developed process.

[0038] Figures 6-9 A cross-sectional view of a structure 100 is shown, with the formation of Figure 1 the steps of structure 100. Figure 6 A cross-sectional view of a structure is shown, after optional removal of liner nitride layer 202, exposing liner oxide layer 204. Liner nitride layer 202 can be removed using any suitable etching process, such as, for example, a hot phosphorus process. Figure 6Optionally, a dopant is also shown to be introduced to form a delayed implant region 174, which will ultimately be located within and / or below the HR poly layer 140. Any form of mask 208 can be formed to direct the doping. The mask 208 can be any mask material used to, for example, pattern the HR poly layer 140. The delayed implant region 174 can be formed using any now known or later developed doping process, such as in-situ formation or ion implantation. Figure 6 Any mask material that is patterned to form the HR poly layer 140 is shown in the locations indicated and can be other active regions of the IC. The delayed implant region 174 can be formed using any now known or later developed doping process, such as in-situ formation or ion implantation. Figure 6 A dopant is also shown to be introduced to form a disordered crystalline layer 210 below the STI 110 (and the pair of spaced apart active regions 120, 122, if provided). As noted above, the dopant can include argon (Ar), neon (Ne), krypton (Kr), xenon (Xe), helium (He), or combinations thereof, for example. In one particular embodiment, argon (Ar) is used.

[0039] Figure 7 The disordered crystalline layer 210 ( Figure 6 ) is shown to be converted into a doped buried poly layer 130 located below the STI 110 and a HR poly layer 140 located below the doped buried poly layer 130, i.e., after the mask 208 is removed using any suitable ashing process. In one embodiment, the conversion can be accomplished by annealing. The annealing can include any appropriate rapid thermal processing (RTP), for example, and can have any temperature and / or duration to obtain the desired depth of the layers 132, 140. The delayed implant region 174 can limit the extent to which the layers 132, 140 extend into the substrate 102, if provided. In addition, the dopant concentration in the layers 132, 140 and the conversion process can control the thickness of the layers 132, 140. As Figure 7 indicated, the conversion results in the HR poly layer 140, the doped buried semiconductor layer 132, and a (recrystallized) single crystalline semiconductor material 212 located above the doped buried semiconductor layer 132.

[0040] Figures 8-9 A cross-sectional view is shown of forming a pair of contacts 144, 146 operatively coupled to the doped buried poly layer 132 in a spaced apart manner. In Figure 8 , a mask 220 is formed that exposes the active regions 120, 122. Figure 8 A dopant is also shown to be introduced into the single crystalline semiconductor material 212 to form a doped single crystalline semiconductor material 150 that extends alongside the STI 110. That is, the doped single crystalline semiconductor material 150 is located in the substrate 102 and extends vertically along the side 151 of the STI 100. The dopant can be introduced in any manner, such as ion implantation. The mask 220 can be removed using any appropriate ashing process. Figure 9Another mask 222 is shown that forms the exposed active regions 120, 122 and STI 110. The mask 222 can be the same as the mask 222 used to dope the source / drain regions (not shown) of active devices in other regions of the IC. Figure 8 The dopant is shown introduced into the single-crystal semiconductor material 212 to form an upper layer 158 of contacts 144, 146 having a higher dopant concentration than the doped single-crystal semiconductor material 150. The mask 222 can be removed using any appropriate ashing process, and an ILD layer 124 Figure 1 ) formed over the structure. As Figure 1 shown, metal contacts or wiring 160 in any now known or later developed form can be formed through the ILD layer 124 to complete the contacts 144, 146.

[0041] Figures 10-12 A cross-sectional view is shown for forming the structure 100 as Figure 3 shown. Figure 10 A cross-sectional view is shown with a mask 224 formed over the structure, similar to that shown in Figures 5 Here, in contrast to Figures 6-9 , the spacer nitride layer 202 remains over the active regions 120, 122. That is, during the doping of the STI 210 and the spaced apart active regions 120, 122 with the inert dopant, each active region 120, 122 includes a spacer nitride layer 204 over it, as will be described. The spacer nitride layer 202 prevents the vertical portions 180, 182 Figure 3 ) of the STI 110 from recrystallizing. The mask 224 exposes the active regions 120, 122 and the STI 110. At this stage, the delay implant region 174 can be formed by doping (e.g., ion implantation) to ultimately be within and / or below the HR poly layer 140. However, Figure 10 This process is not shown to illustrate that this step can be optionally omitted. Any form of mask 224 can be formed to direct the doping. The mask 224 can be, for example, any mask material patterned at Figure 10 shown and possibly other active regions of the IC to form the HR poly layer 140. Figure 10 Doping with the inert dopant is also shown to form the disordered crystalline layer 210 under the STI 110 (and the pair of spaced apart active regions 120, 122, if provided). As noted, the inert dopant can include argon (Ar), neon (Ne), krypton (Kr), xenon (Xe), helium (He), or combinations thereof, for example. In one particular embodiment, argon (Ar) is used.

[0042] Figure 11 The disordered crystalline layer 210 Figure 10) into doped buried polysilicon layer 130 located below STI 110 and HR polysilicon layer 140 located below doped buried polysilicon layer 130, i.e., after removal of mask 224 using any suitable ashing process Figure 10 ) In one embodiment, the conversion can be accomplished by annealing. As noted, the annealing can include, for example, any suitable rapid thermal processing (RTP) and can have any temperature and / or duration to obtain the desired depth of layers 132, 140. Where provided, retardation implant region 174 (not shown) can limit the extent to which layers 132, 140 extend into substrate 102. In addition, the dopant concentration in layers 132, 140 and the conversion process can control the thickness of layers 132, 140. Here, due to the presence of liner nitride layer 202, doped buried polysilicon layer 132 includes vertical portions 180, 182 that extend vertically along the sides 152 of STI 110 in each active region 120, 122. Thus, this conversion results in HR polysilicon layer 140, doped buried semiconductor layer 132, and vertical portions 180, 182 of doped buried semiconductor layer 132 that extend along the sides 151 of STI 110.

[0043] Figure 12 A cross-sectional view is shown of removal of liner nitride layer 202, e.g., with a hot phosphorous process. Figure 12 Also shown is formation of pairs of contacts 144, 146 by forming doped poly semiconductor material 184 in each active region 120, 122 that is operably coupled to upper surface 186 of vertical portions 180, 182 of doped buried polysilicon layer 132. More particularly, Figure 12 A cross-sectional view is shown of formation of mask 230 and introduction of dopants, e.g., by ion implantation through liner oxide layer 204, to form doped poly semiconductor material 184. Figure 3 A cross-sectional view is shown of removal of mask 230 and formation of metal contacts or wiring 160 through ILD layer 124 and liner oxide layer 204 Figure 12 ) to complete structure 100 after contacts 144, 146, as described herein.

[0044] Figure 13 A cross-sectional view is shown of formation Figure 4 of structure 100, as shown. Figure 4 Embodiments of Figure 1 and 3 can be formed with fewer steps than embodiments of Figure 13 A cross-sectional view is shown of optional mask 240 that exposes STI 110. At this stage, retardation implant region 174 (not shown) can optionally be formed by doping (e.g., ion implantation). However, Figure 13The process is not shown to illustrate that this step can be optionally omitted. The mask 240 can be formed in any form to direct the doping. For example, the mask 240 can be a photoresist mask formed, for example, by spin-coating a photoresist material onto the substrate 102, exposing the photoresist to light through a mask, and developing the photoresist to remove the photoresist in areas where the light passed through the mask. The photoresist can then be removed, for example, by ashing. The mask 240 can also be formed by any other now known or later developed mask formation process. Figure 4 Any mask material that is patterned to form the HR poly layer 140 at the locations shown and possibly other active regions of the IC is shown. Figure 13 Doping with an inert dopant is also shown, forming a disordered crystalline layer 210 under the STI 110. As noted, the inert dopant can include, for example, argon (Ar), neon (Ne), krypton (Kr), xenon (Xe), helium (He), or combinations thereof. In one particular embodiment, argon (Ar) is used.

[0045] Figure 4 The conversion of the disordered crystalline layer 210 Figure 13 ) into the doped buried poly layer 130 under the STI 110 and the HR poly layer 140 under the doped buried poly layer 130, i.e., after the mask 240 Figure 13 ) is removed using any suitable ashing process, is shown. As noted, the conversion can be accomplished by annealing, as described herein. Where provided, the delayed implant region 174 (not shown) can limit the extent to which the layers 132, 140 extend into the substrate 102. In addition, the dopant concentration in the layers 132, 140 and the conversion process can control the thickness of the layers 132, 140. As Figure 4 shown, in this embodiment, the pair of contacts 144, 146 includes forming a metal contact or wire 160 that extends through the STI 110 to the upper surface 188 of the doped buried poly layer 132. The metal contact or wire 160 can be formed using any now known or later developed contact / wire formation process. In one non-limiting example, the contact or wire 160 can be formed by patterning a mask, etching an opening to a corresponding depth, and forming a conductor in the opening. The conductor can include a refractory metal liner and a contact or wire metal. The refractory metal liner (not labeled for clarity) can include, for example, ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), iridium (Ir), rhodium (Rh), and platinum (Pt), among others, or mixtures thereof. The metal of the contact or wire can be any now known or later developed contact / wire metal, such as, but not limited to, copper (Cu) or tungsten (W).

[0046] In any of the method embodiments described herein, the isolation ring 170 can be formed at any desired juncture, such as at the juncture with the STI 110. In the case where the isolation ring 170 includes a trench isolation, it can be formed in substantially similar fashion to the STI 110.

[0047] Embodiments of the present disclosure provide a structure 100 for providing a polyresistor 130. As shown, the structure 100 includes a substrate 102, a STI 110 formed in the substrate 102, a doped buried poly layer 132 formed in the substrate 102 under the STI 110, and a HR poly layer 140 formed in the substrate 102 under the doped buried poly layer 132. The doped buried poly layer 132 and the HR poly layer 140 can be formed in any now known or later developed process.Figure 1 , 3 and 4, structure 100 does not include oxide / STI underneath resistor 120, which improves heat dissipation from the resistor to substrate 102. The structure also improves resistor density (with smaller area) by allowing stacked polysilicon resistors underneath STI 110 and above STI 100 (see additional resistor 242 above STI 110 in Figure 4 . Additional resistor 242 can be employed in any embodiment. HR polysilicon layer 140 provides an isolation region underneath polysilicon resistor 130, which reduces parasitic leakage from active devices to substrate 102. See U.S. Patent No. 10,192,779. Here, HR polysilicon layer 140 also reduces substrate coupling and improves frequency response to provide improved thermal conductivity from polysilicon resistor 130.

[0048] The foregoing method is used in the manufacture of the integrated circuit chip. The resulting integrated circuit chip can be distributed by the manufacturer to a customer, consumer, end user, etc. who performs final assembly of the device as part of a (a) final product which incorporates the use of the integrated circuit chip or (b) intermediate products (intermediate assemblies) which are then used as a component in the end product. Where the resulting integrated circuit chip results in a final product, of either type (a) or (b), there are no restrictions on the use of the integrated circuit chip.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" or "optionally" means that the subsequently described event or circumstance can or can not occur, and that the description includes instances where the event occurs and instances where it does not.

[0050] Approximating language can be applied to any quantitative representation, such as one or more terms that modify a value, which can allow for variation in the value that does not materially change the stated function or purpose. Accordingly, a value modified by a term or terms, such as "about", "approximately”, and "substantially”, is not to be limited to the precise value specified. In at least some instances, an approximate language can correspond to the precision of an instrument for measuring the value. In this context, and unless otherwise indicated, all ranges noted are approximate, whether stated explicitly or not, and include all sub-ranges therein and therebetween, unless otherwise indicated. "Approximately”, applied to a range of values, applies to both values, and unless otherwise indicated, can indicate + / - 10% of the stated value, unless otherwise dependent on the precision of an instrument for measuring the value.

[0051] All devices or steps of the following claims, or corresponding structures, materials, acts, and equivalents thereof, are intended to include any structure, material, or acts for performing the functions described in connection with other claimed elements. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the present disclosure to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. Embodiments were chosen and described in order to best explain the principles of the present disclosure and the practical application, and to enable others skilled in the art to understand various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A structure for an integrated circuit, comprising: Shallow trench isolation STI, which includes a lower surface; A doped buried polysilicon layer located at least partially beneath the lower surface of the STI; The high resistivity HR polysilicon layer located beneath the doped buried polysilicon layer; and Contact pairs operably coupled to the doped buried polysilicon layer in a spaced-out manner. The resistivity of the HR polysilicon layer is higher than that of the doped buried polysilicon layer.

2. The structure according to claim 1, wherein, The HR polycrystalline silicon layer includes an inert dopant.

3. The structure according to claim 1, wherein, The doped buried polysilicon layer located beneath the STI includes a boron dopant.

4. The structure according to claim 1, further comprising: Define the isolation ring of the doped buried polysilicon layer.

5. The structure according to claim 4, wherein, The isolation ring is one of trench isolation and doped trap.

6. The structure according to claim 1, further comprising: The delayed implantation region is located below the HR polysilicon layer, within the HR polysilicon layer, or both within and below the HR polysilicon layer.

7. The structure according to claim 1, wherein, Each contact includes a doped single-crystal semiconductor material extending alongside the STI, and each contact is operatively coupled to a lateral end of the doped buried polycrystalline silicon layer.

8. The structure according to claim 7, wherein, Each contact is in contact with the upper surface of the HR polysilicon layer.

9. The structure according to claim 1, wherein, The doped buried polysilicon layer includes a pair of vertically extending portions along the side of the STI, wherein each contact includes a doped semiconductor material operatively coupled to the upper surface of the corresponding vertical portion of the doped buried polysilicon layer.

10. The structure according to claim 1, wherein, Each contact extends through the STI to the upper surface of the doped buried polysilicon layer.

11. A structure for an integrated circuit, comprising: Shallow trench isolation STI, which includes a lower surface; A resistor comprising a doped buried polysilicon layer, located at least partially beneath the lower surface of the STI; A high resistivity HR polycrystalline silicon layer located beneath the resistor; and Contact pairs operably coupled to the resistor in a spaced-out manner. The HR polysilicon layer includes an inert dopant, and The doped buried polysilicon layer includes a boron dopant, and The resistivity of the HR polysilicon layer is higher than that of the doped buried polysilicon layer.

12. The structure according to claim 11, further comprising: Define the isolation ring of the doped buried polysilicon layer.

13. The structure according to claim 11, wherein, Each contact includes a doped single-crystal semiconductor material extending adjacent to the STI, and each contact is operatively coupled to a lateral end of the doped buried polysilicon layer, wherein each contact contacts the upper surface of the HR polysilicon layer.

14. The structure according to claim 11, wherein, The doped buried polysilicon layer includes a pair of vertically extending portions along the side of the STI, wherein each contact includes a doped semiconductor material operatively coupled to the upper surface of the corresponding vertical portion of the doped buried polysilicon layer.

15. The structure according to claim 11, wherein, Each contact extends through the STI to the upper surface of the doped buried polysilicon layer.

16. A method for forming a structure for an integrated circuit, comprising: Shallow trench isolation (STI) is formed in the substrate; The substrate is doped with an inert dopant to form a disordered crystalline layer beneath the STI; The disordered crystalline layer is transformed into a doped buried polysilicon layer below the STI and a high resistivity (HR) polysilicon layer below the doped buried polysilicon layer; and Contact pairs are formed that are operatively coupled to the doped buried polysilicon layer in a spaced-out manner. The resistivity of the HR polysilicon layer is higher than that of the doped buried polysilicon layer.

17. The method of claim 16, further comprising: Doping is performed to form a delayed implantation region below, within, or both inside and below the HR polysilicon layer.

18. The method according to claim 16, wherein, Forming the contact pair includes: forming a doped single-crystal semiconductor material extending adjacent to the STI in each active region of the active region pair defined by the STI, each contact being operatively coupled to a lateral end of the doped buried polysilicon layer, and each contact contacting the upper surface of the HR polysilicon layer.

19. The method of claim 16, wherein, The STI defines a pair of active regions, and during doping of the STI with the inert dopant, each active region includes a pad nitride layer located above it, wherein the doped buried polysilicon layer includes a vertical portion extending vertically along the side of the STI in each active region, and wherein forming the contact pair includes forming a doped polysilicon material in each active region, the doped polysilicon material being operatively coupled to the upper surface of the vertical portion of the doped buried polysilicon layer.

20. The method of claim 16, wherein, Forming the contact pair includes forming a metal contact that extends through the STI to the upper surface of the doped buried polysilicon layer.

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