Semiconductor device

Abstract

The present application provides a kind of semiconductor device.The present application is based on the basic idea that wants to effectively utilize the space generated in the 3rd wiring layer (M3) by the 0th wiring layer (M0) that can exist by the miniaturization of FINFET, the auxiliary line (AL) is configured in the space generated in the 3rd wiring layer, and the auxiliary line (AL) is electrically connected with the word line (WL).Therefore, the countermeasures (research) based on the new insight that the rising time of word line voltage is greatly affected by the wiring resistance of word line are realized, so that the high-speed operation of SRAM using FINFET can be realized.

Description

[0001] This invention application is a divisional application of the invention application with an international filing date of March 26, 2015, international application number PCT / JP2015 / 059514, national application number 201580048810.7 which entered the Chinese national phase, and the invention title "Semiconductor Device". Technical Field

[0002] This invention relates to semiconductor devices, and for example to techniques that are effectively applied in semiconductor devices having a FINFET. Background Technology

[0003] Japanese Patent Application Publication No. 2013-26594 (Patent Document 1) discloses a technique related to the cell layout of SRAM (Static Random Access Memory).

[0004] Japanese Patent Application Publication No. 11-111860 (Patent Document 2) discloses a technology related to a semiconductor device that can achieve high integration while pursuing high speed of operation in a semiconductor device with a memory cell.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2013-26594

[0008] Patent Document 2: Japanese Patent Application Publication No. 11-111860 Summary of the Invention

[0009] For example, a conventional planar MISFET (Metal Insulator Semiconductor Field Effect Transistor) is used as SRAM (Static Random Access Memory). In this SRAM, a first wiring layer (contact wiring), a second wiring layer (bit line / power line), a third wiring layer (word line / power line), a fourth wiring layer (power line), and a fifth wiring layer (power line) are formed, disposed above the planar MISFET.

[0010] In recent years, the size of MISFETs, a key component of silicon-based LSI (Large Scale Integration), particularly the gate length, has been shrinking. While this shrinkage follows a scaling rule, various problems arise with each device upgrade, making it difficult to simultaneously suppress short-channel effects and ensure high current drive capability. Therefore, research and development of novel device structures to replace traditional planar MISFETs are actively underway.

[0011] FINFET is one of the novel device structures mentioned above; it is a three-dimensional MISFET, unlike planar MISFETs. In recent years, FINFET has attracted much attention as an important device candidate.

[0012] A FinFET has fins formed by processing a semiconductor layer. These fins are elongated, rectangular areas, and their two side faces serve as the channels for the FinFET. Furthermore, the gate electrode of the FinFET is formed above the two side faces of the fin, spanning across the fin, forming a so-called dual-gate structure. Based on this configuration, the FinFET offers better potential control over the channel region compared to conventional single-gate MISFETs. Therefore, using a FinFET provides advantages such as high breakdown strength between the source and drain regions, and the ability to suppress short-channel effects even with a short gate length. Moreover, by using the two side faces of the fin as channels in a FinFET, the area of ​​the channel region through which current flows can be increased, resulting in a high current drive force. In other words, using a FinFET can be expected to simultaneously suppress short-channel effects and ensure a high current drive force.

[0013] Furthermore, when using FinFETs, since they can be miniaturized more than planar MISFETs, the bottommost wiring layer can be formed on the same layer as the FinFET below the first wiring layer. Therefore, an SRAM using FinFETs can be composed of the bottommost wiring layer (0th wiring layer), the 1st wiring layer (bit line / power line), the 2nd wiring layer (word line / power line), the 4th wiring layer (power line), and the 5th wiring layer (power line). That is, in an SRAM using FinFETs, since space is formed on the 3rd wiring layer, it is desirable to make efficient use of this space.

[0014] Other issues and novel features of the present invention will become apparent from the description and accompanying drawings.

[0015] One embodiment of the semiconductor device includes: a FINFET, which includes a gate electrode formed above a semiconductor substrate; and a bottom wiring layer, which includes a top wiring connected above the gate electrode and a substrate wiring formed above the semiconductor substrate. In this case, since the top wiring and the substrate wiring can be electrically connected within the bottom wiring layer to form a wiring network, a space is formed in the upper wiring layer. From the viewpoint of improving the performance of the semiconductor device, the upper wiring layer forming this space is effectively utilized.

[0016] Invention Effects

[0017] According to one embodiment, the performance of semiconductor devices can be improved. Attached Figure Description

[0018] Figure 1 It is a diagram showing the layout structure of a semiconductor chip.

[0019] Figure 2 This is a top view diagram that roughly shows the overall structure of SRAM.

[0020] Figure 3 This is an equivalent circuit diagram showing the storage cell of SRAM.

[0021] Figure 4 (a) is a cross-sectional view showing a schematic construction of a planar FET. Figure 4 (b) is a cross-sectional view showing a schematic construction of a FINFET.

[0022] Figure 5 (a) is a table showing the wiring layers used in an SRAM employing planar FETs. Figure 5 (b) is a table showing the wiring layers used in an SRAM that uses FINFET.

[0023] Figure 6 This is a waveform diagram showing the relationship between the word line voltage and the read time during SRAM readout.

[0024] Figure 7 (a) is a top view showing the layout structure within the semiconductor substrate and the 0th wiring layer. Figure 7 (b) is a top view showing the layout structure of the first to third wiring layers.

[0025] Figure 8 It is along Figure 7 The sectional view obtained by cutting along line AA in (b).

[0026] Figure 9 It is along Figure 7 The sectional view obtained by cutting along line BB of (b).

[0027] Figure 10 It is shown that... Figure 8 The corresponding sectional view of the variant example.

[0028] Figure 11 It is shown that... Figure 9 The corresponding sectional view of the variant example.

[0029] Figure 12 (a) is a table showing the wiring layers in the peripheral circuitry of an SRAM using planar FETs. Figure 12 (b) is a table showing the wiring layers in the peripheral circuitry of an SRAM using FINFETs. Additionally, Figure 12 (c) is a table showing the wiring layers in the peripheral circuit of an SRAM using FINFET, with the basic idea of ​​implementation 2 introduced.

[0030] Figure 13 This is a top view showing the layout structure of the storage module in Embodiment 2.

[0031] Figure 14 It is along Figure 13 The sectional view is obtained by cutting along line AA.

[0032] Figure 15 It is along Figure 13 The sectional view is obtained by cutting along the BB line.

[0033] Figure 16 This is a cross-sectional view illustrating an example of the connection between a memory cell array and a word driver.

[0034] Figure 17 This is a cross-sectional view illustrating an example of the connection relationship between the memory cell array and the I / O circuitry.

[0035] Figure 18 This is a cross-sectional view showing an example of the connection relationship between the I / O circuit and the control circuit section.

[0036] Figure 19 This is a cross-sectional view showing an example of the connection between the word driver and the control circuit section.

[0037] Figure 20 This is a top view showing the layout structure of the storage module in Embodiment 3.

[0038] Figure 21 This is an equivalent circuit diagram showing the memory cell of a dual-port SRAM.

[0039] Figure 22 (a) is a top view showing the layout structure within the semiconductor substrate and the 0th wiring layer. Figure 22(b) is a top view showing the layout structure of the first to third wiring layers.

[0040] Figure 23 It is along Figure 22 The sectional view obtained by cutting along line AA in (b).

[0041] Figure 24 It is along Figure 22 The sectional view obtained by cutting along line BB of (b). Detailed Implementation

[0042] In the following embodiments, for convenience, they will be described in multiple chapters or embodiments when necessary. However, unless otherwise specified, the above multiple chapters or embodiments are not unrelated to each other, but are related as variations, details, complementary descriptions, etc., where one is a part or all of the other.

[0043] Furthermore, in the following embodiments, when referring to the number of elements (including number, value, quantity, range, etc.), except where specifically stated or where it is explicitly limited to a specific number in principle, it is not limited to that specific number; it may be more than or less than that specific number.

[0044] Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily required, except where specifically stated or where they are considered obviously necessary in principle.

[0045] Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of constituent elements, etc., the meaning includes shapes that are substantially similar or analogous to the shape, except where specifically stated or where it is believed to be obviously not so in principle. The same applies to the numerical values ​​and ranges mentioned above.

[0046] Furthermore, in all the accompanying drawings used to illustrate the embodiments, the same reference numerals are used in principle to label the same components, and repeated descriptions are omitted. In addition, for ease of understanding, even top views are sometimes marked with shaded lines.

[0047] (Implementation Method 1)

[0048] Semiconductor chip layout structure

[0049] Referring to the accompanying drawings, the semiconductor device of Embodiment 1 will be described. First, the layout structure of the semiconductor chip in which a system including a microcomputer is formed will be described. Figure 1This is a diagram showing the layout structure of the semiconductor chip CHP according to Embodiment 1. The semiconductor chip CHP includes a CPU (Central Processing Unit) 1, RAM (Random Access Memory) 2, logic circuits 3, EEPROM (Electrically Erasable Programmable Read Only Memory) 4, flash memory 5, and I / O (Input / Output) circuits 6.

[0050] CPU (circuit) 1, also known as the central processing unit, is equivalent to the heart of a computer. CPU 1 reads and interprets commands from storage devices, and performs various calculations or controls based on these commands.

[0051] RAM (circuit) 2 is a memory capable of random access to stored information, that is, reading out or rewriting stored information at any time; it is also called a memory capable of being written to and read out at any time. As an IC memory, RAM comes in two types: DRAM (Dynamic RAM, Dynamic Random Access Memory), which uses dynamic circuitry, and SRAM (Static RAM, Static Random Access Memory), which uses static circuitry. DRAM is a write-and-read memory that requires memory retention, while SRAM is a write-and-read memory that does not require memory retention. In this embodiment 1, RAM 2 is constructed using SRAM.

[0052] Logic circuit 3 is a circuit that processes voltage and / or current signals that change continuously over time, i.e., a circuit that processes logic signals, and is composed of, for example, amplifier circuits, conversion circuits, modulation circuits, oscillation circuits, power supply circuits, etc.

[0053] EEPROM 4 and Flash Memory 5 are types of electrically rewritable non-volatile memory capable of both write and erase operations, also known as electrically erasable programmable read-only memory. The memory cells of EEPROM 4 and Flash Memory 5 are composed of storage (memory) transistors such as MONOS (Metal Oxide Nitride Oxide Semiconductor) or MNOS (Metal Nitride Oxide Semiconductor). The write and erase operations of EEPROM 4 and Flash Memory 5 utilize, for example, the Fowler-Nordheim tunneling phenomenon. Furthermore, hot electrons or hot holes can also be used for write or erase operations. The difference between EEPROM 4 and Flash Memory 5 is that EEPROM 4 is a non-volatile memory that can be erased, for example, at the byte level, while Flash Memory 5 is a non-volatile memory that can be erased, for example, at the word line level. Typically, flash memory 5 stores programs used by CPU 1 to perform various processes. In contrast, EEPROM 4 stores various data that are frequently rewritten.

[0054] I / O circuit 6 is an input / output circuit, used to output data from inside the semiconductor chip CHP to devices connected to the outside of the semiconductor chip CHP, and to input data from devices connected to the outside of the semiconductor chip CHP to the inside of the semiconductor chip.

[0055] The semiconductor chip CHP in this embodiment 1 is laid out as described above. Hereinafter, the SRAM constituting RAM2 will be described.

[0056] SRAM structure

[0057] Figure 2 This is a top-view block diagram that roughly shows the overall structure of SRAM. The following section focuses on... Figure 2 The overall structure of the SRAM shown will be described. This SRAM includes a memory mat circuit MM, I / O circuitry (input / output circuitry) 100, a word driver WD, a row decoder RD, a control circuit CU, a column decoder CD, word lines WL, bit lines BL and complementary bit lines / BL forming bit line pairs, cell power lines ARVDD, and local ground lines ARVSS. Preferably, there are multiple bit line pairs (BL, / BL), cell power lines ARVDD, and local ground lines ARVSS.

[0058] The memory cluster circuit MM has a memory cell array MCA, a ground wire switch circuit ARGSW1, and a ground wire switch circuit ARGSW2. The memory cell array MCA has multiple memory cells MC arranged in a horizontal and vertical configuration.

[0059] I / O circuit 100 includes column selection switch circuit CSS, unit power supply voltage line control circuit ARVC, readout amplifier circuit SA, and write driver circuit WDC.

[0060] Next, regarding Figure 2 The connection relationships of the components of the SRAM are explained below. The cell power supply voltage line control circuit ARVC is connected to the memory cell MC via the cell power supply line ARVDD. Here, along... Figure 2 Multiple storage cells (MCs) arranged horizontally in the middle are connected to, for example, the same cell power line (ARVDD). Additionally, along... Figure 2 Multiple storage cells (MCs) arranged vertically in the middle are grounded via the same local ground line (ARVSS).

[0061] The column select switch circuit CSS and the memory cell MC are connected via bit line pairs (BL, / BL). Here, for example, along... Figure 2 The horizontally configured multiple memory cells (MCs) are connected via the same bit line (BL) and also via the same complementary bit line ( / BL).

[0062] The word drive WD and the memory cell MC are connected via word line WL. Here, for example, along... Figure 2 Multiple storage cells (MCs) arranged vertically in the middle are connected to the same word line (WL).

[0063] Next, regarding Figure 2 The operation of the SRAM will be explained below. The control circuit unit (CU) receives the chip enable signal CEN, the write enable signal WEN, and the address signal Add. When the chip enable signal CEN is inactive, the control circuit unit (CU) is in the off state. When the chip enable signal CEN is active, the control circuit unit (CU) is in the on state and performs SRAM read and write operations.

[0064] When the write enable signal WEN indicates that data is to be written, the control circuit CU activates the write driver circuit WDC. The write driver circuit WDC is activated during a write operation, transmitting the input data signal Din to the column selection switch circuit CSS. The write driver circuit WDC is inactive except when a write operation is being performed.

[0065] When the write enable signal WEN indicates data read, the control circuit CU activates the sense amplifier circuit SA. The sense amplifier circuit SA is activated during a read operation, amplifying the weak read data signal transmitted from the column selection switch circuit CSS and generating the output data signal Dout. The sense amplifier circuit SA is inactive except during read operations.

[0066] The control circuit unit (CU) generates the row address RAdd and the column address CAdd based on the address signal Add.

[0067] The line decoder RD takes the line address RAdd as input and decodes it, then controls the word driver WD based on the decoding result. The word driver WD has multiple word drivers corresponding to multiple lines. The word driver corresponding to the line represented by the decoding result of line address RAdd is activated to drive the corresponding word line WL.

[0068] The column decoder CD inputs the column address CAdd and decodes it. Based on the decoding result, it controls the column selection switch circuit CSS and the unit power supply voltage line control circuit ARVC.

[0069] The column selection switch circuit CSS selects the bit line pair (BL, / BL) corresponding to the column address CAdd from among multiple bit line pairs (BL, / BL) corresponding to multiple columns. The selected bit line pair (BL, / BL) is connected to the sense amplifier circuit SA during a read operation and to the write driver circuit WDC during a write operation. Furthermore, before performing a read or write operation, the selected bit line pair (BL, / BL) is charged to the level of the external power supply voltage Vdd by a bit line precharge circuit (not shown).

[0070] The cell power line control circuit ARVC controls the voltage level of the cell power line ARVDD for each column. During a write operation, the ARVC causes the voltage of the selected column's cell power line ARVDD to drop from the external power supply voltage Vdd level, while maintaining the voltage of the other columns' cell power lines ARVDD at the external power supply voltage Vdd level. Conversely, during a read operation and in standby mode, the ARVC maintains the voltage of all cell power lines ARVDD at the external power supply voltage Vdd level.

[0071] Structure of SRAM storage cells

[0072] Next, the equivalent circuit of the memory cell MC that constitutes SRAM will be explained. Figure 3 This is an equivalent circuit diagram showing the SRAM storage cell MC in Embodiment 1. For example... Figure 3As shown, the memory cell MC is located at the intersection of a pair of complementary bit lines (bit line BL, bit line / (slash) BL) and a word line WL. It consists of a pair of driver MISFETs (Qd1, Qd2), a pair of load MISFETs (Qp1, Qp2), and a pair of transfer MISFETs (Qt1, Qt2). The driver MISFETs (Qd1, Qd2) and transfer MISFETs (Qt1, Qt2) are n-channel MISFETs, while the load MISFETs (Qp1, Qp2) are p-channel MISFETs.

[0073] Of the six MISFETs constituting the memory cell MC, the driving MISFET Qd1 and the load MISFET Qp1 form a CMOS inverter INV1, and the driving MISFET Qd2 and the load MISFET Qp2 form a CMOS inverter INV2. The input / output terminals (accumulation nodes A and B) of this pair of CMOS inverters INV1 and INV2 are cross-connected to form a flip-flop circuit that serves as the information storage unit for storing 1 bit of information. Furthermore, one input / output terminal (accumulation node A) of this flip-flop circuit is connected to one of the source and drain regions of the transfer MISFET Qt1, and the other input / output terminal (accumulation node B) is connected to one of the source and drain regions of the transfer MISFET Qt2.

[0074] Furthermore, one of the source and drain regions of the transfer MISFET Qt1 is connected to the bit line BL, and the other of the source and drain regions of the transfer MISFET Qt2 is connected to the bit line / BL. Additionally, one end of the trigger circuit (each source region of the load MISFETs Qp1 and Qp2) is connected to the power supply voltage (Vcc), and the other end (each source region of the drive MISFETs Qd1 and Qd2) is connected to the reference voltage (Vss).

[0075] To explain the operation of the above circuit, when the accumulation node A of a CMOS inverter INV1 is at a high potential (“H”), the driving MISFET Qd2 becomes ON, thereby causing the accumulation node B of the other CMOS inverter INV2 to become low potential (“L”). Therefore, the driving MISFET Qd1 becomes OFF, and accumulation node A remains at a high potential (“H”). In other words, a latch-up circuit that cross-connects a pair of CMOS inverters INV1 and INV2 maintains the states of their respective accumulation nodes A and B, preserving information during the period when a power supply voltage is applied.

[0076] Word line WL is connected to the gate electrodes of the transfer MISFETs Qt1 and Qt2, and the conduction and deconduction of the transfer MISFETs Qt1 and Qt2 are controlled by word line WL. That is, when word line WL is at a high potential ("H"), since the transfer MISFETs Qt1 and Qt2 are turned on, the latch circuit is electrically connected to the complementary bit lines (bit lines BL and slash BL), so the potential state ("H" or "L") of the accumulation nodes A and B is reflected to the bit lines DL and / DL, and is read out as information of the memory cell MC.

[0077] To write information to the memory cell MC, the word line WL is set to the "H" potential level, the transfer MISFETs Qt1 and Qt2 are set to the ON state, and the information on the bit lines BL and / BL is transmitted to the accumulation nodes A and B. In this manner, the SRAM can be activated.

[0078] Basic idea of ​​implementation method 1

[0079] Next, the basic idea of ​​this implementation method 1 will be explained. Figure 4 This diagram illustrates the basic idea of ​​Embodiment 1. Figure 4 (a) is a cross-sectional view showing a schematic construction of a planar FET. Figure 4 (b) is a cross-sectional view showing a schematic construction of a FINFET.

[0080] First of all, Figure 4 In (a), for a planar FET, a gate electrode GE is formed over a gate insulating film on a semiconductor substrate, and a contact interlayer insulating film (CIL) is formed to cover the gate electrode GE. Furthermore, a plug PLG is formed through the contact interlayer insulating film CIL, and this plug PLG is connected to a wiring L1 disposed above the contact interlayer insulating film CIL. In a semiconductor device having this planar FET configuration, no wiring is formed on the contact interlayer insulating film CIL. Therefore, in a semiconductor device having a planar FET, the lowest wiring layer is a first wiring layer that includes the wiring L1 disposed above the contact interlayer insulating film CIL.

[0081] On the other hand, Figure 4In (b), the FINFET has a fin formed above the semiconductor substrate 1S. This fin is a region in the shape of a long, thin strip (cubic parallelepiped), and its two side faces serve as the channel of the FINFET. Furthermore, the gate electrode GE of the FINFET is formed across the two side faces of the fin in a shape that spans the fin, forming a so-called dual-gate structure. According to this configuration, the gate electrode GE provides better potential control over the channel region compared to conventional single-gate (planar) MISFETs. Therefore, using a FINFET offers advantages such as high breakdown strength between the source and drain regions, and the ability to suppress short-channel effects even with a short gate length. Moreover, in the FINFET, since the two side faces of the fin are used as the channel, the area of ​​the channel region through which current flows can be increased, resulting in a high current drive force. In other words, using a FINFET allows for both suppression of short-channel effects and ensuring a high current drive force.

[0082] In this FINFET configuration, compared to a planar FET, due to the gradual miniaturization of the gate electrode GE, a top-mounted wiring PO connected to the gate electrode GE can be formed in the interlayer insulating film, and a substrate-mounted wiring OD can be formed above the semiconductor substrate 1S. Furthermore, in a semiconductor device with a FINFET, corresponding to the miniaturization of the FINFET, the top-mounted wiring PO and the substrate-mounted wiring OD can be electrically connected inside the interlayer insulating film. That is, in a semiconductor device with a FINFET, a wiring network consisting of the top-mounted wiring PO and the substrate-mounted wiring OD can be formed inside the interlayer insulating film. Moreover, as... Figure 4 As shown in (b), the overhead wiring PO and the substrate-above wiring OD are electrically connected to wiring L1 via plug PLG.

[0083] Therefore, in a semiconductor device with a FINFET, the wiring network formed by the overhead wiring PO and the substrate wiring OD inside the contact interlayer insulating film is the lowest wiring layer. That is, in a semiconductor device with a FINFET, the lowest wiring layer is the 0th wiring layer, which is formed inside the contact interlayer insulating film and includes the overhead wiring PO and the substrate wiring OD.

[0084] Based on the above explanation, since FINFETs are smaller than planar FETs, in semiconductor devices with FINFETs, a wiring network consisting of the overlay wiring PO and the overlay wiring OD can be provided as the 0th wiring layer inside the interlayer insulating film. Furthermore, the basic idea of ​​this embodiment 1 is based on the fact that a 0th wiring layer can be provided in a semiconductor device with FINFETs.

[0085] The following will explain this point. Figure 5 (a) is a table showing the wiring layers used in an SRAM employing planar FETs. For example... Figure 5 As shown in (a), in an SRAM using planar FETs, since a 0th wiring layer (M0) cannot be configured, wiring layers 1 (M1) to 5 (M5) are used. Specifically, contact wiring is configured on the 1st wiring layer (M1), and bit lines and power lines are configured on the 2nd wiring layer (M2). Furthermore, word lines and power lines are configured on the 3rd wiring layer (M3), and power lines are configured on the 4th wiring layer (M4) and 5th wiring layer (M5).

[0086] In contrast, Figure 5 (b) is a table showing the wiring layers used in SRAM employing FINFETs. (See table below.) Figure 5 As shown in (b), in an SRAM using FINFETs, since a 0th wiring layer (M0) can be set, wiring layers 0 through 5 (M5) can be used. Specifically, contact wiring is provided on the 0th wiring layer (M0), and bit lines and power lines are provided on the 1st wiring layer (M1). Furthermore, word lines and power lines are provided on the 2nd wiring layer (M2), and power lines are provided on the 4th and 5th wiring layers (M5). Therefore, in an SRAM using FINFETs, since the 0th wiring layer can be set by miniaturizing the FINFETs, as shown in (b), the 0th wiring layer can be set, and the 0th wiring layer can be used, and the 0th wiring layer can be used, and the 5 ... Figure 5 As shown in (b), for example, the third wiring layer (M3) is not used. In other words, in an SRAM using FINFETs, space is created in the third wiring layer (M3).

[0087] The basic idea of ​​this embodiment 1 is to make effective use of the space. That is, the basic idea of ​​this embodiment 1 is to make effective use of the space generated in the third wiring layer (M3) by the 0th wiring layer (M0) that can exist due to the miniaturization of FINFET. In other words, the basic idea of ​​this embodiment 1 is to make effective use of the third wiring layer that does not need to be used as a wiring layer to constitute SRAM, and in particular, to improve the performance of semiconductor devices, the space generated in the third wiring layer is utilized.

[0088] Hereinafter, examples of specific implementations of the basic idea of ​​Embodiment 1 will be described. Specifically, based on the new insights proposed by the inventors of the present invention, and from the viewpoint of seeking to improve the performance of semiconductor devices, a structural example that effectively utilizes the space generated in the third wiring layer will be described.

[0089] Research on improvement

[0090] High-speed operation is expected in SRAM using FinFETs. Here, Figure 6 This is a waveform diagram showing the relationship between the word line voltage and read time during SRAM readout. Figure 6 In the diagram, (1) shows the waveform of a memory cell located at the proximal end of the word driver, and (2) shows the waveform of a memory cell located at the distal end of the word driver. Figure 6 As shown, memory cells located at the far end of the word driver take longer to rise in word line voltage compared to those located at the near end. Therefore, to adequately ensure the bit line potential difference, the read timing must be delayed, which is a major obstacle to high-speed SRAM operation.

[0091] Regarding this point, the inventors of this invention first investigated improving the driving capability of the transistors constituting the word driver in order to improve the main cause of this obstacle, but this countermeasure did not improve the waveform of the word line voltage. Therefore, the inventors of this invention conducted in-depth research and discovered that the wiring resistance of the word line affects the waveform rounding. That is, the inventors of this invention derived a new insight that the rise time of the word line voltage is greatly affected by the wiring resistance of the word line. Therefore, based on this rediscovered insight, the inventors of this invention discovered that if the resistance of the word line can be reduced, the rounding of the word line voltage waveform can be eliminated, thereby finding a direction to achieve high-speed operation of SRAM. Therefore, in this Embodiment 1, based on the new insight that high-speed operation of SRAM can be achieved by reducing the resistance of the word line, in order to achieve the reduction of the resistance of the word line, it is studied how to effectively utilize the space generated in the third wiring layer. Hereinafter, the technical idea of ​​this Embodiment 1 will be explained.

[0092] Planar layout structure of storage cells

[0093] Figure 7 This is a top view showing the planar layout structure of the SRAM storage cells according to Embodiment 1. In particular, Figure 7 (a) is a top view showing the layout structure within the semiconductor substrate and the 0th wiring layer. Figure 7 (b) is a top view showing the layout structure of the first to third wiring layers. Furthermore, although a fourth and fifth wiring layer also exist in the SRAM memory cells, these wiring layers are not significantly related to the technical concept of Embodiment 1, and therefore are omitted from the description and illustrations in the following description and drawings.

[0094] For example Figure 7As shown in (a), the SRAM memory cell consists of six transistors (FINFETs): a pair of driving MISFETs (Qd1, Qd2), a pair of load MISFETs (Qp1, Qp2), and a pair of transfer MISFETs (Qt1, Qt2) formed on a semiconductor substrate. In this case, the driving MISFETs (Qd1, Qd2) and the transfer MISFETs (Qt1, Qt2) are n-channel MISFETs, while the load MISFETs (Qp1, Qp2) are p-channel MISFETs.

[0095] like Figure 7 As shown in (a), a device isolation region is formed on a semiconductor substrate, and active regions ACT1n, ACT1p, ACT2n, and ACT2p are defined by this device isolation region. Specifically, the active region ACT1n, defined by the device isolation region, is formed extending in the x-direction, and the active region ACT1p is formed next to the active region ACT1n, separated by the device isolation region, and also extending in the x-direction. Furthermore, the active region ACT2p is formed next to the active region ACT1p, separated by the device isolation region, and also extending in the x-direction. Moreover, the active region ACT2n is formed next to the active region ACT2p, separated by the device isolation region, and also extending in the x-direction. Thus, in an SRAM, as... Figure 7 As shown in (a), active regions ACT1n, ACT1p, ACT2p, and ACT2n are formed side by side in the y direction, separated by component isolation regions, and each active region ACT1n, ACT1p, ACT2p, and ACT2n is formed in a manner that extends in the x direction.

[0096] The active regions ACT1n and ACT2n are semiconductor regions in which n-type impurities such as phosphorus or arsenic have been introduced into the semiconductor substrate, while the active regions ACT1p and ACT2p are semiconductor regions in which p-type impurities such as boron have been introduced into the semiconductor substrate.

[0097] First, focusing on the active region ACT1n, gate electrodes GE1 and GE3 are formed in a manner that intersects with the active region ACT1n extending in the x-direction. That is, gate electrodes GE1 and GE3 are configured to be parallel to each other and extend in the y-direction. At this time, a transmission MISFET Qt1 is formed by the gate electrode GE1 and the active regions ACT1n formed on both sides of the gate electrode GE1. In this transmission MISFET Qt1, the active regions ACT1n formed on both sides of the gate electrode GE1 serve as the source region and the drain region, and a substrate overlay wiring OD is disposed above the active regions ACT1n that serve as the source region or the drain region.

[0098] On the other hand, the gate electrode GE1 of the MISFET Qt1 for transmission extends from above the active region ACT1n to above the device isolation region.

[0099] Furthermore, focusing on the active region ACT1n within the memory cell, a driving MISFET Qd1 is formed through the gate electrode GE3 and the active regions ACT1n formed on both sides of the gate electrode GE3. In this driving MISFET Qd1, the active regions ACT1n formed on both sides of the gate electrode GE3 serve as the source region and the drain region, respectively, and a substrate overlay wiring OD is disposed above the active regions ACT1n that serve as the source region or the drain region. In this way, a transport MISFET Qt1 and a driving MISFET Qd1 are formed in the active region ACT1n.

[0100] Next, focusing on the active region ACT1p, a gate electrode GE3 is formed in a manner that intersects with the active region ACT1p extending in the x-direction. That is, the gate electrode GE3, disposed above the active region ACT1n, further extends in the y-direction until it reaches above the active region ACT1p. The load MISFET Qp1 is formed by the gate electrode GE3 and the active regions ACT1p formed on both sides of the gate electrode GE3. Therefore, it can be seen that the gate electrode GE3 functions as the gate electrode of the driving MISFET Qd1 due to its relationship with the active region ACT1n, and functions as the gate electrode of the load MISFET Qp1 due to its relationship with the active region ACT1p.

[0101] In the load-use MISFET Qp1, a substrate-above-wire OD is disposed above the active region ACT1p formed on one side of the gate electrode GE3. Within the memory cell, the end of the gate electrode GE4 is disposed near the left end of the active region ACT1p. Furthermore, a direct-above-wire PO is formed above the gate electrode GE4, and this direct-above-wire PO is connected to the substrate-above-wire OD disposed above the active region ACT1p.

[0102] Next, focusing on the active region ACT2p, a gate electrode GE4 is formed in a manner that intersects the active region ACT2p extending in the x-direction. This gate electrode GE4 is positioned near the left end of the active region ACT1p and is formed to extend in the y-direction and intersect the active region ACT2p. The gate electrode GE4 and the active regions ACT2p formed on both sides of the gate electrode GE4 together form a load MISFET Qp2.

[0103] In the load MISFET Qp2, an over-substrate wiring OD is disposed above the active region ACT2p formed on one side of the gate electrode GE4, and this over-substrate wiring OD is connected to the over-substrate wiring PO. Moreover, the over-substrate wiring PO is configured to be connected to the top of the gate electrode GE3.

[0104] Furthermore, focusing on the active region ACT2n, gate electrodes GE4 and GE2 are formed in a manner that three-dimensionally intersects with the active region ACT2n extending in the x-direction. That is, gate electrodes GE4 and GE2 are arranged parallel to each other and extend in the y-direction. At this time, a driving MISFET Qd2 is formed by the gate electrode GE4 and the active region ACT2n formed on both sides of the gate electrode GE4. In this driving MISFET Qd2, the active regions ACT2n formed on both sides of the gate electrode GE4 become the source region and the drain region, and a substrate overlay OD is arranged above the active region ACT2, which becomes the source region and the drain region. At this time, one end of the gate electrode GE4 is arranged near the left end of the active region ACT1p, and extends in the y-direction in a manner that three-dimensionally intersects with both the active regions ACT2p and ACT2n. Therefore, one end of the gate electrode GE4 is connected to the overhead overlay PO. Furthermore, it is known that the gate electrode GE4 functions as the gate electrode of the load MISFET Qp2 due to its relationship with the active region ACT2p, and functions as the gate electrode of the drive MISFET Qd2 due to its relationship with the active region ACT2n.

[0105] On the other hand, a transfer MISFET Qt2 is formed by a gate electrode GE2 and active regions ACT2n formed on both sides sandwiching the gate electrode GE2. In this transfer MISFET Qt2, the active regions ACT2n formed on both sides of the gate electrode GE2 serve as the source region and the drain region, and a substrate-above wiring OD is disposed above the active regions ACT2n that serve as the source and drain regions. In addition, the gate electrode GE2 of the transfer MISFET Qt2 extends from above the active regions ACT2n to above the device isolation region. The layout within the semiconductor substrate and the 0th wiring layer is configured in the manner described above.

[0106] Next, use Figure 7 Section (b) describes the layout structure for wiring layers 1 through 3. For example... Figure 7 As shown in (b), the plurality of traces L1 configured in the first wiring layer include, for example, power lines VSS, VDD, bit lines BL, and complementary bit lines / BL. Furthermore, these traces are arranged side-by-side with each other in the y-direction and extend in the x-direction respectively. Moreover, as... Figure 7As shown in (b), the wiring L3 configured in the third wiring layer includes, for example, auxiliary lines AL and power lines VL, which are arranged side by side with each other in the x-direction and extend in the y-direction respectively. Furthermore, in Figure 7 In (b), the wiring configured on the second wiring layer overlaps with the wiring L3 configured on the third wiring layer, therefore... Figure 7 Not shown in (b). The layout of the first to third wiring layers is constructed in the manner described above.

[0107] Cross-sectional structure of storage cell

[0108] the following, Figure 8 It is along Figure 7 The sectional view obtained by cutting along line AA in (b). Figure 8 In this process, gate electrode GE2, gate electrode GE4, and substrate wiring OD are disposed above the semiconductor substrate 1S, and a contact interlayer insulating film CIL is formed to cover the gate electrode GE2, gate electrode GE4, and substrate wiring OD. On the other hand, a diffusion layer DL is formed within the semiconductor substrate. Furthermore, a plug PLG1 and a power line VSS are formed on the contact interlayer insulating film CIL; for example, the substrate wiring OD and the power line VSS are electrically connected via the plug PLG1. Next, an interlayer insulating film IL1 is formed above the contact interlayer insulating film CIL, including the power line VSS, and a plug PLG2, a power line VL2, and a word line WL are formed on this interlayer insulating film IL1. At this time, the power line VSS and the power line VL2 are electrically connected via the plug PLG2.

[0109] Hereinafter, an interlayer insulating film IL2 is formed above the interlayer insulating film IL1 above the power line VL2 and the word line WL. Power line VL3, auxiliary line AL, plug PLG3A, and plug PLG3B are formed on the interlayer insulating film IL2. Furthermore, power line VL2 and power line VL3 are electrically connected via plug PLG3A, and word line WL and auxiliary line AL are electrically connected via plug PLG3B.

[0110] Figure 9 It is along Figure 7 The sectional view obtained by cutting along line BB of (b). Figure 9 As shown, a fin FIN and a gate electrode GE2 are formed above the semiconductor substrate 1S, and a contact interlayer insulating film CIL is formed to cover the gate electrode GE2. Moreover, a plurality of wirings L1 are formed on the contact interlayer insulating film CIL, including a power line VSS, a bit line BL, a complementary bit line / BL, and a power line VDD.

[0111] Next, an interlayer insulating film IL1 is formed above the contact interlayer insulating film CIL, including above multiple wirings L1, and a word line WL is formed on this interlayer insulating film IL1. Furthermore, an interlayer insulating film IL2 is formed above the interlayer insulating film IL1, including above the word line WL, and multiple plugs PLG3B and auxiliary lines AL are formed on this interlayer insulating film IL2. At this time, the word line WL and the auxiliary line AL are electrically connected through the multiple plugs PLG3B. Similarly, in Figure 9 Although not illustrated, for example... Figure 8 The power lines VL2 and VL3 shown are electrically connected via multiple plugs PLG3A.

[0112] The memory cell of Embodiment 1 is constructed in the manner described above. That is, the semiconductor device of Embodiment 1 includes a memory cell forming region, in which memory cells storing information are formed. In this case, the memory cell forming region includes: a semiconductor substrate; a FINFET, which includes a gate electrode formed above the semiconductor substrate; and a bottommost wiring layer, which includes a top wiring connected to the gate electrode and a substrate wiring formed above the semiconductor substrate. Furthermore, the memory cell forming region includes a first wiring layer formed above the bottommost wiring layer, a second wiring layer formed above the first wiring layer and including word lines, and a third wiring layer formed above the second wiring layer and including the first wiring. The top wiring in the bottommost wiring layer is electrically connected to the substrate wiring, and a wiring network including both the top wiring and the substrate wiring is formed in the bottommost wiring layer.

[0113] Features of Implementation Method 1

[0114] Hereinafter, the features of Embodiment 1 will be described. The first feature of Embodiment 1 is, for example, Figure 8 and Figure 9 As shown, the word line WL formed on the second wiring layer is electrically connected to the auxiliary line AL formed on the third wiring layer. Therefore, according to Embodiment 1, the resistance of the word line WL can be reduced. That is, by electrically connecting the word line WL formed on the second wiring layer to the auxiliary line AL formed on the third wiring layer, the auxiliary line AL formed on the third wiring layer can also function as a word line. This means that the number of wiring lines functioning as word lines increases, meaning that in this structure, compared to using only the word line WL formed on the second wiring layer, the overall resistance of the word line can be reduced. In other words, by using the word line WL and the auxiliary line AL connected in parallel to form the word line, the overall resistance of the word line can be reduced. As a result, even for memory cells located far from the word driver, the roundness of the word line voltage rise waveform can be improved, thereby increasing the read speed. That is, according to Embodiment 1, high-speed operation of SRAM using FINFETs can be achieved.

[0115] Thus, in this embodiment 1, based on the fundamental idea of ​​effectively utilizing the space created in the third wiring layer (M3) by the 0th wiring layer (M0) which is possible due to the miniaturization of FINFETs, a structure is adopted in which an auxiliary line AL is arranged in the space created by the third wiring layer and electrically connected to the word line WL. This achieves a countermeasure (research) based on the novel insight that the rise time of the word line voltage is greatly affected by the wiring resistance of the word line, enabling high-speed operation of the SRAM using FINFETs. In other words, in this embodiment 1, from the viewpoint of reducing the resistance of the word line WL, the performance of the SRAM with FINFETs is improved by utilizing the basic idea of ​​this embodiment 1.

[0116] In particular, based on the viewpoint of seeking to reduce the overall resistance of the word lines, for example... Figure 9 As shown, it is preferable to electrically connect the word line WL formed on the second wiring layer and the auxiliary line AL formed on the third wiring layer using multiple plugs PLG3B. This is because, by using multiple plugs PLG3B to electrically connect the word line WL and the auxiliary line AL, compared to connecting the word line WL and the auxiliary line AL using a single plug PLG3B, the overall resistance of the word line can be reduced. Therefore, by at least electrically connecting the word line WL and the auxiliary line AL, high-speed operation of the SRAM can be achieved due to the reduction in the overall resistance of the word line. However, to further reduce the overall resistance of the word line and improve the high-speed operation of the SRAM, it is preferable to use multiple plugs PLG3B to electrically connect the word line WL and the auxiliary line AL.

[0117] Next, the second feature of this embodiment 1 is, for example, Figure 8 and Figure 9 As shown, power line VL2 formed on the second wiring layer is electrically connected to power line VL3 formed on the third wiring layer. Therefore, according to Embodiment 1, the stability of the power line can be improved. Specifically, by electrically connecting power line VL2 formed on the second wiring layer to power line VL3 formed on the third wiring layer, the overall resistance of the power line can be reduced. This suppresses power drop (voltage drop) on the power line. As a result, the operational stability of the SRAM can be improved.

[0118] In particular, in SRAM using FinFETs, the power supply voltage used in the SRAM can be reduced as the FinFETs are miniaturized, thereby reducing the SRAM's power consumption. On the other hand, a lower power supply voltage also means greater susceptibility to power drops. In this case, if the power drop becomes significant, the risk of the SRAM malfunctioning increases. In this regard, in this embodiment 1, since the power line VL2 formed on the second wiring layer and the power line VL3 formed on the third wiring layer are connected in parallel, the overall resistance of the power lines can be reduced. This means that the power lines in this embodiment 1 suppress power drops based on parasitic resistance (wiring resistance), thereby improving the operational stability of the SRAM. That is, according to this embodiment 1, by using miniaturized FinFETs in the SRAM, power consumption due to power supply voltage drops can be reduced, and since the second feature of this embodiment 1 is adopted, the overall resistance of the power lines can be reduced, thus eliminating SRAM operational instability caused by power drops. In other words, according to this embodiment 1, the good effects of reducing SRAM power consumption and improving SRAM operational stability can be obtained.

[0119] Furthermore, from the viewpoint of reducing the overall resistance of the power lines, it is preferable to electrically connect power lines VL2 and VL3 using multiple plugs PLG3A. This is because, by using multiple plugs PLG3A to electrically connect power lines VL2 and VL3, compared to connecting power lines VL2 and VL3 using a single plug PLG3A, the overall resistance of the power lines can be reduced. In this case, since the overall resistance of the power lines can be further reduced, power degradation is less likely to occur, thereby further improving the operational stability of the SRAM.

[0120] As described above, in this Embodiment 1, the basic idea of ​​this Embodiment 1 is utilized from the viewpoints of reducing the overall resistance of the word lines (first feature point) and reducing the overall resistance of the power lines. Specifically, in order to reduce the overall resistance of the word lines, an auxiliary line AL (first feature point) electrically connected to the word line WL is arranged in the space generated in the third wiring layer, and in order to reduce the overall resistance of the power lines, a power line VL3 (second feature point) electrically connected to the power line VL2 is arranged in the space generated in the third wiring layer. As a result, according to this Embodiment 1, it is possible to improve the performance of the SRAM with FINFET.

[0121] Variations

[0122] Hereinafter, a variation of Implementation 1 will be described. Figure 10 Is with Figure 8The corresponding diagram is a cross-sectional view of the storage unit in this modified example. Similarly, Figure 11 Is with Figure 9 The corresponding figure is a cross-sectional view of the storage unit in this modified example.

[0123] like Figure 10 and Figure 11 As shown, a key feature of this modified example is that, in either the sectional view or the top view, the word line WL formed on the second wiring layer and the auxiliary line AL formed on the third wiring layer, although not electrically connected, are configured to overlap. This makes the word line WL less susceptible to external noise. Specifically, the overlapping configuration of the word line WL and the auxiliary line AL allows the auxiliary line AL to function as a shield protecting the word line WL from external noise, thereby improving the noise immunity of the word line WL. Therefore, according to this modified example, since SRAM malfunctions caused by noise superimposed on the word line WL can be suppressed, the operational reliability of the SRAM can be improved.

[0124] As described above, in this modification, the basic idea of ​​Embodiment 1 is utilized to improve the noise immunity of the word line WL. Specifically, to improve the noise immunity of the word line WL, an auxiliary line AL is arranged in the space generated in the third wiring layer that overlaps with the word line WL in both top and cross-sectional views. As a result, according to this modification, the auxiliary line AL can function as a shield to protect the word line WL from external noise, thereby improving the noise immunity of the word line WL. That is, according to this modification, the operational reliability of the SRAM with FINFETs can be improved.

[0125] (Implementation Method 2)

[0126] Basic idea of ​​implementation method 2

[0127] Figure 12 (a) is a table showing the wiring layers of the peripheral circuitry for an SRAM using planar FETs. (See table for details.) Figure 12 As shown in (a), in the peripheral circuit using a planar FET, since a 0th wiring layer (M0) cannot be provided, wiring layers 1 (M1) to 4 (M4) are used. Specifically, contact wiring, signal wiring, and power lines are arranged on the 1st wiring layer (M1), and signal wiring and power lines are arranged on the 2nd wiring layer (M2). Furthermore, signal wiring and power lines are arranged on the 3rd wiring layer (M3), and power lines are arranged on the 4th wiring layer (M4).

[0128] In contrast, Figure 12 (b) is a table showing the wiring layers of the peripheral circuitry for an SRAM using FINFETs. Figure 12As shown in (b), in the peripheral circuit using a FINFET, since a 0th wiring layer (M0) can be provided, wiring layers 0 to 4 (M4) are used. Specifically, contact wiring, signal wiring, and power lines are arranged on the 0th wiring layer (M0), and signal wiring and power lines are arranged on the 1st wiring layer (M1). Furthermore, signal wiring and power lines are arranged on the 2nd wiring layer (M2), and power lines are arranged on the 4th wiring layer (M4). Therefore, in the peripheral circuit using a FINFET, since the 0th wiring layer is provided by miniaturizing the FINFET, as... Figure 12 As shown in (b), for example, the third wiring layer (M3) is in an unused state. In other words, in the peripheral circuit using FINFET, space is created in the third wiring layer (M3).

[0129] Here, the gate electrode of the FINFET is also formed on the 0th wiring layer (M0), and the multiple wirings constituting the 0th wiring layer need to be arranged to avoid the gate electrode of the FINFET. That is, since the gate electrode of the FINFET is also present on the 0th wiring layer, the layout of the wiring on the 0th wiring layer is limited compared to the other 1st to 4th wiring layers. Therefore, in the case where signal wirings, power lines, and contact wiring constituting the peripheral circuit are formed on the 0th to 2nd and 4th wiring layers in the peripheral circuit using the FINFET, there are more restrictions on the layout compared to the case where signal wirings, power lines, and contact wiring constituting the peripheral circuit are formed on the 1st to 4th wiring layers in the peripheral circuit using a planar FET. As a result, in the peripheral circuit using the FINFET, if signal wirings, power lines, and contact wiring constituting the peripheral circuit are formed on the 0th to 2nd and 4th wiring layers, the occupied area of ​​the peripheral circuit becomes larger. That is, even if a FINFET that is smaller than a planar FET is used, it is not possible to reduce the occupied area of ​​the peripheral circuit to a sufficiently small size.

[0130] Therefore, in this embodiment 2, in order to reduce the area occupied by the peripheral circuit, the space generated in the third wiring layer is effectively utilized. That is, the basic idea of ​​this embodiment 2 is to effectively utilize the space generated in the third wiring layer (M3) by the 0th wiring layer (M0), which is possible due to the miniaturization of the FINFET. In other words, the basic idea of ​​this embodiment 2 is to effectively utilize the third wiring layer, which does not need to be used as a wiring layer to constitute the peripheral circuit, and in particular, from the viewpoint of reducing the area of ​​the peripheral circuit, utilize the space generated in the third wiring layer. Specifically, in a peripheral circuit using a FINFET, such as... Figure 12As shown in (c), not only wiring layers 0 through 2 and 4 are used, but also a third wiring layer that creates space is used to form signal wiring, power lines, and contact wiring constituting the peripheral circuit. Therefore, since the number of wiring layers required for configuring the peripheral circuit can be increased, the planar size (layout area) of the peripheral circuit can be reduced. That is, Figure 12 (c) is a table showing the wiring layer of the peripheral circuitry of the SRAM using FINFETs, in accordance with the basic idea of ​​Embodiment 2. Figure 12 As shown in (c), in this embodiment 2, not only are the 0th to 2nd wiring layers and the 4th wiring layer used, but also the 3rd wiring layer, which generates space, is used. This embodies the basic idea of ​​this embodiment 2, and the layout of the peripheral circuit will be implemented concretely hereafter. Hereinafter, examples illustrating the basic idea of ​​this embodiment 2 will be described. Specifically, from the viewpoint of reducing the area occupied by the peripheral circuit of the SRAM, a structural example that effectively utilizes the space generated in the 3rd wiring layer will be described.

[0131] Storage module layout structure

[0132] Figure 13 This is a top view showing the layout structure of the storage module in Embodiment 2. Figure 13 As shown, the storage module of this embodiment 2 includes a storage cell array MCA, an I / O circuit 100, a control circuit unit CU, and a word driver WD. Figure 13 As can be seen from the diagram, the I / O circuit 100, the control circuit section CU, and the word driver WD constituting the peripheral circuit are formed by wiring OD formed above the substrate of the 0th wiring layer, wiring L1 formed on the 1st wiring layer, wiring L2 formed on the 2nd wiring layer, and wiring L3 formed on the 3rd wiring layer, respectively, reflecting the basic idea of ​​this embodiment 2.

[0133] In particular, Figure 13 In the layout shown, the 0th wiring layer, which serves as the lowest wiring layer for the peripheral circuitry, is formed by wiring OD above the substrate extending in a direction parallel to the word lines (y-direction). This is because, although in Figure 13 Not shown in the diagram, but a FINFET gate electrode is also formed in the 0th wiring layer. The 0th wiring layer is limited by the presence of this gate electrode and is only composed of wiring OD above the substrate parallel to the extending direction (y-direction) of the FINFET gate electrode. Additionally, in Figure 13 In this configuration, multiple wirings L1 formed on the first wiring layer extend in the x-direction, and these wirings L1 include signal wirings and power lines. Furthermore, in... Figure 13In this embodiment, multiple wirings L2 formed on the second wiring layer also extend in the x-direction, and the multiple wirings L2 include signal wirings and power lines. Therefore, in this embodiment 2, both the wiring L1 formed on the first wiring layer and the wiring L2 formed on the second wiring layer are configured to extend in the x-direction.

[0134] Next, in Figure 13 In this configuration, multiple traces L3 formed on the third wiring layer extend in the y-direction, and the multiple traces L3 include signal traces and power lines. Based on the above description, for example, signal traces formed on the second wiring layer and signal traces formed on the third wiring layer extend in directions that intersect each other. Furthermore, the signal traces formed on the second wiring layer and the signal traces formed on the third wiring layer can be configured either without electrical connection or with electrical connection.

[0135] Cross-sectional structure of peripheral circuit

[0136] Figure 14 It is along Figure 13 A sectional view obtained by cutting along line AA. For example... Figure 14 As shown, a diffusion layer DL, serving as a semiconductor region, is formed within the semiconductor substrate 1S. A gate electrode GE for a FINFET and a substrate-surface wiring OD are formed above the semiconductor substrate 1S. Furthermore, a contact interlayer insulating film CIL is formed to cover the gate electrode GE and the substrate-surface wiring OD. A plug PLG1 and wiring L1 are formed on this contact interlayer insulating film CIL. For example, the substrate-surface wiring OD and wiring L1 are electrically connected via the plug PLG1.

[0137] Next, as Figure 14 As shown, an interlayer insulating film IL1 is formed above the contact interlayer insulating film CIL above the wiring L1, and plugs PLG2 and wiring L2 are formed on the interlayer insulating film IL1. Furthermore, wiring L1 and wiring L2 are electrically connected to each other via, for example, multiple plugs PLG2. Further, as... Figure 14 As shown, an interlayer insulating film IL2 is formed above an interlayer insulating film IL1, including above wiring L2. A plug PLG3 and wiring L3 are formed on the interlayer insulating film IL2. For example, wiring L2 and wiring L3 are electrically connected through the plug PLG3.

[0138] Figure 15 It is along Figure 13 A sectional view obtained by cutting along the BB line. For example... Figure 14 As shown, the fins FIN of a FINFET and the gate electrode GE are formed on the semiconductor substrate 1S. Furthermore, a contact interlayer insulating film CIL is formed to cover the gate electrode GE, and wiring L1 is formed on the contact interlayer insulating film CIL.

[0139] Next, as Figure 14 As shown, an interlayer insulating film IL1 is formed above the contact interlayer insulating film CIL above the wiring L1, and plugs PLG2 and wiring L2 are formed on the interlayer insulating film IL1. Wiring L1 and wiring L2 are electrically connected to each other via, for example, multiple plugs PLG2. Furthermore, as... Figure 14 As shown, an interlayer insulating film IL2 is formed above an interlayer insulating film IL1 above wiring L2, and a plug PLG3 and wiring L3 are formed on the interlayer insulating film IL2. For example, wiring L2 and wiring L3 are electrically connected through the plug PLG3.

[0140] As described above, in this embodiment 2, wiring L3 is formed on the third wiring layer. That is, in this embodiment 2, space is effectively utilized by forming wiring L3 on the third wiring layer, which becomes space. As a result, in the peripheral circuit of this embodiment 2, signal wiring and power wiring are configured using the 0th to 4th wiring layers. Therefore, compared to the case where the third wiring layer is not used, the layout area (planar area) of the peripheral circuit can be reduced, thereby reducing the overall footprint of the memory module. This means that a semiconductor chip (for example, see reference...) can be realized... Figure 1 The miniaturization of semiconductor chips enables the miniaturization of semiconductor devices. Furthermore, reducing the size of the semiconductor chip means increasing the number of semiconductor chips that can be obtained from the semiconductor wafer, which translates to a reduction in the manufacturing cost per semiconductor chip. Therefore, according to Embodiment 2, the effect of reducing the manufacturing cost of semiconductor devices can also be achieved.

[0141] Connection relationships between the components of a storage module

[0142] (1) Connection relationship between memory cell array MCA and word driver WD

[0143] Figure 16 This is a cross-sectional view illustrating an example of the connection between the memory cell array (MCA) and the word driver (WD). For example... Figure 16 As shown, the memory cell array MCA and the word driver WD can be electrically connected via, for example, wiring L2 formed on the second wiring layer and wiring L3 formed on the third wiring layer.

[0144] (2) Connection relationship between memory cell array MCA and I / O circuit 100

[0145] Figure 17 This is a cross-sectional view illustrating an example of the connection relationship between the memory cell array MCA and the I / O circuit 100. (See diagram below.) Figure 17As shown, the memory cell array MCA and the I / O circuit 100 enable, for example, the wiring L1 of the memory cell array MCA formed on the first wiring layer and the wiring L1 of the I / O circuit 100 formed on the first wiring layer to be electrically connected to the wiring L2 formed on the second wiring layer via the plug PLG2.

[0146] (3) Connection relationship between I / O circuit 100 and control circuit CU

[0147] Figure 18 This is a cross-sectional view showing an example of the connection relationship between the I / O circuit 100 and the control circuit section CU. For example... Figure 18 As shown, the I / O circuit 100 and the control circuit section CU can be electrically connected via, for example, wiring L3 formed on the third wiring layer.

[0148] (4) Connection between word driver WD and control circuit CU

[0149] Figure 19 This is a cross-sectional view illustrating an example of the connection between the word driver WD and the control circuit unit CU. (Example) Figure 19 As shown, the word driver WD and the control circuit CU can be electrically connected via, for example, wiring L2 formed on the second wiring layer.

[0150] (Implementation Method 3)

[0151] Storage module layout structure

[0152] Figure 20 This is a top view showing the layout structure of the storage module in Embodiment 3. Figure 20In this embodiment, the third wiring layer of the memory cell array (MCA) includes: wiring HL1 extending in the y-direction, overlapping with word lines formed in the second wiring layer; wiring HL2 extending in the y-direction, arranged on the same straight line as wiring HL1 and overlapping with word lines; and wiring HL3 extending in the x-direction, intersecting word lines when viewed from above. At this time, one end of wiring HL1 and one end of wiring HL2 are arranged opposite each other separately when viewed from above, and wiring HL3 extends in the x-direction, intersecting word lines, passing between one end of wiring HL1 and one end of wiring HL2. That is, in this embodiment 3, wiring HL1 and wiring HL2 are formed in the third wiring layer in a manner that partially overlaps with word lines, and wiring HL3 extending in the x-direction, intersecting word lines, is arranged in the space between wiring HL1 and wiring HL2. Therefore, according to this embodiment 3, it is possible to arrange wiring HL3 extending in the x-direction, intersecting word lines, in the third wiring layer, and also to form wiring HL1 and wiring HL2 electrically connected to word lines in the third wiring layer. Therefore, even when there is wiring HL3 extending in the x-direction intersecting the word line in the third wiring layer, the overall resistance of the word line can be reduced by arranging wiring HL1 and wiring HL2 above the word line in a manner that sandwiches wiring HL3 when viewed from above. In addition, wiring HL1 and wiring HL2, even if they are not electrically connected to the word line, can function as shielding lines to protect the word line from external noise as long as they are arranged to overlap with the word line when viewed from above.

[0153] For example, wiring HL3 extending in the x-direction intersecting the word line is used as a wiring capacitor to generate a negative potential for the negative boost circuit connected to I / O circuit 100. Furthermore, the width of wiring HL3 does not need to be the same as the width of wiring HL1 or wiring HL2; it can be thinner or thicker. Additionally, multiple wiring HL3s can exist.

[0154] (Implementation Method 4)

[0155] Equivalent circuit of memory cell

[0156] Figure 21 This is an equivalent circuit diagram showing the memory cell of a dual-port SRAM. For example... Figure 21As shown, a dual-port SRAM has a pair of complementary bit lines (ABL, / ABL), a pair of complementary bit lines (BBL, / BBL), two word lines AWL and BWL. Furthermore, the memory cell of the dual-port SRAM is composed of a pair of driver MISFETs (Qd1, Qd2), a pair of load MISFETs (Qp1, Qp2), a pair of transfer MISFETs (Qt1A, Qt2A), and a pair of transfer MISFETs (Qt1A, Qt2A). The driver MISFETs (Qd1, Qd2) and transfer MISFETs (Qt1A, Qt2A, Qt1B, Qt2B) are n-channel MISFETs, while the load MISFETs (Qp1, Qp2) are p-channel MISFETs.

[0157] A dual-port SRAM configured in this way has two input / output ports for input and output data, enabling data to be read from one port and written to the other port simultaneously, thus providing the advantage of high-speed data processing.

[0158] Layout structure of storage cells

[0159] Figure 22 This is a top view showing the layout structure of the storage cells. Specifically, Figure 22 (a) is a top view showing the layout structure within the semiconductor substrate and the 0th wiring layer. Figure 22 (b) is a top view showing the layout structure of the first to third wiring layers. Furthermore, a fourth and fifth wiring layer also exist in the SRAM memory cells; these wiring layers are omitted in the description and illustrations of the following specifications and figures.

[0160] For example Figure 22 As shown in (a), the SRAM memory cell is composed of eight transistors (FINFETs) formed on a semiconductor substrate, including a pair of driving MISFETs (Qd1, Qd2), a pair of load MISFETs (Qp1, Qp2), a pair of transfer MISFETs (Qt1A, Qt2A), and a pair of transfer MISFETs (Qt1B, Qt2B). In this case, the pair of driving MISFETs (Qd1, Qd2), the pair of transfer MISFETs (Qt1A, Qt2A), and the pair of transfer MISFETs (Qt1B, Qt2B) are n-channel MISFETs, while the pair of load MISFETs (Qp1, Qp2) are p-channel MISFETs.

[0161] In addition, such as Figure 22As shown in (a), a 0th wiring layer is formed above the semiconductor substrate. This 0th wiring layer has an overlying wiring PO and an overlying wiring OD. A wiring mesh is formed in the 0th wiring layer by electrically connecting the overlying wiring PO and the overlying wiring OD. The layout within the semiconductor substrate and the 0th wiring layer is configured as described above.

[0162] Next, use Figure 22 Section (b) describes the layout structure for wiring layers 1 through 3. For example... Figure 22 As shown in (b), the plurality of wirings L1 configured in the first wiring layer include, for example, power lines VSS, power lines VDD, bit lines (ABL, BBL), and complementary bit lines ( / ABL, / BBL). Furthermore, these wirings are arranged side-by-side in the y-direction and extend in the x-direction respectively. Moreover, as... Figure 22 As shown in (b), the wiring L2 configured in the second wiring layer includes word lines AWL and BWL arranged in the x-direction and extending in the y-direction. Furthermore, the wiring L3 configured in the third wiring layer includes, for example, auxiliary lines AL1 and AL2, which are arranged side-by-side in the x-direction and extend in the y-direction respectively. Here, word line AWL is electrically connected to auxiliary line AL2, and word line BWL is electrically connected to auxiliary line AL1. In top view, auxiliary lines AL1 and AL2 are staggered from each other. The layout of the first to third wiring layers is constructed in the manner described above.

[0163] Cross-sectional structure of storage cell

[0164] the following, Figure 23 It is along Figure 22 The sectional view obtained by cutting along line AA in (b). Figure 23 In this process, a diffusion layer is formed within the semiconductor substrate 1S. On the other hand, a gate electrode GE and an over-substrate wiring OD are disposed above the semiconductor substrate 1S, and a contact interlayer insulating film CIL is formed to cover the gate electrode GE and the over-substrate wiring OD. Furthermore, a plug PLG1 and a power line VSS are formed on the contact interlayer insulating film CIL. For example, the over-substrate wiring OD and the power line VSS are electrically connected via the plug PLG1. Next, an interlayer insulating film IL1 is formed above the contact interlayer insulating film CIL, including the power line VSS, and word lines AWL and BWL are formed on this interlayer insulating film IL1.

[0165] Next, an interlayer insulating film IL2 is formed above the interlayer insulating film IL1, which includes the word line AWL and the word line BWL. An auxiliary line AL1 and a plug PLG3 are formed on the interlayer insulating film IL2. Furthermore, the word line BWL and the auxiliary line AL1 are electrically connected through the plug PLG3.

[0166] Figure 24 It is along Figure 22 The sectional view obtained by cutting along line BB of (b). Figure 24 As shown, a fin FIN and a gate electrode GE are formed above the semiconductor substrate 1S, and a contact interlayer insulating film CIL is formed to cover the gate electrode GE. Furthermore, multiple wirings L1 are formed on the contact interlayer insulating film CIL.

[0167] Next, an interlayer insulating film IL1 is formed above the contact interlayer insulating film CIL, which includes multiple wirings L1, and a word line AWL is formed on this interlayer insulating film IL1. Furthermore, an interlayer insulating film IL2 is formed above the interlayer insulating film IL1, which includes the word line AWL, and multiple plugs PLG3 and auxiliary lines AL2 are formed on this interlayer insulating film IL2. At this time, the word line AWL and the auxiliary line AL2 are electrically connected through the multiple plugs PLG3.

[0168] Features of Implementation Method 4

[0169] In this embodiment 4, a dual-port SRAM storage cell with multiple ports for writing or reading information is used as a premise. Furthermore, for example... Figure 22 As shown, the feature of this embodiment 4 is that it has an auxiliary line AL2 electrically connected to the word line AWL and an auxiliary line AL1 electrically connected to the word line BWL. When viewed from above, the auxiliary lines AL1 and AL2 are arranged offset from each other.

[0170] Therefore, firstly, in this embodiment 4, since an auxiliary line AL2 electrically connected to the word line AWL is provided, the resistance of the word line AWL can be reduced. Similarly, in this embodiment 4, since an auxiliary line AL1 electrically connected to the word line BWL is provided, the resistance of the word line BWL can be reduced. Therefore, in this embodiment 4, the resistance of each of the two word lines AWL and BWL in the memory cell of the dual-port SRAM can be reduced. Here, since the dual-port SRAM itself can perform read and write operations simultaneously using two ports, it has the advantage of being able to perform data processing at high speed. Therefore, the dual-port SRAM of this embodiment 4 also has the above-mentioned advantages, and, according to this embodiment 4, since the resistance of each of the two word lines AWL and BWL can be reduced, even higher speed operation can be achieved.

[0171] Here, from the viewpoint of reducing the resistance of each of the two word lines AWL and BWL, it is preferable to extend the auxiliary line AL2 over the entire range above the word line AWL, and to extend the auxiliary line AL1 over the entire range above the word line BWL. However, in this embodiment 4, it is not configured in this way, for example... Figure 22As shown in (b), in top view, auxiliary lines AL1 and AL2 are arranged staggered from each other. This is for the reasons explained below. Since a dual-port SRAM uses two ports to perform read and write operations simultaneously, it is possible to apply voltage to two adjacent word lines AWL and BWL simultaneously. In this case, crosstalk occurs between the two adjacent word lines AWL and BWL. That is, in top view, without staggering auxiliary lines AL1 and AL2, crosstalk occurs between the two adjacent word lines AWL and BWL, and also between auxiliary lines AL1 and AL2. As a result, the operational reliability of the dual-port SRAM decreases. Therefore, in this embodiment 4, auxiliary lines AL2, which are electrically connected to word line AWL, and AL1, which is electrically connected to word line BWL, are arranged staggered from each other in top view. As a result, according to this embodiment 4, the resistance of word line AWL and word line BWL can be reduced by the presence of auxiliary lines AL1 and AL2, and crosstalk between auxiliary lines AL1 and AL2 can be suppressed by staggering the auxiliary lines AL1 and AL2.

[0172] Based on the above description, the dual-port SRAM according to Embodiment 4 can suppress the decrease in operational reliability caused by crosstalk, and can achieve high-speed operation by reducing the resistance of the two word lines (AWL, BWL).

[0173] The invention described above is based on the embodiments of the present invention and is specifically explained by the inventor of the present invention. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit.

[0174] Explanation of reference numerals in the attached figures

[0175] 1S Semiconductor Substrate

[0176] AL auxiliary lines

[0177] CIL Interlayer Insulation Film

[0178] DL diffusion layer

[0179] GE2 gate electrode

[0180] GE4 gate electrode

[0181] IL1 interlayer insulating film

[0182] IL2 interlayer insulating film

[0183] Wiring above OD substrate

[0184] PLG1 Plug

[0185] PLG2 plug

[0186] PLG3A plug

[0187] PLG3B plug

[0188] Wiring directly above PO

[0189] VL2 power cord

[0190] VL3 power cord

[0191] VSS cabling

[0192] WL lettering.

Claims

1. A semiconductor device comprising: Semiconductor substrate (1S); A first fin (FIN) and a second fin (FIN) are formed on the semiconductor substrate (1S). The first gate electrode (GE) is bridged on the first fin (FIN) and extends along the first direction; The second gate electrode (GE) is bridged on the second fin (FIN) and extends along the first direction; The first FINFET includes the first fin (FIN) and the first gate electrode (GE). The second FINFET includes a second fin (FIN) and the second gate electrode (GE). SRAM memory cell (MC) including the first FINFET; A memory array (MCA) includes the SRAM memory cell (MC), bit line pairs (BL, / BL) connected to the SRAM memory cell (MC), word lines (WL) connected to the SRAM memory cell (MC) and including a sixth wiring and a seventh wiring (AL), and a first wiring (PO) connected to the first gate electrode (GE). I / O circuit (100) configured to perform read and write operations on the SRAM memory cell (MC), the I / O circuit (100) includes the second FINFET, a second wiring (PO) connected to the second gate electrode (GE), a third wiring (L1) connected to the second wiring (PO), a fourth wiring (L2) connected to the third wiring (L1), and a fifth wiring (L3) connected to the fourth wiring (L2); A contact interlayer insulating film (CIL) is formed on the semiconductor substrate (1S) and covers the first gate electrode (GE) and the second gate electrode (GE). The bottommost wiring layer (M0) is formed within the contact interlayer insulating film (CIL) and includes the first wiring (PO), the second wiring (PO), and the over-substrate wiring (OD) formed on the semiconductor substrate (1S), wherein the first wiring (PO) and the over-substrate wiring (OD) are electrically connected to each other inside the bottommost wiring layer (M0); The first wiring layer (M1) is formed within the contact interlayer insulating film (CIL) and on the bottommost wiring layer (M0); A first insulating film (IL1) is formed on the contact interlayer insulating film (CIL). A second wiring layer (M2) is formed within the first insulating film (IL1); A second insulating film (IL2) formed on the first insulating film (IL1); and The second insulating film (IL2) formed within the third wiring layer (M3). The bit line pairs (BL, / BL) are formed within the first wiring layer (M1) and extend along a second direction intersecting the first direction. The third wiring (L1) is formed within the first wiring layer (M1) and extends along the second direction. The semiconductor device further includes a first power line (VSS) and a second power line (VDD) formed within the first wiring layer (M1) and extending along the second direction. The fourth wiring (L2) is formed within the second wiring layer (M2) and extends along the first direction. The fifth wiring (L3) is formed within the third wiring layer (M3) and extends along the second direction. The sixth wiring is formed within the second wiring layer (M2) and extends along the first direction. The seventh wiring (AL) is formed within the third wiring layer (M3) and extends along the first direction. The sixth wiring and the seventh wiring (AL) are electrically connected to each other via a first plug (PLG3B) formed within the second insulating film (IL2).

2. The semiconductor device according to claim 1, wherein, Above the storage array (MCA), the seventh wiring (AL) includes a first local wiring (HL1) and a second local wiring (HL2), which are arranged in a straight line in the first direction and are separated from each other in the first direction when viewed from above. The semiconductor device also includes cross wiring (HL3) disposed within the third wiring layer (M3). The crossover cabling (HL3) extends along the second direction and passes between the first local cabling (HL1) and the second local cabling (HL2) in the first direction.

3. The semiconductor device according to claim 1, wherein, The I / O circuit (100) includes a word driver connected to the SRAM memory cell (MC) via the sixth wiring and the seventh wiring (AL). The sixth wiring and the seventh wiring (AL) are electrically connected to each other via a plurality of second plugs (PLG3) formed within the second insulating film (IL2).

4. The semiconductor device according to claim 1, wherein, It also includes a first power line connected to the SRAM memory cell (MC) and supplying a first voltage to the SRAM memory cell (MC). The first power line includes an eighth wiring (VL2) that extends along the first direction and is disposed within the second wiring layer (M2).

5. The semiconductor device according to claim 4, wherein, The first power line also includes a ninth wiring (VL3), which extends along the first direction and is disposed within the third wiring layer (M3). The 8th wiring and the 9th wiring are electrically connected to each other via a 3rd plug formed within the 2nd insulating film (IL2).

6. The semiconductor device according to claim 5, wherein, The 8th wiring and the 9th wiring are electrically connected to each other via a plurality of 3rd plugs formed within the 2nd insulating film (IL2).

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