Display panel and display device

Abstract

The present application discloses a display panel and a display device, belonging to the field of display technology. The display panel includes: a substrate, a plurality of sub-pixels arranged in an array in the display area, and a plurality of data signal lines, one data signal line is electrically connected to a column of sub-pixels; and, a plurality of fan-out leads electrically connected to the plurality of data signal lines one by one, the plurality of fan-out leads include: a plurality of first fan-out leads and a plurality of second fan-out leads, a part of the first fan-out leads is located in the display area and a part is located in the non-display area, and all of the second fan-out leads are located in the non-display area; wherein, the first fan-out leads and the second fan-out leads are arranged in different layers, and the orthographic projection of the part of the first fan-out leads located in the non-display area on the substrate intersects with the orthographic projection of the second fan-out leads on the substrate. By adjusting the arrangement order of the plurality of fan-out leads, the order of the driving signals does not need to be adjusted, thereby effectively simplifying the driving mode of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly relates to a display panel and a display device. Background Art

[0002] Currently, in order to provide users with a better visual experience, the display screen (also known as the display panel) in a display device is developing towards a larger screen size and a full-screen design.

[0003] A display device generally includes a display panel and a driving chip. The display panel has a display area and a non-display area, and the display panel may include: a plurality of sub-pixels arranged in an array and a plurality of data signal lines located in the display area, and a plurality of fan-out leads located in the non-display area; each data signal line can be electrically connected to a column of sub-pixels, and each data signal line can be electrically connected to the driving chip through a fan-out lead. In this way, the driving chip can send a driving signal to the data signal line through the fan-out lead so that the display panel can display an image.

[0004] However, in the above display panel, the space occupied by the fan-out leads is relatively large, resulting in a relatively large width of the non-display area in the display panel, and further resulting in a relatively low screen-to-body ratio of the display device, which affects the display effect of the display device. Summary of the Invention

[0005] Embodiments of the present application provide a display panel and a display device, which can improve the screen-to-body ratio of the display panel. The technical solutions are as follows:

[0006] On the one hand, a display panel is provided. The display panel has a display area and a non-display area located outside the display area. The display panel includes:

[0007] a substrate;

[0008] a plurality of sub-pixels arranged in an array and a plurality of data signal lines located in the display area, and one data signal line is electrically connected to a column of the sub-pixels;

[0009] and a plurality of fan-out leads electrically connected to the plurality of data signal lines one by one. The plurality of fan-out leads include: a plurality of first fan-out leads and a plurality of second fan-out leads. Part of the first fan-out leads is located in the display area and part is located in the non-display area, and all of the second fan-out leads are located in the non-display area;

[0010] wherein, the first fan-out leads and the second fan-out leads are arranged in different layers, and a projection of a part of the first fan-out leads located in the non-display area on the substrate intersects with a projection of the second fan-out leads on the substrate.

[0011] Optionally, the non-display area has a first fan-out area and a second fan-out area, and the first fan-out area is closer to the display area than the second fan-out area;

[0012] The first fan-out lead includes: a first sub-lead located in the first fan-out area and a second sub-lead located in the second fan-out area;

[0013] Wherein, in the first fan-out area, at least one of the first sub-leads is distributed between two adjacent second fan-out leads; in the second fan-out area, multiple second sub-leads are divided into two groups, and the multiple second fan-out leads are all located between the two groups of second sub-leads.

[0014] Optionally, the first fan-out lead further includes: a third sub-lead for connecting the first sub-lead and the second sub-lead, and a cross region exists between the orthographic projection of the third sub-lead on the substrate and the orthographic projection of the second fan-out lead on the substrate.

[0015] Optionally, the first fan-out lead further includes: a fourth sub-lead located in the display area, and the fourth sub-lead is electrically connected to the data signal line and the first sub-lead respectively;

[0016] Wherein, the fourth sub-lead and the data signal line are arranged in different layers, and the data signal line is closer to the substrate than the fourth sub-lead.

[0017] Optionally, each sub-lead in the first fan-out lead is arranged in the same layer and has the same material; or, the part of the first fan-out lead located in the non-display area is arranged in the same layer and has the same material as the data signal line.

[0018] Optionally, the display panel further includes: a first power signal line located in the non-display area and electrically connected to the sub-pixel, and an overlapping region exists between the orthographic projection of the first power signal line on the substrate and the orthographic projection of the multiple fan-out leads on the substrate;

[0019] Wherein, the first power signal line has: a first sub-signal line and a second sub-signal line which are arranged in different layers and overlap with each other, the first sub-signal line is located on the side of the first fan-out lead away from the substrate, and the second sub-signal line is located on the side of the second fan-out lead away from the substrate.

[0020] Optionally, the display panel further includes: a touch layer located in the display area, and the multiple sub-pixels are closer to the substrate than the touch layer;

[0021] When each sub-lead in the first fan-out lead is arranged in the same layer and has the same material, the first sub-signal line is arranged in the same layer and has the same material as the touch electrode in the touch layer;

[0022] Alternatively, when the part of the first fan-out lead located in the non-display area is arranged in the same layer and has the same material as the data signal line, the first sub-signal line is arranged in the same layer and has the same material as at least one of the touch electrode and the fourth sub-lead.

[0023] Optionally, the display panel further includes: a second power signal line located in the non-display area and electrically connected to the sub-pixel, and a positive projection of the second power signal line on the substrate does not coincide with a positive projection of the plurality of fan-out leads on the substrate;

[0024] Wherein, the second power signal line has: a third sub-signal line and a fourth sub-signal line that are arranged in different layers and overlap each other, the third sub-signal line is arranged in the same layer and has the same material as the second sub-signal line, and the fourth sub-signal line is arranged in the same layer and has the same material as the data signal line.

[0025] Optionally, the sub-pixel includes: a pixel driving circuit, the third sub-signal line, the second sub-signal line are arranged in the same layer and have the same material as the source and drain electrodes of the thin film transistor in the pixel driving circuit, and the data signal line is arranged in the same layer and has the same material as the transfer electrode electrically connected to the source and drain electrodes in the pixel driving circuit.

[0026] Optionally, the plurality of second fan-out leads are divided into two groups, each fan-out lead in one group of second fan-out leads is arranged in the same layer and has the same material as one electrode of the storage capacitor of the pixel driving circuit, and each fan-out lead in the other group of second fan-out leads is arranged in the same layer and has the same material as the other electrode of the storage capacitor;

[0027] Wherein, the plurality of second fan-out leads in one group of second fan-out leads and the plurality of second fan-out leads in the other group of second fan-out leads are arranged in a staggered manner.

[0028] Optionally, the display panel further includes: a plurality of pads located in the non-display area and electrically connected to the plurality of fan-out leads one by one, and an arrangement order of the plurality of pads is the same as an arrangement order of the corresponding plurality of data signal lines.

[0029] Optionally, the plurality of data signal lines include: a plurality of first data signal lines electrically connected to the plurality of first fan-out leads one by one, and a plurality of second data signal lines electrically connected to the plurality of second fan-out leads one by one;

[0030] Among them, the multiple first data signal lines are divided into two groups of first data signal lines, and the multiple second data signal lines are all arranged between the two groups of first data signal lines.

[0031] On the other hand, a display device is provided, and the device includes: a power supply component and the above-mentioned display panel, and the display panel is electrically connected to the power supply component.

[0032] The beneficial effects brought by the technical solution provided by the embodiment of the present application at least include:

[0033] The embodiment of the present application provides a display panel, including: a substrate, multiple sub-pixels, multiple data signal lines, and multiple fan-out leads. Since a part of the first fan-out leads among the multiple fan-out leads in the display area first leads from both sides of the display area to the middle of the display area, and then leads out from the middle of the display area to the non-display area, a part of the first fan-out leads in the non-display area does not need to converge from both sides to the middle, thereby reducing the space occupied by the first fan-out leads in the non-display area, and further improving the screen-to-body ratio of the display device. Also, since the first fan-out leads and the second fan-out leads in the display panel are arranged in different layers, and the orthographic projection of the part of the first fan-out leads in the non-display area on the substrate intersects with the orthographic projection of the second fan-out leads on the substrate. In this way, not only can the short circuit between the first fan-out leads and the second fan-out leads in the intersection area be avoided, but also in the non-display area, the first fan-out leads can be moved from the middle of the non-display area to both sides to adjust the arrangement order of the multiple fan-out leads in the non-display area, so that the arrangement order of the multiple pads electrically connected to the multiple fan-out leads one by one is the same as the arrangement order of the corresponding multiple data signal lines. When the driving chip in the display device sends driving signals to the corresponding multiple data signal lines through the multiple fan-out leads corresponding to the multiple pads, the order of the driving signals does not need to be adjusted, thereby effectively simplifying the driving method of the display panel. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1 is a schematic structural diagram of a common display device at present;

[0036] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0037] Figure 3Yes Figure 2 A cross-sectional view of the shown display panel at B - B'.

[0038] Figure 4 A schematic structural diagram of a first fan - out lead provided by an embodiment of the present application.

[0039] Figure 5 Yes Figure 4 A schematic diagram of the film layer structure of the shown display panel at C - C'.

[0040] Figure 6 A partial structural schematic diagram of a part of the display panel located in the non - display area provided by an embodiment of the present application.

[0041] Figure 7 Yes Figure 6 A cross - sectional view of the first power supply signal line at D - D'.

[0042] Figure 8 Yes Figure 2 Another cross - sectional view of the shown display panel at B - B'. Detailed implementation manners

[0043] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0044] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0045] Please refer to Figure 1 , Figure 1 A schematic structural diagram of a common display device at present. The display device may include a display panel 00 and a driving chip 01; the display panel 00 has a display area 0a and a non - display area 0b, and the display panel 00 may include: a plurality of sub - pixels 10 and a plurality of data signal lines 20 located in the display area 0a, and a plurality of fan - out leads 30 located in the non - display area 0b; each data signal line 20 may be electrically connected to a column of sub - pixels 10, and each data signal line 20 may be electrically connected to the driving chip 01 through a fan - out lead 30. In this way, the driving chip 01 may send a driving signal to the data signal line 20 through the fan - out lead 30, so that the display panel 00 can display a picture.

[0046] However, since the length of the driving chip 01 is usually smaller than the width of the display panel 00, multiple fan-out leads 30 need to be arranged in a wiring manner that converges from both sides to the middle in the non-display area 0b. In this way, the space occupied by the fan-out leads 30 in the non-display area 0b is relatively large, resulting in a relatively large width of the non-display area 0b in the display panel 00, and further resulting in a relatively low screen-to-body ratio of the display device, which affects the display effect of the display device.

[0047] Please refer to Figure 2 , Figure 2 FIG. is a schematic structural diagram of a display panel provided by an embodiment of the present application. The display panel 000 has a display area 00a and a non-display area 00b located outside the display area 00a. Here, the display panel 000 may be an organic light emitting display (Organic Light Emitting Display; abbreviated as OLED) display panel or an active matrix organic light emitting diode (Active Matrix / Organic Light Emitting Diode; abbreviated as AM-OLED) display panel. When the display panel 000 is an OELD display panel or an AM-OLED display panel, the display panel 000 may be a top-emission display panel or a bottom-emission display panel.

[0048] For a clearer view of the structure of the display panel, please refer to Figure 3 , Figure 3 is Figure 2 a cross-sectional view of the display panel shown at B-B'. The display panel 000 may include: a substrate 100, multiple sub-pixels 200, multiple data signal lines 300, and multiple fan-out leads 400.

[0049] Multiple sub-pixels 200 in the display panel 000 are arranged in an array in the display area 00a. Exemplarily, the sub-pixel 200 may include a light emitting device 201 and a pixel driving circuit 202, and the light emitting device 201 is electrically connected to the pixel driving circuit 202. Through the pixel driving circuit 202, the light emitting device 201 can be driven to emit light.

[0050] Multiple data signal lines 300 in the display panel 000 are located in the display area 00a, and one data signal line 300 is electrically connected to one column of sub-pixels 200. Exemplarily, each data signal line 300 may be electrically connected to the pixel driving circuits 202 of the respective sub-pixels 200 in the same column of sub-pixels 200. In this way, when a driving signal is loaded on the data signal line, it can drive the light emitting devices 201 in the respective sub-pixels 200 electrically connected thereto to emit light.

[0051] A plurality of fan-out leads 400 in the display panel 000 are electrically connected to a plurality of data signal lines 300 in a one-to-one correspondence. Among them, the plurality of fan-out leads 400 include: a plurality of first fan-out leads 401 and a plurality of second fan-out leads 402. A part of the first fan-out leads 401 is located in the display area 00a, and a part is located in the non-display area 00b, while all of the second fan-out leads are located in the non-display area 00b. Exemplarily, the plurality of data signal lines 300 in the display panel 000 may include: a plurality of first data signal lines electrically connected to the plurality of first fan-out leads 401 in a one-to-one correspondence, and a plurality of second data signal lines electrically connected to the plurality of second fan-out leads 402 in a one-to-one correspondence; among them, the plurality of first data signal lines are divided into two groups of first data signal lines, and the plurality of second data signal lines are all arranged between the two groups of first data signal lines. That is to say, the plurality of second data signal lines are closer to the middle of the display area 00a relative to the plurality of first data signal lines. That is, the first data signal lines in the display panel 000 are the data signal lines located on both sides of the display area 00a, and the second data signal lines are the data signal lines located in the middle of the display area 00a.

[0052] In this case, the part of the first fan-out lead 401 located in the display area 00a can first be led from both sides of the display area 00a to the middle of the display area 00a, and then led out from the middle of the display area 00a to the non-display area 00b. In this way, the part of the first fan-out lead 401 located in the non-display area 00b does not need to converge from both sides to the middle in the non-display area 00b, thereby reducing the space occupied by the first fan-out lead 401 in the non-display area 0b, and further improving the screen-to-body ratio of the display device.

[0053] Among them, the part of the first fan-out lead 401 located in the display area 00a is arranged in a different layer from the plurality of data signal lines 300. It should be noted that the different-layer arrangement of any two conductive structures in the embodiments of the present application means that there is an insulating layer between the two conductive layers where the two conductive structures are located. Exemplarily, as Figure 3 shown, the conductive layer to which the plurality of data signal lines 300 belong is not the same conductive layer as the conductive layer to which the part of the first fan-out lead 401 located in the display area 00a belongs, and there is an insulating layer between the conductive layer to which the data signal lines 300 belong and the conductive layer to which the part of the first fan-out lead 401 located in the display area 00a belongs.

[0054] In this way, when the part of the first fan-out lead 401 located in the display area 00a is led from both sides of the display area 00a to the middle of the display area 00a, it is possible to avoid short circuits at the crossing positions between the part of the first fan-out lead 401 located in the display area 00a and the plurality of data signal lines 300.

[0055] In this case, the first fan-out lead 401 is led from both sides of the display area 00a to the middle of the display area 00a, so that the first fan-out lead 401 will cross part of the data signal lines 300, and then lead out from the middle of the display area 00a to the non-display area 00b. When the first fan-out lead 401 leads out from the middle of the display area 00a to the non-display area 00b, it is closer to the middle of the non-display area 00b than the second fan-out lead 402 connected to the data signal lines 300 crossed by this first fan-out lead 401; while within the display area 00a, the data signal lines 300 crossed by this first fan-out lead 401 are closer to the middle of the display area 00a than the data signal lines 300 connected to the first fan-out lead 401. It can be seen from this that when the first fan-out lead 401 leads out from the middle of the display area 00a to the non-display area 00b, the arrangement order of the multiple fan-out leads 400 (including the first fan-out lead 401 and the second fan-out lead 402) is different from the arrangement order of the corresponding multiple data signal lines 200.

[0056] Exemplarily, when the first fan-out lead 401 leads out from the middle of the display area 00a to the non-display area 00b, the arrangement order of the multiple fan-out leads 400 (including the first fan-out lead 401 and the second fan-out lead 402) is A2, A1, A3, A5, A4, while the arrangement order of the multiple data signal lines 200 corresponding to the multiple fan-out leads 400 is A1, A2, A3, A4, A5.

[0057] In the embodiment of the present application, the first fan-out lead 401 and the second fan-out lead 402 in the display panel 000 are arranged in different layers, and the orthographic projection of the part of the first fan-out lead 401 located in the non-display area 00b on the substrate 100 and the orthographic projection of the second fan-out lead 402 on the substrate 100 have an overlapping area. In this way, not only can the short circuit between the first fan-out lead 401 and the second fan-out lead 402 in the overlapping area be avoided, but also within the non-display area 00b, the first fan-out lead 401 can be moved from the middle of the non-display area 00b to both sides, so as to adjust the arrangement order of the multiple fan-out leads 400 within the non-display area 00b.

[0058] Exemplarily, the display panel 000 further includes: a plurality of pads 500. The plurality of pads 500 in the display panel 000 are electrically connected to the multiple fan-out leads 400 located in the non-display area 00b one by one. After adjusting the arrangement order of the multiple fan-out leads 400 within the non-display area 00b, it can be ensured that the arrangement order of the multiple pads 500 is the same as the arrangement order of the corresponding multiple data signal lines 200. For example, the arrangement order of the multiple pads 500 is: A1, A2, A3, A4, A5, and the arrangement order of the multiple data signal lines 200 is also: A1, A2, A3, A4, A5.

[0059] In this case, in the display panel 000, the arrangement order of the multiple pads 500 that are electrically connected to the multiple fan-out leads 400 one by one is the same as the arrangement order of the corresponding multiple data signal lines 200. When the driving chip in the display device sends a driving signal to the corresponding multiple data signal lines 200 through the multiple pads 500 and the multiple fan-out leads corresponding to the multiple pads 500, the order of the driving signals does not need to be adjusted, thereby effectively simplifying the driving method of the display panel.

[0060] In summary, the embodiment of the present application provides a display panel, including: a substrate, multiple sub-pixels, multiple data signal lines, and multiple fan-out leads. Since the partial fan-out leads of the first fan-out lead in the multiple fan-out leads located in the display area first lead from both sides of the display area to the middle of the display area, and then lead out from the middle of the display area to the non-display area, the partial fan-out leads of the first fan-out lead located in the non-display area do not need to converge from both sides to the middle, thereby reducing the space occupied by the first fan-out lead in the non-display area, and further increasing the screen-to-body ratio of the display device. Also, since the first fan-out lead and the second fan-out lead in the display panel are arranged in different layers, and the orthographic projection of the partial fan-out lead of the first fan-out lead located in the non-display area on the substrate intersects with the orthographic projection of the second fan-out lead on the substrate. In this way, not only can the short circuit between the first fan-out lead and the second fan-out lead in the intersection area be avoided, but also in the non-display area, the first fan-out lead can be moved from the middle of the non-display area to both sides to adjust the arrangement order of the multiple fan-out leads in the non-display area, so that the arrangement order of the multiple pads that are electrically connected to the multiple fan-out leads one by one is the same as the arrangement order of the corresponding multiple data signal lines. When the driving chip in the display device sends a driving signal to the corresponding multiple data signal lines through the multiple fan-out leads corresponding to the multiple pads, the order of the driving signals does not need to be adjusted, thereby effectively simplifying the driving method of the display panel.

[0061] Please refer to Figure 4 , Figure 4 is a schematic structural diagram of a first fan-out lead provided by an embodiment of the present application. The non-display area 00b has a first fan-out area 00b1 and a second fan-out area 00b2, and the first fan-out area 00b1 is closer to the display area 00a than the second fan-out area 00b2. The first fan-out lead 401 includes: a first sub-lead 4011 located in the first fan-out area 00b1, and a second sub-lead 4012 located in the second fan-out area 00b2.

[0062] In the first fan-out area 00b1, at least one first sub-lead 4011 is distributed between two adjacent second fan-out leads 402. That is, the arrangement order of the multiple first sub-leads 4011 in the non-display area 00b is different from the arrangement order of the multiple data signal lines 300.

[0063] In the second fan-out region 00b2, multiple second sub-leads 4012 are divided into two groups, and multiple second fan-out leads 402 are all located between the two groups of second sub-leads 4012. That is to say, the arrangement order of the multiple second sub-leads 4012 in the non-display region 00b can be the same as the arrangement order of the multiple data signal lines 300.

[0064] In this application, the non-display region 00b further has a bending region 00b3 located between the first fan-out region 00b1 and the second fan-out region 00b2. The first fan-out lead 401 may further include: a fifth sub-signal line 4015 located in the bending region 00b3. Within the same first fan-out lead 401, the first fan-out lead 401 and the second sub-lead 4012 can be electrically connected through the fifth sub-signal line 4015.

[0065] Among them, the part of the display panel 000 located in the bending region 00b3 needs to be bent later. Since in the non-display region 00b, the first fan-out region 00b1 is closer to the display region 00a than the second fan-out region 00b2. Therefore, after bending the part of the display panel 000 located in the bending region 00b3, the part of the display panel 000 located in the second fan-out region 00b2 can be bent to the back of the display panel 000, thereby improving the screen-to-body ratio of the display device integrated with this display panel 000.

[0066] In order to further improve the screen-to-body ratio of the display device integrated with this display panel 000, it is necessary to ensure that the structure integrated in the part of the display panel 000 located in the first fan-out region 00b1 is not excessive. For this reason, in the embodiment of this application, the arrangement order of the multiple fan-out leads 400 is not adjusted within the first fan-out lead 401, but the order of the multiple fan-out leads 400 is adjusted within the second fan-out lead 402.

[0067] Optionally, as Figure 4As shown, the first fan-out lead 401 further includes: a third sub-lead 4013 for connecting the first sub-lead 4011 and the second sub-lead 4012. The orthographic projection of the third sub-lead 4013 on the substrate 100 and the orthographic projection of the second fan-out lead 402 on the substrate have an overlapping area. Exemplarily, the third sub-lead 4013 can be distributed within the second fan-out region 00b2, and both ends of the third sub-lead 4031 can be electrically connected to the fifth sub-lead 4015 and the second sub-lead 4012 respectively. In the present application, by arranging the third sub-lead 4013 that intersects with the second fan-out lead 402 within the second fan-out region 00b2, the order of multiple fan-out leads 400 can be adjusted within the second fan-out lead 402, such that the arrangement order of multiple fan-out leads 400 within the second fan-out lead 402 is the same as the arrangement order of the corresponding multiple data signal lines 200. Furthermore, the arrangement order of multiple pads 500 that are electrically connected to the multiple fan-out leads 400 one by one is also the same as the arrangement order of the corresponding multiple data signal lines 200.

[0068] Optionally, please continue to refer to Figure 4 , the first fan-out lead 401 further includes: a fourth sub-lead 4014 located within the display region 00a. The fourth sub-lead 4014 is electrically connected to the data signal line 300 and the first sub-lead 4011 respectively. Among them, the fourth sub-lead 4014 and the data signal line 300 are arranged on different layers, and the data signal line 300 is closer to the substrate 100 than the fourth sub-lead 4014. In this case, the fourth sub-lead 4014 in the first fan-out lead 401 leads from both sides of the display region 00a to the middle of the display region 00a, and then leads out from the middle of the display region 00a to the non-display region 00b and is electrically connected to the first sub-lead 4011 within the non-display region 00b. In this way, the fourth sub-lead 4014 will cross the data signal line 300 that is electrically connected to the second fan-out lead 402. Since the fourth sub-lead 4014 and the data signal line 300 are arranged on different layers, it is possible to avoid a short circuit between the fourth sub-lead 4014 and the data signal line 300 in the overlapping area.

[0069] In the embodiment of the present application, as Figure 5 shown, Figure 5 is Figure 4Schematic diagram of the film structure of the display panel at CC' is shown. The pixel driving circuit 202 in each sub-pixel 200 in the display panel 000 may include: at least one thin film transistor (TFT) 2021, a storage capacitor 2022 and a switching electrode 2023. Among them, in each sub-pixel 200, the switching electrode 2023 can be electrically connected to the source and drain of the TFT 2021. And the switching electrode 2023 in each sub-pixel 200 can also be electrically connected to the light-emitting device 201 in this sub-pixel 200. For example, one of the source and drain of the TFT 2021 can be electrically connected to the light-emitting device through the switching electrode 2023, and the other of the source and drain of the TFT 2021 can be electrically connected to the data signal line 300.

[0070] In the present application, the data signal line 300 can be arranged in the same layer and made of the same material as the switching electrode 2023 in the pixel driving circuit 202. It should be noted that in the embodiments of the present application, two conductive structures are arranged in the same layer and made of the same material, which means that the two conductive structures are in the same conductive layer, and the conductive layer is formed by the same patterning process. Here, a patterning process refers to: photoresist coating, exposure, development, etching and photoresist stripping. For example, Figure 5 As shown, the conductive layer to which the data signal line 300 belongs and the conductive layer to which the switching electrode 2023 belongs are the same conductive layer.

[0071] It should also be noted that, since the fourth sub-lead 4014 in the first fan-out lead 401 in the above embodiment is arranged at a different layer from the data signal line 300, and the data signal line 300 is closer to the substrate 100 than the fourth sub-lead 4014. Therefore, the pixel driving circuit 202 also needs to include: an auxiliary transfer electrode 2024 electrically connected to the transfer electrode 2023. The auxiliary transfer electrode 2024 can be arranged at the same layer as the fourth sub-lead 4014 and made of the same material, so that the electrical connection between the transfer electrode 2023 and the light-emitting device 201 can be achieved through the auxiliary transfer electrode 2024.

[0072] In the embodiment of the present application, the plurality of second fan-out leads 402 in the display panel 000 can generally be arranged in the same layer and with the same material as two electrodes of the storage capacitor 2022. Exemplarily, the plurality of second fan-out leads 402 are divided into two groups, wherein each fan-out lead in one group of second fan-out leads 402 is arranged in the same layer and with the same material as one electrode of the storage capacitor 2022 of the pixel driving circuit 201, and each fan-out lead in the other group of second fan-out leads 402 is arranged in the same layer and with the same material as another electrode of the storage capacitor 2022; wherein, the plurality of second fan-out leads 402 in one group of second fan-out leads 402 are staggered with the plurality of second fan-out leads 402 in the other group of second fan-out leads 402.

[0073] In the present application, the portion of the first fan-out lead 401 within the display area 00a and the portion of the first fan-out lead 401 within the non-display area 00b may be provided on the same layer or on different layers.

[0074] In a possible implementation, when the portion of the first fan-out lead 401 within the display area 00a and the portion of the first fan-out lead 401 within the non-display area 00b are provided on the same layer, each sub-lead in the first fan-out lead 401 is provided on the same layer and has the same material. That is, the fourth sub-lead 4014 of the first fan-out lead 401 within the display area 00a and the first sub-lead 4011, the second sub-lead 4012, the third sub-lead 4013, and the fifth sub-lead 4015 of the first fan-out lead 401 within the non-display area 00b are provided on the same layer and have the same material.

[0075] In another possible implementation, when the portion of the first fan-out lead 401 within the display area 00a and the portion of the first fan-out lead 401 within the non-display area 00b are provided on different layers, the portion of the first fan-out lead 401 within the display area 00a and the portion of the first fan-out lead 401 within the non-display area 00b are provided on different layers, and the portion of the first fan-out lead 401 within the non-display area 00b is provided on the same layer and has the same material as the data signal line 300. That is, the data signal line 300 and the first sub-lead 4011, the second sub-lead 4012, the third sub-lead 4013, and the fifth sub-lead 4015 of the first fan-out lead 401 within the non-display area 00b are provided on the same layer and have the same material.

[0076] It should be noted that since multiple second fan-out leads 300 within the display panel 000 are usually provided on the same layer and have the same material as the two electrodes of the storage capacitor 2022, and there are insulating layers between the two conductive layers where the two electrodes of the storage capacitor 2022 are located and the conductive layer where the data signal line 300 is located, and there are insulating layers between the two electrodes of the storage capacitor 2022 and the conductive layer where the fourth sub-signal line 4014 is located. Therefore, in the above two alternative implementations, it can be ensured that there is no short-circuit problem even when the first fan-out lead 401 and the second fan-out lead 402 cross within the non-display area 00b.

[0077] In the embodiments of the present application, please refer to Figure 6 , Figure 6It is a schematic diagram of a partial structure of a part located in the non-display area of a display panel provided by an embodiment of the present application. The display panel 000 further includes: a first power signal line 600 located in the non-display area 00b and electrically connected to the sub-pixels 200. The orthographic projection of the first power signal line 600 on the substrate 100 overlaps with the orthographic projection of a plurality of fan-out leads 400 on the substrate. Optionally, the first power signal line 600 is a VDD power signal line, and a power signal can be transmitted to a plurality of sub-pixels 200 through the first power signal line 600.

[0078] To more clearly see the structure of the first power signal line, please refer to Figure 7 , Figure 7 is Figure 6 a cross-sectional view of the first power signal line shown at D-D'. Among them, the first power signal line 600 has: a first sub-signal line 601 and a second sub-signal line 602 that are arranged in different layers and overlap with each other. The first sub-signal line 601 is located on the side of the first fan-out lead 401 away from the substrate 100, and the second sub-signal line 602 is located on the side of the second fan-out lead 402 away from the substrate 100. As Figure 6 shown, the first power signal line 600 may include: a substrate 100, and a first inorganic layer 603, a first sub-signal line 601, a second inorganic layer 604, and a second sub-signal line 602 that are stacked in a direction perpendicular to and away from the substrate 100.

[0079] In the embodiment of the present application, the first sub-signal line 601 and the second sub-signal line 602 in the first power signal line 600 are arranged in different layers and overlap with each other, thereby reducing the resistance of the first power signal line 600, and further reducing the load of the first power signal line 600. It should be noted that there are a plurality of vias at other positions of the first sub-signal line 601 except at D-D'. In this way, the first sub-signal line 601 can overlap with the second sub-signal line 602 through these vias.

[0080] In the present application, the first sub-signal line 601 is located on the side of the first fan-out lead 401 away from the substrate 100. In this way, the first fan-out lead 401 can be shielded by the first sub-signal line 601, and further interference from external signals to the first fan-out lead 401 can be avoided; similarly, the second sub-signal line 602 is located on the side of the second fan-out lead 402 away from the substrate 100. In this way, the second fan-out lead 402 can be shielded by the second sub-signal line 602, and further interference from the signal in the first fan-out lead 401 and external signals to the second fan-out lead 402 can be avoided.

[0081] Optionally, as Figure 8As shown, the display panel 000 further includes: a touch layer 800 located within the display area 00a, and the plurality of sub-pixels 200 are closer to the substrate 100 than the touch layer 800. Exemplarily, the display panel 000 may further include: a packaging layer 900 for packaging the light-emitting devices 201 within the sub-pixels 200, and the touch layer 800 is located on a side of the packaging layer 900 facing away from the substrate 100.

[0082] In the embodiments of the present application, there are the following two cases for the setting position of the first sub-signal line 601 in the first voltage signal line 600:

[0083] In the first case, when each sub-lead in the first fan-out lead 401 is arranged in the same layer and has the same material, the first sub-signal line 601 is arranged in the same layer and has the same material as the touch electrode in the touch layer 800.

[0084] In the second case, when the portion of the first fan-out lead 401 located within the non-display area 00b is arranged in the same layer and has the same material as the data signal line 300, the first sub-signal line 601 is arranged in the same layer and has the same material as at least one of the touch electrode and the fourth sub-lead 4014.

[0085] For the setting position of the second sub-signal line 602 in the first voltage signal line 600, the second sub-signal line 602 may be arranged in the same layer and have the same material as the source and drain electrodes of the TFT 2023.

[0086] Please continue to refer to Figure 5 , the display panel 000 further includes: a second power supply signal line 700 located within the non-display area 00b and electrically connected to the sub-pixels 200, and the orthographic projection of the second power supply signal line 700 on the substrate 100 does not coincide with the orthographic projections of the plurality of fan-out leads 400 on the substrate 100. Optionally, the second power supply signal line 700 is a VSS power supply signal line.

[0087] Wherein, the second power supply signal line 700 has: a third sub-signal line and a fourth sub-signal line that are arranged in different layers and overlap with each other, the third sub-signal line is arranged in the same layer and has the same material as the second sub-signal line 602, and the fourth sub-signal line is arranged in the same layer and has the same material as the data signal line 300.

[0088] In the embodiments of the present application, the third sub-signal line and the fourth sub-signal line in the second power supply signal line 700 are arranged in different layers and overlap with each other, thereby reducing the resistance of the second power supply signal line 700, and further reducing the load of the second power supply signal line 700.

[0089] In summary, the embodiment of the present application provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data signal lines, and a plurality of fan-out leads. Since some of the fan-out leads in the first fan-out lead among the plurality of fan-out leads first lead from both sides of the display area to the middle of the display area, and then lead out from the middle of the display area to the non-display area, the fan-out leads in the non-display area of the first fan-out lead do not need to converge from both sides to the middle, thereby reducing the space occupied by the first fan-out lead in the non-display area, and further improving the screen-to-body ratio of the display device. Also, since the first fan-out lead and the second fan-out lead in the display panel are arranged in different layers, and the orthographic projection of the part of the first fan-out lead in the non-display area on the substrate intersects with the orthographic projection of the second fan-out lead on the substrate. In this way, not only can the short circuit between the first fan-out lead and the second fan-out lead in the intersection area be avoided, but also in the non-display area, the first fan-out lead can be moved from the middle of the non-display area to both sides to adjust the arrangement order of the plurality of fan-out leads in the non-display area, so that the arrangement order of the plurality of pads electrically connected to the plurality of fan-out leads one by one is the same as the arrangement order of the corresponding plurality of data signal lines. When the driving chip in the display device sends a driving signal to the corresponding plurality of data signal lines through the plurality of fan-out leads corresponding to the plurality of pads, the order of the driving signals does not need to be adjusted, thereby effectively simplifying the driving method of the display panel.

[0090] The embodiment of the present application also provides a display device, which can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0091] The display device may include: a power supply component and the display panel 000 in the above embodiment; the power supply component is electrically connected to the display panel 000 for supplying power to the display panel 000.

[0092] It should be noted that in the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. And it can be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be an intermediate layer. Additionally, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there may be more than one intermediate layer or element. Further, it can be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Like reference numerals throughout indicate like elements.

[0093] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "plural" refers to two or more, unless otherwise clearly defined.

[0094] The above are only optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel has a display area and a non-display area located around the display area. The non-display area has a first fan-out area and a second fan-out area, and the first fan-out area is closer to the display area than the second fan-out area. The display panel includes: a substrate; a plurality of sub-pixels arranged in an array in the display area and a plurality of data signal lines, and one of the data signal lines is electrically connected to a column of the sub-pixels; a plurality of fan-out leads electrically connected to the plurality of data signal lines one by one. The plurality of fan-out leads include: a plurality of first fan-out leads and a plurality of second fan-out leads. Part of the first fan-out leads is located in the display area and part is located in the non-display area, and all of the second fan-out leads are located in the non-display area. The first fan-out leads include: a first sub-lead located in the first fan-out area and a second sub-lead located in the second fan-out area. In the first fan-out area, at least one of the first sub-leads is distributed between two adjacent second fan-out leads. In the second fan-out area, the plurality of second sub-leads are divided into two groups, and all of the second fan-out leads are located between the two groups of second sub-leads. In the first fan-out area, the arrangement order of the plurality of fan-out leads is different from the arrangement order of the plurality of data signal lines. In the second fan-out area, the arrangement order of the plurality of fan-out leads is the same as the arrangement order of the plurality of data signal lines. And a plurality of pads located in the non-display area and electrically connected to the plurality of fan-out leads one by one. The arrangement order of the plurality of pads is the same as the arrangement order of the corresponding plurality of data signal lines. Wherein, the plurality of data signal lines include: a plurality of first data signal lines electrically connected to the plurality of first fan-out leads one by one, and a plurality of second data signal lines electrically connected to the plurality of second fan-out leads one by one. The plurality of second data signal lines are closer to the middle of the display area than the plurality of first data signal lines. The first fan-out leads and the second fan-out leads are arranged in different layers, and the orthographic projection of the part of the first fan-out leads located in the non-display area on the substrate intersects with the orthographic projection of the second fan-out leads on the substrate.

2. The display panel according to claim 1, wherein The first fan-out lead further includes: a third sub-lead for connecting the first sub-lead and the second sub-lead, and the orthographic projection of the third sub-lead on the substrate intersects with the orthographic projection of the second fan-out lead on the substrate.

3. The display panel according to claim 1, wherein The first fan-out lead further includes: a fourth sub-lead located in the display area, and the fourth sub-lead is electrically connected to the data signal line and the first sub-lead respectively. Wherein, the fourth sub-lead and the data signal line are arranged in different layers, and the data signal line is closer to the substrate than the fourth sub-lead.

4. The display panel according to claim 3, wherein Each of the sub-leads in the first fan-out lead is arranged in the same layer and has the same material; or, the part of the first fan-out lead located in the non-display area is arranged in the same layer and has the same material as the data signal line.

5. The display panel according to claim 4, characterized in that The display panel further includes: a first power signal line located in the non-display area and electrically connected to the sub-pixels, and an overlapping area exists between the orthographic projection of the first power signal line on the substrate and the orthographic projection of the plurality of fan-out leads on the substrate; Wherein, the first power signal line has: a first sub-signal line and a second sub-signal line that are arranged in different layers and overlap with each other, the first sub-signal line is located on a side of the first fan-out lead away from the substrate, and the second sub-signal line is located on a side of the second fan-out lead away from the substrate.

6. The display panel according to claim 5, wherein The display panel further includes: a touch layer located in the display area, and the plurality of sub-pixels are closer to the substrate than the touch layer; When each sub-lead in the first fan-out lead is arranged in the same layer and has the same material, the first sub-signal line is arranged in the same layer and has the same material as the touch electrode in the touch layer; Alternatively, when a part of the first fan-out lead located in the non-display area is arranged in the same layer and has the same material as the data signal line, the first sub-signal line is arranged in the same layer and has the same material as at least one of the touch electrode and the fourth sub-lead.

7. The display panel according to claim 5, wherein, The display panel further includes: a second power signal line located in the non-display area and electrically connected to the sub-pixels, and the orthographic projection of the second power signal line on the substrate does not coincide with the orthographic projection of the plurality of fan-out leads on the substrate; Wherein, the second power signal line has: a third sub-signal line and a fourth sub-signal line that are arranged in different layers and overlap with each other, the third sub-signal line is arranged in the same layer and has the same material as the second sub-signal line, and the fourth sub-signal line is arranged in the same layer and has the same material as the data signal line.

8. The display panel according to claim 7, wherein The sub-pixel includes: a pixel driving circuit, the third sub-signal line, the second sub-signal line are arranged in the same layer and have the same material as the source and drain electrodes of the thin film transistor in the pixel driving circuit, and the data signal line is arranged in the same layer and has the same material as the transfer electrode electrically connected to the source and drain electrodes in the pixel driving circuit.

9. The display panel according to claim 8, wherein, The plurality of second fan-out leads are divided into two groups, and each fan-out lead in one group of second fan-out leads is arranged in the same layer and has the same material as one electrode of the storage capacitor of the pixel driving circuit, and each fan-out lead in the other group of second fan-out leads is arranged in the same layer and has the same material as the other electrode of the storage capacitor; Wherein, the plurality of second fan-out leads in one group of second fan-out leads and the plurality of second fan-out leads in the other group of second fan-out leads are alternately distributed.

10. The display panel according to any one of claims 1 to 9, characterized in that, The plurality of first data signal lines are divided into two groups of first data signal lines, and the plurality of second data signal lines are all arranged between the two groups of first data signal lines.

11. A display device, characterized in that, Including: A power supply component and the display panel according to any one of claims 1 to 10, and the display panel is electrically connected to the power supply component.

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