Thin film transistor and manufacturing method thereof, array substrate and display device

Abstract

The present disclosure provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor includes: an active layer located on one side of a substrate; a first interlayer dielectric layer located on a side of the active layer away from the substrate; a source electrode penetrating the first interlayer dielectric layer and connected to the active layer; a second interlayer dielectric layer located on a side of the first interlayer dielectric layer away from the active layer and covering the source electrode; and a drain electrode including a first portion, the first portion penetrating the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.

Description

[0001] This application is a divisional application of the original application with application number 201980000094.3 (filing date is January 29, 2019, invention name: thin film transistor and manufacturing method thereof, array substrate and display device). Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. Background Art

[0003] In order to meet the demand for high-resolution display, the PPI (Pixels Per Inch) of display panels needs to be higher and higher. In particular, display products based on VR (Virtual Reality) technology have more stringent requirements on resolution. Summary of the invention

[0004] According to one aspect of an embodiment of the present disclosure, a thin film transistor is provided, comprising: an active layer, a light shielding layer and a gate located on one side of a substrate, the light shielding layer being located between the substrate and the active layer, the orthographic projection of the active layer on the substrate overlapping with the orthographic projection of the light shielding layer on the substrate; a first interlayer dielectric layer being located on a side of the active layer away from the substrate; a source electrode penetrating the first interlayer dielectric layer and connected to the active layer, the orthographic projection of the source electrode on the substrate at least partially not overlapping with the orthographic projection of the light shielding layer on the substrate; a second interlayer dielectric layer being located on a side of the first interlayer dielectric layer away from the active layer and covering the source electrode; and a drain electrode comprising a first portion and a second portion connected to the first portion and configured to be connected to a first electrode, the first portion penetrating the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer, the second portion being located on a side of the second interlayer dielectric layer away from the first interlayer dielectric layer, wherein: the orthographic projection of a region where the second portion is configured to be connected to the first electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode on the substrate.

[0005] In some embodiments, an orthographic projection of the second portion of the drain on the substrate at least partially does not overlap with an orthographic projection of the source on the substrate.

[0006] In some embodiments, an orthographic projection of the second portion of the drain on the substrate is located between an orthographic projection of the source on the substrate and an orthographic projection of the first portion on the substrate.

[0007] In some embodiments, the projection of the drain on the substrate is a first projection, the projection of the gate on the substrate is a second projection, and the length of the first projection in a reference direction is greater than the length of the second projection in the reference direction.

[0008] In some embodiments, the active layer includes a first contact portion that is in direct contact with the source, and a second contact portion that is in direct contact with the drain, and the second portion is configured to have an orthographic projection on the substrate of an area connected to the first electrode located between an orthographic projection of the first contact portion on the substrate and an orthographic projection of the second contact portion on the substrate.

[0009] In some embodiments, the thin film transistor further includes: a buffer layer located between the substrate and the active layer, and the light shielding layer is located between the substrate and the buffer layer.

[0010] In some embodiments, the thin film transistor includes a gate dielectric layer, wherein: the gate dielectric layer is located on a side of the active layer away from the substrate; the gate is located on a side of the gate dielectric layer away from the active layer; and the first interlayer dielectric layer is located on a side of the gate dielectric layer away from the substrate and covers the gate.

[0011] In some embodiments, the material of the active layer includes an oxide semiconductor.

[0012] In some embodiments, a length of an orthographic projection of the active layer on the substrate along a reference direction is greater than a length of an orthographic projection of the light shielding layer on the substrate along the reference direction.

[0013] In some embodiments, a length of an orthographic projection of the active layer on the substrate along a reference direction is greater than a length of an orthographic projection of the drain on the substrate along the reference direction.

[0014] In some embodiments, the orthographic projection of a region where the second portion is configured to be connected to the first electrode on the substrate at least partially overlaps with the orthographic projection of the light shielding layer on the substrate.

[0015] In some embodiments, along the reference direction, a distance between an orthographic projection of the first contact portion on the substrate and an orthographic projection of the gate on the substrate is greater than a distance between an orthographic projection of the second contact portion on the substrate and an orthographic projection of the gate on the substrate.

[0016] According to another aspect of the embodiments of the present disclosure, there is provided an array substrate, comprising: the thin film transistor described in any one of the above embodiments.

[0017] In some embodiments, the array substrate further includes: a planarization layer located on a side of the second interlayer dielectric layer of the thin film transistor away from the first interlayer dielectric layer, the planarization layer having an opening corresponding to the second portion of the drain of the thin film transistor; and a first electrode at least partially located in the opening and in contact with the second portion of the drain.

[0018] In some embodiments, the first electrode is a pixel anode; the array substrate further includes: an insulating layer located on a side of the first electrode away from the second portion of the drain; and a common electrode located on a side of the insulating layer away from the first electrode.

[0019] According to another aspect of the embodiments of the present disclosure, there is provided a display device, comprising: the array substrate described in any one of the above embodiments.

[0020] According to another aspect of the embodiments of the present disclosure, a method for manufacturing a thin film transistor is provided, comprising: forming an active layer, a light shielding layer and a gate electrode located on one side of a substrate, the light shielding layer being located between the substrate and the active layer, the orthographic projection of the active layer on the substrate overlapping with the orthographic projection of the light shielding layer on the substrate; forming a first interlayer dielectric layer located on a side of the active layer away from the substrate; forming a source electrode penetrating the first interlayer dielectric layer and connected to the active layer, the orthographic projection of the source electrode on the substrate not overlapping with the orthographic projection of the light shielding layer on the substrate; forming a second interlayer dielectric layer located on a side of the first interlayer dielectric layer away from the active layer and covering the source electrode; and forming a drain electrode, the drain electrode comprising a first portion and a second portion connected to the first portion and configured to be connected to a first electrode, the first portion penetrating the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer, the second portion being located on a side of the second interlayer dielectric layer away from the first interlayer dielectric layer, the orthographic projection of the region of the second portion configured to be connected to the first electrode on the substrate at least partially overlapping with the orthographic projection of the gate electrode on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0022] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0023] Figure 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure;

[0024] Figure 2 is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure;

[0025] Figure 3 is a schematic structural diagram of a thin film transistor according to yet another embodiment of the present disclosure;

[0026] Figure 4 is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure;

[0027] Figure 5 is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure;

[0028] Figure 6 is a structural schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0029] Figure 7 is a structural schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0030] Figure 8 is a schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;

[0031] Figure 9A-9G Schematic cross-sectional views of structures obtained at different stages of forming a thin film transistor according to some embodiments of the present disclosure are shown.

[0032] It should be understood that the size of each part shown in the accompanying drawings is not drawn according to the actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0033] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0034] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprises" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0035] In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be an intermediate component between the specific component and the first component or the second component. When a specific component is described as being connected to other components, the specific component may be directly connected to the other components without an intermediate component, or may not be directly connected to the other components but have an intermediate component.

[0036] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries, such as general dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.

[0037] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0038] When the PPI is large, the pitch between adjacent sub-pixels needs to be very small. The inventors noticed that since the pitch between adjacent sub-pixels is very small, when forming the source and drain of the thin film transistor in each sub-pixel, the source and drain are easily overlapped, resulting in poor reliability of the thin film transistor, thereby generating poor display phenomena such as dark spots, affecting the display effect.

[0039] To this end, the embodiments of the present disclosure propose the following technical solutions.

[0040] Figure 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.

[0041] like Figure 1 As shown, the thin film transistor 100 includes an active layer 102 , a first interlayer dielectric layer 103 , a source electrode 104 , a second interlayer dielectric layer 105 , and a drain electrode 106 located on one side of a substrate 101 .

[0042] The substrate 101 may be, for example, a glass substrate. However, the present disclosure is not limited thereto. For example, in some embodiments, the substrate 101 may also be a flexible substrate such as a polyimide (PI) substrate.

[0043] The active layer 102 is located on one side, such as the upper side, of the substrate 101. In some embodiments, the material of the active layer 102 may include polysilicon, such as low temperature polysilicon (LTPS). In other embodiments, the material of the active layer 102 may include an oxide semiconductor.

[0044] The first interlayer dielectric layer 103 is located on a side of the active layer 102 away from the substrate 101. For example, the material of the first interlayer dielectric layer 103 may include silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0045] The source electrode 104 penetrates the first interlayer dielectric layer 103 and is connected to the active layer 102. The source electrode 104 may be, for example, a stack of Ti / Al / Ti. In some embodiments, the source electrode 104 may contact a surface of the active layer 102 away from the substrate 101 (also referred to as an upper surface).

[0046] The second interlayer dielectric layer 105 is located on a side of the first interlayer dielectric layer 103 away from the active layer 102 and covers the source electrode 104. The material of the second interlayer dielectric layer 105 may be the same as or different from the material of the first interlayer dielectric layer 105. For example, the material of the second interlayer dielectric layer 105 may include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0047] The drain 106 includes a first portion 116. The first portion 116 penetrates the second interlayer dielectric layer 105 and the first interlayer dielectric layer 103 and is connected to the active layer 102. In some embodiments, the first portion 116 may be in contact with the surface of the active layer 102 away from the substrate 101. As an example, the first portion 116 may be a stack of Ti / Al / Ti. It should be understood that the thin film transistor 100 also includes a gate dielectric layer and a gate. In some embodiments, the thin film transistor 100 may be a top-gate thin film transistor. In other embodiments, the thin film transistor 100 may be a bottom-gate thin film transistor. In the case where the thin film transistor 100 is a top-gate thin film transistor, as Figure 1 As shown, the gate dielectric layer 107 is located on the side of the active layer 102 away from the substrate 101, the gate 108 is located on the side of the gate dielectric layer 107 away from the active layer 102, and the first interlayer dielectric layer 103 is located on the side of the gate dielectric layer 107 away from the substrate 101 and covers the gate 108. In some embodiments, the gate dielectric layer 107 may cover the active layer 102.

[0048] In the above embodiment, the source electrode 104 penetrates the first interlayer dielectric layer 103, the second interlayer dielectric layer 105 covers the source electrode 104, and the first portion 116 of the drain electrode 106 penetrates the second interlayer dielectric layer 105. In such a thin film transistor, the source electrode 104 and the drain electrode 106 are located in different layers, and the two will not overlap even if they are arranged very close in the direction parallel to the surface of the substrate 101, thereby improving the reliability of the thin film transistor. When the thin film transistor is applied to a display panel, the occurrence of poor display phenomena such as dark spots caused by the overlap of the source and drain electrodes can be reduced, thereby improving the display effect of the display panel.

[0049] Figure 2 is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure.

[0050] and Figure 1 Compared with the thin film transistor 100 shown in FIG. Figure 2 The drain electrode 106 in the thin film transistor 200 further includes a second portion 126 connected to the first portion 116. The second portion 126 is located on a side of the second interlayer dielectric layer 105 away from the first interlayer dielectric layer 103. The second portion 126 is configured to be connected to the first electrode. Here, the first electrode may be, for example, a pixel electrode or an anode.

[0051] In some embodiments, the orthographic projection of the second portion 126 of the drain electrode 106 on the substrate 101 partially overlaps with the orthographic projection of the source electrode 104 on the substrate 101, thereby helping to reduce the size of the thin film transistor. In some embodiments, the second portion 126 of the drain electrode 106 extends on the surface of the second interlayer dielectric layer 105 in a direction toward the source electrode 104, rather than extending in a direction away from the source electrode 104, thereby helping to further reduce the size of the thin film transistor.

[0052] In the above embodiment, the drain 106 also includes a second portion 126 configured to be connected to the first electrode. The second interlayer dielectric layer 105 covers the source 104, and the second portion 126 of the drain 106 is located on the side of the second interlayer dielectric layer 105 away from the first interlayer dielectric layer 103. Such a thin film transistor makes the contact between the first electrode and the drain 106 more reliable. In addition, since the source 104 and the second portion 126 of the drain 106 are located in different layers, the two will not overlap even if they are arranged very close in the direction parallel to the surface of the substrate 101, thereby improving the reliability of the thin film transistor. When the thin film transistor is applied to a display panel, the occurrence of poor display phenomena such as dark spots caused by the overlap of the source and the drain can be reduced, thereby improving the display effect of the display panel.

[0053] Figure 3 is a schematic structural diagram of a thin film transistor according to yet another embodiment of the present disclosure.

[0054] and Figure 2 Compared with the thin film transistor 200 shown in FIG. Figure 3 The active layer 102 in the thin film transistor 300 shown may have at least one of a first recess and a second recess. Here, the source electrode 104 contacts the bottom surface and the side surface of the first recess, and the first portion 116 of the drain electrode 106 contacts the bottom surface and the side surface of the second recess. Such a thin film transistor can increase the contact area between at least one of the source electrode 104 and the first portion 116 of the drain electrode 106 and the active layer 102, thereby reducing the contact resistance.

[0055] Figure 4 is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure.

[0056] and Figure 3 Compared with the thin film transistor 300 shown in FIG. Figure 4 The thin film transistor 400 shown also includes a buffer layer 109 located between the substrate 101 and the active layer 102. In some embodiments, the buffer layer 109 may include, for example, a silicon nitride layer and a silicon oxide layer. The silicon nitride layer is located between the substrate 101 and the silicon oxide layer, and the silicon oxide layer is located between the silicon nitride layer and the active layer 102. The silicon nitride layer can block metal ions such as sodium ions and potassium ions in the substrate 101 from entering the active layer 102, thereby preventing the metal ions from adversely affecting the performance of the active layer 102. On the one hand, the silicon oxide layer has good interface performance with the active layer 102, and on the other hand, it can also play a role in heat insulation. For example, the active layer 102 is polycrystalline silicon converted from amorphous silicon using excimer laser annealing (ELA). When the laser irradiates the amorphous silicon, the silicon oxide layer can block the heat from being transferred downward, thereby more effectively converting the amorphous silicon into polycrystalline silicon.

[0057] At least one of the source 104 and the first portion 116 of the drain 106 may penetrate the active layer 102 and extend into the buffer layer 109, for example, to a silicon oxide layer in the buffer layer 109. For example, a portion of the source 104 is embedded in the buffer layer 109. For another example, a portion of the first portion 116 may be embedded in the buffer layer 109. For another example, a portion of the source 104 and a portion of the first portion 116 are both embedded in the buffer layer 109.

[0058] Figure 5 is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure.

[0059] and Figure 4 Compared with the thin film transistor 400 shown in FIG. Figure 5The thin film transistor 500 shown further includes a light shielding layer 110 located between the substrate 101 and the buffer layer 109. Here, the orthographic projection of the active layer 102 on the substrate 101 at least partially overlaps with the orthographic projection of the light shielding layer 110 on the substrate 101. In some embodiments, the material of the light shielding layer 110 may include a metal material having light shielding properties such as molybdenum.

[0060] The shading layer 110 can block light from the side of the substrate 101 away from the active layer 102 (for example, light emitted by the backlight module when the thin film transistor is used in a liquid crystal display panel) to reduce the current generated by the active layer 102 when exposed to light, thereby reducing the leakage current of the thin film transistor 400.

[0061] It should be noted that although Figure 3-Figure 5 The drain 106 is shown to include the second portion 126 , but this is not limiting. In some embodiments, the drain 106 may not include the second portion 126 .

[0062] Figure 6 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

[0063] like Figure 6 As shown, the array substrate 600 includes a thin film transistor provided by any one of the above embodiments (eg, the thin film transistor 100 / 200 / 300 / 400 / 500).

[0064] In some embodiments, the array substrate 600 may further include a planarization layer 201 and a first electrode 202 .

[0065] The planarization layer 201 is located on a side of the second interlayer dielectric layer 105 of the thin film transistor 400 away from the first interlayer dielectric layer 103. The planarization layer 201 has an opening 211 that partially exposes the second portion 126 of the drain electrode 106 of the thin film transistor 400, that is, the opening 211 is connected to the second portion 126. The material of the planarization layer 201 may include, for example, a resin material, etc.

[0066] The first electrode 202 is at least partially located in the opening 211 and in contact with the second portion 126. For example, a portion of the first electrode 202 is located on the bottom and sidewalls of the opening 211, and the other portion is located on the planarization layer 201.

[0067] In some embodiments, the first electrode 202 may be an anode. In this case, the array substrate may further include a pixel defining layer partially covering the first electrode 202 .

[0068] In some other embodiments, the first electrode 202 may be a pixel electrode. In some embodiments, the array substrate may further include a common electrode (hereinafter referred to as a common electrode). Figure 7In other embodiments, the array substrate may not include the common electrode. For example, the common electrode may be disposed in the color filter substrate.

[0069] Figure 7 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.

[0070] and Figure 6 Compared with the array substrate 600 shown in FIG. Figure 7 The array substrate 700 shown further includes an insulating layer 203 and a common electrode 204. The insulating layer 203 is located on a side of the first electrode 202 away from the second portion 126, and the common electrode 204 is located on a side of the insulating layer 203 away from the first electrode 202. The insulating layer 203 isolates the first electrode 202 and the common electrode 204 so that the first electrode 202 and the common electrode 204 are insulated from each other. In some embodiments, the insulating layer 203 may cover a portion of the planarization layer 201. For example, the material of the insulating layer 203 may include silicon nitride, etc.

[0071] The present disclosure also provides a display device. The display device may include the array substrate 600 / 700 of any of the above embodiments. In some embodiments, the display device may be, for example, a display panel, a mobile terminal, a television, a monitor, a notebook computer, a digital photo frame, a navigator, an electronic paper, a virtual reality system, or any other product or component with a display function.

[0072] In some embodiments, the display device may be an organic light-emitting diode (OLED) display panel. In other embodiments, the display device may be a liquid crystal display panel. Since the source and drain of the thin film transistor in the display panel are located in different layers, the occurrence of poor display phenomena such as dark spots caused by the overlap of the source and drain is reduced, thereby improving the display effect of the display panel.

[0073] Figure 8 It is a schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. Figure 9A-9G The cross-sectional schematic diagrams of the structures obtained at different stages of forming a thin film transistor according to some embodiments of the present disclosure are shown. Figure 8 , Figure 9A-9G The formation process of a thin film transistor according to some embodiments of the present disclosure is introduced.

[0074] In step 802, an active layer 102 is formed on one side of the substrate 101, such as Fig.9A shown.

[0075] In some implementations, the buffer layer 109 located on one side of the substrate 101 may be formed first, and then the active layer 102 may be formed on the side of the buffer layer 109 away from the substrate 101. In other implementations, the light shielding layer 110 located on one side of the substrate 101 may be formed first, and then the buffer layer 109 located on one side of the substrate 101 and covering the light shielding layer 110 may be formed, and then the active layer 102 may be formed on the side of the buffer layer 109 away from the substrate 101. Here, the orthographic projection of the active layer 102 on the substrate 101 at least partially overlaps with the orthographic projection of the light shielding layer 110 on the substrate 101.

[0076] In some embodiments, see Fig.9A After forming the active layer 102 on one side of the substrate 101, a gate dielectric layer 107 is formed on the side of the active layer 102 away from the substrate 101, and then a gate 108 is formed on the side of the gate dielectric layer 107 away from the active layer 102. In this way, a top-gate thin film transistor can be formed. In some implementations, the gate dielectric layer 107 can cover the active layer 102.

[0077] In other embodiments, before forming the active layer 102 on one side of the substrate 101, a gate may be formed on one side of the substrate 101, and then a gate dielectric layer may be formed on the side of the gate away from the substrate 101. In this way, a bottom-gate thin film transistor may be formed.

[0078] In step 804, a first interlayer dielectric layer 103 is formed on a side of the active layer 102 away from the substrate 101. Fig. 9B In some embodiments, the first interlayer dielectric layer 103 may be located on a side of the gate dielectric layer 107 away from the substrate 101 and cover the gate 108 .

[0079] In step 806 , a source electrode 104 is formed which penetrates the first interlayer dielectric layer 103 and is connected to the active layer 102 .

[0080] For example, a first opening 10 penetrating the first interlayer dielectric layer 103 may be formed first, and the first opening 10 exposes a portion of the active layer 102, such as Fig. 9C As shown. In some implementations, the first opening 10 exposes the upper surface of the active layer 102. In other implementations, the first opening 10 may extend below the upper surface of the active layer 102. For example, a suitable etchant may be used to etch the first interlayer dielectric layer 103 and the active layer 102 to form the first opening 10. Then, a source electrode 104 is formed which is at least partially located in the first opening 10 and contacts the active layer 102, as shown in FIG. Fig.9D shown.

[0081] In some embodiments, when forming the buffer layer 109 , the first opening 10 formed may extend into the buffer layer 109 , that is, the active layer 102 may be overetched to reduce the process difficulty. In this case, the source electrode 104 may extend into the buffer layer 109 .

[0082] In step 808, a second interlayer dielectric layer 105 is formed on a side of the first interlayer dielectric layer 103 away from the active layer 102 and covering the source electrode 104. Fig.9E shown.

[0083] In step 810, the drain 106 is formed to form a thin film transistor. Here, the drain 106 includes at least a first portion 116. The first portion 116 penetrates the second interlayer dielectric layer 105 and the first interlayer dielectric layer 103 and is connected to the active layer 102. In some embodiments, the drain 106 also includes a second portion 126 connected to the first portion 116. The second portion 126 is located on a side of the second interlayer dielectric layer 105 away from the first interlayer dielectric layer 103. In some embodiments, the orthographic projection of the second portion 126 on the substrate 101 partially overlaps with the orthographic projection of the source 104 on the substrate 101.

[0084] For example, a second opening 20 penetrating the second interlayer dielectric layer 105 and the first interlayer dielectric layer 103 may be formed first, and the second opening 20 exposes a portion of the active layer 102, such as Fig.9F In some implementations, the second opening 20 exposes the upper surface of the active layer 102. In other implementations, the second opening 20 may extend below the upper surface of the active layer 102. Then, the source electrode 106 is formed, as shown in FIG. Figure 9G Here, the first portion 116 of the source electrode 106 is located in the second opening 20 and contacts the active layer 102 .

[0085] In some embodiments, when the buffer layer 109 is formed, the second opening 20 may extend into the buffer layer 109 , that is, the active layer 102 may be overetched to reduce the process difficulty. In this case, the first portion 116 may extend into the buffer layer 109 .

[0086] So far, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution disclosed here.

[0087] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A thin film transistor, comprising: An active layer, a light shielding layer and a gate located on one side of a substrate, wherein the light shielding layer is located between the substrate and the active layer, and an orthographic projection of the active layer on the substrate overlaps with an orthographic projection of the light shielding layer on the substrate; A first interlayer dielectric layer, located on a side of the active layer away from the substrate; a source electrode, penetrating the first interlayer dielectric layer and connected to the active layer, wherein there is a cross section in which an orthographic projection of the source electrode on the substrate does not overlap with an orthographic projection of the light shielding layer on the substrate; A second interlayer dielectric layer, located on a side of the first interlayer dielectric layer away from the active layer and covering the source electrode; and A drain electrode, comprising a first portion and a second portion connected to the first portion and configured to be connected to the first electrode, wherein the first portion penetrates the second interlayer dielectric layer and the first interlayer dielectric layer and is connected to the active layer, and the second portion is located on a side of the second interlayer dielectric layer away from the first interlayer dielectric layer, wherein: The second portion is configured so that an orthographic projection of a region connected to the first electrode on the substrate partially overlaps with an orthographic projection of the gate on the substrate.

2. The thin film transistor according to claim 1, wherein: An orthographic projection of the second portion of the drain on the substrate at least partially does not overlap with an orthographic projection of the source on the substrate.

3. The thin film transistor according to claim 2, wherein: An orthographic projection of the second portion of the drain on the substrate is located between an orthographic projection of the source on the substrate and an orthographic projection of the first portion on the substrate.

4. The thin film transistor according to any one of claims 1 to 3, wherein: The projection of the drain on the substrate is a first projection, the projection of the gate on the substrate is a second projection, and the length of the first projection in the reference direction is greater than the length of the second projection in the reference direction.

5. The thin film transistor according to claim 3, wherein: The active layer includes a first contact portion directly in contact with the source, and a second contact portion directly in contact with the drain, the second portion being configured such that an orthographic projection of an area connected to the first electrode on the substrate is located between an orthographic projection of the first contact portion on the substrate and an orthographic projection of the second contact portion on the substrate.

6. The thin film transistor according to claim 1, further comprising: A buffer layer is located between the substrate and the active layer, and the light shielding layer is located between the substrate and the buffer layer.

7. The thin film transistor according to claim 6, wherein: The thin film transistor comprises a gate dielectric layer, wherein: The gate dielectric layer is located on a side of the active layer away from the substrate; The gate is located on a side of the gate dielectric layer away from the active layer; The first interlayer dielectric layer is located at a side of the gate dielectric layer away from the substrate and covers the gate.

8. The thin film transistor according to claim 1, wherein: The material of the active layer includes an oxide semiconductor.

9. The thin film transistor according to claim 1, wherein: A length of an orthographic projection of the active layer on the substrate along a reference direction is greater than a length of an orthographic projection of the light shielding layer on the substrate along the reference direction.

10. The thin film transistor according to claim 1, wherein: A length of an orthographic projection of the active layer on the substrate along a reference direction is greater than a length of an orthographic projection of the drain on the substrate along the reference direction.

11. The thin film transistor according to claim 1, wherein: The second portion is configured such that an orthographic projection of a region connected to the first electrode on the substrate at least partially overlaps with an orthographic projection of the light shielding layer on the substrate.

12. The thin film transistor according to claim 5, wherein: Along the reference direction, a distance between an orthographic projection of the first contact portion on the substrate and an orthographic projection of the gate on the substrate is greater than a distance between an orthographic projection of the second contact portion on the substrate and an orthographic projection of the gate on the substrate.

13. An array substrate, comprising: A thin film transistor as claimed in any one of claims 1 to 12.

14. The array substrate according to claim 13, further comprising: A planarization layer, located on a side of the second interlayer dielectric layer of the thin film transistor away from the first interlayer dielectric layer, the planarization layer having an opening corresponding to the second portion of the drain electrode of the thin film transistor; and The first electrode is at least partially located in the opening and contacts the second portion of the drain electrode.

15. The array substrate according to claim 14, wherein the first electrode is a pixel electrode; The array substrate further includes: an insulating layer, located on a side of the first electrode away from the second portion of the drain electrode; The common electrode is located on a side of the insulating layer away from the first electrode.

16. A display device, comprising: An array substrate as described in any one of claims 13 to 15.

17. A method for manufacturing a thin film transistor, comprising: An active layer, a light shielding layer and a gate are formed on one side of a substrate, wherein the light shielding layer is located between the substrate and the active layer, and an orthographic projection of the active layer on the substrate overlaps with an orthographic projection of the light shielding layer on the substrate; forming a first interlayer dielectric layer located on a side of the active layer away from the substrate; forming a source electrode penetrating the first interlayer dielectric layer and connected to the active layer, wherein there is a cross section in which an orthographic projection of the source electrode on the substrate does not overlap with an orthographic projection of the light shielding layer on the substrate; forming a second interlayer dielectric layer located on a side of the first interlayer dielectric layer away from the active layer and covering the source electrode; and A drain is formed, the drain comprising a first portion and a second portion connected to the first portion and configured to be connected to the first electrode, the first portion penetrates the second interlayer dielectric layer and the first interlayer dielectric layer and is connected to the active layer, and the second portion is located on a side of the second interlayer dielectric layer away from the first interlayer dielectric layer, wherein: The second portion is configured so that an orthographic projection of a region connected to the first electrode on the substrate partially overlaps with an orthographic projection of the gate on the substrate.

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