High-voltage LED manufacturing method and high-voltage LED

Abstract

The application discloses a high-voltage LED manufacturing method and a high-voltage LED. The manufacturing method comprises the following steps: providing a substrate; forming an epitaxial structure on the surface of the substrate; etching the epitaxial structure to form an electrode pattern and a groove; forming a first barrier layer, a second barrier layer and a third barrier layer; forming a transparent conductive layer, a metal layer and an insulating layer; the first barrier layer covers the sidewall of the groove, the exposed substrate of the groove and part of the surface of the epitaxial structure, so that the transparent conductive layer is prevented from contacting the exposed P-type layer, the active layer and the N-type layer of the groove; the second barrier layer covers the etched groove sidewall of the electrode pattern, the exposed N-type layer of the etched groove and part of the surface of the epitaxial structure, so that the transparent conductive layer is prevented from contacting the exposed P-type layer, the active layer and the N-type layer of the etched groove of the electrode pattern, the line width during formation of the transparent conductive layer is reduced, the insulating layer covers the first barrier layer, the thickness of the passivation layer covering the groove is increased, the leakage of the high-voltage LED is inhibited, and the moisture corrosion resistance is improved.

Description

Technical Field

[0001] This application relates to the field of LED technology, and in particular to a method for manufacturing a high-voltage LED and a high-voltage LED obtained by the method. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor light-emitting device that uses the electroluminescence principle of a semiconductor PN junction to convert electrical energy into light energy. It has advantages such as small size, low power consumption, and long lifespan, and is now widely used in various lighting scenarios, backlighting, automotive lights, and other fields.

[0003] With the continuous development of the LED industry, a new type of high-voltage (HV) LED chip structure has attracted much attention. Compared with ordinary LEDs, high-voltage LEDs can reduce packaging costs, the number of components and solder joints, improve device reliability, and achieve higher power under low current drive. Currently, high-voltage LEDs on the market have relatively vertical trench angles and thin insulating layers covering the trenches, which affects the insulation coverage of the trenches and makes them prone to leakage, thus affecting the performance of high-voltage LEDs. In addition, existing methods for manufacturing high-voltage LEDs suffer from a large linewidth of the transparent conductive layer during fabrication, affecting light emission. Therefore, providing a high-voltage LED fabrication method that can enhance the insulation coverage of the trenches and reduce the linewidth of the transparent conductive layer has become a research focus for those skilled in the art. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a method for manufacturing a high-voltage LED. When manufacturing an LED using this method, the insulation coverage of the trench can be enhanced and the linewidth of the transparent conductive layer can be reduced, thereby improving the performance of the high-voltage LED.

[0005] To address the above problems, the embodiments of this application provide the following technical solutions:

[0006] A method for manufacturing a high-voltage LED, the method comprising:

[0007] Provide a substrate;

[0008] An epitaxial structure is formed on the surface of the substrate, the epitaxial structure including an N-type layer, an active layer and a P-type layer arranged sequentially away from the surface of the substrate;

[0009] The epitaxial structure is etched along a first direction to form an electrode pattern and a trench, the trench surrounding the electrode pattern, wherein the etched trench of the electrode pattern exposes a portion of the surface of the N-type layer, the trench exposes a portion of the surface of the substrate, and the first direction is perpendicular to the surface of the substrate;

[0010] A barrier layer is formed, comprising a first barrier layer, a second barrier layer, and a third barrier layer. The first barrier layer covers the trench sidewalls and the exposed substrate surface of the trench, extending along the trench sidewalls to the side of the epitaxial structure facing away from the substrate surface, covering a portion of the epitaxial structure's surface facing away from the substrate surface. The second barrier layer covers the electrode pattern etching channel sidewalls and the exposed N-type layer surface of the electrode pattern etching channel, extending along the electrode pattern etching channel sidewalls to the side of the epitaxial structure facing away from the substrate surface, covering a portion of the epitaxial structure's surface facing away from the substrate surface. The third barrier layer covers a portion of the epitaxial structure's surface facing away from the substrate surface. The first, second, and third barrier layers are not connected to each other.

[0011] A transparent conductive layer is formed, which covers the side of the epitaxial structure away from the substrate surface, and covers the portion of the first barrier layer extending to the side of the epitaxial structure away from the substrate surface, the portion of the second barrier layer extending to the side of the epitaxial structure away from the substrate surface, and the third barrier layer.

[0012] A metal layer is formed, which covers the second barrier layer and the portion of the transparent conductive layer corresponding to the third barrier layer;

[0013] An insulating layer is formed, which covers the transparent conductive layer, the metal layer, and the first barrier layer.

[0014] Optionally, etching the epitaxial structure along the first direction to form the trench includes:

[0015] The epitaxial structure is etched along the first direction to form a first trench, and the first trench exposes a portion of the surface of the N-type layer.

[0016] The N-type layer portion exposed by the first trench is etched along the first direction to form a second trench. The second trench exposes the surface of the substrate portion and corresponds to the first trench. The second trench and the first trench together constitute the trench.

[0017] Optionally, the second barrier layer includes multiple sub-barrier layers, the refractive index of the P-type layer is a first preset value, and the refractive index of the insulating layer is a second preset value; forming the second barrier layer includes:

[0018] The plurality of second sub-blocking layers are sequentially formed along a direction away from the substrate surface, and the refractive index of the plurality of second sub-blocking layers gradually changes from the first preset value to the second preset value.

[0019] Optionally, the manufacturing method also includes:

[0020] The back side of the substrate is ground to thin the substrate to a predetermined thickness;

[0021] A Bragg reflective layer is formed on the back side of the substrate.

[0022] This application embodiment also provides a high-voltage LED, which includes:

[0023] Substrate;

[0024] An epitaxial structure located on the surface of the substrate includes an N-type layer, an active layer, and a P-type layer arranged sequentially along a side away from the surface of the substrate.

[0025] Electrode patterns and trenches, the trenches surrounding the electrode patterns, the etched channels of the electrode patterns extending along a first direction to expose a portion of the surface of the N-type layer, the trenches extending along the first direction to expose a portion of the surface of the substrate, the first direction being perpendicular to the surface of the substrate;

[0026] A barrier layer, comprising a first barrier layer, a second barrier layer, and a third barrier layer, wherein the first barrier layer covers the trench sidewalls and the exposed substrate surface of the trench, and extends along the trench sidewalls to the side of the epitaxial structure opposite to the substrate surface, covering a portion of the epitaxial structure surface opposite to the substrate surface; the second barrier layer covers the electrode pattern etching channel sidewalls and the exposed N-type layer surface of the electrode pattern etching channel, and extends along the electrode pattern etching channel sidewalls to the side of the epitaxial structure opposite to the substrate surface, covering a portion of the epitaxial structure surface opposite to the substrate surface; the third barrier layer covers a portion of the epitaxial structure surface opposite to the substrate surface, and the first barrier layer, the second barrier layer, and the third barrier layer are not connected to each other;

[0027] A transparent conductive layer covers the side of the epitaxial structure away from the substrate surface, and covers the portion of the first barrier layer extending to the side of the epitaxial structure away from the substrate surface, the portion of the second barrier layer extending to the side of the epitaxial structure away from the substrate surface, and the third barrier layer.

[0028] A metal layer that covers the second barrier layer and also covers the portion of the transparent conductive layer corresponding to the third barrier layer;

[0029] An insulating layer that covers the transparent conductive layer, the metal layer, and the first barrier layer.

[0030] Optionally, the trench includes a first trench and a second trench, the first trench and the second trench being opposite to each other, the first trench extending along the first direction to the N-type layer, exposing a portion of the surface of the N-type layer, and the second trench extending from the exposed portion of the N-type layer surface of the first trench to the substrate surface along the first direction.

[0031] Optionally, the refractive index of the P-type layer is a first preset value, the refractive index of the insulating layer is a second preset value, and the second barrier layer includes a plurality of second sub-barrier layers arranged sequentially along the side away from the substrate surface, wherein the refractive index of the plurality of second sub-barrier layers gradually changes from the first preset value to the second preset value.

[0032] Optionally, the thickness of the first barrier layer can be in the range of [value missing]. Including endpoint values, the length of the portion of the first barrier layer extending to the surface of the epitaxial structure along the second direction ranges from 1 μm to 2 μm, including endpoint values; the second barrier layer is SiO. x Layer or SiN y For the first layer, 0 ≤ x ≤ 2, 0 ≤ y ≤ 1, the thickness of the second barrier layer ranges from [value missing]. Including the endpoint value, the length of the portion of the second barrier layer extending to the surface of the epitaxial structure along the second direction ranges from 1 μm to 2 μm, including the endpoint value, and the second direction is parallel to the substrate surface.

[0033] Optionally, the thickness of the transparent conductive layer can be in the range of [value missing]. Including endpoint values; the thickness of the metal layer ranges from 1.3 μm to 2.1 μm, including endpoint values; the thickness of the insulating layer ranges from... Includes endpoint values.

[0034] Optionally, the substrate has a preset thickness, and the high-voltage LED further includes:

[0035] A Bragg reflective layer, which is located on the back side of the substrate.

[0036] Compared with existing technologies, the above technical solution has the following advantages:

[0037] The technical solution provided in this application includes: providing a substrate; forming an epitaxial structure on the surface of the substrate; etching the epitaxial structure to form electrode patterns and trenches; forming a barrier layer, the barrier layer including a first barrier layer, a second barrier layer, and a third barrier layer; sequentially forming a transparent conductive layer, a metal layer, and an insulating layer; wherein, the first barrier layer covers the trench sidewalls and the exposed substrate surface of the trench, and the first barrier layer extends along the trench sidewalls to the substrate surface, covering the surface of the epitaxial structure portion, so that the first barrier layer can cover the exposed P-type layer, the active layer, and the N-type layer on the trench sidewalls, preventing subsequent formation of... The transparent conductive layer contacts the exposed P-type layer, active layer, and N-type layer of the trench; the second barrier layer covers the sidewall of the etched trench of the electrode pattern and the exposed N-type layer surface of the etched trench of the electrode pattern, and extends along the sidewall of the etched trench of the electrode pattern to the surface of the epitaxial structure, covering a portion of the surface of the epitaxial structure, so that the second barrier layer can cover the exposed P-type layer, active layer, N-type layer of the etched trench sidewall of the electrode pattern and the exposed N-type layer surface of the etched trench of the electrode pattern, preventing the subsequently formed transparent conductive layer from contacting the exposed P-type layer, active layer, and N-type layer of the etched trench of the electrode pattern. Therefore, the high-voltage LED fabrication method provided in this application avoids contact between the subsequently formed transparent conductive layer and the epitaxial structure exposed by the electrode pattern etching channel and the epitaxial structure exposed by the trench. This means that when forming the transparent conductive layer, it is not necessary to increase the exposure dose to avoid contact between the transparent conductive layer and the epitaxial structure exposed by the electrode pattern etching channel and the trench, which would lead to an increase in the linewidth of the transparent conductive layer. This helps to reduce the linewidth when forming the transparent conductive layer, thereby helping to ensure the light-emitting area of ​​the high-voltage LED and improve the working performance of the fabricated high-voltage LED.

[0038] In addition, the manufacturing method includes forming an insulating layer that covers the first barrier layer, such that the passivation layer covering the trench includes the first barrier layer and the insulating layer covering the first barrier layer. This results in a thicker passivation layer covering the trench compared to the passivation layer thickness of the high-voltage LED trench produced by existing manufacturing methods. This helps to enhance the insulation coverage of the trench, thereby helping to suppress leakage current in the high-voltage LED, enhance the VF4 performance of the high-voltage LED, and the thicker passivation layer covering the trench also improves the high-voltage LED's resistance to moisture corrosion, helping to suppress aging of the high-voltage LED due to moisture corrosion. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A flowchart illustrating a high-voltage LED manufacturing method provided in this application embodiment;

[0041] Figures 2 to 12 This is a schematic diagram of the structure formed after different process steps in a high-voltage LED manufacturing method provided in this application embodiment. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0044] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0045] As described in the background section, providing a method for fabricating high-voltage LEDs that enhances insulation coverage of trenches and reduces ITO linewidth has become a research focus for those skilled in the art.

[0046] Compared to ordinary LEDs, high-voltage LEDs have higher voltages. When integrating them into a package, the number of LEDs required in the package can be reduced, thus reducing the number of components and solder joints, and improving the reliability of the package. Furthermore, the higher voltage of high-voltage LEDs eliminates the need for significant voltage conversion, resulting in lower transformer losses and simpler driving designs. High-voltage LEDs also have lower current draw, leading to less heat generation and lower heat dissipation requirements, further contributing to their reliability. Additionally, high-voltage LEDs are created by deeply etching trenches into a pre-fabricated epitaxial structure, isolating it into multiple independent chips. Insulating material is deposited within these trenches, and these independent chips are connected in series via electrode bridging to form a light-emitting diode. Driven by a small current, they can achieve high power. Different driving voltages can be achieved by connecting different numbers of chips in series; for example, 2, 3, or 6 chips connected in series result in high-voltage LEDs with voltages of approximately 6V, 9V, and 18V, respectively.

[0047] Currently, the commonly used manufacturing process for high-voltage LEDs in the market is as follows: providing a substrate; forming an epitaxial structure on the substrate; etching the epitaxial structure to form electrode patterns; deep etching to form deep etching trenches, the top of which is flush with the surface of the epitaxial structure; forming an electrode barrier layer; forming a transparent conductive layer; forming a metal electrode; forming an insulating layer. Among these, the barrier layer is designed according to the electrode morphology and is a single layer of SiO2; the insulating layer is a relatively thin layer of SiO2. At the same time, the angle of the deep etching trenches is relatively vertical, which makes the insulating layer poorly insulating against the deep etching trenches, potentially leading to leakage and affecting the performance of the high-voltage LED.

[0048] Furthermore, in high-voltage LEDs, the transparent conductive layer covers the surface of the epitaxial structure, specifically the P-type layer. It is known that the top of a deep etching trench is flush with the surface of the epitaxial structure, and the sidewalls of the trench expose the P-type, active, and N-type layers within the epitaxial structure. Additionally, the film formed during the fabrication of the transparent conductive layer covers both the epitaxial surface and the deep etching trench. This means the film formed during the fabrication of the transparent conductive layer will directly contact the P-type, active, and N-type layers in the epitaxial structure. Therefore, the transparent conductive layer in the deep etching trench needs to be completely removed in subsequent processes. If the transparent conductive layer is not completely removed in the subsequent deep etching trench, the remaining transparent conductive layer will be electrically connected to the exposed epitaxial structure, affecting the normal operation of the high-voltage LED. To prevent the formed transparent conductive layer from contacting the P-type, N-type, and active layers in the epitaxial structure, and to ensure that the transparent conductive layer does not overlap with the mesa region, it is necessary to completely remove the transparent conductive layer in the deep etching trenches. However, due to the difficulty in developing and etching the transparent conductive layer in the deep etching trenches, a high exposure metering is required during etching to completely remove the transparent conductive layer. This results in a large linewidth of the transparent conductive layer, a loss of light-emitting area, and an impact on the performance of high-voltage LEDs.

[0049] Based on the above research, this application provides a method for manufacturing a high-voltage LED, such as... Figure 1 As shown, the manufacturing method includes the following steps:

[0050] S1: As Figure 2 As shown, a substrate 10 is provided;

[0051] S2: Continue as follows Figure 2 As shown, an epitaxial structure 20 is formed on the surface of the substrate 10. The epitaxial structure 20 includes an N-type layer 21, an active layer 22, and a P-type layer 23 sequentially along a direction away from the surface of the substrate 10. The active layer 23 is a multilayer quantum well layer. In this embodiment, the epitaxial structure includes an N-type layer 21, an active layer 22, and a P-type layer 23. However, this embodiment is not limited to this. In other embodiments of this application, the epitaxial structure may include other film layers besides the N-type layer 21, the active layer 22, and the P-type layer 23, depending on the specific situation. It should be noted that the P-type layer is P-type GaN, the N-type layer is N-type GaN, and the active layer is a multilayer quantum well layer. However, this embodiment is not limited to this, depending on the specific situation.

[0052] S3: As Figure 3 and Figure 4 As shown, Figure 4 for Figure 3A cross-sectional view along the AA1 direction shows that the epitaxial structure 20 is etched along a first direction to form an electrode pattern 24 and a trench 25. The trench 25 surrounds the electrode pattern 24, and the epitaxial structure surrounded by the trench is a mesa region. The etched trenches of the electrode pattern 24 expose a portion of the surface of the N-type layer 23, and the trenches 25 expose a portion of the surface of the substrate 10. The first direction is perpendicular to the surface of the substrate 10. It should be noted that the etched trenches of the electrode pattern 24 exposing a portion of the surface of the N-type layer 23 means that the depth of the etched trenches when etching the epitaxial structure to form the electrode pattern extends into the N-type layer 23, thereby exposing a portion of the surface of the N-type layer 23.

[0053] S4: As Figure 5 and Figure 6 As shown, Figure 6 for Figure 5 A cross-sectional view along the BB1 ​​direction shows a barrier layer 30, which includes a first barrier layer 31, a second barrier layer 32, and a third barrier layer 33. The first barrier layer 31 covers the sidewalls of the trench 25 and the exposed portion of the substrate 10 surface, extending along the sidewalls of the trench 25 to the side of the epitaxial structure 20 facing away from the substrate 10 surface, thus covering a portion of the epitaxial structure 20 surface facing away from the substrate 10 surface; the second barrier layer 32 covers the sidewalls of the etched channel of the electrode pattern 24 and the exposed N-type layer 23. The first barrier layer 31, the second barrier layer 32, and the third barrier layer 33 are all non-contacting. The first barrier layer 31, the second barrier layer 32, and the third barrier layer 33 are all non-contacting.

[0054] S5: As Figure 7 and Figure 8 As shown, Figure 8 for Figure 7A cross-sectional view along the CC1 direction shows a transparent conductive layer 40. This transparent conductive layer 40 covers the side of the epitaxial structure 20 facing away from the surface of the substrate 10, and covers the portion of the first barrier layer 31 extending to the side of the epitaxial structure 20 facing away from the surface of the substrate 10, the portion of the second barrier layer 32 extending to the side of the epitaxial structure 20 facing away from the surface of the substrate 10, and the third barrier layer 33. Forming the transparent conductive layer includes: forming a transparent conductive layer covering the surface of the epitaxial structure, the trench surface, and the surface of the electrode pattern etched trench by sputtering; annealing the formed transparent conductive layer using a rapid annealing furnace at a temperature of 500℃~650℃ for 1 minute. For 10 minutes, using positive photoresist as a mask, wet etching is performed to form the transparent conductive layer, and then the photoresist is removed. It should be noted that the first barrier layer 31, the second barrier layer 32, and the third barrier layer 33 cover a portion of the surface of the epitaxial structure facing away from the substrate 10. Therefore, the transparent conductive layer 40 covering the surface of the epitaxial structure 10 refers to the transparent conductive layer 40 covering the portion of the surface of the epitaxial structure 20 excluding the portion covered by the first barrier layer 31, the second barrier layer 32, and the third barrier layer 33. It should also be noted that the third barrier layer 33 is the electrode barrier layer formed during the fabrication of high-voltage LEDs in existing methods.

[0055] S6: As Figure 9 As shown, a metal layer 50 is formed, which covers the second barrier layer 32 and the portion of the transparent conductive layer 40 corresponding to the third barrier layer 33 to form a metal electrode. The formation of the metal layer includes: using a negative photoresist as a mask, performing metal evaporation by electron beam evaporation to form the metal layer, then stripping the metal from the photoresist surface and removing the photoresist. It should be noted that, as is known above, the second barrier layer 32 of the transparent conductive layer extends to the portion of the epitaxial structure 20 away from the surface of the substrate 10. Therefore, the above-mentioned metal layer 50 covering the second barrier layer 32 means that the metal layer 50 covers the portion of the second barrier layer 32 that is not covered by the transparent conductive layer 40. That is, the metal layer 50 covering the second barrier layer 32 means that the metal layer 50 covers the portion of the second barrier layer 32 located on the sidewall of the etching channel of the electrode pattern 24 and the portion of the second barrier layer 32 located on the surface of the exposed N-type layer portion of the etching channel of the electrode pattern 24.

[0056] S7: As Figure 10 and Figure 11 As shown, Figure 11 for Figure 10A cross-sectional view along the DD1 direction shows an insulating layer 60 covering the transparent conductive layer 40, the metal layer 50, and the first barrier layer 33 to provide insulation protection for the high-voltage LED. In this embodiment, the insulating layer is formed using a PECVD process; however, this embodiment is not limited to this method and may be adapted to the specific circumstances. It should be noted that, since the transparent conductive layer 40 is known to cover the portion of the first barrier layer 31 extending to the side of the epitaxial structure 20 away from the surface of the substrate 10, the insulating layer 60 covering the first barrier layer 31 means that the insulating layer 60 covers the portion of the first barrier layer 31 not covered by the transparent conductive layer 40. That is, the insulating layer 60 covering the first barrier layer 31 means that the insulating layer 60 covers the portion of the first barrier layer 31 located on the sidewall of the trench 25 and the portion of the first barrier layer 31 located on the exposed surface of the substrate 10 of the trench 25 covered by the first barrier layer 31. Furthermore, the insulating layer 60 covering the transparent conductive layer 40 means that the insulating layer 60 covers the portion of the transparent conductive layer 40 not covered by the metal layer 50.

[0057] Specifically, in this embodiment, when fabricating a high-voltage LED using the aforementioned method, after forming the electrode image and trench, a first barrier layer is formed. This first barrier layer covers the trench sidewalls and the exposed substrate surface of the trench. The trench exposes the exposed substrate surface, causing the P-type layer, active layer, and N-type layer to be exposed on the trench sidewalls. The first barrier layer covers the exposed substrate surface of the trench sidewalls, ensuring that the P-type layer, active layer, and N-type layer are covered, thus preventing the subsequent formation of the transparent conductive layer from contacting the exposed P-type layer, active layer, and N-type layer. Furthermore, the first barrier layer extends along the trench sidewalls to the substrate surface, covering the surface of the epitaxial structure portion, thereby enclosing the area where the trench connects to the epitaxial structure, further preventing the subsequent formation of the transparent conductive layer. The layer contacts the exposed P-type layer, active layer, and N-type layer of the trench; and the fabrication method includes forming a second barrier layer, the second barrier layer covering the sidewall of the etched trench of the electrode pattern and the surface of the exposed N-type layer of the etched trench of the electrode pattern, such that the second barrier layer can cover the exposed P-type layer, active layer, N-type layer of the etched trench sidewall of the electrode pattern and the surface of the exposed N-type layer of the etched trench of the electrode pattern, preventing the subsequently formed transparent conductive layer from contacting the exposed P-type layer, active layer, and N-type layer of the etched trench of the electrode pattern. The second barrier layer also extends along the sidewall of the etched trench of the electrode pattern to the surface of the epitaxial structure, covering a portion of the surface of the epitaxial structure, such that the second barrier layer also wraps the area where the etched trench of the electrode pattern meets the surface of the epitaxial structure, preventing the subsequently formed transparent conductive layer from contacting the exposed P-type layer, active layer, and N-type layer of the etched trench of the electrode pattern. Therefore, before forming the transparent conductive layer, the high-voltage LED fabrication method provided in this application forms a first barrier layer covering the exposed P-type layer, active layer, and N-type layer of the trench, and a second barrier layer covering the exposed P-type layer, active layer, and N-type layer of the electrode pattern etching channel. This prevents the subsequently formed transparent conductive layer from contacting the exposed epitaxial structure of the electrode pattern etching channel and the exposed epitaxial structure of the trench. Even if some transparent conductive layer remains in the electrode pattern etching channel and the trench, it will not affect the operation of the fabricated high-voltage LED. Thus, when forming the transparent conductive layer, it is not necessary to increase the exposure dose to completely remove the transparent conductive layer remaining in the electrode pattern etching channel and the trench, thereby avoiding the problem of a large linewidth of the transparent conductive layer. This helps to reduce the linewidth when forming the transparent conductive layer, thereby helping to ensure the light-emitting area of ​​the high-voltage LED and improve the working performance of the fabricated high-voltage LED.

[0058] Furthermore, in this embodiment, the manufacturing method includes forming an insulating layer that covers the first barrier layer, such that the passivation layer covering the trench includes the first barrier layer and an insulating layer covering the first barrier layer. This results in a thicker passivation layer covering the trench compared to the passivation layer thickness of the high-voltage LED trench produced by existing manufacturing methods. Under the premise that the trench has the same angle, this helps to enhance the insulation coverage of the trench, thereby helping to suppress leakage current of the high-voltage LED, enhance the VF4 performance of the high-voltage LED, and the thicker passivation layer covering the trench can also improve the resistance of the high-voltage LED to moisture corrosion, helping to suppress the aging of the high-voltage LED caused by moisture corrosion.

[0059] Based on the above embodiments, in one embodiment of this application, etching the epitaxial structure along the first direction to form the trench includes: as follows Figure 12 As shown, the epitaxial structure 20 is etched along the first direction to form a first trench 251, and the first trench 251 exposes a portion of the surface of the N-type layer 21; the portion of the surface of the N-type layer 21 exposed by the first trench 251 is etched along the first direction to form a second trench 252, the second trench 252 exposes a portion of the surface of the substrate 10, and the second trench 252 corresponds to the first trench 251, and the second trench 252 and the first trench 251 constitute the trench.

[0060] Specifically, in this embodiment, forming the first trench includes: cleaning the epitaxial structure, coating the surface of the epitaxial structure with photoresist, homogenizing the photoresist, and then performing exposure and development to prepare an etching pattern. Afterwards, ICP etching is performed to etch the electrode pattern and the first trench, and the photoresist is removed. Forming the second trench includes: spin-coating a positive photoresist onto the surface of the epitaxial structure having the electrode pattern and the first trench. The positive photoresist is located both on the surface of the epitaxial structure excluding the area containing the electrode pattern and the trench, and on the surface of the epitaxial structure exposed by the electrode pattern etching trench. The thickness of the positive photoresist is 10μm to 18μm. The positive photoresist is then subjected to a soft bake at 90℃ to 100℃ for 100s to 300s, followed by one exposure at 270mJ to 400mJ, and then one development for 80s. After 160 seconds, a hardening process is performed at a temperature of 100-140 seconds for 15-40 minutes. Then, negative photoresist is spin-coated, homogenized, and followed by a second soft bake at 90-100°C for 100-300 seconds. A second exposure is then performed at 100-200 mJ, followed by baking at 100-120°C for 90-160 seconds. Finally, a second development is performed for 60-100 seconds to form the second trench, and the photoresist is removed. In this embodiment, the upper width of the trench ranges from 15 μm to 25 μm, including the endpoints; the lower width ranges from 6 μm to 12 μm, including the endpoints. However, this embodiment is not limited and depends on the specific circumstances.

[0061] Based on the above embodiments, in one embodiment of this application, the refractive index of the P-type layer is a first preset value, the refractive index of the insulating layer is a second preset value, and the second barrier layer includes a plurality of sub-barrier layers arranged sequentially along the side away from the substrate surface. Forming the second barrier layer includes: sequentially forming a plurality of sub-barrier layers along the side away from the substrate surface, wherein the refractive index of the plurality of sub-barrier layers gradually changes from the first preset value to the second preset value. This ensures that during the transmission of light emitted from the active layer from the P-type layer to the insulating layer, the refractive index of the film layers through which the light beam passes gradually changes, thereby causing the total internal reflection angle during light transmission to gradually change. This prevents the total internal reflection angle from remaining consistently large due to the significant difference in refractive indices between the P-type layer and the insulating layer, thus helping to suppress total internal reflection and improve light emissivity. It should be noted that when forming a plurality of sub-barrier layers with gradually changing refractive indices, the thickness of each sub-barrier layer also changes with the refractive index. Therefore, when forming a plurality of sub-barrier layers, it is necessary to calculate the thickness of each sub-barrier layer based on its respective refractive index using the principle of light transmission to obtain a plurality of sub-barrier layers with gradually changing refractive index and thickness. It should also be noted that, in the embodiments of this application, the first barrier layer and the second barrier layer are formed in the same process step. The first barrier layer includes a plurality of sub-barrier layers, which are arranged sequentially along the side away from the substrate surface. The refractive index of the plurality of sub-barrier layers gradually changes from the first preset value to the second preset value. The thickness of the plurality of sub-barrier layers is also calculated using the principle of light transmission.

[0062] Specifically, in one embodiment of this application, the P-type layer is P-type GaN with a refractive index of 2.4, and the insulating layer is a SiO2 layer with a refractive index of approximately 1.5. Forming the second barrier layer includes: sequentially depositing multiple sub-barrier layers using a PECVD process, wherein the refractive index of these sub-barrier layers gradually decreases from 2.4 to 1.5. The thickness of each sub-barrier layer is calculated using the principle of light transmission based on its respective refractive index, resulting in a second barrier layer with gradually changing refractive index and thickness. The first barrier layer and the second barrier layer are formed in the same step using the same method, and will not be described further here. Optionally, in one embodiment of this application, the first barrier layer is SiO2. x Or SiN y The second barrier layer is SiO x Or SiN y The first barrier layer is SiO2, but this application's embodiments are not limited to this one; the specific method depends on the situation. x Or SiN y The second barrier layer is SiO x Or SiN yWhen the layers are in place, 0≤x≤2, 0≤y≤1. The refractive indices of the first and second barrier layers are controlled by adjusting the values ​​of x and y.

[0063] Based on the above embodiments, in one embodiment of this application, when forming the barrier layer, a positive photoresist is used as a mask to design the morphology of the barrier layer, and wet etching is performed, so that the first barrier layer in the final formed barrier layer covers the trench sidewall and the surface of the substrate portion exposed by the trench, and the first barrier layer extends along the trench sidewall to the substrate surface, covering the surface of the epitaxial structure portion, such that the second barrier layer in the barrier layer covers the etching channel sidewall of the electrode pattern and the surface of the N-type layer portion exposed by the electrode pattern etching channel, and extends along the etching channel sidewall of the electrode pattern to the surface of the epitaxial structure, covering the surface of the epitaxial structure portion. The length of the portion of the first barrier layer covering the epitaxial structure surface along the second direction ranges from 1 μm to 2 μm, including the endpoint value; the length of the portion of the second barrier layer extending to the epitaxial structure surface along the second direction ranges from 1 μm to 2 μm, including the endpoint value. However, this embodiment of the application does not limit this, and it depends on the specific situation. The second direction is parallel to the substrate surface. It should be noted that, since the first barrier layer covers the area where the trench connects to the epitaxial structure, and the second barrier layer covers the area where the electrode pattern connects to the epitaxial structure, the transparent conductive layer can be designed to be relatively larger, extending outwards from the periphery of the mesa region, thereby increasing the light-emitting area. In the embodiments of this application, the length of the transparent conductive layer extending outwards from the periphery of the mesa region ranges from 0 to 1 μm, including the right endpoint. However, this embodiment of the application is not limited to this, and the specific length depends on the circumstances.

[0064] Optionally, based on the above embodiments, in one embodiment of this application, the thickness of the transparent conductive layer ranges from [value missing]. Including endpoint values; the thickness of the metal layer ranges from 1.3 μm to 2.1 μm, including endpoint values; the thickness of the insulating layer ranges from... Endpoint values ​​are included, but the embodiments in this application are compared and not limited, depending on the specific circumstances.

[0065] It should be noted that when fabricating high-voltage LEDs, multiple high-voltage LEDs are formed on a substrate and isolated by trenches. Therefore, based on the above embodiments, in one embodiment of this application, after forming the insulating layer, the fabrication method further includes:

[0066] S8: Perform electrical sampling tests on multiple high-voltage LEDs formed on the same substrate to ensure the electrical performance of the fabricated high-voltage LEDs;

[0067] S9: Grind the back side of the substrate to thin the substrate to a preset thickness;

[0068] S10: A Bragg reflective layer is formed on the back side of the substrate, the back side of the substrate being opposite to the surface of the substrate;

[0069] S11: Cut multiple high-voltage LEDs on the same substrate to obtain a single high-voltage LED;

[0070] S12: Test and sort individual LEDs to obtain high-voltage LEDs that can be supplied to customers.

[0071] Accordingly, embodiments of this application also provide a high-voltage LED, which includes:

[0072] Substrate 10, such as Figure 2 As shown;

[0073] Extensional structure 20, continuing as follows Figure 2 As shown, the epitaxial structure 20 is located on the surface of the substrate 10 and includes an N-type layer 21, an active layer 22 and a P-type layer 23 arranged sequentially along the side away from the surface of the substrate 10.

[0074] Electrode patterns 24 and trenches 25, as shown Figure 3 and Figure 4 As shown, the trench 25 surrounds the electrode pattern 24, and the etching channel of the electrode pattern 24 extends along a first direction to expose a portion of the surface of the N-type layer 21. The trench 25 extends along the first direction to expose a portion of the surface of the substrate 10, and the first direction is perpendicular to the surface of the substrate 10. It should be noted that the etching channel of the electrode pattern 24 exposing a portion of the surface of the N-type layer 23 means that the depth of the etching channel when etching the epitaxial structure to form the electrode pattern extends into the N-type layer 23, thereby exposing a portion of the surface of the N-type layer 23.

[0075] Barrier layer 30, such as Figure 5 and Figure 6As shown, the barrier layer 30 includes a first barrier layer 31, a second barrier layer 32, and a third barrier layer 33. The first barrier layer 31 covers the sidewalls of the trench 25 and a portion of the substrate 10 exposed by the trench 25, extending along the sidewalls of the trench 25 to the side of the epitaxial structure 20 facing away from the substrate 10, covering a portion of the surface of the epitaxial structure 20 facing away from the substrate 10. The second barrier layer 32 covers the sidewalls of the etching channel of the electrode pattern 24 and a portion of the N-type layer 21 exposed by the etching channel of the electrode pattern 24, extending along the sidewalls of the etching channel of the electrode pattern 24 to the side of the epitaxial structure 20 facing away from the substrate 10, covering a portion of the surface of the epitaxial structure 20 facing away from the substrate 10. The third barrier layer 33 covers a portion of the surface of the epitaxial structure 20 facing away from the substrate 10, and the first barrier layer 31, the second barrier layer 32, and the third barrier layer 33 are not connected to each other.

[0076] Transparent conductive layer 40, such as Figure 7 and Figure 8 As shown, the transparent conductive layer 40 covers the side of the epitaxial structure 20 away from the surface of the substrate 10, and covers the portion of the first barrier layer 31 extending to the side of the epitaxial structure 20 away from the surface of the substrate 10, the portion of the second barrier layer 32 extending to the side of the epitaxial structure 20 away from the surface of the substrate 10, and the third barrier layer 33. It should be noted that the first barrier layer 31, the second barrier layer 32, and the third barrier layer 33 are known to cover a portion of the surface of the epitaxial structure away from the surface of the substrate 10. Therefore, the transparent conductive layer 40 covering the surface of the epitaxial structure 10 refers to the transparent conductive layer 40 covering the portion of the surface of the epitaxial structure 20 excluding the portion covered by the first barrier layer 31, the second barrier layer 32, and the third barrier layer 33.

[0077] Metal layer 50, such as Figure 9 As shown, the metal layer 50 covers the second barrier layer 32 and also covers the portion of the transparent conductive layer 40 corresponding to the third barrier layer 33. It should be noted that, as is known from the above, the transparent conductive layer and the second barrier layer 32 extend to the portion of the epitaxial structure 20 away from the surface of the substrate 10. Therefore, the above statement that the metal layer 50 covers the second barrier layer 32 means that the metal layer 50 covers the portion of the second barrier layer 32 that is not covered by the transparent conductive layer 40. That is, the statement that the metal layer 50 covers the second barrier layer 32 means that the metal layer 50 covers the portion of the second barrier layer 32 that covers the sidewall of the etching channel of the electrode pattern 24 and the portion of the surface of the N-type layer exposed by the etching channel of the electrode pattern 24.

[0078] Insulation layer 60, such as Figure 10 and Figure 11 As shown, the insulating layer 60 covers the transparent conductive layer 40, the metal layer 50, and the first barrier layer 31. It should be noted that the transparent conductive layer 40 covers the portion of the first barrier layer 31 extending to the side of the epitaxial structure 20 opposite to the surface of the substrate 10. Therefore, the statement that the insulating layer 60 covers the first barrier layer 31 means that the insulating layer 60 covers the portion of the first barrier layer 31 not covered by the transparent conductive layer 40. Specifically, the statement that the insulating layer 60 covers the first barrier layer 31 means that the insulating layer 60 covers the portion of the first barrier layer 31 covering the sidewall of the trench 25 and the portion of the first barrier layer 31 covering the exposed surface of the substrate 10 of the trench 25. Furthermore, the statement that the insulating layer 60 covers the transparent conductive layer 40 means that the insulating layer 60 covers the portion of the transparent conductive layer 40 not covered by the metal layer 50.

[0079] Specifically, in this embodiment, the high-voltage LED includes a first barrier layer. The first barrier layer covers the trench sidewall and the exposed substrate surface of the trench. The trench exposes the substrate surface, causing the trench sidewall to expose the P-type layer, the active layer, and the N-type layer. The first barrier layer covers the trench sidewall and the exposed substrate surface, allowing it to cover the exposed P-type layer, the active layer, and the N-type layer, preventing the subsequent formation of the transparent conductive layer from contacting the exposed P-type layer, the active layer, and the N-type layer. Furthermore, the first barrier layer extends along the trench sidewall to the substrate surface, covering the surface of the epitaxial structure, thus enclosing the area where the trench connects to the epitaxial structure, further preventing the subsequent formation of the transparent conductive layer from contacting the exposed P-type layer, the active layer, and the N-type layer.

[0080] The high-voltage LED further includes a second barrier layer. The second barrier layer covers the sidewalls of the etched channel of the electrode pattern and the exposed N-type layer surface of the etched channel of the electrode pattern. This allows the second barrier layer to cover the exposed P-type layer, active layer, and N-type layer on the sidewalls of the etched channel of the electrode pattern, as well as the exposed N-type layer surface of the etched channel of the electrode pattern, preventing the subsequently formed transparent conductive layer from contacting the exposed P-type layer, active layer, and N-type layer of the etched channel of the electrode pattern. The second barrier layer also extends along the sidewalls of the etched channel of the electrode pattern to the surface of the epitaxial structure, covering a portion of the surface of the epitaxial structure. This allows the second barrier layer to also enclose the area where the etched channel of the electrode pattern meets the surface of the epitaxial structure, preventing the subsequently formed transparent conductive layer from contacting the exposed P-type layer, active layer, and N-type layer of the etched channel of the electrode pattern.

[0081] Therefore, the high-voltage LED provided in this application embodiment has a first barrier layer covering the exposed P-type layer, active layer, and N-type layer of the trench, and a second barrier layer covering the exposed P-type layer, active layer, and N-type layer of the electrode pattern etching channel. This avoids contact between the subsequently formed transparent conductive layer and the exposed epitaxial structure of the electrode pattern etching channel and the trench. Even if some transparent conductive layer remains in the electrode pattern etching channel and the trench, it will not affect the operation of the fabricated high-voltage LED. Thus, when forming the transparent conductive layer, it is not necessary to increase the exposure dose in order to completely remove the transparent conductive layer portion remaining in the electrode pattern etching channel and the trench, thereby avoiding the problem of a large linewidth of the transparent conductive layer. This helps to reduce the linewidth when forming the transparent conductive layer, thereby helping to ensure the light-emitting area of ​​the high-voltage LED and improve the working performance of the fabricated high-voltage LED.

[0082] In addition, in this embodiment, the high-voltage LED includes an insulating layer that covers the first barrier layer, such that the passivation layer covering the trench includes the first barrier layer and the insulating layer covering the first barrier layer. This results in a thicker passivation layer covering the trench compared to the passivation layer thickness of the high-voltage LED produced by existing manufacturing methods. This helps to enhance the insulation coverage of the trench, thereby helping to suppress leakage current in the high-voltage LED, enhancing the VF4 performance of the high-voltage LED, and the thicker passivation layer covering the trench also improves the high-voltage LED's resistance to moisture corrosion, helping to suppress aging of the high-voltage LED due to moisture corrosion.

[0083] Based on the above embodiments, in one embodiment of this application, such as Figure 12 As shown, the trench 25 includes a first trench 251 and a second trench 252, which are opposite to each other. The first trench 251 extends along the first direction to the surface of the N-type layer 21, and the second trench 252 extends along the first direction to the surface of the substrate 10. Optionally, in this embodiment, the upper top width of the formed trench ranges from 15μm to 25μm, including the endpoint value; the lower bottom width of the trench ranges from 6μm to 12μm, including the endpoint value. However, this embodiment is not limited and depends on the specific circumstances.

[0084] Based on the above embodiments, in one embodiment of this application, the refractive index of the P-type layer is a first preset value, the refractive index of the insulating layer is a second preset value, and the second barrier layer includes a plurality of second sub-barrier layers arranged sequentially away from the substrate surface. The refractive index of the plurality of second sub-barrier layers gradually changes from the first preset value to the second preset value. This allows the refractive index of the film layers through which the light emitted from the active layer travels from the P-type layer to the insulating layer to gradually change, thereby causing the total internal reflection angle during light transmission to gradually change. This prevents the total internal reflection angle from remaining consistently large due to the significant difference in refractive indices between the P-type layer and the insulating layer, thus helping to suppress total internal reflection and improve light emissivity. It should be noted that when forming multiple sub-barrier layers with gradually changing refractive indices, the thickness of each sub-barrier layer also changes with the refractive index. Therefore, when forming multiple sub-barrier layers, it is necessary to calculate the thickness of each sub-barrier layer based on its respective refractive index using the principle of light transmission to obtain multiple sub-barrier layers with gradually changing refractive indices and thicknesses. It should also be noted that, in the embodiments of this application, the first barrier layer and the second barrier layer are formed in the same process step. The first barrier layer includes a plurality of sub-barrier layers, which are arranged sequentially along the side away from the substrate surface. The refractive index of the plurality of sub-barrier layers gradually changes from the first preset value to the second preset value. The thickness of the plurality of sub-barrier layers is also calculated using the principle of light transmission.

[0085] Specifically, in one embodiment of this application, the P-type layer is P-type GaN with a refractive index of 2.4, and the insulating layer is a SiO2 layer with a refractive index of approximately 1.5. Forming the second barrier layer includes: sequentially depositing multiple sub-barrier layers using a PECVD process, wherein the refractive index of these sub-barrier layers gradually decreases from 2.4 to 1.5. The thickness of each sub-barrier layer is calculated using the principle of light transmission based on its respective refractive index, resulting in a second barrier layer with gradually changing refractive index and thickness. The first barrier layer and the second barrier layer are formed in the same step using the same method, and will not be described further here. Optionally, in one embodiment of this application, the first barrier layer is SiO2. x Or SiN y The second barrier layer is SiO x Or SiN y The first barrier layer is SiO2, but this application's embodiments are not limited to this one; the specific method depends on the situation. x Or SiN y The second barrier layer is SiO x Or SiN y When the layers are in place, 0≤x≤2, 0≤y≤1. The refractive indices of the first and second barrier layers are controlled by adjusting the values ​​of x and y.

[0086] Optionally, in one embodiment of this application, the thickness of the first barrier layer ranges from [value missing]. Including endpoint values, the length of the portion of the first barrier layer extending to the surface of the epitaxial structure along the second direction ranges from 1 μm to 2 μm, including endpoint values; the thickness of the second barrier layer ranges from... The length of the portion of the second barrier layer extending to the surface of the epitaxial structure along the second direction, including the endpoint value, ranges from 1 μm to 2 μm. The second direction is parallel to the substrate surface, but this embodiment does not limit this; it depends on the specific circumstances. It should be noted that since the first barrier layer covers the area where the trench connects to the epitaxial structure, and the second barrier layer covers the area where the electrode pattern connects to the epitaxial structure, the transparent conductive layer can be designed to be relatively larger, extending outwards from the periphery of the mesa region, thus increasing the light-emitting area. In this embodiment, the length of the transparent conductive layer extending outwards from the periphery of the mesa region ranges from 0 to 1 μm, including the right endpoint value. However, this embodiment does not limit this; it depends on the specific circumstances.

[0087] Optionally, based on the above embodiments, in one embodiment of this application, the thickness of the transparent conductive layer ranges from [value missing]. Including endpoint values; the thickness of the metal layer ranges from 1.3 μm to 2.1 μm, including endpoint values; the thickness of the insulating layer ranges from... Endpoint values ​​are included, but the comparison of embodiments in this application is not limited and depends on the specific circumstances.

[0088] Based on the above embodiments, in one embodiment of this application, the thickness of the substrate is a preset thickness, and the high-voltage LED further includes a Bragg reflector layer located on the back side of the substrate.

[0089] In summary, this application provides a method for fabricating a high-voltage LED and a high-voltage LED. The method includes: providing a substrate; forming an epitaxial structure on the surface of the substrate; etching the epitaxial structure to form electrode patterns and trenches; forming a barrier layer, the barrier layer including a first barrier layer, a second barrier layer, and a third barrier layer; and sequentially forming a transparent conductive layer, a metal layer, and an insulating layer; wherein the first barrier layer covers the trench sidewalls and the exposed substrate surface of the trench, and extends along the trench sidewalls to the substrate surface, covering the surface of the epitaxial structure, such that the first barrier layer can cover the exposed P-type layer, the active layer, and the N-type layer on the trench sidewalls, and enclose the trench and the epitaxial structure. The second barrier layer covers the sidewalls of the etched trench of the electrode pattern and the exposed N-type layer surface of the etched trench of the electrode pattern, and extends along the sidewalls of the etched trench to the surface of the epitaxial structure, covering a portion of the surface of the epitaxial structure. This allows the second barrier layer to cover the exposed P-type layer, active layer, N-type layer and the exposed N-type layer surface of the etched trench of the electrode pattern, and to enclose the area where the etched trench of the electrode pattern meets the surface of the epitaxial structure, thus preventing the subsequently formed transparent conductive layer from contacting the exposed P-type layer, active layer and N-type layer of the etched trench. Therefore, before forming the transparent conductive layer, the high-voltage LED fabrication method provided in this application forms a first barrier layer covering the exposed P-type layer, active layer, and N-type layer of the trench, and a second barrier layer covering the exposed P-type layer, active layer, and N-type layer of the electrode pattern etching channel. This avoids contact between the subsequently formed transparent conductive layer and the exposed epitaxial structure of the electrode pattern etching channel and the exposed epitaxial structure of the trench. This eliminates the need to increase the exposure dose and thus the linewidth of the transparent conductive layer during its formation, preventing contact between the transparent conductive layer and the exposed epitaxial structure of the electrode pattern etching channel and the exposed epitaxial structure of the trench. This helps to reduce the linewidth during the formation of the transparent conductive layer, thereby helping to ensure the light-emitting area of ​​the high-voltage LED and improve the working performance of the fabricated high-voltage LED.

[0090] Furthermore, the manufacturing method includes forming an insulating layer that covers the first barrier layer, such that the passivation layer covering the trench includes the first barrier layer and the insulating layer covering the first barrier layer. This results in a thicker passivation layer covering the trench compared to the passivation layer thickness of the high-voltage LED trench produced by existing manufacturing methods. This helps to enhance the insulation coverage of the trench, thereby helping to suppress leakage current in the high-voltage LED, enhance the VF4 performance of the high-voltage LED, and the thicker passivation layer covering the trench also improves the high-voltage LED's resistance to moisture corrosion, helping to suppress aging of the high-voltage LED due to moisture corrosion.

[0091] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0092] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a high-voltage LED, characterized in that, include: Provide a substrate; An epitaxial structure is formed on the surface of the substrate, the epitaxial structure including an N-type layer, an active layer and a P-type layer arranged sequentially away from the surface of the substrate; The epitaxial structure is etched along a first direction to form an electrode pattern and a trench. The trench surrounds the electrode pattern, the etched trench of the electrode pattern exposes a portion of the surface of the N-type layer, and the trench exposes a portion of the surface of the substrate. The first direction is perpendicular to the surface of the substrate. A barrier layer is formed, the barrier layer including a first barrier layer, a second barrier layer and a third barrier layer, the first barrier layer covering the trench sidewall and the substrate surface exposed by the trench, and extending along the trench sidewall to the side of the epitaxial structure opposite to the substrate surface, covering a portion of the surface of the epitaxial structure opposite to the substrate surface. The second barrier layer covers the sidewall of the etched channel of the electrode pattern and the surface of the N-type layer exposed by the etched channel of the electrode pattern, and extends along the sidewall of the etched channel of the electrode pattern to the side of the epitaxial structure away from the substrate surface, covering a portion of the surface of the epitaxial structure away from the substrate surface. The third barrier layer covers a portion of the surface of the epitaxial structure away from the substrate surface, and the first barrier layer, the second barrier layer, and the third barrier layer are not in contact with each other; A transparent conductive layer is formed, which covers the side of the epitaxial structure away from the substrate surface, and covers the portion of the first barrier layer extending to the side of the epitaxial structure away from the substrate surface, the portion of the second barrier layer extending to the side of the epitaxial structure away from the substrate surface, and the third barrier layer. A metal layer is formed, which covers the second barrier layer and the portion of the transparent conductive layer corresponding to the third barrier layer; An insulating layer is formed, which covers the transparent conductive layer, the metal layer, and the first barrier layer; The first barrier layer and the second barrier layer include multiple sub-barrier layers, the refractive index of the P-type layer is a first preset value, and the refractive index of the insulating layer is a second preset value; Forming the second barrier layer includes: The plurality of sub-blocking layers are sequentially formed along a direction away from the substrate surface, and the refractive index of the plurality of sub-blocking layers gradually changes from a first preset value to a second preset value; The thickness of the sub-blocking layer is obtained based on the refractive index of each sub-blocking layer.

2. The manufacturing method according to claim 1, characterized in that, Etching the epitaxial structure along a first direction to form the trench includes: The epitaxial structure is etched along the first direction to form a first trench, and the first trench exposes a portion of the surface of the N-type layer. The N-type layer portion exposed by the first trench is etched along the first direction to form a second trench. The second trench exposes the surface of the substrate portion and corresponds to the first trench. The second trench and the first trench together constitute the trench.

3. The manufacturing method according to claim 1, characterized in that, The production method also includes: The back side of the substrate is ground to thin the substrate to a predetermined thickness; A Bragg reflective layer is formed on the back side of the substrate.

4. A high-voltage LED, characterized in that, The high-voltage LED is manufactured using the high-voltage LED manufacturing method according to any one of claims 1-3, wherein the high-voltage LED comprises: Substrate; An epitaxial structure located on the surface of the substrate includes an N-type layer, an active layer, and a P-type layer arranged sequentially along a side away from the surface of the substrate. Electrode patterns and trenches, the trenches surrounding the electrode patterns, the etched channels of the electrode patterns extending along a first direction to expose a portion of the surface of the N-type layer, the trenches extending along the first direction to expose a portion of the surface of the substrate, the first direction being perpendicular to the surface of the substrate; A barrier layer, comprising a first barrier layer, a second barrier layer, and a third barrier layer, wherein the first barrier layer covers the trench sidewalls and the substrate surface exposed by the trench, and extends along the trench sidewalls to the side of the epitaxial structure opposite to the substrate surface, covering a portion of the surface of the epitaxial structure opposite to the substrate surface; the second barrier layer covers the etched channel sidewalls of the electrode pattern and the N-type layer surface exposed by the etched channel of the electrode pattern, and extends along the etched channel sidewalls of the electrode pattern to the side of the epitaxial structure opposite to the substrate surface, covering a portion of the surface of the epitaxial structure opposite to the substrate surface; the third barrier layer covers a portion of the surface of the epitaxial structure opposite to the substrate surface, and the first barrier layer, the second barrier layer, and the third barrier layer are not connected to each other; A transparent conductive layer covers the side of the epitaxial structure away from the substrate surface, and covers the portion of the first barrier layer extending to the side of the epitaxial structure away from the substrate surface, the portion of the second barrier layer extending to the side of the epitaxial structure away from the substrate surface, and the third barrier layer. A metal layer that covers the second barrier layer and also covers the portion of the transparent conductive layer corresponding to the third barrier layer; An insulating layer covering the transparent conductive layer, the metal layer, and the first barrier layer; The second barrier layer includes multiple sub-barrier layers, the refractive index of the P-type layer is a first preset value, and the refractive index of the insulating layer is a second preset value; the second barrier layer includes multiple sub-barrier layers formed sequentially along a direction away from the substrate surface, and the refractive index of the multiple sub-barrier layers gradually changes from the first preset value to the second preset value; The thickness of the sub-blocking layer is obtained based on the refractive index of each sub-blocking layer.

5. The high-voltage LED according to claim 4, characterized in that, The trench includes a first trench and a second trench, the first trench and the second trench are opposite to each other, the first trench extends along the first direction to the N-type layer, exposing a portion of the surface of the N-type layer, and the second trench extends from the exposed portion of the N-type layer surface of the first trench to the substrate surface along the first direction.

6. The high-voltage LED according to claim 4, characterized in that, The thickness of the first barrier layer ranges from 3800 Å to 4500 Å, including the endpoints; the length of the portion of the first barrier layer extending to the surface of the epitaxial structure along the second direction ranges from 1 μm to 2 μm, including the endpoints; the second barrier layer is SiO. x Layer or SiN y The thickness of the second barrier layer ranges from 3800 Å to 4500 Å, including the endpoint values. The length of the portion of the second barrier layer extending to the surface of the epitaxial structure along the second direction ranges from 1 μm to 2 μm, including the endpoint values. The second direction is parallel to the surface of the substrate.

7. The high-voltage LED according to claim 4, characterized in that, The thickness of the transparent conductive layer ranges from 600 Å to 1100 Å, including the endpoints; the thickness of the metal layer ranges from 1.3 μm to 2.1 μm, including the endpoints; and the thickness of the insulating layer ranges from 1800 Å to 2500 Å, including the endpoints.

8. The high-voltage LED according to claim 4, characterized in that, The substrate has a preset thickness, and the high-voltage LED also includes: A Bragg reflective layer, which is located on the back side of the substrate.

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