Communication circuits and communication systems

Abstract

The present application discloses a communication circuit and a communication system, which includes a switching circuit, a charge and discharge circuit, an RS trigger circuit and an RS‑485 chip. Among them, the switching circuit can control the level of the set end of the RS trigger circuit based on the level of the signal sending end in the communication circuit. The RS trigger circuit can adjust the level of its output end based on the level of its set end and the level of the signal sending end to which the reset end is connected. Since the output end of the RS trigger circuit is connected to the receive enable pin and the transmit enable pin of the RS‑485 chip, the RS trigger circuit can switch the signal transceiver mode of the RS‑485 chip by adjusting the level of its output end. Since the solution provided by the present application does not require an MCU to switch the signal transceiver mode of the RS‑485 chip, the control efficiency of the RS‑485 chip is effectively improved and the control complexity of the RS‑485 chip is reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a communication circuit and a communication system. Background Art

[0002] Recommended Standard 485 (RS-485) is a differential signal transmission standard. Two devices in a communication system can implement differential signal transmission based on RS-485.

[0003] In related art, the two devices in the communication system both include a microcontroller unit (MCU) and an RS-485 chip. When the MCU in either device needs to send a signal, it can first control the transmit enable pin of the RS-485 chip to be valid, so that the RS-485 chip transmits the signal sent by the MCU to the RS-485 chip of the other device based on RS-485. When the MCU needs to receive a signal, it can control the receive enable pin of the RS-485 chip to be valid, so that the RS-485 chip can transmit the signal sent by the other device to the MCU.

[0004] However, the above communication method requires the MCU to control the valid states of the transmit enable pin and receive enable pin of the RS-485 chip, thereby controlling the RS-485 chip to send or receive signals. As a result, the control of the RS-485 chip is more complex and less efficient. Summary of the Invention

[0005] This application provides a communication circuit and communication system that can solve the problem of high complexity and low efficiency of MCU control of RS-485 chip in related technologies. The technical solution is as follows:

[0006] In one aspect, a communication circuit is provided, comprising a signal transmitting end and a signal receiving end, wherein the signal transmitting end and the signal receiving end are configured to connect to a communication chip, and wherein the communication circuit comprises: an RS-485 chip, a switch circuit, a charge and discharge circuit, and a reset and set RS trigger circuit;

[0007] The receiving pin of the RS-485 chip is connected to the signal receiving end, the transmitting pin of the RS-485 chip is connected to the signal transmitting end, the receiving enable pin and the transmitting enable pin of the RS-485 chip are respectively connected to the first power supply end and the output end of the RS trigger circuit, and the first transmission pin and the second transmission pin of the RS-485 chip are both used to connect to the communication bus;

[0008] The control end of the switch circuit is connected to the signal transmitting end, the first end of the switch circuit is connected to the first power supply end and the charge-discharge circuit respectively, and the second end of the switch circuit and the charge-discharge circuit are both connected to the ground end. The switch circuit is configured to disconnect the first end from the second end if the level of the signal transmitting end is a first level, so that the first power supply end charges the charge-discharge circuit, and connect the first end to the second end if the level of the signal transmitting end is a second level, wherein the second level is a higher level than the first level.

[0009] The charge-discharge circuit is further connected to the set terminal of the RS trigger circuit, and is configured to maintain the level of the set terminal at the second level after charging, and discharge through the switch circuit after the first terminal and the second terminal are connected, and maintain the level of the set terminal at the second level during the discharge process;

[0010] The reset terminal of the RS trigger circuit is connected to the signal sending terminal, and the RS trigger circuit is used to adjust the level of the output terminal based on the level of the set terminal and the level of the reset terminal;

[0011] The effective level of the receive enable pin is the first level, and the effective level of the transmit enable pin is the second level.

[0012] Optionally, the switching circuit includes: a switching transistor;

[0013] The gate of the switching transistor is connected to the signal sending end as the control end, the first electrode of the switching transistor is connected to the first power supply end and the charging and discharging circuit as the first end, and the second electrode of the switching transistor is connected to the ground end and the charging and discharging circuit as the second end.

[0014] Optionally, the switching transistor is an N-type metal oxide semiconductor (MOS) transistor.

[0015] Optionally, the charging and discharging circuit includes: a first diode, a first resistor and a capacitor;

[0016] The anode of the first diode is connected to the first power supply terminal, the first terminal of the switch circuit, and one terminal of the first resistor, respectively; the cathode of the first diode is connected to the set terminal of the RS trigger circuit, the other terminal of the first resistor, and one terminal of the capacitor, respectively;

[0017] The other end of the capacitor is connected to the second end of the switch circuit and the ground end respectively.

[0018] Optionally, the communication circuit further includes: a current limiting circuit;

[0019] The current limiting circuit is respectively connected to the first power supply end, the receive enable pin, the transmit enable pin, the transmit pin, the first end of the switch circuit, the reset end of the RS trigger circuit and the charge and discharge circuit. The current limiting circuit is used to limit the current of the signal from the first power supply end and transmit it to the switch circuit, the charge and discharge circuit, the receive enable pin and the transmit enable pin respectively, and to limit the current of the signal from the signal transmitting end and transmit it to the reset end and the transmit pin respectively.

[0020] Optionally, the current limiting circuit includes: a second resistor, a third resistor and a fourth resistor;

[0021] One end of the second resistor is connected to the first end of the switch circuit and the charge-discharge circuit respectively, the other end of the second resistor is connected to the first power supply terminal and one end of the third resistor respectively, and the other end of the third resistor is connected to the receive enable pin and the transmit enable pin respectively;

[0022] One end of the fourth resistor is connected to the signal sending end, and the other end of the fourth resistor is connected to the reset end of the RS trigger circuit and the sending pin respectively.

[0023] Optionally, the communication circuit further includes: a matching circuit;

[0024] The matching circuit is respectively connected to the second power supply terminal, the ground terminal, the first transmission pin and the second transmission pin. The matching circuit is used to pull up the level of the first transmission pin to the third level and pull down the level of the second transmission pin to the fourth level under the drive of the second power supply terminal and the ground terminal.

[0025] Optionally, the matching circuit includes: a fifth resistor and a sixth resistor;

[0026] One end of the fifth resistor is connected to the second power supply end, and the other end of the fifth resistor is connected to the first transmission pin;

[0027] One end of the sixth resistor is connected to the second transmission pin, and the other end of the sixth resistor is connected to the ground end.

[0028] Optionally, the matching circuit further includes: a seventh resistor;

[0029] One end of the seventh resistor is connected to the first transmission pin, and the other end of the seventh resistor is connected to the second transmission pin.

[0030] Optionally, the RS trigger circuit includes: a set subcircuit and a reset subcircuit, the set subcircuit is connected to the set terminal and the output terminal respectively, and the reset subcircuit is connected to the reset terminal and the output terminal respectively;

[0031] The setting subcircuit includes: a second diode, a third diode, a fourth diode, an eighth resistor, a ninth resistor, a tenth resistor, a first transistor and a second transistor;

[0032] The reset subcircuit includes: a fifth diode, a sixth diode, a seventh diode, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a third transistor and a fourth transistor.

[0033] In another aspect, a communication system is provided, comprising: a communication bus, a first device and a second device;

[0034] The first device includes: a first communication chip and a first communication circuit, wherein the first communication chip is connected to a signal transmitting end and a signal receiving end of the first communication circuit respectively;

[0035] The second device includes: a second communication chip and a second communication circuit, the second communication chip being connected to a signal transmitting end and a signal receiving end of the second communication circuit respectively;

[0036] One end of the communication bus is connected to the first transmission pin and the second transmission pin of the RS-485 chip in the first communication circuit, and the other end of the communication bus is connected to the first transmission pin and the second transmission pin of the RS-485 chip in the second communication circuit;

[0037] Wherein, the first communication circuit and the second communication circuit are both the communication circuits described in the above aspects.

[0038] The beneficial effects of the technical solution provided by this application include at least:

[0039] The present application provides a kind of communication circuit and communication system, and the communication circuit includes a switching circuit, a charge and discharge circuit, an RS trigger circuit and an RS-485 chip.Wherein, the switching circuit can control the level of the set end of the RS trigger circuit based on the level of the signal transmitting end in the communication circuit.The RS trigger circuit can adjust the level of its output end based on the level of its set end and the level of the signal transmitting end to which the reset end is connected.Since the output end of the RS trigger circuit is connected to the receiving enable pin and the transmitting enable pin of the RS-485 chip, the RS trigger circuit can realize the switching of the signal transceiver mode of the RS-485 chip by adjusting the level of its output end.Since the solution provided by the present application does not require an MCU to switch the signal transceiver mode of the RS-485 chip, the control efficiency of the RS-485 chip is effectively improved, and the control complexity of the RS-485 chip is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 This is a schematic diagram of the structure of a communication system provided by an embodiment of the present application;

[0042] Figure 2 This is a schematic diagram of the structure of a communication circuit provided in an embodiment of the present application;

[0043] Figure 3 is a structural diagram of another communication circuit provided in an embodiment of the present application;

[0044] Figure 4 This is a schematic diagram of the structure of an RS trigger circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic diagram of the structure of a communication system provided in an embodiment of the present application, see Figure 1 The communication system includes: a communication bus, a first device 10 and a second device 20.

[0047] The first device 10 includes a first communication chip U1 and a first communication circuit 11. The first communication chip U1 is connected to a signal transmitting terminal TX1 and a signal receiving terminal RX1 of the first communication circuit 11 respectively.

[0048] The second device 20 includes: a second communication chip U2 and a second communication circuit 12 , wherein the second communication chip U2 is connected to a signal transmitting terminal TX2 and a signal receiving terminal RX2 of the second communication circuit 12 .

[0049] The communication bus is an RS-485 communication bus, which includes a first communication bus L1 and a second communication bus L2. The first communication bus L1 is connected to the first transmission pin A1 of the RS-485 chip 111 in the first communication circuit 11 and the first transmission pin A2 of the RS-485 chip 121 in the second communication circuit 12, respectively. The second communication bus L2 is connected to the second transmission pin B1 of the RS-485 chip 111 in the first communication circuit 11 and the second transmission pin B2 of the RS-485 chip 121 in the second communication circuit 12, respectively.

[0050] In the embodiments of the present application, the first device 10 and the second device 20 can be two devices in the same electronic device. Alternatively, the first device 10 and the second device 20 can be two devices in different electronic devices. In other words, the communication system provided in the embodiments of the present application can implement communication between two devices in the same electronic device, or can implement communication between different electronic devices.

[0051] It is understood that each of the first communication circuit 11 and the second communication circuit 12 has the function of both receiving and transmitting signals. That is, the first communication chip U1 in the first device 10 can receive signals from the second device 20 via the first communication circuit 11 and can transmit signals to the second device 20 via the first communication circuit 11. Similarly, the second communication chip U2 in the second device can receive signals from the first device 10 via the second communication circuit 12 and can transmit signals to the first device 10 via the second communication circuit 12.

[0052] The first communication chip U1 in the first device 10 and the second communication chip U2 in the second device 20 may be integrated circuits (ICs) in electronic devices capable of communicating via an RS-485 bus. For example, the first communication chip U1 and the second communication chip U2 may both be MCUs.

[0053] Figure 2 This is a schematic diagram of the structure of a communication circuit provided in an embodiment of the present application. The communication circuit can be applied to Figure 1In the communication system shown, for example, the communication circuit can be Figure 1 The first communication circuit 11 or the second communication circuit 12 in the communication system shown. Figure 2 The communication circuit has a signal transmitting terminal TX and a signal receiving terminal RX. The signal transmitting terminal TX and the signal receiving terminal RX are used to connect to the communication chip. The communication circuit includes: an RS-485 chip 110, a switch circuit 120, a charge and discharge circuit 130, and an RS trigger circuit 140.

[0054] The receiving pin R of the RS-485 chip 110 is connected to the signal receiving end RX, the transmitting pin D of the RS-485 chip is connected to the signal transmitting end TX, and the receiving enable pin of the RS-485 chip 110 is connected to the signal receiving end RX. and the sending enable pin DE are respectively connected to the first power supply terminal V1 and the output terminal P_Q of the RS trigger circuit 140, the first transmission pin A and the second transmission pin B of the RS-485 chip 110 are both used to connect to the communication bus, the power pin of the RS-485 chip 110 is connected to the power supply terminal VCC, and the ground pin of the RS-485 chip 110 is connected to the ground terminal GND.

[0055] The RS-485 chip 110 is used to: If the receiving enable pin is a valid level, the signal of the first transmission pin A and the second transmission pin B is transmitted to the receiving pin R, and if the level of the transmission enable pin DE is a valid level, the signal of the transmission pin D is transmitted to the first transmission pin A and the second transmission pin B.

[0056] Among them, the receive enable pin The effective level of the transmission enable pin DE is a first level, and the effective level of the transmission enable pin DE is a second level, which is a higher level than the first level. For example, the first level may be a level with an amplitude of 0 volts (i.e., a low level), and the second level may be a level with an amplitude of the voltage of the first power supply terminal V1 (i.e., a high level).

[0057] In the embodiment of the present application, the signal transmitted by the first transmission pin A and the second transmission pin B is a differential signal. When the level is at a valid level, the RS-485 chip 110 operates in receive mode and can receive the differential signal on the communication bus through the first transmission pin A and the second transmission pin B. Subsequently, the RS-485 chip 110 can convert the differential signal on the first transmission pin A and the second transmission pin B into a single-ended signal (also called a level signal) and output it to the receive pin R. The receive pin R can then transmit the single-ended signal to the communication chip through the signal receiving terminal RX.

[0058] When the transmit enable pin DE of the RS-485 chip 110 is at an active level, the RS-485 chip 110 operates in transmit mode and can receive a single-ended signal from the signal transmitting end TX via the transmit pin D. The RS-485 chip 110 then converts the single-ended signal into a differential signal and outputs it to the first transmission pin A and the second transmission pin B.

[0059] Based on the above analysis, it can be seen that by controlling the receive enable pin of the RS-485 chip 110 and the level of the transmit enable pin DE can switch the working mode of the RS-485 chip 110, thereby realizing signal sending and receiving.

[0060] Continue to refer Figure 2 The control terminal C of the switch circuit 120 is connected to the signal transmitting terminal TX. The first terminal 1 of the switch circuit 120 is connected to the first power terminal V1 and the charge-discharge circuit 130, respectively. The second terminal 2 of the switch circuit 120 and the charge-discharge circuit 130 are both connected to the ground terminal GND. The switch circuit 120 is configured to disconnect the first terminal 1 from the second terminal 2 when the level of the signal transmitting terminal TX is a first level, thereby allowing the first power terminal V1 to charge the charge-discharge circuit 130. The switch circuit 120 is configured to connect the first terminal 1 to the second terminal 2 when the level of the signal transmitting terminal TX is a second level.

[0061] like Figure 2 As shown, the charge-discharge circuit 130 is also connected to the set terminal P_S of the RS trigger circuit 140. The charge-discharge circuit 130 is configured to maintain the level of the set terminal P_S at the second level after charging, and to discharge through the switch circuit 120 after the first terminal 1 and the second terminal 2 of the switch circuit 120 are conductive, and to maintain the level of the set terminal P_S at the second level during the discharge process.

[0062] The reset terminal P_R of the RS trigger circuit 140 is connected to the signal transmitting terminal TX. The RS trigger circuit 140 is configured to adjust the level of its output terminal P_Q based on the level of its set terminal P_S and the level of its reset terminal P_R. If the level of the set terminal P_S of the RS trigger circuit 140 is a first level, the level of the output terminal P_Q is controlled to be the first level. If the level of the set terminal P_S is a second level and the level of the reset terminal P_R is the first level, the level of the output terminal P_Q is controlled to be the second level.

[0063] Table 1

[0064]

[0065] Table 1 is a truth table of the RS trigger circuit 140. In the truth table, the value "1" indicates a high level (ie, the second level), and the value "0" indicates a low level (ie, the first level).n represents the level of the output terminal P_Q of the RS trigger circuit 140 at the previous moment, that is, the level before the transition. n+1 represents the current level of the output terminal P_Q of the RS trigger circuit 140, that is, the level after the transition.

[0066] In the embodiment of the present application, the default levels of the signal transmitting terminal TX and the signal receiving terminal RX of the communication circuit are both the second level. In this case, the first terminal 1 and the second terminal 2 of the switch circuit 120 are turned on, and the charge and discharge circuit 130 can make the level of the set terminal P_S of the RS trigger circuit 140 the first level. Since the level of the reset terminal P_R of the RS trigger circuit 140 is the second level, as shown in Table 1, the level of the output terminal P_Q of the RS trigger circuit 140 is the same as the level of the set terminal P_S, which is also the first level. At this time, since the receive enable pin of the RS-485 chip 110 is a valid level, so the RS-485 chip 110 can convert the differential signal received by the first transmission pin A and the second transmission pin B into a single-ended signal and output it to the receiving pin R. Based on the above analysis, it can be seen that the RS-485 chip 110 works in the receiving mode by default.

[0067] When the communication chip sends a signal through the RS-485 chip 110, the RS-485 chip 110 needs to be converted from the default working mode (i.e., receiving mode) to the sending mode. It is understandable that the amount of data transmitted by the communication chip each time can be fixed, for example, 10 bits of data can be transmitted each time. In addition, the level of the start bit of the data transmitted each time is defaulted to a low level (i.e., the first level). Thus, each time the communication chip sends data through the RS-485 chip, the level of the signal transmitting end TX will jump from a high level (i.e., the second level) to a low level (i.e., the first level). At this time, the switch circuit 120 can disconnect the first end 1 from the second end 2 so that the first power supply end V1 charges the charge and discharge circuit 130.

[0068] After charging, the charge-discharge circuit 130 can maintain the level of the set terminal P_S at the second level (i.e., a high level). Based on the truth table shown in Table 1, it can be seen that when the set terminal P_S of the RS trigger circuit 140 is at the second level and the reset terminal P_R is at the first level, the level of the output terminal P_Q of the RS trigger circuit 140 will jump from the default first level to the second level. At this time, since the transmit enable pin DE of the RS-485 chip 110 is at a valid level, the RS-485 chip 110 can automatically switch from the default receive mode to the transmit mode, and can transmit the start bit of the data received at the transmit pin D to the first transmission pin A and the second transmission pin B.

[0069] When the communication chip transmits data to the signal transmitting terminal TX via the RS-485 chip 110, if the level of the transmitted data is low, the signal transmitting terminal TX is at a low level. Referring to the above-described start bit transmission process, it can be seen that the transmit enable pin DE of the RS-485 chip 110 can maintain a valid level, and the RS-485 chip 110 can transmit the low-level data received at the transmit pin D to the first transmission pin A and the second transmission pin B.

[0070] If the level of the data sent by the communication chip is high, the signal transmitting terminal TX is high (i.e., the second level), and the reset terminal P_R of the RS trigger circuit 140 is also high. At this time, the switch circuit 120 can conduct the first terminal 1 and the second terminal 2, thereby causing the RS trigger circuit 140 to discharge through the switch circuit 120, and during the discharge process, the level of the set terminal P_S can be maintained at the second level. Based on the truth table shown in Table 1, it can be seen that when the levels of the set terminal P_S, the reset terminal P_R, and the output terminal P_Q of the RS trigger circuit 140 are all at the second level at the previous moment, the first power supply terminal V1 can enable the sending enable pin DE and the receiving enable pin of the RS-485 chip 110. That is, the transmission enable pin DE of the RS-485 chip 110 is still at a valid level, and the RS-485 chip 110 is still working in the transmission mode.

[0071] After the communication chip has sent the data, the level of the signal transmitting end TX can be restored to the default second level. At this time, the reset end P_R of the RS trigger circuit 140 is at the second level. Since the switch circuit 120 has completed the discharge, the set end P_S of the RS trigger circuit 140 is at the first level. At this time, based on the truth table of the RS trigger circuit 140 shown in Table 1, it can be seen that the level of the output end P_Q of the RS trigger circuit 140 is the same as the level of the set end P_S, that is, it will jump from the second level to the first level. At this time, due to the receive enable pin of the RS-485 chip 110 is a valid level, so the RS-485 chip 110 can automatically switch from the sending mode to the receiving mode.

[0072] In an embodiment of the present application, the discharge duration of the charge-discharge circuit 130 can be set based on the duration required for the communication chip to send data each time through the RS-485 chip 110. For example, the discharge duration can be greater than or equal to the duration of each data transmission by the communication chip through the RS-485 chip 110. Thus, it can be ensured that during the data transmission process, the set terminal P_S of the RS trigger circuit 140 can maintain the second level so that the transmission enable pin DE of the RS-485 chip 110 remains at a valid level. After the charge-discharge circuit 130 is discharged, the level of the set terminal P_S of the RS trigger circuit 140 will drop to the first level.

[0073] It is understandable that the RS-485 chip 110 receives the enable pin by controlling the RS trigger circuit 140. The RS trigger circuit 140 can also act as a data holder to stabilize the receiving enable pin DE of the RS-485 chip 110. In addition, the level of the output terminal P_Q of the RS trigger circuit 140 is changed to control the receiving enable pin of the RS-485 chip 110. The level of the transmission enable pin DE can avoid packet loss when the RS-485 chip 110 transmits and receives signals when the switching rate of the switching circuit 120 is too high.

[0074] It is also understood that the charging and discharging circuit 130 and the RS trigger circuit 140 are provided between the switch circuit 120 and the RS-485 chip 110, which can improve the switching delay caused by the on-off state change of the switch circuit 120. In addition, the receiving enable pin of the RS-485 chip 110 can be ensured. The level of the transmission enable pin DE can be switched to the corresponding valid level in time to ensure the reliability of the RS-485 chip 110 in sending and receiving signals.

[0075] In summary, the present application embodiment provides a kind of communication circuit, and this communication circuit includes a switching circuit, a charge and discharge circuit, an RS trigger circuit and an RS-485 chip.Wherein, this switching circuit can control the level of the set end of the RS trigger circuit based on the level of the signal transmitting end in the communication circuit.This RS trigger circuit can adjust the level of its output end based on the level of its set end and the level of the signal transmitting end to which the reset end is connected.Because the output end of this RS trigger circuit is connected with the receiving enable pin and the transmitting enable pin of RS-485 chip, therefore RS trigger circuit can realize the switching of the signal transceiver mode of RS-485 chip by adjusting the level of its output end.Because the scheme provided by the embodiment of the present application does not need MCU to switch the signal transceiver mode of RS-485 chip, thus effectively improving the control efficiency of RS-485 chip, and reducing the control complexity of RS-485 chip.

[0076] Figure 3 This is a schematic diagram of another communication circuit provided in an embodiment of the present application. Figure 3 The switching circuit 120 may include a switching transistor Q1. The gate (Gate, G) of the switching transistor Q1 serves as a control terminal C and is connected to the signal transmitting terminal TX. The first electrode of the switching transistor Q1 serves as a first terminal 1 and is respectively connected to the first power supply terminal V1 and the charge-discharge circuit 130. The second electrode of the switching transistor Q1 serves as a second terminal 2 and is respectively connected to the ground terminal GND and the charge-discharge circuit 130.

[0077] The switch transistor Q1 may be an N-type MOS transistor, a first electrode of the switch transistor Q1 may be a drain (Drain, D), and a second electrode of the switch transistor Q1 may be a source (Source, S).

[0078] It is understood that when the signal transmitting terminal TX is at the first level, the voltage of the gate G of the switching transistor Q1 is less than or equal to the voltage of its source S, and the switching transistor Q1 is in the off state. At this time, the first power supply terminal V1 can charge the charging and discharging circuit 130.

[0079] When the signal transmitting terminal TX is at the second level, the voltage at the gate G of the switching transistor Q1 is greater than the voltage at its source S. Accordingly, the voltage between the gate G and source S of the switching transistor Q1 is greater than the threshold voltage of the switching transistor Q1, and the drain D and source S of the switching transistor Q1 are conductive. As a result, the voltage at the drain D of the switching transistor Q1 is pulled down to the first level by the ground terminal GND. In other words, the voltage at the first terminal 1 of the switching circuit 120 is pulled down to the first level by the ground terminal GND.

[0080] Continue to refer Figure 3The charge-discharge circuit 130 may include: a first diode D1, a first resistor R1, and a capacitor C1. The anode of the first diode D1 is connected to the first power supply terminal V1, the first terminal 1 of the switch circuit 120, and one end of the first resistor R1, respectively. The cathode of the first diode D1 is connected to the set terminal P_S of the RS trigger circuit 140, the other end of the first resistor R1, and one end of the capacitor C1, respectively. The other end of the capacitor C1 is connected to the second terminal 2 of the switch circuit 120 and the ground terminal GND, respectively.

[0081] When the switch transistor Q1 in the switch circuit 120 is off, the first power terminal V1 can charge the capacitor C1 through the first resistor R1. After the capacitor C1 is charged, the terminal of the capacitor C1 connected to the set terminal P_S is at a high level (ie, a second level).

[0082] When the switching transistor Q1 in the switching circuit 120 is in the on state, based on the unidirectional conductivity of the first diode D1, it can be seen that the first diode D1 is in the off state. Therefore, the capacitor C1 can be discharged through the first resistor R1 and the on-state switching transistor Q1. Furthermore, during the discharge process of the capacitor C1, the capacitor C1 can maintain the level of the set terminal P_S of the RS trigger circuit 140 at the second level.

[0083] It is understandable that the driving capability of the switch transistor Q1 is relatively weak. If the receive enable pin of the RS-485 chip 110 is directly controlled by the switch transistor Q1 and the level of the transmit enable pin DE, the RS-485 chip 110 will have a weak ability to transmit and receive signals, and the received or transmitted signals cannot be transmitted over long distances. In the embodiment of the present application, since the RS trigger circuit 140 has the ability to retain data and has a strong driving capability, a charge and discharge circuit 130 and an RS trigger circuit 140 are set between the switch transistor Q1 and the RS-485 chip 110, and the receive enable pin of the RS-485 chip 110 is controlled by the output terminal P_Q of the RS trigger circuit 140. and the level of the send enable pin DE, thereby driving the RS-485 chip 110 to send and receive signals with a stronger driving capability, so as to achieve long-distance transmission of signals.

[0084] Optionally, continue to refer to Figure 3 The communication circuit may further include: a current limiting circuit 150. The current limiting circuit 150 is respectively connected to the first power supply terminal V1 and the receiving enable pin The transmission enable pin DE, the transmission pin D, the first terminal 1 of the switch circuit 120 , the reset terminal P_R of the RS trigger circuit 140 , and the charge and discharge circuit 130 are connected.

[0085] In the embodiment of the present application, the current limiting circuit 150 is used to limit the current of the signal of the first power supply terminal V1 and transmit it to the switch circuit 120, the charge and discharge circuit 130, the receiving enable pin 110 and the like. and a transmission enable pin DE, and is used to limit the current of the signal at the signal transmitting end TX and transmit it to the reset end P_R of the RS trigger circuit 140 and the transmission pin D of the RS-485 chip 110 respectively.

[0086] like Figure 3 As shown, the current limiting circuit 150 may include: a second resistor R2, a third resistor R3 and a fourth resistor R4. One end of the second resistor R2 is connected to the first terminal 1 of the switch circuit 120 and the charge and discharge circuit 130 respectively, and the other end of the second resistor R2 is connected to the first power supply terminal V1 and one end of the third resistor R3 respectively. The other end of the third resistor R3 is connected to the receive enable pin of the RS-485 chip 110. One end of the fourth resistor R4 is connected to the signal transmitting terminal TX, and the other end of the fourth resistor R4 is connected to the reset terminal P_R of the RS trigger circuit 140 and the transmitting pin D of the RS-485 chip 110 respectively.

[0087] In the embodiment of the present application, the second resistor R2 is used to limit the current of the signal at the first power supply terminal V1 and transmit it to the drain D of the switching transistor Q1 and the capacitor C1 respectively, so as to prevent the performance of the switching transistor Q1 and the capacitor C1 from being damaged when the signal at the first power supply terminal V1 is too large. The third resistor R3 is used to limit the current of the signal at the first power supply terminal V1 and transmit it to the receive enable pin of the RS-485 chip 110 respectively. and the transmission enable pin DE, thereby preventing the performance of the RS-485 chip 110 from being damaged.

[0088] Optionally, the second resistor R2 can also be used to: if the first terminal 1 and the second terminal 2 of the switch circuit 120 are turned off, then under the drive of the first power supply terminal V1, pull up the level of the set terminal P_S of the RS trigger circuit 140 to the second level. The third resistor R3 can also be used to: if the first terminal 1 and the second terminal 2 of the switch circuit 120 are turned off and the output level of the RS trigger circuit 140 is uncertain, under the drive of the first power supply terminal V1, pull up the receive enable pin of the RS-485 chip 110 to the second level. and the transmission enable pin DE are pulled up to the second level.

[0089] The fourth resistor R4 is used to limit the current of the signal at the signal transmitting terminal TX before transmitting it to the reset terminal P_R of the RS trigger circuit 140 and the transmit pin D of the RS-485 chip 110, further preventing the performance of the RS-485 chip 110 from being damaged when the signal at the signal transmitting terminal TX is too large. In addition, the fourth resistor R4 can also delay the signal at the signal transmitting terminal TX to ensure that the level of the transmit enable terminal DE of the RS-485 chip 110 has jumped to a valid level when the signal at the signal transmitting terminal TX is transmitted to the transmit pin D of the RS-485 chip 110.

[0090] Alternatively, as Figure 3 As shown, the communication circuit may further include a matching circuit 160. The matching circuit 160 is connected to the second power supply terminal V2, the ground terminal GND, the first transmission pin A and the second transmission pin B respectively.

[0091] In the embodiment of the present application, the matching circuit 160 is configured to pull the voltage level of the first transmission pin A up to a third level and pull the voltage level of the second transmission pin B down to a fourth level, driven by the second power supply terminal V2 and the ground terminal GND. The third level is greater than the fourth level, i.e., the third level is higher than the fourth level. Furthermore, the voltage difference between the third and fourth levels should be greater than the threshold level of the RS-485 chip (typically ±200 millivolts).

[0092] The second power supply terminal V2 and the first power supply terminal V1 are both DC power supplies in the communication system, and the DC voltages of the second power supply terminal V2 and the first power supply terminal V1 can be set according to the communication requirements.

[0093] refer to Figure 3 The matching circuit 160 may include a fifth resistor R5 and a sixth resistor R6. One end of the fifth resistor R5 is connected to the second power supply terminal V2, and the other end of the fifth resistor R5 is connected to the first transmission pin A. One end of the sixth resistor R6 is connected to the second transmission pin B, and the other end of the sixth resistor R6 is connected to the ground terminal GND.

[0094] It is understood that when the RS-485 communication bus is in an open or idle state (i.e., when no signal is transmitted on the RS-485 communication bus), the differential voltage between the two buses in the RS-485 communication bus may be 0. At this time, the RS-485 communication bus is in an uncertain state, and the communication state of the RS-485 chip 110 is easily interfered with by external factors.

[0095] In the embodiment of the present application, the matching circuit 160 allows the fifth resistor R5, driven by the second power supply terminal V2, to pull up the voltage level of the first transmission pin A to the third voltage level, and allows the sixth resistor R6, driven by the ground terminal GND, to pull down the voltage level of the second transmission pin B to the fourth voltage level. Thus, when the RS-485 communication bus is in an open or idle state, the differential voltage between the RS-485 communication buses is not zero and remains stable, thereby preventing external factors from interfering with the communication state of the RS-485 chip 110.

[0096] Continue to refer Figure 3 The matching circuit 160 may further include a seventh resistor R7. One end of the seventh resistor R7 is connected to the first transmission pin A, and the other end of the seventh resistor R7 is connected to the second transmission pin B.

[0097] Among them, the seventh resistor R7 can be used as a terminal resistor to match the characteristic impedance of the RS-485 communication bus to avoid signal reflection in the RS-485 communication bus during the communication process between the first device 10 and the second device 20, thereby improving the communication quality of the communication system.

[0098] Figure 4 This is a schematic diagram of the structure of an RS trigger circuit 140 provided in an embodiment of the present application, with reference to Figure 4 , the RS trigger circuit 140 may include a set sub-circuit 141 and a reset sub-circuit 142 .

[0099] like Figure 4 As shown, the setting sub-circuit 141 includes: a second diode D2, a third diode D3, a fourth diode D4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first transistor T1 and a second transistor T2.

[0100] The cathode of the second diode D2 is connected to the set terminal P_S of the RS trigger circuit 140, and the anode of the second diode D2 is respectively connected to one end of the eighth resistor R8, the anode of the third diode D3, and the anode of the fourth diode D4. The cathode of the fourth diode D4 is connected to the output terminal P_Q of the RS trigger circuit 140, and the cathode of the third diode D3 is connected to the base of the first transistor T1. The collector of the first transistor T1 is respectively connected to the first power supply terminal V1, the other end of the eighth resistor R8, and one end of the ninth resistor R9. The other end of the ninth resistor R9 is respectively connected to the collector of the second transistor T2 and the output terminal P_Q of the RS trigger circuit 140. The emitter of the first transistor T1 is respectively connected to the base of the second transistor T2 and one end of the tenth resistor R10. The other end of the tenth resistor R10 is respectively connected to the emitter of the second diode T2 and the ground terminal GND.

[0101] Continue to refer Figure 4 The reset sub-circuit 142 may include: a fifth diode D5, a sixth diode D6, a seventh diode D7, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a third transistor T3, and a fourth transistor T4.

[0102] The cathode of the fifth diode D5 is connected to the collector of the second transistor T2. The anode of the fifth diode D5 is connected to one end of the eleventh resistor R11, the anode of the sixth diode D6, and the anode of the seventh diode D7. The cathode of the seventh diode D7 is connected to the reset terminal P_R of the RS trigger circuit 140, and the cathode of the sixth diode D6 is connected to the base of the third transistor T3. The collector of the third transistor T3 is connected to the third power supply terminal V3, the other end of the eleventh resistor R11, and one end of the twelfth resistor R12. The other end of the twelfth resistor R12 is connected to the collector of the fourth transistor T4 and the output terminal P_Q of the RS trigger circuit 140. The emitter of the third transistor T3 is connected to the base of the fourth transistor T4 and one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to the emitter of the fourth transistor T4 and the ground terminal GND.

[0103] It can be understood that the RS trigger circuit 140 uses two NAND gates to achieve state transitions of its set terminal P_S, reset terminal P_R, and output terminal P_Q. The second diode D2 and the fourth diode D4 in the set subcircuit 141 form an AND gate, and the first transistor T1 and the second transistor T2 form a NOT gate. The fifth diode D5 and the seventh diode D7 in the reset subcircuit 142 form an AND gate, and the third transistor T3 and the fourth transistor T4 form a NOT gate. Optionally, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can all be NPN transistors.

[0104] In this embodiment of the present application, the NAND gate in the set subcircuit 141 receives as input the voltage level at the set terminal P_S and the voltage level at the output terminal P_Q of the RS flip-flop circuit 140, and outputs the voltage level at the collector of the second transistor T2. The operating principle of the set subcircuit 141 is as follows: the voltage level at the set terminal P_S and the voltage level at the output terminal P_Q of the RS flip-flop circuit 140 are ANDed together through the AND gate formed by the second diode D2 and the fourth diode D4, and then NOTed together through the NOT gate formed by the first transistor T1 and the second transistor T2. The voltage level at the collector of the second transistor T2 is the output of the set subcircuit 141, i.e., the NAND result.

[0105] The NAND gate in reset subcircuit 142 receives the NAND result from set subcircuit 141 and the level at reset terminal P_R as input, and its output is the level at output terminal P_Q of RS flip-flop circuit 140. The operating principle of reset subcircuit 142 is as follows: the level at reset terminal P_R of RS flip-flop circuit 140 and the NAND result from set subcircuit 141 are ANDed together through an AND gate formed by a fifth diode D5 and a seventh diode D7, and then NOTed together through a NOT gate formed by a third transistor T3 and a fourth transistor T4. The level at the collector of fourth transistor T4 is the output of reset subcircuit 142, i.e., the NAND result.

[0106] In Table 1, the set terminal P_S and the reset terminal P_R of the RS trigger circuit 140 are both at the second level, and the level of the output terminal P_Q at a moment (ie, P_Q n ) is at the first level, P_Q of the RS trigger circuit 140 n+1 The true value is uncertain. When P_Q n When the true value is "0" (that is, the RS-485 chip 110 is working in the receiving mode at the last moment), if the communication chip wants to send data through the RS-485 chip, the level of the set terminal P_S of the RS trigger circuit 140 is set to the first level. Since the starting bit of the data sent by the communication chip each time is the first level by default, the level of the reset terminal P_R connected to the signal transmitting terminal TX is also the first level. It can be seen that in the embodiment of the present application, the true value of the set terminal P_S and the reset terminal P_R as shown in Table 1 will not be "1", and P_Q n The true value of is "0".

[0107] In summary, the present application embodiment provides a kind of communication circuit, and this communication circuit includes a switching circuit, a charge and discharge circuit, an RS trigger circuit and an RS-485 chip.Wherein, this switching circuit can control the level of the set end of the RS trigger circuit based on the level of the signal transmitting end in the communication circuit.This RS trigger circuit can adjust the level of its output end based on the level of its set end and the level of the signal transmitting end to which the reset end is connected.Because the output end of this RS trigger circuit is connected with the receiving enable pin and the transmitting enable pin of RS-485 chip, therefore RS trigger circuit can realize the switching of the signal transceiver mode of RS-485 chip by adjusting the level of its output end.Because the scheme provided by the embodiment of the present application does not need MCU to switch the signal transceiver mode of RS-485 chip, thus effectively improving the control efficiency of RS-485 chip, and reducing the control complexity of RS-485 chip.

[0108] In this application, the terms "first", "second", etc. are used to distinguish identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on the quantity and execution order.

[0109] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A communication circuit, characterized in that: The communication circuit has a signal transmitting end (TX) and a signal receiving end (RX), the signal transmitting end (TX) and the signal receiving end (RX) are used to connect to a communication chip, and the communication circuit includes: an RS-485 chip (110), a switch circuit (120), a charge and discharge circuit (130) and a reset RS trigger circuit (140); The receiving pin (R) of the RS-485 chip (110) is connected to the signal receiving end (RX), the transmitting pin (D) of the RS-485 chip (110) is connected to the signal transmitting end (TX), and the receiving enable pin (D) of the RS-485 chip (110) is connected to the signal transmitting end (TX). and a transmission enable pin (DE) are respectively connected to a first power supply terminal (V1) and an output terminal (P_Q) of the RS trigger circuit (140), and a first transmission pin (A) and a second transmission pin (B) of the RS-485 chip (110) are both used for connecting to a communication bus; The control end (C) of the switch circuit (120) is connected to the signal transmitting end (TX), the first end (1) of the switch circuit (120) is respectively connected to the first power supply end (V1) and the charge-discharge circuit (130), the second end (2) of the switch circuit (120) and the charge-discharge circuit (130) are both connected to the ground end (GND), and the switch circuit (120) is used to disconnect the first end (1) from the second end (2) if the level of the signal transmitting end (TX) is a first level, so that the first power supply end (V1) charges the charge-discharge circuit (130), and to connect the first end (1) to the second end (2) if the level of the signal transmitting end (TX) is a second level, wherein the second level is a high level relative to the first level; The charge-discharge circuit (130) is also connected to the set terminal (P_S) of the RS trigger circuit (140), and the charge-discharge circuit (130) is used to maintain the level of the set terminal (P_S) at the second level after charging, and to discharge through the switch circuit (120) after the first terminal (1) and the second terminal (2) are connected, and to maintain the level of the set terminal (P_S) at the second level during the discharge process; The reset terminal (P_R) of the RS trigger circuit (140) is connected to the signal transmitting terminal (TX), and the RS trigger circuit (140) is used to adjust the level of the output terminal (P_Q) based on the level of the set terminal (P_S) and the level of the reset terminal (P_R); Among them, the receive enable pin The effective level of is the first level, and the effective level of the transmit enable pin (DE) is the second level; The switching circuit (120) comprises: a switching transistor (Q1); the gate of the switching transistor (Q1) is connected to the signal transmitting end (TX) as the control end (C); the first electrode of the switching transistor (Q1) is connected to the first power supply end and the charging and discharging circuit (130) as the first end (1); and the second electrode of the switching transistor (Q1) is connected to the ground end (GND) and the charging and discharging circuit (130) as the second end (2); The charge and discharge circuit (130) comprises: a first diode (D1), a first resistor (R1) and a capacitor (C1); the anode of the first diode (D1) is respectively connected to the first power supply terminal (V1), the first terminal (1) of the switch circuit (120) and one end of the first resistor (R1); the cathode of the first diode (D1) is respectively connected to the set terminal (P_S) of the RS trigger circuit (140), the other end of the first resistor (R1) and one end of the capacitor (C1); the other end of the capacitor (C1) is respectively connected to the second terminal (2) of the switch circuit (120) and the ground terminal (GND).

2. The communication circuit according to claim 1, wherein: The switch transistor (Q1) is an N-type metal oxide semiconductor (MOS) transistor.

3. The communication circuit according to claim 1 or 2, characterized in that: The communication circuit further includes: a current limiting circuit (150); The current limiting circuit (150) is respectively connected to the first power supply terminal (V1), the receiving enable pin The transmission enable pin (DE), the transmission pin (D), the first end (1) of the switch circuit (120), the reset end (P_R) of the RS trigger circuit (140), and the charge and discharge circuit (130) are connected, and the current limiting circuit (150) is used to limit the current of the signal of the first power supply end (V1) and transmit it to the switch circuit (120), the charge and discharge circuit (130), the reception enable pin (DE), the first end (1) of the switch circuit (120), the reset end (P_R) of the RS trigger circuit (140), and the charge and discharge circuit (130). and the transmit enable pin (DE), and is used to limit the current of the signal from the signal transmitting end (TX) and transmit it to the reset end (P_R) and the transmit pin (D) respectively.

4. The communication circuit according to claim 3, wherein: The current limiting circuit (150) comprises: a second resistor (R2), a third resistor (R3) and a fourth resistor (R4); One end of the second resistor (R2) is connected to the first end (1) of the switch circuit (120) and the charge-discharge circuit (130), respectively; the other end of the second resistor (R2) is connected to the first power supply end (V1) and one end of the third resistor (R3), respectively; the other end of the third resistor (R3) is connected to the receive enable pin (V1). Connected to the transmit enable pin (DE); One end of the fourth resistor (R4) is connected to the signal transmitting end (TX), and the other end of the fourth resistor (R4) is respectively connected to the reset end (P_R) of the RS trigger circuit (140) and the transmitting pin (D).

5. The communication circuit according to claim 1 or 2, characterized in that: The communication circuit further includes: a matching circuit (160); The matching circuit (160) is respectively connected to the second power supply terminal (V2), the ground terminal (GND), the first transmission pin (A), and the second transmission pin (B). The matching circuit (160) is used to pull up the level of the first transmission pin (A) to a third level and pull down the level of the second transmission pin (B) to a fourth level under the drive of the second power supply terminal (V2) and the ground terminal (GND).

6. The communication circuit according to claim 5, characterized in that The matching circuit (160) includes: a fifth resistor (R5) and a sixth resistor (R6); One end of the fifth resistor (R5) is connected to the second power supply end (V2), and the other end of the fifth resistor (R5) is connected to the first transmission pin (A); One end of the sixth resistor (R6) is connected to the second transmission pin (B), and the other end of the sixth resistor (R6) is connected to the ground terminal (GND).

7. The communication circuit according to claim 6, characterized in that The matching circuit (160) further includes: a seventh resistor (R7); One end of the seventh resistor (R7) is connected to the first transmission pin (A), and the other end of the seventh resistor (R7) is connected to the second transmission pin (B).

8. The communication circuit according to claim 1 or 2, characterized in that: The RS trigger circuit (140) comprises: a set subcircuit (141) and a reset subcircuit (142), wherein the set subcircuit (141) is connected to the set terminal (P_S) and the output terminal (P_Q) respectively, and the reset subcircuit (142) is connected to the reset terminal (P_R) and the output terminal (P_Q) respectively; The setting subcircuit (141) includes: a second diode (D2), a third diode (D3), a fourth diode (D4), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), a first transistor (T1), and a second transistor (T2); The reset subcircuit (142) includes: a fifth diode (D5), a sixth diode (D6), a seventh diode (D7), an eleventh resistor (R11), a twelfth resistor (R12), a thirteenth resistor (R13), a third transistor (T3) and a fourth transistor (T4); The cathode of the second diode (D2) is connected to the set end (P_S) of the RS trigger circuit (140), the anode of the second diode (D2) is respectively connected to one end of the eighth resistor (R8), the anode of the third diode (D3), and the anode of the fourth diode (D4), the cathode of the fourth diode (D4) is connected to the output end (P_Q) of the RS trigger circuit (140), the cathode of the third diode (D3) is connected to the base of the first transistor (T1), and the collector of the first transistor (T1) is respectively connected to the The first power supply terminal (V1), the other end of the eighth resistor (R8), and one end of the ninth resistor (R9) are connected, the other end of the ninth resistor (R9) is respectively connected to the collector of the second transistor (T2) and the output terminal (P_Q) of the RS trigger circuit (140), the emitter of the first transistor (T1) is respectively connected to the base of the second transistor (T2) and one end of the tenth resistor (R10), and the other end of the tenth resistor (R10) is respectively connected to the emitter of the second diode (D2) and the ground terminal (GND); The cathode of the fifth diode (D5) is connected to the collector of the second transistor (T2), the anode of the fifth diode (D5) is respectively connected to one end of the eleventh resistor (R11), the anode of the sixth diode (D6), and the anode of the seventh diode (D7), the cathode of the seventh diode (D7) is connected to the reset terminal (P_R) of the RS trigger circuit (140), the cathode of the sixth diode (D6) is connected to the base of the third transistor (T3), and the collector of the third transistor (T3) is respectively connected to the third power supply terminal (V3 ), the other end of the eleventh resistor (R11) and one end of the twelfth resistor (R12) are connected, the other end of the twelfth resistor (R12) are respectively connected to the collector of the fourth transistor (T4) and the output end (P_Q) of the RS trigger circuit (140), the emitter of the third transistor (T3) is respectively connected to the base of the fourth transistor (T4), one end of the thirteenth resistor (R13) is connected, and the other end of the thirteenth resistor (R13) is respectively connected to the emitter of the fourth transistor (T4) and the ground end (GND).

9. A communication system, comprising: a communication bus, a first device (10) and a second device (20); The first device (10) comprises: a first communication chip (U1) and a first communication circuit (11), wherein the first communication chip (U1) is respectively connected to a signal transmitting end (TX1) and a signal receiving end (RX1) of the first communication circuit (11); The second device (20) comprises: a second communication chip (U2) and a second communication circuit (12), wherein the second communication chip (U2) is respectively connected to a signal transmitting end (TX2) and a signal receiving end (RX2) of the second communication circuit (12); One end of the communication bus is connected to a first transmission pin (A1) and a second transmission pin (B1) of an RS-485 chip (111) in the first communication circuit (11), and the other end of the communication bus is connected to a first transmission pin (A2) and a second transmission pin (B2) of an RS-485 chip (121) in the second communication circuit (12); Wherein, the first communication circuit (11) and the second communication circuit (12) are both the communication circuits according to any one of claims 1 to 8.

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