Packaging core components and manufacturing methods

Abstract

The present disclosure relates to a semiconductor core assembly and a method for forming the same. The semiconductor core assembly as herein described can be used to form a semiconductor package assembly, a PCB assembly, a PCB spacer assembly, a chip carrier assembly, an intermediate carrier assembly (e.g., for a graphics card), etc. In one embodiment, a silicon substrate core is constructed by direct laser patterning. One or more conductive interconnects are formed in the substrate core, and one or more redistribution layers are formed on its surface. Subsequently, the silicon substrate core can be used as a core structure for a semiconductor package, a PCB, a PCB spacer, a chip carrier, an intermediate carrier, etc.

Description

[0001] background

[0002] field

[0003] Embodiments of the present disclosure generally relate to electronic mounting structures and methods of forming the same. More specifically, the embodiments described herein relate to semiconductor packages and PCB assemblies and methods of forming the same. Background Art

[0004] As the demand for miniaturized electronic devices and components continues to increase, the need for faster processing capabilities with greater circuit density places corresponding demands on the materials, structures, and processes used in the manufacture of such integrated circuit chips. However, in addition to these trends toward greater integration and performance, there is a constant pursuit of reducing manufacturing costs.

[0005] Generally speaking, integrated circuit chips have been fabricated on organic packaging substrates coupled to circuit boards (e.g., printed circuit boards (PCBs)) due to the ease of forming features and connections in organic packaging substrates and the relatively low packaging manufacturing costs associated with organic composite materials. However, with increasing circuit density and further miniaturization of electronic devices, the utilization of organic packaging substrates with conventional interconnected PCBs has become impractical due to limitations in material structure resolution required to maintain device scale and associated performance requirements. More recently, passive silicon interposers have been utilized as redistribution layers to fabricate 2.5D and 3D integrated circuits to compensate for some of the limitations associated with organic packaging substrates. The utilization of silicon interposers is driven by potentials for low-power chip-to-chip communication with high bandwidth density, as well as for heterogeneous integration in advanced electronic assembly and packaging applications. However, the formation of features, such as through-silicon vias (TSVs), in silicon interposers remains difficult and costly. In particular, high-aspect-ratio TSV etching, chemical mechanical planarization, and semiconductor back-end-of-the-line (BEOL) interconnects result in high costs.

[0006] Therefore, there is a need in the art for improved semiconductor packages and PCB core assemblies having increased density and methods of forming the same. Summary of the Invention

[0007] The present disclosure generally relates to electronic mounting structures and methods of forming the same.

[0008] In one embodiment, a semiconductor device assembly is provided. The semiconductor device assembly includes a silicon core structure having a first surface opposite a second surface and a thickness of less than approximately 1000 μm. One or more conductive interconnects are formed through the silicon core structure and protrude from the first surface and the second surface. The semiconductor device assembly further includes a first redistribution layer formed on the first surface and a second redistribution layer formed on the second surface. The first redistribution layer and the second redistribution layer each have one or more conductive contacts formed thereon.

[0009] In one embodiment, a semiconductor device assembly is provided. The semiconductor device assembly includes a silicon core structure, a passivation layer, and a dielectric layer. The silicon core structure has a thickness of less than about 1000 μm. The passivation layer surrounds the silicon core structure and includes a thermal oxide. The dielectric layer is formed on the passivation layer and includes an epoxy resin having silicon dioxide particles disposed therein.

[0010] In one embodiment, a semiconductor device assembly is provided. The semiconductor device includes: a silicon core structure; a passivation layer surrounding the silicon structure and comprising thermal oxide; a dielectric layer surrounding the passivation layer and formed of epoxy resin; and a redistribution layer formed on the dielectric layer. The redistribution layer further includes: an adhesion layer formed of molybdenum and formed on the dielectric layer; a copper seed layer formed on the adhesion layer; and a copper layer formed on the copper seed layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

[0012] Figure 1A Schematically illustrates a cross-sectional view of a semiconductor core assembly according to embodiments described herein.

[0013] Figure 1B Schematically illustrates a cross-sectional view of a semiconductor core assembly according to embodiments described herein.

[0014] Figure 2 To illustrate the method for forming a Figure 1A and Figure 1B Flowchart of the process of producing semiconductor core components.

[0015] Figure 3 is a flow chart illustrating a process for constructing a substrate for a semiconductor core assembly according to embodiments described herein.

[0016] Figures 4A to 4D Schematically illustrates a method according to an embodiment described herein Figure 3 Cross-sectional views of a substrate at different stages of the depicted process.

[0017] Figure 5 is a flow chart illustrating a process for forming an insulating layer on a core structure of a semiconductor core component according to embodiments described herein.

[0018] 6A to 6I Schematically illustrates a method according to an embodiment described herein Figure 5 Cross-sectional views of the core structure at different stages of the depicted process.

[0019] Figure 7 is a flow chart illustrating a process for forming an insulating layer on a core structure of a semiconductor core component according to embodiments described herein.

[0020] Figures 8A to 8E Schematically illustrates a method according to an embodiment described herein Figure 7 Cross-sectional views of the core structure at different stages of the depicted process.

[0021] Figure 9 is a flow chart illustrating a process for forming interconnects in a semiconductor core assembly according to embodiments described herein.

[0022] Figures 10A to 10H Schematically illustrates a method according to an embodiment described herein Figure 9 Cross-sectional views of a semiconductor core assembly at different stages of the depicted process.

[0023] Figure 11 is a flow chart illustrating a process for forming a redistribution layer on a semiconductor core component according to embodiments described herein.

[0024] Figures 12A to 12L Schematically illustrates a method according to an embodiment described herein Figure 11 Cross-sectional views of a semiconductor core assembly at different stages of the depicted process.

[0025] Figure 13A A cross-sectional view of a chip carrier structure including a semiconductor core component according to embodiments described herein is schematically illustrated.

[0026] Figure 13B Schematically illustrates a cross-sectional view of a PCB structure including a semiconductor core component according to embodiments described herein.

[0027] Figure 13C Schematically illustrates a cross-sectional view of a PCB structure including a semiconductor core component according to embodiments described herein.

[0028] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0029] The present disclosure relates to a semiconductor core assembly and a method for forming the same. The semiconductor core assembly as herein described can be used to form a semiconductor package assembly, a PCB assembly, a PCB spacer assembly, a chip carrier assembly, an intermediate carrier assembly (e.g., for a graphics card), etc. In one embodiment, a silicon substrate core is constructed by direct laser patterning. One or more conductive interconnects are formed in the substrate core, and one or more redistribution layers are formed on its surface. Subsequently, the silicon substrate core can be used as a core structure for a semiconductor package, a PCB, a PCB spacer, a chip carrier, an intermediate carrier, etc.

[0030] The method and apparatus disclosed herein, including a novel thin form factor semiconductor core structure, are intended to replace more conventional semiconductor packages, PCBs, and chip carrier structures that utilize glass fiber-filled epoxy frames. In general, the scalability of current semiconductor packages, PCBs, spacers, and chip carriers is limited by the insufficient rigidity and planarity of the materials (e.g., epoxy molding compounds, FR-4 and FR-5 grades of glass fiber woven cloth with epoxy resin adhesive, etc.) commonly used to form these various structures. The inherent properties of these materials cause difficulties in patterning and utilizing the fine (e.g., micron-scale) features formed therein. In addition, as a result of the properties (e.g., insulation) of the currently used materials, a mismatch in thermal expansion (CTE) coefficient may occur between the glass fiber frame, board, molding compound, and any chip arranged adjacent thereto. Therefore, current packages, PCBs, spacers, and carrier structures require larger solder bumps with larger spacing to mitigate the effects of any warpage caused by CTE mismatch. Therefore, conventional semiconductor packages, PCBs, spacers, and carrier frames are characterized by low electrical bandwidth throughout the structure, resulting in reduced overall power efficiency. The methods and apparatus described herein provide semiconductor core structures that overcome many of the shortcomings associated with the conventional semiconductor packages, PCBs, spacers, and carrier structures described above.

[0031] Figure 1A and Figure 1BA cross-sectional view of a thin form factor semiconductor core assembly 100 according to some embodiments is shown. The semiconductor core assembly 100 can be used for structural support and electrical interconnection of a semiconductor package mounted thereon. In a further example, the semiconductor core assembly 100 can serve as a carrier structure for surface mounted devices such as chips or graphics cards. The semiconductor core assembly 100 generally includes a core structure 102, an optional passivation layer 104, and an insulating layer 118.

[0032] In one embodiment, the core structure 102 includes a patterned (eg, structured) substrate formed of any suitable substrate material. For example, the core structure 102 includes a substrate formed of a III-V compound semiconductor material, silicon, crystalline silicon (eg, Si <100> or Si <111> ), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polysilicon, silicon nitride, quartz, glass (e.g., borosilicate glass), sapphire, aluminum oxide, and / or a ceramic material. In one embodiment, the core structure 102 comprises a single crystal p-type or n-type silicon substrate. In one embodiment, the core structure 102 comprises a polycrystalline p-type or n-type silicon substrate. In another embodiment, the core structure 102 comprises a p-type or n-type silicon solar substrate. The substrate used to form the core structure 102 may further have a polygonal or circular shape. For example, the core structure 102 may include a substantially square silicon substrate with or without chamfered edges, the lateral dimensions of the silicon substrate being between about 120 mm and about 180 mm. In another example, the core structure 102 may include a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 50 mm, for example, about 300 mm.

[0033] The thickness T1 of the core structure 102 is between about 50 μm and about 1000 μm, such as between about 70 μm and about 800 μm. For example, the thickness T1 of the core structure 102 is between about 80 μm and about 400 μm, such as between about 100 μm and about 200 μm. In another example, the thickness T1 of the core structure 102 is between about 70 μm and about 150 μm, such as between about 100 μm and about 130 μm. In another example, the thickness T1 of the core structure 102 is between about 700 μm and about 800 μm, such as between about 725 μm and about 775 μm.

[0034] The core structure 102 further includes one or more holes or core through-holes 103 (hereinafter referred to as "core through-holes") formed therein to enable conductive interconnects to be routed through the core structure 102. Generally speaking, the shape of the one or more core through-holes 103 is substantially cylindrical. However, other suitable forms of core through-holes 103 are also considered. The core through-holes 103 can be formed as single and separate core through-holes 103 passing through the core structure 102, or formed in one or more groups or arrays. In one embodiment, the minimum pitch P1 between each core through-hole 103 is less than about 1000 μm, such as between about 25 μm and about 200 μm. For example, the pitch P1 is between about 40 μm and about 150 μm. In one embodiment, the diameter V1 of the one or more core through-holes 103 is less than about 500 μm, such as the diameter V1 is less than about 250 μm. For example, the diameter V1 of the core through hole 103 is between about 25 μm and about 100 μm, such as between about 30 μm and about 60 μm. In one embodiment, the diameter V1 of the core through hole 103 is about 40 μm.

[0035] An optional passivation layer 104 can be formed on one or more surfaces of the core structure 102, including the first surface 106, the second surface 108, and one or more sidewalls of the core through-hole 103. In one embodiment, the passivation layer 104 is formed on substantially all external surfaces of the core structure 102, such that the passivation layer 104 substantially surrounds the core structure 102. Thus, the passivation layer 104 provides a protective outer barrier for the core structure 102 to prevent corrosion and other forms of damage. In one embodiment, the passivation layer 104 is formed by an oxide film or an oxide layer (such as a thermal oxide layer). In some examples, the thickness of the passivation layer 104 is between about 100 nm and about 3 μm, such as a thickness between about 200 nm and about 2.5 μm. In one example, the thickness of the passivation layer 104 is between about 300 nm and about 2 μm, such as a thickness of about 1.5 μm.

[0036] The insulating layer 118 is formed on one or more surfaces of the core structure 102 or the passivation layer 104 and may substantially encapsulate the passivation layer 104 and / or the core structure 102. Figure 1A As depicted, insulating layer 118 may extend into core via 103 and coat passivation layer 104 formed on the sidewalls of core via 103 or directly coat core structure 102, thereby defining a diameter V2. In one embodiment, insulating layer 118 has a thickness T2 of less than about 50 μm, such as less than about 20 μm, from an outer surface of core structure 102 or passivation layer 104 to an adjacent outer surface of insulating layer 118 (e.g., major surfaces 105, 107). For example, thickness T2 of insulating layer 118 is between about 5 μm and about 10 μm.

[0037] In one embodiment, the insulating layer 118 is formed of a polymer-based dielectric material. For example, the insulating layer 118 is formed of a flowable buildup material. Therefore, although referred to below as an "insulating layer," the insulating layer 118 may also be described as a dielectric layer. In a further embodiment, the insulating layer 118 is formed of an epoxy material with a ceramic filler, such as silicon dioxide (SiO2) particles. Other examples of ceramic fillers that may be used to form the insulating layer 118 include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16 , zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12 ), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), etc. In some examples, the size of the particles of the ceramic filler used to form the insulating layer 118 is in the range of about 40 nm to about 1.5 μm (such as between about 80 nm and about 1 μm). For example, the size of the particles of the ceramic filler is in the range of about 200 nm to about 800 nm (such as between about 300 nm and about 600 nm). In some embodiments, the size of the particles included in the ceramic filler is less than about 10% of the width or diameter of the adjacent core through-hole 103 in the core structure 102, such as less than about 5% of the width or diameter of the core through-hole 103.

[0038] One or more through-assembly holes or vias 113 (hereinafter referred to as "through-assembly vias") are formed through the insulating layer 118, wherein the insulating layer 118 extends into the core via 103. For example, the through-assembly via 113 can be centrally formed within the core via 103 having the insulating layer 118 disposed therein. Thus, the insulating layer 118 forms one or more sidewalls of the through-assembly via 113, wherein the diameter V2 of the through-assembly via 113 is less than the diameter V1 of the core via 103. In one embodiment, the diameter V2 of the through-assembly via 113 is less than approximately 100 μm, such as less than approximately 75 μm. For example, the diameter V2 of the through-assembly via 113 is less than approximately 50 μm, such as less than approximately 35 μm. In one embodiment, the diameter of the through-assembly via 113 is between approximately 25 μm and approximately 50 μm, such as between approximately 35 μm and approximately 40 μm.

[0039] The through-component vias 113 provide a channel through which one or more electrical interconnects 144 are formed in the semiconductor core component 100. In one embodiment, the electrical interconnects 144 are formed to pass through the entire thickness of the semiconductor core component 100 (i.e., from the first major surface 105 to the second major surface 107 of the semiconductor core component 100). For example, the longitudinal length of the electrical interconnects 144 corresponding to the total thickness of the semiconductor core component 100 is between about 50 μm and about 1000 μm, such as a longitudinal length between about 200 μm and about 800 μm. In one example, the longitudinal length of the electrical interconnects 144 is between about 400 μm and about 600 μm, such as a longitudinal length of about 500 μm. In another embodiment, the electrical interconnects 144 are formed to pass through only a portion of the thickness of the semiconductor core component 100. In a further embodiment, the electrical interconnects 144 may extend from a major surface of the semiconductor core component 100 (such as Figure 1A The electrical interconnect 144 may be formed of any conductive material used in the fields of integrated circuits, circuit boards, chip carriers, etc. For example, the electrical interconnect 144 may be formed of a metal material such as copper, aluminum, gold, nickel, silver, palladium, tin, etc.

[0040] exist Figure 1A In the depicted embodiment, the lateral thickness of the electrical interconnect 144 is equal to the diameter V2 of the through-component via 113 in which the electrical interconnect 144 is formed. Figure 1B As depicted, the semiconductor core component 100 further includes an adhesive layer 140 and / or a seed layer 142 formed thereon for electrical isolation of the electrical interconnect 144. In one embodiment, the adhesive layer 140 is formed on the surface of the insulating layer 118 adjacent to the electrical interconnect 144 (including the sidewall of the through-component via 113). Figure 1B As depicted, the lateral thickness of electrical interconnect 144 is less than the diameter V2 of through-assembly via 113 in which electrical interconnect 144 is formed. In yet another embodiment, electrical interconnect 144 covers only the surface of the sidewalls of through-assembly via 113 and thus may have a hollow core therethrough.

[0041] Adhesion layer 140 may be formed of any suitable material, including but not limited to titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, etc. In one embodiment, the thickness B1 of adhesion layer 140 is between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the thickness B1 of adhesion layer 140 is between about 75 nm and about 125 nm, such as about 100 nm.

[0042] The optional seed layer 142 comprises a conductive material, including but not limited to copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. The seed layer 142 can be formed on the adhesion layer 140 or directly on the sidewalls of the through-component via 113 (e.g., on the insulating layer 118 without an adhesion layer therebetween). In one embodiment, the seed layer 142 has a thickness between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, the seed layer 142 has a thickness between about 150 nm and about 250 nm, such as about 200 nm.

[0043] In some embodiments (such as Figure 1B The semiconductor core assembly 100 further includes one or more redistribution layers 150 formed on the first side 175 and / or the second side 177 of the semiconductor core assembly 100 (the redistribution layers 150 are formed on the first side 175 and / or the second side 177 of the semiconductor core assembly 100). Figure 1B 17 is depicted as being formed on second side 177). In one embodiment, redistribution layer 150 is formed of a material substantially the same as insulating layer 118 (e.g., a polymer-based dielectric material), and thereby forms an extension thereof. In other embodiments, redistribution layer 150 is formed of a material different from insulating layer 118. For example, redistribution layer 150 can be formed of a photodefinable polyimide material, a non-photosensitive polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), silicon dioxide, and / or silicon nitride. In another example, redistribution layer 150 is formed of an inorganic dielectric material different from insulating layer 118. In one embodiment, redistribution layer 150 has a thickness between about 5 μm and about 50 μm, such as a thickness between about 10 μm and about 40 μm. For example, redistribution layer 150 has a thickness between about 20 μm and about 30 μm, such as about 25 μm.

[0044] The redistribution layer 150 may include one or more redistribution connections 154 formed to pass through the redistribution vias 153 to reposition the contact points of the electrical interconnects 144 to desired locations on the surface of the semiconductor core component 100 (such as the main surfaces 105, 107). In some embodiments, the redistribution layer 150 may further include one or more external electrical connections (not shown) (such as ball grid arrays or solder balls) formed on the main surfaces 105, 107. Generally speaking, the redistribution vias 153 and the redistribution connections 154 have substantially similar or smaller lateral dimensions relative to the through-component vias 113 and the electrical interconnects 144, respectively. For example, the diameter V3 of the redistribution vias 153 is between about 2 μm and about 50 μm, such as between about 10 μm and about 40 μm, such as between about 20 μm and about 30 μm. Furthermore, the redistribution layer 150 may include an adhesion layer 140 and a seed layer 142 formed on surfaces adjacent to the redistribution connections 154 (including sidewalls of the redistribution vias 153 ).

[0045] Figure 2 A flow chart illustrating a representative method 200 for forming a semiconductor core assembly is shown. The method 200 has a plurality of operations 210, 220, 230, and 240. Each operation is referred to as Figures 3 to 12L A method may include one or more additional operations, which may be performed before any defined operation, between two defined operations, or after all defined operations (unless the context excludes the possibility).

[0046] Generally speaking, the method 200 includes, at operation 210, constructing a substrate serving as a core structure (eg, a frame), referring to Figure 3 and Figures 4A to 4D At operation 220, an insulating layer is formed on the core structure 102 and the insulating layer is formed on the core structure 102. Figure 5 、 6A to 6I 、 Figure 7 and Figures 8A to 8E At operation 230, one or more interconnects are formed through the core structure 102 and the insulating layer, and reference is made to Figure 9 and Figures 10A to 10H At operation 240, a redistribution layer is formed on the insulating layer to relocate the interconnected contact points to desired locations on the surface of the assembled core assembly, and the core assembly is then cut into individual pieces. In some embodiments, in addition to the first redistribution layer, one or more additional redistribution layers may be formed, as described in more detail below. Figure 11 and Figures 12A to 12L A more detailed description is given further.

[0047] Figure 3 A flow chart is shown of a representative method 300 for configuring a substrate 400 for use as a core structure. Figures 4A to 4D Schematically illustrated Figure 3 Cross-sectional views of a substrate 400 at various stages of the substrate structuring process 300 are shown. Therefore, for clarity, the following are described together. Figure 3 and Figures 4A to 4D .

[0048] Method 300 begins at operation 310 and corresponds to Figure 4A As described above with reference to the core structure 102, the substrate 400 is formed of any suitable substrate material, including but not limited to III-V compound semiconductor materials, silicon, crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polysilicon, silicon nitride, quartz, glass materials (e.g., borosilicate glass), sapphire, aluminum oxide, and / or ceramic materials. In one embodiment, substrate 400 is a single crystal p-type or n-type silicon substrate. In one embodiment, substrate 400 is a polycrystalline p-type or n-type silicon substrate. In another embodiment, substrate 400 is a p-type or n-type silicon solar cell substrate.

[0049] The substrate 400 may further have a polygonal or circular shape. For example, the substrate 400 may include a substantially square silicon substrate with or without chamfered edges, the lateral dimensions of the silicon substrate being between about 140 mm and about 180 mm. In another example, the substrate 400 may include a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example, about 300 mm. Unless otherwise stated, the embodiments and examples described herein are performed on substrates having a thickness between about 50 μm and about 1000 μm (such as a thickness between about 90 μm and about 780 μm). For example, the thickness of the substrate 400 is between about 100 μm and about 300 μm, such as a thickness between about 110 μm and about 200 μm.

[0050] Prior to operation 310, the substrate 400 may be sliced ​​and separated from the bulk material by wire sawing, scribing and breaking, mechanical friction sawing, or laser cutting. Slicing typically results in mechanical defects or deformities (such as scratches, microcracks, chipping, and other mechanical defects) in the surface of the substrate formed from the slice. Therefore, at operation 310, the substrate 400 is exposed to a first damage removal process to smooth and planarize its surface and remove mechanical defects in preparation for subsequent structuring operations. In some embodiments, the substrate 400 may be further thinned by adjusting the process parameters of the first damage removal process. For example, as exposure to the first damage removal process increases, the thickness of the substrate 400 may be reduced.

[0051] At operation 310, the first damage removal process includes exposing the substrate 400 to a substrate polishing process and / or an etching process, followed by exposure to a rinsing and drying process. In some embodiments, operation 310 includes a chemical mechanical polishing (CMP) process. In one embodiment, the etching process is a wet etching process including a buffered etching process that selectively removes desired materials (e.g., contaminants and other undesirable compounds). In other embodiments, the etching process is a wet etching process utilizing an isotropic aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the wet etching process. In one embodiment, the substrate 400 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 400 is immersed in an aqueous KOH etching solution for etching.

[0052] In some embodiments, during the etching process, the etching solution is heated to a temperature between about 30° C. and about 100° C. (such as between about 40° C. and 90° C.). For example, the etching solution is heated to a temperature of about 70° C. In other embodiments, at operation 310, the etching process is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes. The thickness of the substrate 400 is adjusted by controlling the time that the substrate 400 is exposed to the etchant (e.g., etching solution) used during the etching process. For example, as the exposure to the etchant increases, the final thickness of the substrate 400 decreases. Alternatively, as the exposure to the etchant decreases, the substrate 400 can have a greater final thickness.

[0053] At operation 320, the now planarized and substantially defect-free substrate 400 is patterned to form one or more core vias 403 therein (at Figure 4B Four core vias 403 are depicted in the cross section of substrate 400 . Core vias 403 are used to form direct contact electrical interconnections through substrate 400 .

[0054] In general, one or more core through holes 403 can be formed by laser ablation (e.g., direct laser patterning). Any suitable laser ablation system can be used to form one or more core through holes 403. In some examples, the laser ablation system utilizes an infrared (IR) laser source. In some examples, the laser source is a picosecond ultraviolet (UV) laser. In other examples, the laser is a femtosecond UV laser. In yet other examples, the laser source is a femtosecond green laser. The laser source of the laser ablation system generates a continuous laser beam or a pulsed laser beam for patterning the substrate 400. For example, the laser source can generate a pulsed laser beam with a frequency between 5kHz and 500kHz (such as between 10kHz and about 200kHz). In one example, the laser source is configured to deliver a pulsed laser beam with an output power between about 10 watts and about 100 watts at a wavelength between about 200nm and about 1200nm and a pulse duration between about 10ns and about 5000ns. The laser source is configured to form any desired pattern of features in the substrate 400 , including the core via 403 .

[0055] In some embodiments, prior to patterning, the substrate 400 is optionally coupled to a carrier plate (not shown). The optional carrier plate can provide mechanical support for the substrate 400 during patterning and can prevent the substrate 400 from breaking. The carrier plate can be formed of any suitable chemically and thermally stable rigid material (including but not limited to glass, ceramic, metal, etc.). In some examples, the thickness of the carrier plate is between about 1 mm and about 10 mm, such as between about 2 mm and about 5 mm. In one embodiment, the carrier plate has a textured surface. In other embodiments, the carrier plate has a polished or smoothed surface. The substrate 400 can be coupled to the carrier plate using any suitable temporary adhesive material (including but not limited to wax, glue, or similar adhesive material).

[0056] In some embodiments, patterning the substrate 400 may cause undesirable mechanical defects on the surface of the substrate 400, including chipping, cracking, and / or warping. Therefore, after performing operation 320 to form the core through hole 403 in the substrate 400, at operation 330, the substrate 400 is exposed to a second damage removal and cleaning process (substantially similar to the first damage removal process at operation 310) to smooth the surface of the substrate 400 and remove undesirable debris. As described above, the second damage removal process includes exposing the substrate 400 to a wet or dry etching process, followed by rinsing and drying. The etching process is performed for a predetermined duration to smooth the surface of the substrate 400, and in particular the surface exposed to the laser patterning operation. On the other hand, the etching process is used to remove any undesirable debris remaining on the substrate 400 from the patterning process.

[0057] After the mechanical defects in the substrate 400 are removed at operation 330, the substrate 400 is Figure 4D The substrate 400 is exposed to a passivation process at step 340 to grow or deposit a passivation film or layer (such as an oxide layer 404) on a desired surface of the substrate 400 (e.g., the entire surface of the substrate 400). In one embodiment, the passivation process is a thermal oxidation process. The thermal oxidation process is performed at a temperature between about 800° C. and about 1200° C. (such as between about 850° C. and about 1150° C.). For example, the thermal oxidation process is performed at a temperature between about 900° C. and about 1100° C. (such as between about 950° C. and about 1050° C.). In one embodiment, the thermal oxidation process is a wet oxidation process using water vapor as an oxidant. In one embodiment, the thermal oxidation process is a dry oxidation process using molecular oxygen as an oxidant. It is contemplated that at operation 340, the substrate 400 may be exposed to any suitable passivation process to form the oxide layer 404 or any other suitable passivation layer on the substrate 400. The resulting oxide layer 404 typically has a thickness between about 100 nm and about 3 μm, such as between about 200 nm and about 2.5 μm. For example, the oxide layer 404 has a thickness between about 300 nm and about 2 μm, such as about 1.5 μm.

[0058] After passivation, substrate 400 is ready for use as a core structure 402 for the formation of a core assembly, such as semiconductor core assembly 100 . Figure 5 and Figure 7 Flowcharts are shown of representative methods 500 and 700 , respectively, for forming insulating layer 618 on core structure 402 . 6A to 6I Schematically illustrated Figure 5 Cross-sectional views of the core structure 402 at different stages of the depicted method 500, and Figures 8A to 8E Schematically illustrated Figure 7 Cross-sectional views of the core structure 402 at different stages of the depicted method 700. For clarity, the following are described together. Figure 5 and 6A to 6I , and this article describes Figure 7 and Figures 8A to 8E .

[0059] Generally speaking, method 500 begins at operation 502 and Figure 6A, wherein the first surface 406 of the core structure 402 at the first side 475 (now having the core through-hole 403 formed therein and the oxide layer 404 formed thereon) is placed and fixed on the first insulating film 616a. In one embodiment, the first insulating film 616a includes one or more layers formed of a polymer-based dielectric material. For example, the first insulating film 616a includes one or more layers formed of a flowable buildup material. In one embodiment, the first insulating film 616a includes a flowable epoxy layer 618a. Generally speaking, the thickness of the epoxy layer 618a is less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the thickness of the epoxy layer 618a is between about 10 μm and about 25 μm.

[0060] The epoxy layer 618a may be formed of an epoxy containing a ceramic filler, such as an epoxy filled with (e.g., containing) silicon dioxide (SiO2) particles. Other examples of ceramic fillers that may be used to form the epoxy layer 618a and other layers of the insulating film 616a include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16 , zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12 ), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), etc. In some examples, the ceramic filler used to form the epoxy resin layer 618a has a particle size ranging from about 40 nm to about 1.5 μm (such as between about 80 nm and about 1 μm). For example, the ceramic filler used to form the epoxy resin layer 618a has a particle size ranging from about 200 nm to about 800 nm (such as between about 300 nm and about 600 nm).

[0061] In some embodiments, the first insulating film 616a further includes one or more protective layers. For example, the first insulating film 616a includes a polyethylene terephthalate (PET) protective layer 622a (such as a biaxial PET protective layer 622a). However, any suitable number and combination of layers and materials are contemplated for the first insulating film 616a. In some embodiments, the entire insulating film 616a has a thickness of less than about 120 μm, such as a thickness of less than about 90 μm.

[0062] In some embodiments, after securing the core structure 402 to the first insulating film 616a, the core structure 402 can then be placed on a carrier 624 adjacent to its first side 475 for additional mechanical stabilization during later processing operations. Generally speaking, the carrier 624 is formed from any suitable mechanically and thermally stable material capable of withstanding temperatures above 100°C. For example, in one embodiment, the carrier 624 comprises polytetrafluoroethylene (PTFE). In another example, the carrier 624 is formed from polyethylene terephthalate (PET).

[0063] In operation 504 and Figure 6B 4. At the second side 477 of the core structure 402, the first protective film 660 is fixed to the second surface 408. The protective film 660 is coupled to the core structure 402 on the second side 477 and opposite the first insulating film 616a, so that the protective film 660 covers the core through-hole 403. In one embodiment, the protective film 660 is formed of a material similar to the protective layer 622a. For example, the protective film 660 is formed of PET (such as biaxial PET). However, the protective film 660 can be formed of any suitable protective material. In some embodiments, the thickness of the protective film 660 is between about 50 μm and about 150 μm.

[0064] At operation 506, the core structure 402 (now secured to the insulating film 616a at a first side 475 and to the protective film 660 at a second side 477) is exposed to a first lamination process. During the lamination process, the core structure 402 is exposed to elevated temperatures, causing the epoxy layer 618a of the insulating film 616a to soften and flow into the open voids or volumes between the insulating film 616a and the protective film 660 (such as into the core vias 403). Thus, as Figure 6C As depicted, core via 403 is at least partially filled (eg, occupied) by the insulating material of epoxy layer 618a. Additionally, core structure 402 is partially surrounded by the insulating material of epoxy layer 618a.

[0065] In one embodiment, the lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed by using a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C and is performed for a period of time between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 1 psi and about 150 psi, while applying a temperature between about 80°C and about 140°C to the core structure 402 and the insulating film 616a for a period of time between about 1 minute and about 30 minutes. For example, the lamination process is performed by applying a pressure between about 10 psi and about 100 psi and a temperature between about 100°C and about 120°C for a period of time between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a period of time of about 5 minutes.

[0066] At operation 508, the protective film 660 is removed and the core structure 402 (now having the laminated insulating material of the epoxy layer 618a at least partially surrounding the core structure 402 and partially filling the core through-holes 403) is placed on the second protective film 662. Figure 6D As depicted, the second protective film 662 is coupled to the core structure 402 adjacent to the first side 475 such that the second protective film 662 is disposed against (e.g., adjacent) the protective layer 622a of the insulating film 616a. In some embodiments, the core structure 402 (now coupled to the protective film 662) can optionally be placed on a carrier 624 for additional mechanical support on the first side 475. In some embodiments, the protective film 662 is placed on the carrier 624 before coupling the protective film 662 to the core structure 402. In general, the protective film 662 is substantially similar in composition to the protective film 660. For example, the protective film 662 can be formed from PET (such as biaxial PET). However, the protective film 662 can be formed from any suitable protective material. In some embodiments, the thickness of the protective film 662 is between about 50 μm and about 150 μm.

[0067] After coupling the core structure 402 to the second protective film 662, in operations 510 and Figure 6E, a second insulating film 616b (substantially similar to the first insulating film 616a) is placed over the second side 477, thereby replacing the protective film 660. In one embodiment, the second insulating film 616b is positioned on the second side 477 of the core structure 402 such that the epoxy layer 618b of the second insulating film 616b covers the core through-holes 403. In one embodiment, the placement of the second insulating film 616b on the core structure 402 can form one or more gaps between the insulating film 616b and the laminated insulating material of the epoxy layer 618a (partially surrounding the core structure 402 and partially filling the core through-holes 403). Similar to the insulating film 616a, the second insulating film 616b may include one or more layers formed of a polymer-based dielectric material. As Figure 6E As depicted, the second insulating film 616b includes an epoxy layer 618b substantially similar to the epoxy layer 618a described above. The second insulating film 616b may further include a protective layer 622b formed of a material similar to the protective layer 622a, such as PET.

[0068] At operation 512, as Figure 6F As depicted, a third protective film 664 is positioned over the second insulating film 616b. Generally speaking, the protective film 664 is substantially similar in composition to the protective films 660 and 662. For example, the protective film 664 is formed from PET (such as biaxially woven PET). However, the protective film 664 can be formed from any suitable protective material. In some embodiments, the thickness of the protective film 664 is between approximately 50 μm and approximately 150 μm.

[0069] In operation 514 and Figure 6G At step 504, the core structure 402 (now secured to the insulating film 616b and the protective film 664 on the second side 477 and to the protective film 662 and the optional carrier 624 on the first side 475) is exposed to a second lamination process. Similar to the lamination process at operation 504, the core structure 402 is exposed to an elevated temperature, causing the epoxy layer 618b of the insulating film 616b to soften and flow into any open voids or volumes between the insulating film 616b and the laminated insulating material of the epoxy layer 618a, thereby integrating itself with the insulating material of the epoxy layer 618a. As a result, the core vias 403 become completely filled (e.g., encapsulated, sealed) with the insulating material of both epoxy layers 618a, 618b.

[0070] In one embodiment, the second lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed by using a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C and is performed for a period of time between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 1 psi and about 150 psi, while applying a temperature between about 80°C and about 140°C to the core structure 402 and the insulating film 616a for a period of time between about 1 minute and about 30 minutes. For example, the lamination process is performed by applying a pressure between about 10 psi and about 100 psi and a temperature between about 100°C and about 120°C for a period of time between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a period of time of about 5 minutes.

[0071] After lamination, at operation 516, the core structure 402 is released from the carrier 624 and the protective films 662, 664 are removed, resulting in a laminated intermediate core assembly 602. Figure 6H As depicted, the intermediate core assembly 602 includes a core structure 402 having one or more core through-holes 403, one or more core through-holes 403 passing through the core structure 402 and formed and filled with the insulating dielectric material of insulating films 616a, 616b. The insulating dielectric material of epoxy layers 618a, 618b further coats the core structure 402 having an oxide layer 404 formed thereon, such that the insulating material covers at least two surfaces or sides (e.g., surfaces 406, 408) of the core structure 402. In some examples, at operation 516, protective layers 622a, 622b are also removed from the intermediate core assembly 602. Generally speaking, protective layers 622a and 622b, carrier 624, and protective films 662 and 664 are removed from the intermediate core assembly 602 by any suitable mechanical process (such as peeling off from the intermediate core assembly 602).

[0072] After removing the protective layers 622a, 622b and the protective films 662, 664, the intermediate core assembly 602 is exposed to a curing process to fully cure (i.e., harden by chemical reaction and cross-linking) the insulating dielectric material of the epoxy layers 618a, 618b, thereby forming an insulating layer 618. The insulating layer 618 substantially surrounds the core structure 402 and fills the core through-hole 403. For example, the insulating layer 618 contacts or encapsulates at least the portions 107, 477 (including the surfaces 406, 408) of the core structure 402.

[0073] In one embodiment, the curing process is performed at an elevated temperature to fully cure the intermediate core assembly 602. For example, the curing process is performed at a temperature between about 140° C. and about 220° C. for a period of between about 15 minutes and about 45 minutes, such as between about 160° C. and about 200° C. for a period of between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the curing process at operation 516 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0074] After curing, at operation 518, one or more through-assembly vias 613 are drilled through the intermediate core assembly 602 to form a channel through the entire thickness of the intermediate core assembly 602 for subsequent interconnect formation. In some embodiments, the intermediate core assembly 602 can be placed on a carrier (such as carrier 624) for mechanical support during the formation of the through-assembly vias 613. The through-assembly vias 613 are drilled through the core through-holes 403 formed in the core structure 402 and subsequently filled with the insulating layer 618. Therefore, the insulating layer 618 filled within the core through-holes 403 can circumferentially surround the through-assembly vias 613. By lining the walls of the core through-holes 403 with the epoxy resin material containing the ceramic filler of the insulating layer 618, the completed (e.g., final) semiconductor core assembly 1270 (see FIG. 1 ) can be more compact and durable than other conventional interconnect structures that utilize conventional through-hole insulating liners or films. Figure 11 and Figure 12K and Figure 12L Capacitive coupling between the conductive silicon-based core structure 402 and the interconnect 1044 (see Figure 9 and Figures 10A to 10H Furthermore, the flowable nature of the epoxy material of insulating layer 618 enables more consistent and reliable encapsulation and insulation, thereby enhancing electrical performance by minimizing leakage current of the completed semiconductor core assembly 1270.

[0075] In one embodiment, the diameter of the through-component via 613 is less than about 100 μm, such as less than about 75 μm. For example, the diameter of the through-component via 613 is less than about 50 μm, such as less than about 35 μm. In some embodiments, the diameter of the through-component via 613 is between about 25 μm and about 50 μm, such as between about 35 μm and about 40 μm. In one embodiment, the through-component via 613 is formed using any suitable mechanical process. For example, a mechanical drilling process is used to form the through-component via 613. In one embodiment, the through-component via 613 is formed through the intermediate core component 602 by laser ablation. For example, an ultraviolet laser is used to form the through-component via 613. In one embodiment, the frequency of the laser source used for laser ablation is between about 5 kHz and about 500 kHz. In one embodiment, the laser source is configured to deliver a pulsed laser beam with a pulse energy between about 50 microjoules (μJ) and about 500 μJ and a pulse duration between about 10 ns and about 100 ns. The use of an epoxy material containing small ceramic filler particles further facilitates more precise and accurate laser patterning of small diameter vias, such as through-component via 613, because the small ceramic filler particles in the epoxy material exhibit reduced laser reflection, scattering, diffraction, and transmission of the laser light away from the area where the via is to be formed during the laser ablation process.

[0076] In some embodiments, the through-component via 613 is formed within (e.g., through) the core via 403 such that the average thickness of the remaining epoxy material containing ceramic filler (e.g., dielectric insulating material) on the sidewalls of the core via 403 is between about 1 μm and about 50 μm. For example, the average thickness of the remaining epoxy material containing ceramic filler on the sidewalls of the core via 403 is between about 5 μm and about 40 μm, such as between about 10 μm and about 30 μm. Thus, the resulting structure after forming the through-component via 613 can be described as a "via-in-via" (e.g., a via formed with dielectric material centered within the through-hole of the core structure). The via-in-via structure includes a dielectric sidewall passivation composed of an epoxy material filled with ceramic particles and disposed on a thin layer of thermal oxide formed on the sidewalls of the core via 403.

[0077] After forming the through-component vias 613, the intermediate core component 602 is exposed to a decontamination process. During the decontamination process, any undesirable residues and / or debris caused by the laser ablation during the formation of the through-component vias 613 are removed from the intermediate core component 602. Thus, the decontamination process cleans the through-component vias 613 for subsequent metallization. In one embodiment, the decontamination process is a wet decontamination process. Any suitable solvent, etchant, and / or combination thereof can be used for the wet decontamination process. In one example, methanol can be used as a solvent and copper (II) chloride dihydrate (CuCl2·H2O) can be used as an etchant. Depending on the thickness of the residue, the exposure duration of the intermediate core component 602 to the wet decontamination process can be different. In another embodiment, the decontamination process is a dry decontamination process. For example, the decontamination process can be a plasma decontamination process using an O2 / CF4 gas mixture. The plasma decontamination process may include generating a plasma by applying a power of about 700 W and flowing O2:CF4 at a ratio of about 10:1 (e.g., 100:10 sccm) for a period of time between about 60 seconds and about 120 seconds. In further embodiments, the decontamination process is a combination of wet and dry processes.

[0078] After the desmear process at operation 518, the intermediate core assembly 602 is ready for forming interconnect paths therein, as described below with reference to Figure 9 and Figures 10A to 10H Provide a description.

[0079] As mentioned above, Figure 5 and 6A to 6I A representative method 500 for forming an intermediate core assembly 602 is illustrated. Figure 7 and Figures 8A to 8E An alternative method 700 is shown that is substantially similar to method 500 but has fewer operations. Generally speaking, method 700 includes five operations 710 through 750. However, operations 710, 740, and 750 of method 700 are substantially similar to operations 502, 516, and 518, respectively, of method 500. Therefore, for clarity, only operations 710, 740, and 750 are described herein. Figure 8B 、 Figure 8C and Figure 8D Operations 720, 730, and 740 are depicted.

[0080] In operation 720 and Figure 8B After the first insulating film 616a is secured to the first surface 406 on the first side 475 of the core structure 402, the second insulating film 616b is coupled to the second surface 408 on the opposite side 477. In some embodiments, the second insulating film 616b is positioned on the surface 408 of the core structure 402 such that the epoxy layer 618b of the second insulating film 616b covers all of the core through holes 403. Figure 8BAs depicted, core vias 403 form one or more voids or gaps between insulating films 616a and 616b. In some embodiments, a second carrier 625 is secured to protective layer 622b of second insulating film 616b for additional mechanical support during later processing operations.

[0081] In operation 730 and Figure 8C At 405°, the core structure 402 (now secured to insulating films 616a and 616b on opposite sides of the core structure 402) is exposed to a single lamination process. During the single lamination process, the core structure 402 is exposed to elevated temperatures, causing the epoxy layers 618a and 618b of the two insulating films 616a and 616b to soften and flow into the open void or volume created by the core through-hole 403 between the insulating films 616a and 616b. As a result, the core through-hole 403 is filled with the insulating material of the epoxy layers 618a and 618b.

[0082] Similar to reference Figure 5 and 6A to 6I The lamination process described, the lamination process at operation 730 can be a vacuum lamination process that can be performed in an autoclave or other suitable device. In another embodiment, the lamination process is performed by using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C and is performed for a period of time between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 1 psi and about 150 psi, while applying a temperature between about 80°C and about 140°C to the core structure 402 and the insulating films 616a, 616b for a period of time between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 10 psi and about 100 psi and a temperature between about 100°C and about 120°C, and is performed for a period of time between about 2 minutes and 10 minutes. For example, the lamination process at operation 730 is performed at a temperature of about 110°C for a period of time of about 5 minutes.

[0083] At operation 740, one or more protective layers of the insulating films 616a, 616b are removed from the core structure 402, thereby producing a laminated intermediate core assembly 602. In one example, the protective layers 622a, 622b are removed from the core structure 402, and thus the intermediate core assembly 602 is also separated from the first carrier 624 and the second carrier 625. In general, the protective layers 622a, 622b and the carriers 624, 625 are removed by any suitable mechanical process, such as peeling therefrom. Figure 8DAs depicted, intermediate core assembly 602 includes core structure 402 having one or more core through-holes 403 formed therein and filled with insulating dielectric material of epoxy layers 618 a and 618 b. The insulating material further coats core structure 402 such that the insulating material covers at least two surfaces or sides of core structure 402 (e.g., surfaces 406, 408).

[0084] After removing the protective layers 622a, 622b, the intermediate core assembly 602 is exposed to a curing process to fully cure the insulating dielectric material of the epoxy resin layers 618a, 618b. The curing of the insulating material results in the formation of the insulating layer 618. Figure 8D Depicted and similar to Figure 6H Corresponding to operation 516 , an insulating layer 618 substantially surrounds the core structure 402 and fills the core vias 403 .

[0085] In one embodiment, the curing process is performed at an elevated temperature to fully cure the intermediate core assembly 602. For example, the curing process is performed at a temperature between about 140° C. and about 220° C. for a period of between about 15 minutes and about 45 minutes, such as between about 160° C. and about 200° C. for a period of between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the curing process at operation 740 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0086] After curing at operation 740, method 700 is substantially similar to operation 520 of method 500. Thus, one or more through-assembly vias 613 are drilled through the intermediate core assembly 602, and the intermediate core assembly 602 is then exposed to a desmear process. After the desmear process is completed, the intermediate core assembly 602 is ready for forming interconnect paths therein, as described below.

[0087] Figure 9 A flow chart illustrating a representative method 900 for forming electrical interconnects through the intermediate core assembly 602 is shown. Figures 10A to 10H Schematically illustrated Figure 9 Cross-sectional views of the intermediate core assembly 602 at different stages of the process of the depicted method 900. Therefore, for the sake of clarity, the following are described together. Figure 9 and Figures 10A to 10H .

[0088] In one embodiment, the electrical interconnects formed through the intermediate core assembly 602 are formed of copper. Thus, the method 900 generally begins with operations 910 and Figure 10AAt , the intermediate core component 602 having through-component vias 613 formed therein has a barrier or adhesion layer 1040 and / or a seed layer 1042 formed thereon. Figure 10H , a partial enlarged view of the bonding layer 1040 and seed layer 1042 formed on the intermediate core component 602 is depicted for reference. The bonding layer 1040 can be formed on a desired surface of the insulating layer 618 (such as a surface corresponding to the main surfaces 1005, 1007 of the intermediate core component 602 and the sidewalls of the through-component via 613) to help promote the adhesion of the subsequently formed seed layer 1042 to the electrical interconnect 1044 and to prevent diffusion. Therefore, in one embodiment, the bonding layer 1040 acts as an bonding layer; in another embodiment, the bonding layer 1040 acts as a barrier layer. However, in both embodiments, the bonding layer 1040 is described below as an "adhesion layer."

[0089] In one embodiment, adhesion layer 1040 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In one embodiment, adhesion layer 1040 has a thickness between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, adhesion layer 1040 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. Adhesion layer 1040 is formed by any suitable deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc.

[0090] Seed layer 1042 can be formed on adhesion layer 1040 or directly on insulating layer 618 (e.g., without adhesion layer 1040). In some embodiments, seed layer 1042 is formed on all surfaces of insulating layer 618, while adhesion layer 1040 is formed only on desired surfaces or portions of the surfaces of insulating layer 618. For example, adhesion layer 1040 can be formed on major surfaces 1005 and 1007 and not on the sidewalls of through-component via 613, while seed layer 1042 is formed on major surfaces 1005 and 1007 and on the sidewalls of through-component via 613. Seed layer 1042 is formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In one embodiment, seed layer 1042 has a thickness between approximately 0.05 μm and approximately 0.5 μm, such as a thickness between approximately 0.1 μm and approximately 0.3 μm. For example, the thickness of the seed layer 1042 is between about 0.15 μm and about 0.25 μm, such as about 0.2 μm. In one embodiment, the thickness of the seed layer 1042 is between about 0.1 μm and about 1.5 μm. Similar to the adhesion layer 1040, the seed layer 1042 is formed by any suitable deposition process (such as CVD, PVD, PECVD, ALD dry process, wet chemical plating process, etc.). In one embodiment, the copper seed layer 1042 can be formed on the molybdenum adhesion layer 1040 on the intermediate core assembly 602. The combination of the molybdenum adhesion and copper seed layers enables improved adhesion to the surface of the insulating layer 618 and reduces undercutting of the conductive interconnects during the subsequent seed layer etching process at operation 970.

[0091] At operations 920 and 930 (respectively Figure 10B and Figure 10C ), a spin-coated / sprayed or dry resist film 1050 (such as a photoresist) is applied to the two main surfaces 1005, 1007 of the intermediate core component 602 and then patterned. In one embodiment, the resist film 1050 is patterned by selective exposure to UV radiation. In one embodiment, an adhesion promoter (not shown) is applied to the intermediate core component 602 before the resist film 1050 is formed. The adhesion promoter improves the adhesion of the resist film 1050 to the intermediate core component 602 by creating an interfacial adhesion layer for the resist film 1050 and by removing any moisture from the surface of the intermediate core component 602. In some embodiments, the adhesion promoter is formed of bis(trimethylsilyl)amine or hexamethyldisilazane (HMDS) and propylene glycol methyl ether acetate (PGMEA).

[0092] At operation 940, the intermediate core assembly 602 is exposed to a resist film development process. Figure 10DAs depicted, the development of the resist film 1050 results in the exposure of the through-component via 613 (which may now have the adhesion layer 1040 and / or the seed layer 1042 formed thereon). In one embodiment, the film development process is a wet process (such as a wet process that includes exposing the resist film 1050 to a solvent). In one embodiment, the film development process is a wet etching process that utilizes an aqueous etching process. For example, the film development process is a wet etching process that utilizes a buffered etching process that selectively targets the desired material. Any suitable wet solvent or combination of wet etchants can be used for the resist film development process.

[0093] At operations 950 and 960 (respectively Figure 10E and Figure 10F Correspondingly, electrical interconnect 1044 is formed through the exposed through-component via 613, and then the resist film 1050 is removed. Interconnect 1044 is formed by any suitable method (including electroplating and chemical plating). In one embodiment, the resist film 1050 is removed via a wet process. Figure 10E and Figure 10F As depicted, after removing the resist film 1050, the electrical interconnect 1044 can completely fill the through-assembly via 613 and protrude from the surfaces 1005, 1007 of the intermediate core assembly 602. In some embodiments, the electrical interconnect 1044 can simply line the sidewalls of the through-assembly via 613 without completely filling the through-assembly via 613. In one embodiment, the electrical interconnect 1044 is formed of copper. In other embodiments, the electrical interconnect 1044 can be formed of any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, etc.

[0094] In operation 970 and Figure 10G At , the intermediate core component 602 having the electrical interconnect 1044 formed therein is exposed to a seed layer etching process to remove the exposed adhesion layer 1040 and seed layer 1042 on its exterior surfaces (e.g., surfaces 1005, 1007). In some embodiments, after the seed layer etching process, the adhesion layer 1040 and / or seed layer 1042 formed between the electrical interconnect 1044 and the sidewalls of the through-component via 613 may remain. In one embodiment, the seed layer etching is a wet etching process that includes rinsing and drying the intermediate core component 602. In one embodiment, the seed layer etching process is a buffered etching process that is selective for the desired material (such as copper, tungsten, aluminum, silver, or gold). In other embodiments, the etching process is an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the seed layer etching process.

[0095] After the seed layer etching process at operation 970, one or more semiconductor core components can be cut into individual pieces from the intermediate core component 602 and used as a fully functional electronic mounting or packaging structure. For example, one or more semiconductor core components can be cut into individual pieces and used as a circuit board structure, a chip carrier structure, an integrated circuit package, etc. Alternatively, the intermediate core component 602 can have one or more redistribution layers 1260 ( Figure 12J and Figure 12K ), to reroute the external contact points of the electrical interconnect 1044 to desired locations on the surface of the final semiconductor core component.

[0096] Figure 11 A flow chart illustrating a representative method 1100 for forming a redistribution layer 1260 on the intermediate core assembly 602 is shown. Figures 12A to 12K Schematically illustrated Figure 11 Cross-sectional views of the intermediate core assembly 602 at different stages of the depicted method 1100. Therefore, for clarity, the following are described together herein. Figure 11 and Figures 12A to 12K .

[0097] Method 1100 is substantially similar to methods 500, 700, and 900 described above. Generally speaking, method 1100 begins with operations 1102 and Figure 12A wherein the insulating film 1216 is fixed to the intermediate core assembly 602 and thereafter laminated. The insulating film 1216 is substantially similar to the insulating films 616a, 616b. In one embodiment, as Figure 12A As depicted, insulating film 1216 includes an epoxy layer 1218 and one or more protective layers. For example, insulating film 1216 may include protective layer 1222. Any suitable combination of layers and insulating materials is contemplated for insulating film 1216. In some embodiments, an optional carrier 1224 is coupled to insulating film 1216 for added support. In some embodiments, a protective film (not shown) may be coupled to insulating film 1216.

[0098] In general, the thickness of epoxy layer 1218 is less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the thickness of epoxy layer 1218 is between about 10 μm and about 25 μm. In one embodiment, the combined thickness of epoxy layer 1218 and PET protective layer 1222 is less than about 120 μm, such as less than about 90 μm. Insulating film 1216, and in particular epoxy layer 1218, is secured to a surface of intermediate core assembly 602 (such as major surface 1005) having exposed electrical interconnects 1044.

[0099] After placing the insulating film 1216, the intermediate core assembly 602 is exposed to a lamination process (substantially similar to the lamination process described with respect to operations 506, 514, and 730). The intermediate core assembly 602 is exposed to an elevated temperature to soften the epoxy layer 1218 of the insulating film 1216, which is then bonded to the insulating layer 618. Thus, the epoxy layer 1218 is integrated with the insulating layer 618 and forms an extension of the insulating layer 618, and is therefore hereinafter described as a single insulating layer 618. The integration of the epoxy layer 1218 with the insulating layer 618 further results in an expanded insulating layer 618 surrounding the previously exposed electrical interconnects 1044.

[0100] In operation 1104 and Figure 12B At 740, protective layer 1222 and carrier 1224 are removed from intermediate core assembly 602 by mechanical means, and intermediate core assembly 602 is exposed to a curing process to fully harden the newly expanded insulating layer 618. In one embodiment, the curing process is substantially similar to the curing process described with reference to operations 516 and 740. For example, the curing process is performed at a temperature between about 140° C. and about 220° C. and for a period of time between about 15 minutes and about 45 minutes.

[0101] Then, at operations 1106 and Figure 12C At 1106, the intermediate core component 602 is selectively patterned by laser ablation. The laser ablation process at operation 1106 forms one or more redistribution vias 1253 in the newly expanded insulating layer 618, and exposes the desired electrical interconnects 1044 for redistribution of their contact points. In one embodiment, the diameter of the redistribution vias 1253 is substantially similar to or smaller than the diameter of the through-component vias 613. For example, the diameter of the redistribution vias 1253 is between about 5 μm and about 600 μm, such as between about 10 μm and about 50 μm, such as between about 20 μm and about 30 μm. In one embodiment, the laser ablation process at operation 1106 is performed using a CO2 laser. In one embodiment, the laser ablation process at operation 1106 is performed using a UV laser. In another embodiment, the laser ablation process at operation 1106 is performed using a green laser. In one example, the laser source can generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver a pulsed laser beam at a wavelength between about 100 nm and about 2000 nm, a pulse duration between about 10E-4 ns and about 10E-2 ns, and with a pulse energy between about 10 μJ and about 300 μJ.

[0102] In operation 1108 and Figure 12DAdhesion layer 1240 and / or seed layer 1242 are optionally formed on one or more surfaces of insulating layer 618. In one embodiment, adhesion layer 1240 and seed layer 1242 are substantially similar to adhesion layer 1040 and seed layer 1042, respectively. For example, adhesion layer 1240 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In one embodiment, adhesion layer 1240 has a thickness between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, adhesion layer 1240 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. Adhesion layer 1240 can be formed by any suitable deposition process, including but not limited to CVD, PVD, PECVD, ALD, etc.

[0103] Seed layer 1242 is formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In one embodiment, seed layer 1242 has a thickness between about 0.05 μm and about 0.5 μm, such as between about 0.1 μm and about 0.3 μm. For example, seed layer 1242 has a thickness between about 0.15 μm and about 0.25 μm, such as about 0.2 μm. Similar to adhesion layer 1240, seed layer 1242 can be formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet chemical plating process, etc. In one embodiment, molybdenum adhesion layer 1240 and copper seed layer 1242 are formed on intermediate core assembly 602 to reduce the formation of undercuts during the subsequent seed layer etching process at operation 1122.

[0104] At operations 1110, 1112, and 1114 (respectively Figure 12E 、 Figure 12F and Figure 12G Correspondingly), a spin-coated / sprayed or dry resist film 1250 (such as a photoresist) is applied to the seed crystal surface of the intermediate core component 602 and subsequently patterned and developed. In one embodiment, an adhesion promoter (not shown) is applied to the intermediate core component 602 before the resist film 1250 is placed. The exposure and development of the resist film 1250 result in the opening of the redistribution through-holes 1253. Therefore, the patterning of the resist film 1250 can be performed by selectively exposing a portion of the resist film 1250 to UV radiation and the subsequent development of the resist film 1250 by a wet process (such as a wet etching process). In one embodiment, the resist film development process is a wet etching process that utilizes a buffered etching process that selectively targets the desired material. In other embodiments, the resist film development process is a wet etching process that utilizes an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the resist film development process.

[0105] At operations 1116 and 1118 (respectively Figure 12H and Figure 12I Correspondingly), the redistribution connection 1244 is formed through the exposed redistribution through-hole 1253, and thereafter the resist film 1250 is removed. In one embodiment, the resist film 1250 is removed via a wet process. Figure 12H and Figure 12I As depicted, after removing the resist film 1250, the redistribution connections 1244 fill the redistribution vias 1253 and protrude from the surface of the intermediate core assembly 602. In one embodiment, the redistribution connections 1244 are formed of copper. In other embodiments, the redistribution connections 1244 are formed of any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, etc. Any suitable method can be used to form the redistribution connections 1244, including electroplating and electroless deposition.

[0106] In operation 1120 and Figure 12J At step 970, the intermediate core assembly 602 having the redistribution connections 1244 formed thereon is exposed to a seed layer etching process substantially similar to operation 970. In one embodiment, the seed layer etching process is a wet etching process that includes rinsing and drying the intermediate core assembly 602. In one embodiment, the seed layer etching process is a wet etching process that utilizes a buffered etching process that selectively targets the desired material of the seed layer 1242. In other embodiments, the etching process is a wet etching process that utilizes an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the seed layer etching process.

[0107] After the seed layer etch process at operation 1120 is completed, the sequence and process described above may be utilized to form one or more additional redistribution layers 1260 on the intermediate core assembly 602. For example, one or more additional redistribution layers 1260 may be formed on opposing surfaces (such as major surface 1007) of the first redistribution layer 1260 and / or the intermediate core assembly 602. In one embodiment, the one or more additional redistribution layers 1260 may be formed from a polymer-based dielectric material (such as a flowable build-up material) that is different from the material of the first redistribution layer 1260 and / or the insulating layer 618. For example, in some embodiments, the insulating layer 618 may be formed from a ceramic fiber filled epoxy while the first and / or any additional redistribution layers 1260 are formed from polyimide, BCB, and / or PBO. Alternatively, at operations 1122 and Figure 12K After forming the desired number of redistribution layers 1260 , one or more completed semiconductor core assemblies 1270 can be cut from the intermediate core assembly 602 .

[0108] The completed semiconductor core assembly 1270 formed at operation 1120 can be used in any suitable package assembly, PCB assembly, PCB spacer assembly, chip carrier assembly, intermediate carrier assembly, etc. Figure 13A In one exemplary embodiment depicted, a single semiconductor core assembly 1270 serves as a carrier for a chip 1360 in a chip carrier assembly 1300. Chip 1360 can be any suitable type of chip (including a memory chip, a microprocessor, a complex system on chip (SoC), or a standard chip). Suitable types of memory chips include DRAM chips or NAND flash memory chips. In some further examples, chip 1360 is a digital chip, an analog chip, or a hybrid chip. Chip 1360 is arranged adjacent to one of the main surfaces 1005, 1007 of semiconductor core assembly 1270. In some embodiments, two or more chips 1360 can be arranged adjacent to a single main surface 1005, 1007. In another embodiment, one or additional devices and / or structures (such as one or more components of a PCB or a package substrate) can be arranged adjacent to chip 1360. For example, one or more passive components (such as capacitors, resistors, inductors, etc.) can be arranged adjacent to chip 1360. In another example, one or more connectors can be arranged adjacent to chip 1360.

[0109] Chip 1360 includes one or more contacts 1348 formed on its active surface 1352. As shown, contacts 1348 are conductively coupled to one or more redistribution connections 1244 of semiconductor core assembly 1270 via one or more solder bumps 1346 disposed between active surface 1352 and major surface 1005. In some embodiments, contacts 1348 can be conductively coupled to one or more interconnects 1044 via one or more solder bumps 1346. In one embodiment, contacts 1348 and / or solder bumps 1346 are formed of a material substantially similar to that of interconnects 1044 and redistribution connections 1244. For example, contacts 1348 and solder bumps 1346 can be formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof.

[0110] In one embodiment, solder bumps 1346 include C4 solder bumps. In one embodiment, solder bumps 1346 include C2 (copper pillars with solder caps) solder bumps. The use of C2 solder bumps can achieve a smaller pitch length and improved thermal and / or electrical properties of chip carrier assembly 1300. Solder bumps 1346 can be formed by any suitable wafer bumping process, including but not limited to electrochemical deposition (ECD) and electroplating.

[0111] exist Figure 13BIn another exemplary embodiment depicted, semiconductor core assembly 1270 is used in PCB assembly 1302. Thus, semiconductor core assembly 1270 is configured to function as a PCB structure for supporting (e.g., carrying) package assembly 1310. The structure and materials of package assembly 1310 can be substantially similar to semiconductor core assembly 1270, but package assembly 1310 includes an embedded die 1326 (substantially surrounded by insulating layer 618) disposed within a cavity 1320 formed within core structure 402. Embedded die 1326 can further include an active surface 1328 having one or more contacts 1330 formed thereon and coupled to interconnects 1342 and / or redistribution connections 1344 of package assembly 1310. Similar to Figure 13A In the chip-carrier assembly 1300, contacts 1330 and / or interconnects 1342 and / or redistribution connections 1344 of the package assembly 1310 are conductively coupled to one or more redistribution connections 1244 of the semiconductor core assembly 1270 via one or more solder bumps 1346 disposed between the active surface 1328 and the main surface 1005. In some embodiments, the contacts 1330 can be conductively coupled to the one or more interconnects 1044 via the one or more solder bumps 1346.

[0112] Figure 13C The figure illustrates yet another exemplary embodiment utilizing a semiconductor core assembly 1270 as a PCB spacer structure within a PCB assembly 1304. As shown, the semiconductor core assembly 1270 is disposed between two PCBs 1362a and 1362b and is configured to position the first PCB 1362a relative to the second PCB 1362b such that a physical space remains between the first PCB 1362a and the second PCB 1362b when they are conductively connected. Accordingly, the PCBs 1362a and 1362b include one or more conductive pads 1368 formed on their major surfaces 1364a and 1364b, respectively. The one or more conductive pads 1368 are conductively coupled to the redistribution connections 1244 and / or the interconnects 1044 of the semiconductor core assembly 1270 via one or more solder bumps 1346. Similar to contacts 1330 and 1348, conductive pad 1368 is formed of a material substantially similar to solder bump 1346, interconnect 1044, and redistribution connection 1244 to enable electrical conductivity therethrough. For example, conductive pad 1368 may be formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof.

[0113] In the embodiment shown above, the utilization of semiconductor core assembly 1270 provides multiple advantages over conventional packaging, PCB, PCB spacer and chip carrier structure. Such benefits include thin form factor and high chip or die to package volume ratio, which achieves larger I / O scaling to meet the increasing bandwidth and power efficiency requirements of artificial intelligence (AI) and high performance computing (HPC). The utilization of structured silicon frame provides optimal material stiffness and thermal conductivity for improved electrical performance, thermal management and reliability of 3-dimensional integrated circuit (3D IC) architecture. In addition, compared to conventional TSV technology, the manufacturing method of the structure of through-assembly vias and through-holes in through-holes described herein provides high performance and flexibility for 3D integration with relatively low manufacturing cost.

[0114] By utilizing the above method, high aspect ratio features can be formed on glass and / or silicon core structures, thereby enabling thinner and narrower circuit boards, chip carriers, integrated circuit packages, etc. to be economically formed. The semiconductor core assembly manufactured utilizing the above method not only provides the benefits of high I / O density and improved bandwidth and power, but also provides the benefits of higher reliability owing to the low stress owing to reduced weight / inertia and the component architecture that allows flexible solder balls to be distributed. Further advantages of the above method include economical manufacturing with double-sided metallization capabilities and high productivity. In addition, the utilization of the silicon core reduces or eliminates the mismatch of the coefficient of thermal expansion (CTE) between the core assembly and any chip connected, thereby achieving smaller solder pitch and increased device density.

[0115] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A semiconductor device assembly comprising: A glass core structure having a first side opposite a second side, the glass core structure further comprising: a through hole comprising a through hole surface defining an opening extending through the glass core structure from the first side to the second side; a conductive interconnect formed through the through hole and protruding from the first side and the second side; an insulating layer disposed directly on the first side, the second side, and a surface of the through-hole; a first redistribution layer formed on the first side; as well as A second redistribution layer is formed on the second side, wherein the first redistribution layer and the second redistribution layer each have one or more conductive contacts formed thereon.

2. The semiconductor device assembly of claim 1, wherein the insulating layer comprises epoxy resin.

3. The semiconductor device assembly of claim 2, wherein the epoxy resin comprises silicon dioxide particles. 4 . The semiconductor device assembly of claim 1 , wherein the insulating layer has a thickness between 5 μm and 50 μm.

5. The semiconductor device assembly of claim 1 , wherein the first redistribution layer and the second redistribution layer each further comprise: an adhesive layer formed on the insulating layer, the adhesive layer comprising molybdenum; a seed layer formed on the adhesive layer; and A copper layer is formed on the seed layer. 6 . The semiconductor device assembly of claim 5 , wherein the adhesion layer has a thickness between 10 nm and 500 nm.

7. The semiconductor device assembly of claim 1 , further comprising: One or more through-vias are disposed through the semiconductor device assembly, each of the one or more through-vias having a copper interconnect formed therein. 8 . The semiconductor device assembly of claim 7 , wherein each of the one or more through-holes is circumferentially defined by the insulating layer. 9 . The semiconductor device assembly of claim 7 , wherein the insulating layer extends through the one or more through-holes from the first side through the glass core structure to the second side.

10. A semiconductor device assembly comprising: A glass core structure having a first side opposite a second side, the glass core structure having a thickness of less than 1000 μm, the glass core structure further comprising: a through hole comprising a through hole surface defining an opening extending through the glass core structure from the first side to the second side; an insulating layer directly formed on at least the first side, the second side, and a surface of the through-hole, the insulating layer comprising an epoxy resin having silicon dioxide particles disposed therein; an adhesion layer formed on the insulating layer in the opening, the adhesion layer comprising molybdenum; and A seed layer is formed on the adhesion layer in the opening, the seed layer comprising copper.

11. The semiconductor device assembly of claim 10, wherein the glass core structure comprises a borosilicate glass substrate.

12. The semiconductor device assembly of claim 10, further comprising: One or more arrays of through-holes are disposed through the semiconductor device assembly, each of the through-holes of the one or more arrays having a diameter less than 500 μm.

13. The semiconductor device assembly of claim 12, wherein the through-hole is one of a plurality of through-holes disposed through the glass core structure, a pitch between each of the plurality of through-holes having a distance between 40 μm and 1000 μm.

14. The semiconductor device assembly of claim 10, further comprising a conductive interconnect formed within the opening and above the seed layer, the seed layer extending from the first side to the second side, the conductive interconnect being circumferentially defined by the insulating layer.

15. The semiconductor device assembly of claim 10, further comprising a first redistribution layer formed on the insulating layer.

16. A semiconductor device assembly comprising: a glass core structure having a first side opposite a second side, and a plurality of through-holes extending from the first side to the second, opposing side, each of the plurality of through-holes including a through-hole surface defining an opening extending through the glass core structure from the first side to the second side; a conductive interconnect formed through each of the plurality of through-holes and protruding from the first side and the second side; an insulating layer, the insulating layer being directly disposed on the first side, the second side, and a surface of each through-hole of the plurality of through-holes, the insulating layer comprising epoxy resin; an adhesion layer formed over the insulating layer within the opening of each of the plurality of through holes, the adhesion layer comprising molybdenum; and A seed layer is formed between the adhesive layer and the conductive interconnect in the opening of each of the plurality of vias, the seed layer comprising copper.

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