Circuit for correcting phase interpolator rolloff integral nonlinearity error

Abstract

Circuitry for correcting phase interpolator rollover integral nonlinearity error includes rollover detector circuitry and correction circuitry. The rollover detector circuitry includes a forward rollover detector circuit for detecting when a forward rollover event of a phase interpolator occurs and a reverse rollover detector circuit for detecting when a reverse rollover event of the phase interpolator occurs. The correction circuitry adds a signed pre-distortion correction to a voltage controlled oscillator (VCO) clock period fractional value when the rollover detector circuitry has detected either a forward rollover event of the phase interpolator or a reverse rollover event of the phase interpolator.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 952,201, filed December 20, 2019, and U.S. Non-Provisional Patent Application Serial No. 16 / 827,691, filed March 23, 2020, the contents of which are incorporated herein by reference in their entirety. Background Technology

[0003] This invention relates to phase interpolation. More specifically, this invention relates to circuitry for correcting nonlinear errors at the seams of phase interpolators.

[0004] Some circuit designs employ frequency synthesizers that synthesize any desired target frequency from a high-frequency voltage-controlled oscillator (VCO) clock. The VCO clock can be quantized as a fixed phase increment per cycle. As is well known in the art, some frequency synthesizers synthesize the target frequency by dividing the VCO clock output by a divisor that has an integer part and may also include a fractional part. One known way to implement this frequency division is to provide a circuit with an accumulator that accumulates a frequency control word (FCW) each VCO clock cycle equal to the number of accumulated phase increments of the VCO clock cycles selected based on the desired target frequency, until the accumulator's output value exceeds a predetermined number (overflow) also selected based on the desired target frequency. The amount by which the accumulator's output value overflows beyond the predetermined number defines the fractional part of the divisor. When the accumulator's accumulated output value exceeds the predetermined number of VCO clock cycles, a CARRY signal is generated, and the fractional part of the divisor in the accumulator delays the CARRY signal to define the clock edge of the synthesized target frequency. This signal output is shown as... Figure 1A and Figure 1B The rising edge of the synthesized target waveform. This process of using a divisor with a fractional part is sometimes called phase interpolation.

[0005] When the VCO clock is divided by an integer (an integer without a fraction), the cumulative phase increment of the VCO clock (referred to herein as the cumulative phase integer (phase I) value) in each cycle of the synthesized target waveform will increase by a constant phase integer Δ (phase IΔ) value, which is equal to the number of phase increments included in each VCO clock cycle within a single target output clock cycle. This increase does not include any VCO clock cycle phase fraction (phase F) value. This is as follows: Figure 1A As shown, the VCO clock waveform (top) and the synthesized target output waveform (bottom) are illustrated, where the VCO frequency has been divided by an integer of 8 to produce the synthesized target output waveform. It can be seen that there is no phase fraction component, phase F; that is, the phase fraction (phase F) of the VCO clock cycle is zero.

[0006] Dividing the VCO clock by the fractional component's digital value modulates the value of the phase integer Δ (phase IΔ) between the maximum and minimum values. This is as follows: Figure 1B The diagram shows the VCO clock waveform (top) and the synthesized target output waveform (bottom), where the VCO frequency has been divided by an integer 8 + 1 / 8. The value of the phase integer Δ (phase IΔ) is 8 for the first seven cycles of the synthesizer output waveform and 9 during the eighth cycle. The value of the phase integer Δ (phase IΔ) returns to 8 in the next cycle of the synthesized target clock waveform.

[0007] You can also from Figure 1B The inspection revealed that the VCO clock cycle phase fraction (phase F) is included in each complete cycle of the synthesized target waveform, as indicated by a pair of vertical dimension lines, showing the presence of the VCO clock cycle phase fraction (phase F) value at the rising edge of each cycle of the synthesized target output waveform. The rising edge of each cycle of the synthesized target waveform coincides with the end of the VCO clock cycle phase fraction (phase F) value, as shown... Figure 1B The right-hand diagram shows each of the vertical dimension lines in the image. The VCO clock cycle phase fraction (phase F) value is also periodic. Figure 1B In the example shown, the VCO clock cycle phase fraction (phase F) value is 1 / 8, then 2 / 8, then 3 / 8, then 4 / 8, then 5 / 8, then 6 / 8, then 7 / 8, then 0, and then returns to 1 / 8 of the continuous cycle of the synthesized target waveform.

[0008] A phase interpolator can be used to output a synthesized waveform from a VCO clock. For example... Figure 1C As shown, and as is well known in the art, the digital portion of the phase interpolator is used to generate the accumulated phase integer (phase I) value and the VCO clock cycle phase fraction (phase F) value for synthesizing any output frequency from a given VCO clock output (e.g., by using the FCW accumulator technique described above). This information can then be used by the analog portion of the phase interpolator to generate the synthesized target waveform.

[0009] As mentioned above, when the VCO clock signal is divided into numbers containing fractional components, the frequency synthesizer operation requires dynamic values ​​for both integer and fractional inputs to the analog section of the phase interpolator because the VCO clock output is not divided by a constant integer for each cycle of the target output clock. Different patterns of dynamic values ​​will be needed for each frequency to be generated.

[0010] Now for reference Figure 2A set of three tables is used to generate the output frequency from the VCO oscillator. These tables show the cumulative phase integer (phase I), phase integer Δ (phase IΔ), and VCO clock cycle phase fraction (phase F) values ​​generated by three illustrative VCO non-integer division values: 8+1 / 8, 8+3 / 8, and 9+7 / 8, respectively. Each column of each table shows the cumulative phase integer (phase I), phase integer Δ (phase IΔ), and VCO clock cycle phase fraction (phase F) components for a consecutive single cycle of the synthesized target waveform. The top line in each table is the cumulative phase integer (phase I) value, which is the total number of cumulative quantized phase increments. This number resets each... n The period of the synthesized target waveform, where n It is the denominator of the fractional part of the VCO clock frequency divided as a divisor of the synthesized target waveform. Figure 2 In each of the three illustrative examples shown, n=8 The second row in each table is the phase integer Δ (phase IΔ) value, which is the integer of the VCO cycle that occurs during a single cycle of the synthesized target waveform. For example, with a phase integer Δ (phase IΔ) value of 8, the immediately preceding cumulative phase integer I value of the previous single cycle of the synthesized target waveform will be less than the current cumulative phase integer I value (e.g., if the immediately preceding cumulative phase integer I value is 40, then the cumulative phase integer I value of the current single cycle of the synthesized target waveform will be 48). The third row in each table is the current VCO clock cycle phase fraction (phase F) value, which is the fractional part of the VCO cycle of the current single cycle of the synthesized target waveform. The fourth row in each table is the VCO clock cycle phase fraction (phase F) value expressed in terms of VCO clock cycle phase in the system, where, as an example, each VCO clock cycle is quantized into 1024 phase increments. For example, it can be seen that in a system where each VCO clock cycle is quantized into 1024 phase increments, 3 / 8 of the VCO clock cycle phase fraction is equal to 384 of the VCO clock cycle phase (=1024×3 / 8).

[0011] according to Figure 2 Upon inspection, those skilled in the art will observe the periodic behavior of the phase integer Δ (phase IΔ) value and the VCO clock cycle phase fraction (phase F) value, where the integer part is modulated between 8 and 9, and where VCO = 8, the fractional part is the divisor of 8, with the value in the ninth column of each table being the same as the value in the first column of that table. The modulation of the phase integer Δ (phase IΔ) value can be referred to as a "seam".

[0012] Those skilled in the art will understand that a different table will be generated for each individual value of the VCO fractional divisor. They will also understand that before the phase integer Δ (phase IΔ) begins to repeat, the number of columns in any table will be equal to the denominator of the value of the VCO periodic phase fraction (phase F).

[0013] Because no phase interpolator will perfectly insert the phase, it is expected that the phase interpolator will have an integral nonlinearity (INL) error. This means that for a given fractional value, the phase interpolator will not perfectly insert the fractional value within the VCO clock cycle. In the prior art, calibration RAM circuitry systems have been used to correct the INL for a given fraction. Summary of the Invention

[0014] According to one aspect of the invention, a circuit for correcting the nonlinearity error of the phase interpolator flip-over integral includes: a flip-over detector circuit for detecting when a phase interpolator flip-over event (hereinafter referred to as an "interpolator flip-over event") occurs; and a correction circuit that, when the flip-over detector circuit detects the interpolator flip-over event, adds a signed pre-distortion correction to the phase fraction of the VCO clock cycle.

[0015] According to one aspect of the invention, the circuit further includes an integral nonlinear distortion pre-correction circuit for pre-correcting the phase fraction of the VCO clock cycle for integral nonlinear distortion.

[0016] According to one aspect of the invention, the flip detector circuit includes a forward flip detector circuit and a reverse flip detector circuit, the former detecting when a forward interpolator flip event occurs, and the latter detecting when a reverse interpolator flip event occurs.

[0017] According to one aspect of the invention, a forward flip detector circuit includes a circuit that compares the actual phase integer Δ with the expected value of the phase integer Δ, and detects a forward interpolator flip event when the actual value of the phase integer Δ is equal to the expected value of the phase integer Δ plus 1; and a reverse flip detector circuit includes a circuit that compares the actual value of the phase integer Δ with the expected value of the phase integer Δ, and detects a reverse interpolator flip event when the actual value of the phase integer Δ is equal to the expected value of the phase integer Δ minus 1.

[0018] According to one aspect of the invention, a circuit that compares the actual phase integer Δ and detects a forward interpolator flip event when the compared Δ equals a expected increment of 1 includes a flip-flop, a subtractor, and a magnitude comparator. The flip-flop has an input showing the current accumulated phase integer value and an output showing the immediately preceding accumulated phase integer value. The subtractor subtracts the current accumulated phase integer value from the immediately preceding accumulated phase integer value to generate the actual phase integer Δ. The magnitude comparator compares the output of the subtractor with the expected phase integer Δ value plus 1. A circuit that compares the actual phase integer Δ and detects a reverse interpolator flip event when Δ equals a expected Δ minus 1 includes a flip-flop, a subtractor, and a magnitude comparator. The flip-flop has an input showing the current accumulated phase integer value and an output showing the immediately preceding accumulated phase integer value. The subtractor subtracts the current accumulated phase integer value from the immediately preceding accumulated phase integer value to generate the actual phase integer Δ. The magnitude comparator compares the output of the subtractor with the expected phase integer Δ value minus 1.

[0019] According to one aspect of the invention, the circuit further includes: circuitry for setting a forward interpolator flip event flag on the CARRY signal when a forward interpolator flip event is detected; and circuitry for setting a reverse interpolator flip event flag on the CARRY signal when a reverse interpolator flip event is detected.

[0020] According to one aspect of the invention, when an interpolator flip event is detected, a correction circuit adds a signed predistortion correction to the VCO clock cycle phase component value. The correction circuit includes: a positive signed predistortion correction circuit that adds a first positive signed predistortion correction to the VCO clock cycle phase component value on the CARRY signal after a positive interpolator flip event is detected; and a negative signed predistortion correction circuit that adds a first negative signed predistortion correction to the VCO clock cycle phase component value on the CARRY signal after a negative interpolator flip event is detected.

[0021] According to one aspect of the invention, the circuit further includes circuitry for setting a second forward interpolator flip event flag on the CARRY signal after setting a forward interpolator flip event flag; and circuitry for setting a second reverse interpolator flip event flag on the CARRY signal after setting a reverse interpolator flip event flag.

[0022] According to one aspect of the invention, the circuit further includes: a positive-signed predistortion correction circuit, which is used to add a second positive-signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal after setting the second interpolator flip event flag; and a negative-signed predistortion correction circuit, which is used to add a negative-signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal after setting the second interpolator flip event flag.

[0023] According to one aspect of the invention, the circuit further includes: a second positive-signed predistortion correction circuit, which is used to add a second positive-signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal after setting the second interpolator flip event flag; and a second negative-signed predistortion correction circuit, which is used to add a second negative-signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal after setting the second interpolator flip event flag.

[0024] According to one aspect of the present invention, a method for correcting nonlinearity error of phase interpolator flip-over integral includes: detecting when a phase interpolator flip-over event occurs, and when an interpolator flip-over event has been detected, adding a signed predistortion correction to the phase fraction of the VCO clock cycle.

[0025] According to one aspect of the invention, detecting when an interpolator flip event occurs includes determining whether a forward interpolator flip event has occurred and determining whether a reverse interpolator flip event has occurred.

[0026] According to one aspect of the invention, determining whether a forward interpolator flip event has occurred includes comparing the actual phase integer Δ between the current accumulated phase integer value and the immediately preceding accumulated phase integer value with the expected phase integer Δ, and indicating that a forward interpolator flip event has occurred when the actual phase integer Δ is equal to the expected phase integer Δ plus 1. Determining whether a reverse interpolator flip event has occurred includes comparing the actual phase integer Δ between the current accumulated phase integer value and the immediately preceding accumulated phase integer value with the expected phase integer Δ, and indicating that a reverse interpolator flip event has occurred when the actual phase integer Δ is equal to the expected phase integer Δ minus 1.

[0027] According to one aspect of the invention, comparing the actual phase integer Δ between the current accumulated phase integer value and the immediately preceding accumulated phase integer value with a expected Δ, and indicating a forward interpolator flip event when the actual phase integer Δ equals the expected Δ plus 1, includes: subtracting the current accumulated phase integer value from the immediately preceding accumulated phase integer value and comparing the difference with the expected phase integer Δ plus 1; and comparing the actual phase integer Δ between the current accumulated phase integer value and the immediately preceding accumulated phase integer value with the expected Δ, and indicating a reverse interpolator flip event when the actual phase integer Δ equals the expected phase integer Δ minus 1, includes: subtracting the current accumulated phase integer value from the immediately preceding accumulated phase integer value and comparing the difference with the expected Δ minus 1.

[0028] According to one aspect of the invention, indicating a forward interpolator flip event when the actual phase integer increment is equal to the expected phase integer Δ plus 1 includes setting a forward interpolator flip event flag, and indicating a reverse interpolator flip event when the actual phase integer Δ is equal to the expected phase integer Δ minus 1 includes setting a reverse interpolator flip event flag.

[0029] According to one aspect of the invention, when an interpolator flip event is detected, adding a signed predistortion correction to the VCO clock cycle phase component value includes: adding a first positive signed predistortion correction to the VCO clock cycle phase component value when a positive interpolator flip event has been detected, and adding a first negative signed predistortion correction to the VCO clock cycle phase component value when a negative interpolator flip event has been detected.

[0030] According to one aspect of the invention, the method further includes: after adding a first positive band-signed predistortion correction to the VCO clock cycle phase fraction value, adding a second positive band-signed predistortion correction to the VCO clock cycle phase fraction value; and after adding the first positive band-signed predistortion correction to the VCO clock cycle fraction portion of the phase interpolator, adding a second negative band-signed predistortion correction to the VCO clock cycle phase fraction value. Attached Figure Description

[0031] The invention will now be explained in more detail with reference to the embodiments and accompanying drawings, in which: Figure 1A and Figure 1B It is a waveform diagram illustrating the concepts of phase integer Δ, VCO clock cycle phase fraction, and flip in a frequency synthesizer environment; Figure 1C This is a block diagram of an illustrative phase interpolator that can be used in a frequency synthesizer; Figure 2It is a table showing the cumulative phase integer (phase I), phase integer Δ (phase IΔ), and VCO clock cycle phase fraction (phase F) values ​​generated by three illustrative VCO division values; Figure 3 This is a block diagram of a circuit for detecting both forward and backward flips according to one aspect of the present invention. Figure 4 This is a block diagram of a circuit according to one aspect of the invention that provides a signed additive correction value to provide predistortion to a VCO periodic phase fraction (phase F), the VCO periodic phase fraction being provided to a phase interpolator at both the forward flip time and the backward flip event. Figure 5 This is a flowchart illustrating an exemplary method for correcting nonlinearity errors in the phase interpolator flip-integral according to one aspect of the present invention; and Figure 6 This is a flowchart illustrating another illustrative method for correcting nonlinear errors in the phase interpolator flip integral according to an aspect of the invention. Detailed Implementation

[0032] Those skilled in the art will recognize that the following description is merely illustrative and not intended to be limiting in any way. Other embodiments will readily occur to those skilled in the art.

[0033] A large variation in the INL error is observed in the circuit simulation because the phase to be interpolated undergoes a flip event. The flip event occurs at the seam and is defined as the value of the phase integer Δ (phase IΔ) between its minimum and maximum values ​​(i.e., at...). Figure 2 In each table, the transition points are from 8 to 9, and from 9 to 8. The flip event occurs when the value of the phase integer Δ (phase IΔ) transitions from low to high (i.e., Figure 2 The positive flip event occurs at 8 to 9 (in the equation), and the value of the phase integer Δ (phase IΔ) transitions from high to low (i.e., Figure 2 The inverse flip event occurs when the synthesized target waveform passes through the flip. This is attributed to the internal power rail voltage being disturbed when the value of the phase integer Δ (phase IΔ) changes (increases to decreases or decreases to increase). After the fractional phase value presented in the second VCO clock cycle following the flip, the internal power rail voltage stabilizes and the INL error caused by the disturbance is not significant.

[0034] Without significant system-level complexity and hardware cost, it is impossible to properly calibrate the aforementioned flip-type INL errors using calibration RAM. This is because each frequency to be generated requires values ​​for different patterns of the phase integer Δ (phase IΔ) and the phase fraction of the VCO clock cycle (phase F), and seam errors behave differently for each frequency. The distortion caused by flip or seam errors can exceed the natural INL of the phase interpolator, resulting in significant additional deterministic jitter. Compensating for this with each frequency variation would require an unreasonably large calibration RAM and continuous calibration. Even with the increased hardware and complexity, the results are often insufficient.

[0035] According to the present invention, the VCO clock cycle phase fraction (phase F) value sent to the phase interpolator is modified at two consecutive VCO clock cycle fraction (phase F) values ​​after the flip event. This can be regarded as a pre-distorted phase value to be interpolated. The pre-distorted phase value can be used to calibrate the INL associated with the seam INL error to reduce interpolation error.

[0036] According to an embodiment of the invention, the error correction hardware generates phase predistortion at two consecutive VCO clock cycle fractions (phase F) values, following both the forward (phase IΔ transitions from low to high) and reverse (phase IΔ transitions from high to low) directions. The error correction hardware generates phase F predistortion that coincides with the modulation of the integer value of either the forward or reverse flip event. The error correction hardware also generates phase F predistortion to correct the error of the second phase F value immediately after modulating the phase integer Δ (phase IΔ) value.

[0037] According to one aspect of the invention, predistortion is automatically adjusted as the frequency changes.

[0038] According to this embodiment, the detection hardware monitors the state of the digital section of the phase interpolator to detect forward and reverse flip events. Then, the detection hardware triggers error correction hardware to pre-distort the phase fraction (phase F) value of the VCO clock cycle to be interpolated, taking into account the expected distortion in the synthesized target waveform.

[0039] Now for reference Figure 3 The block diagram depicts detection hardware in the form of a circuit 10 for detecting both forward and backward flips according to an aspect of the invention.

[0040] Circuit 10 is driven by the digital section 12 of a phase interpolator, which generates the phase to be interpolated. The digital section 12 of the phase interpolator generates an accumulated phase integer (phase I) value output on line 14, a VCO clock cycle phase fraction (phase F) value output on line 16, and asserts the CARRY signal output on line 18. Figure 3In one embodiment of the invention depicted, the accumulated phase integer (phase I) value output 14 is a 6-bit value, and the VCO clock cycle phase fraction F value output 16 is a 12-bit value. However, those skilled in the art will understand that different resolutions of the accumulated phase integer (phase I) value and the VCO clock cycle phase fraction (phase F) value are within the scope of the invention. As is known in the art, a CARRY signal can be provided to a circuit system not used in this invention, which delays the time period equivalent to the accumulated phase integer (phase F) value output on line 16 to define the edges of each new cycle of the synthesized target clock waveform.

[0041] During the assertion, the CARRY signal triggers data flip-flops 20 and 22, with data flip-flop 22 cascaded with data flip-flop 20, to capture consecutive accumulated phase integer (phase I) values ​​14 and VCO clock cycle phase fraction (phase F) values ​​output 16. The accumulated phase integer (phase I) value on line 14 and the VCO clock cycle phase fraction (phase F) value on line 16 are locked into data flip-flop 20 on the CARRY signal assertion on line 18. On the next CARRY signal assertion on line 18, the accumulated phase integer (phase I) value and the VCO clock cycle phase fraction (phase F) value at the output of data flip-flop 20 are locked into data flip-flop 22 and appear at its outputs 24 and 26, while the consecutive accumulated phase integer (phase I) values ​​on line 14 and the VCO clock cycle phase fraction (phase F) values ​​on line 16 are locked into data flip-flop 20. The output of data trigger 22 on lines 24 and 26 provides the cumulative phase integer (phase I) value and VCO clock cycle phase fraction (phase F) value output of the two consecutive CARRY signal assertions delayed on line 18.

[0042] Circuit 10 includes a flip detector circuit shown within dashed line 28, which includes a forward flip detector circuit shown within dashed line 30 and a reverse flip detector circuit shown within dashed line 32. The data trigger 20 is identical for both the forward flip detector circuit 30 and the reverse flip detector circuit 32.

[0043] The subtractor 34 shared by both the forward flip detector circuit 30 and the reverse flip detector circuit 32 subtracts the current accumulated phase integer (phase I) value output 14 from the most recent value, i.e., the previous accumulated phase integer (phase I) value that appeared at the output of the data trigger 20. Its output on line 36 represents the actual phase integer Δ (phase IΔ) value of the current accumulated phase integer (phase I) value (i.e., the difference between the current accumulated phase integer (phase I) value output 14 and the previous accumulated phase integer (phase I) value, i.e., the accumulated phase integer (phase I) value output 14 before the most recent CARRY signal assertion).

[0044] The expected phase integer Δ (NOM_DELTA) value at line 38 is the nominal integer value of the phase integer Δ during the non-flipping period (e.g., Figure 2 The "8" in the top and center of the table and Figure 2 The value of the expected phase integer Δ (NOM_DELTA) is incremented by 1 in the base table and provided to both the forward flip detector circuit 30 and the reverse flip detector circuit 32. In the forward flip detector circuit 30, the expected phase integer Δ (NOM_DELTA) value is incremented by 1, as shown by reference numeral 40 in the adder 42. The output of the adder 42 is compared with the actual phase integer Δ (phase IΔ) value calculated by the subtractor 34 at line 36 by the magnitude comparator 44. If the output of the magnitude comparator 44 at line 46 is false (i.e., the actual phase integer Δ (phase IΔ) value at line 36 is not equal to the incremented expected phase integer Δ (NOM_DELTA) value at the output of the adder 42), then no forward flip event has occurred. If the output of the magnitude comparator 44 at line 46 is true (i.e., the actual phase integer Δ (phase IΔ) value at line 36 is equal to the incremented expected phase integer Δ (NOM_DELTA) value at the output of the adder 42), then a forward flip event has occurred.

[0045] In the inversion detector circuit 32, the expected phase integer Δ (NOM_DELTA) value is decremented by 1, as shown by reference numeral 48 in the adder 50. The output of the adder 50 is compared with the actual phase integer Δ (phase IΔ) value calculated by the subtractor 34 at line 36 by the magnitude comparator 52. If the output of the magnitude comparator 52 at line 54 is false (i.e., the actual phase integer Δ (phase IΔ) value at line 36 is not equal to the decremented expected phase integer Δ (NOM_DELTA) value at the output of the adder 50), no inversion event has occurred. If the output of the magnitude comparator 52 at line 54 is true (i.e., the actual phase integer Δ (phase IΔ) value at line 36 is equal to the decremented expected phase integer Δ (NOM_DELTA) value at the output of the adder 50), an inversion event has occurred.

[0046] The true or false output of comparator 44 on line 46 is latched to data trigger 56 to generate an FDET output on line 58, which is true only if a positive toggle event occurred before the most recent CARRY signal assertion. Data trigger 56 is circuitry used to set the positive interpolator toggle event flag FDET on the CARRY signal assertion when a positive interpolator toggle event has been detected. The output of data trigger 56 is the positive interpolator toggle event flag FDET. The positive interpolator toggle event flag FDET output of data trigger 56 is latched to data trigger 60 on a subsequent CARRY signal assertion to generate an F2DET output on line 62, which is true only if a positive toggle event has already been latched to data trigger 56 on the immediately preceding CARRY signal assertion. Data trigger 60 is circuitry used to set a second positive interpolator toggle event flag on the CARRY signal after setting the first positive interpolator toggle event flag. The output of data trigger 60 is the second positive interpolator flip event flag F2DET.

[0047] Similarly, the true or false output of the magnitude comparator 52 is latched into the data trigger 64 on the next CARRY signal assertion to generate an RDET output on line 66, which is true only if a reverse flip event occurred before the most recent CARRY signal assertion. The data trigger 64 is a circuit for setting the reverse interpolator flip event flag RDET on the CARRY signal assertion when a reverse interpolator flip event has been detected. The output of the data trigger 64 is the reverse interpolator flip event flag RDET. The reverse interpolator flip event flag RDET output of the data trigger 64 is latched into the data trigger 68 on a subsequent CARRY signal assertion to generate an R2DET output on line 70, which is true only if a reverse flip event has been latched into the data trigger 64 on the immediately preceding CARRY signal assertion. Therefore, the data trigger 68 is a circuit for setting a second reverse interpolator flip event flag R2DET on the CARRY signal after setting the reverse interpolator flip event flag RDET. The output of data trigger 68 is the second inverse interpolator flip event flag R2DET.

[0048] Once a forward or reverse flip event is detected, correction is performed by providing a signed flip predistortion correction value to the output of the calibration RAM, which provides correction for the expected INL error from the phase interpolator, as will be explained further below.

[0049] Each new period of the synthesized target waveform will include an integer number of VCO periods (cumulative phase integer (phase I) values) and a VCO period fraction (phase F) value. The integer number of differences in the VCO periods between two consecutive synthesized target waveform periods interpolated by the phase interpolator will be the phase integer Δ (phase IΔ), such as... Figure 2 As mentioned in the table. For the case where the VCO frequency is divided by 8 + 1 / 8, the phase integer Δ (phase IΔ) value will be 8 until the positive flip state, where it will be 9 for one synthesized target waveform period. In this example, the expected phase integer Δ (NOM_DELTA) value control input is programmed to be 8, where the nominal integer value of the phase integer Δ during non-flip events is "8". The expected phase integer Δ (NOM_DELTA) value 1 will be equal to "flip" 9 to assert the positive interpolator flip event flag FDET output at the flip event. This detects the period of the synthesized target waveform where a positive flip has occurred. Figure 3 The detection hardware 10 identifies the synthetic target waveform period to which correction will be applied. For the 9+7 / 8 case, the expected phase integer Δ (NOM_DELTA) value will be 9 until the flip state, where it will be 8 for one synthetic target waveform period. In this example, the expected phase integer Δ (NOM_DELTA) value control input will be programmed to 9, where the nominal integer value of the phase integer Δ during the non-flip period on the synthetic target waveform period is "9". The expected phase integer (NOM_DELTA) value -1 will be equal to "flip" 8 to assert the inverse interpolator flip event flag RDET output. This is the period of the synthetic target waveform where an inverse flip occurs. These flip periods are identified and used to provide pre-distortion correction for calibration, such as... Figure 4 What the lieutenant general saw.

[0050] Now for reference Figure 4The correction circuit 80 serves as the input to the outputs 58, 62, 66, and 70 of FDET, F2DET, RDET, and R2DET, respectively, to pass the predistortion correction value. The forward interpolator toggle event flag FDET on line 58 is used to gating the signed correction value FixF stored at reference numeral 82 as the first signed forward correction value (which may be an 8-bit value) through AND gate 84. The reverse interpolator toggle event flag RDET on line 66 is used to gating the signed correction value FixR stored at reference numeral 86 as the first signed reverse correction value (which may be an 8-bit value) through AND gate 88. The second forward interpolator toggle event flag F2DET on line 62 is used to gating the signed correction value Fix2F stored at reference numeral 90 as the second forward correction value (which may be an 8-bit value) through AND gate 92. The second inverse interpolator toggle event flag R2DET on line 70 is used to gating the signed correction value Fix2R stored at reference numeral 94 as the second signed inverse correction value (which may be an 8-bit value) through AND gate 96. Therefore, the flags on inputs FDET, F2DET, RDET, and R2DET 58, 62, 66, and 70 are used to gating one of the signed correction values ​​FixF, FixR, Fix2F, and Fix2R stored at reference numerals 82, 86, 90, and 94, respectively.

[0051] The outputs of AND gates 84 and 88 are combined in OR gate 98 (which may be an 8-bit value), and the outputs of AND gates 92 and 96 are combined in OR gate 100 (which may be an 8-bit value). The outputs of OR gates 98 and 100 are combined in OR gate 102, which is controlled by one of the signed correction values ​​FixF, FixR, Fix2F, and Fix2R (which may be 8-bit values) stored on reference numerals 82, 86, 90, and 94, respectively.

[0052] From Figure 3 The VCO period fraction (phase F) value of line 26 of the circuit is used as the address of calibration RAM 104 (for pre-correction of integral nonlinear distortion), as is known in the art. Calibration RAM 104 is an integral nonlinear distortion pre-correction circuit in the form of a lookup table, which provides the VCO period fraction phase F value on line 106, which can be a 12-bit value, plus a signed correction value associated with the VCO period fraction (phase F) value on line 108, which can be a 6-bit value. These values ​​are... Figure 3 The CARRY signal assertion on the CARRY output 18 of the digital section of PI 12 is latched to the data trigger 110. The latched outputs appear on lines 112 and 114, respectively, with the value on line 112 being a 12-bit value and the value on line 114 being a 6-bit value.

[0053] In adder 116, the signed lockout correction value on line 114 is added to the VCO period fraction (phase F) value on line 112. The output of adder 116 is the INL correction value (which can be a 12-bit value). The INL correction value is added in signed adder 118 to one of the signed correction values ​​FixF, FixR, Fix2F, and Fix2R that appear at the output of OR gate 102. The output of OR gate 102 will be zero unless one of the FDET, F2DET, RDET, R2DET markers 58, 62, 66, and 70 has reached the output of OR gate 102 via one of the predistortion correction values ​​FixF, FixR, Fix2F, and Fix2R on lines 82, 86, 90, and 94, respectively.

[0054] Therefore, FDET, F2DET, RDET, R2DET inputs 58, 62, 66, and 70 are single-hot markers (meaning that only one of them can be asserted during each cycle). In an exemplary embodiment of the invention, the FixF, FixR, Fix2F, and Fix2R inputs on lines 82, 86, 90, and 94 are 8-bit signed values ​​that are added to / subtracted from the value of the VCO cycle fraction (phase F) output to be interpolated in the analog portion of the PI.

[0055] When the forward interpolator toggle event flag FDET is asserted, the FixF value is propagated to the signed adder 118. When the second forward interpolator toggle event flag F2DET is asserted, the Fix2F value is propagated to the signed adder 118. When the reverse interpolator toggle event flag RDET is asserted, the FixR value is propagated to the signed adder 118. When the second forward interpolator toggle event flag R2DET is asserted, the Fix2R value is propagated to the signed adder 118.

[0056] FixF 82, AND gate 84, OR gate 98, OR gate 102, and signed adder 118 together form a positive signed predistortion correction circuit, used to add positive signed predistortion correction to the phase fraction portion of the phase interpolator on the CARRY signal after setting the positive interpolator flip event flag FDET. FixR 86, AND gate 88, OR gate 98, OR gate 102, and signed adder 118 together form a negative signed predistortion correction circuit, used to add negative signed predistortion correction to the phase fraction portion of the phase interpolator on the CARRY signal after setting the negative interpolator flip event flag RDET. Fix2F 90, AND gate 92, OR gate 100, OR gate 102, and the signed adder 118 together form a second positive signed predistortion correction circuit, used to add the second positive signed predistortion correction to the phase fraction portion of the phase interpolator on the CARRY signal after setting the second positive interpolator toggle event flag F2DET. Fix2R 94, AND gate 96, OR gate 100, OR gate 102, and the signed adder 118 together form a second negative signed predistortion correction circuit, used to add the second negative signed predistortion correction to the phase fraction portion of the phase interpolator on the CARRY signal after setting the second negative interpolator toggle event flag R2DET.

[0057] The signed values ​​of FixF, FixR, Fix2F, and Fix2R at reference numbers 82, 86, 90, and 94 in the attached diagram can be determined by initial system calibration or by simulation, and can be stored in non-volatile memory or loaded into non-volatile memory during system startup.

[0058] The output of the signed adder 118 (which can be a 12-bit value) is latched by a data flip-flop 120, and controlled by... Figure 3 The CARRY signal timing is on the CARRY output 18 of the digital section of PI12, and the corrected VCO cycle fraction (phase F) value (which can be a 12-bit value) is available on line 122.

[0059] The corrected VCO cycle fraction (phase F) value on line 122 allows for the correction of dynamic INL by predistorting the VCO cycle fraction (phase F) value to be interpolated, taking into account the dynamic INL that will occur during the flip cycle and subsequent cycles.

[0060] Now for reference Figure 5 The flowchart illustrates a method 130 for correcting nonlinearity errors in the inversion integral of a phase interpolator according to one aspect of the invention. The method begins at reference numeral 132 in the appendix.

[0061] At reference numeral 134, an interpolator flip event occurs when the phase integer portion of the phase interpolator is detected. At reference numeral 136, when an interpolator flip event has been detected, a signed pre-distortion correction is added to the VCO period fraction F value of the phase interpolator. The method ends at reference numeral 138.

[0062] Now for reference Figure 6 The flowchart illustrates a method 140 for correcting nonlinearity errors in the inversion integral of a phase interpolator according to one aspect of the invention. The method begins at reference numeral 142. In some embodiments, method 140 implements additional optional details of method 130.

[0063] At reference numeral 144, at the current CARRY output, i.e., at the assertion of the CARRY signal, a pre-correction is applied to the fractional part of the phase interpolator signal to apply integral nonlinear distortion. At reference numeral 146, the cumulative phase integer (phase I) value of the digital portion 12 of the phase interpolator is checked at the current CARRY output. At reference numeral 148, the cumulative phase integer (phase I) value of the phase interpolator signal at the current assertion of the CARRY signal is subtracted from the cumulative phase integer (phase I) value of the phase interpolator signal at the most recent past assertion of the CARRY signal.

[0064] At point 150 in the attached diagram, determine whether subtracting results in the expected Δ value. Figure 3 (NOM_DELTA value 38). If the subtraction results in the expected Δ value, the method returns to Appendix 144. If the subtraction does not result in the expected Δ value, the method proceeds to Appendix 152, where it is determined whether the result of the subtraction is one more or less than the expected Δ value. If the result of the subtraction is one more or less than the expected Δ value, a flip event occurs.

[0065] If the subtraction result is one more or one less than the expected Δ value, the flip event is a positive flip event, and the method proceeds to reference numeral 154, where the positive interpolator flip event flag FDET is set, and the first signed pre-distortion correction value for the positive flip is added to the VCO period fraction (phase F) value of the phase interpolator signal at the next assertion of the CARRY signal. The method then proceeds to reference numeral 156, where at the second next assertion of the CARRY signal, the second positive interpolator flip event flag F2DET is set, and the second signed pre-distortion correction value for the positive flip is added to the VCO period fraction (phase F) value of the phase interpolator signal. The method then returns to reference numeral 144.

[0066] If the subtraction result is less than the expected Δ value, the flip is a reverse flip, and the method proceeds to Appendix 158, where the reverse interpolator flip event flag RDET is set, and after the next assertion of the CARRY signal, a first signed pre-distortion correction value for the reverse flip is added to the VCO period fraction (phase F) value of the phase interpolator signal. The method then proceeds to Appendix 160, where after the second next assertion of the CARRY signal, a second reverse interpolator flip event flag R2DET is set, and a second signed pre-distortion correction value for the reverse flip is added to the VCO period fraction (phase F) value of the phase interpolator signal. The method then returns to Appendix 144.

[0067] The solution of this invention results in improved deterministic jitter generated by phase interpolation hardware.

[0068] While embodiments and applications of the invention have been shown and described, it will be apparent to those skilled in the art that further modifications can be made without departing from the inventive concept herein. Therefore, the invention is not limited except in the spirit of the appended claims.

Claims

1. A circuit for correcting the nonlinearity error of the phase interpolator's flip-over integral, comprising: A flip detector circuit, comprising a forward flip detector circuit and a reverse flip detector circuit, wherein the forward flip detector circuit detects when a forward flip event of the phase interpolator occurs, and the reverse flip detector circuit detects when a reverse flip event of the phase interpolator occurs; as well as The correction circuit adds a signed predistortion correction to the phase fraction of the voltage-controlled oscillator (VCO) clock cycle when the flip detector circuit has detected a positive flip event or a negative flip event of the phase interpolator.

2. The circuit according to claim 1, further comprising an integral nonlinear distortion pre-correction circuit, the integral nonlinear distortion pre-correction circuit being used to pre-correct the phase fraction of the VCO clock period for integral nonlinear distortion.

3. The circuit according to claim 1, wherein: The forward flip detector circuit includes a circuit that compares the actual phase integer Δ value with the expected phase integer Δ value, and detects a forward flip event of the phase interpolator when the actual phase integer Δ value equals the expected phase integer Δ value plus 1; and The reverse flip detector circuit includes a circuit that compares the actual phase integer Δ value with the expected phase integer Δ value, and detects a reverse flip event of the phase interpolator when the actual phase integer Δ value is equal to the expected phase integer Δ value minus 1.

4. The circuit according to claim 3, wherein: The circuit that compares the actual phase integer Δ value with the expected phase integer Δ value and detects a positive flip event of the phase interpolator when the actual phase integer Δ value equals the expected phase integer Δ value plus 1 includes a data trigger, a subtractor, and a first magnitude comparator. The data trigger has an input showing the current accumulated phase integer value and an output showing the immediately preceding accumulated phase integer value. The subtractor subtracts the current accumulated phase integer value from the immediately preceding accumulated phase integer value to generate the actual phase integer Δ value. The first magnitude comparator compares the output of the subtractor with the expected phase integer Δ value plus 1. as well as The circuit that compares the actual phase integer Δ value with the expected phase integer Δ value and detects a reverse flip event of the phase interpolator when the actual phase integer Δ value is equal to the expected phase integer Δ value minus 1 includes the data trigger, the subtractor, and the second magnitude comparator. The data trigger has the input where the current accumulated phase integer value appears and the output where the immediately preceding accumulated phase integer value appears. The subtractor subtracts the current accumulated phase integer value from the immediately preceding accumulated phase integer value to generate the actual phase integer Δ value. The second magnitude comparator compares the output of the subtractor with the expected phase integer Δ value minus 1.

5. The circuit of claim 1, wherein the correction circuit adds the signed pre-distortion correction to the VCO clock cycle phase fraction, the correction circuit comprising: A positive-signed predistortion correction circuit, which adds a first positive-signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal assertion after a positive flip event of the phase interpolator has been detected; and a negative-signed predistortion correction circuit, which adds a first negative-signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal assertion after a negative flip event of the phase interpolator has been detected.

6. The circuit according to claim 1, further comprising: Circuitry for setting a positive interpolator flip event flag on the CARRY signal when a positive flip event of the phase interpolator has been detected; as well as A circuit for setting a reverse interpolator flip event flag on the CARRY signal when a reverse interpolator flip event has been detected.

7. The circuit according to claim 6, further comprising: Circuitry for setting a second positive interpolator flip event flag on the CARRY signal assertion after setting the positive interpolator flip event flag; as well as Circuitry for setting a second inverse interpolator flip event flag on the CARRY signal assertion after setting the inverse interpolator flip event flag.

8. The circuit according to claim 7, further comprising: A positively signed predistortion correction circuit is used to add a positively signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal assertion after setting the positive interpolator flip event flag. as well as A reverse-signed predistortion correction circuit is used to add a reverse-signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal assertion after setting the reverse interpolator flip event flag.

9. The circuit according to claim 8, further comprising: The second positive-signed predistortion correction circuit is used to add the second positive-signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal assertion after setting the second positive interpolator flip event flag. as well as The second inverse-signed predistortion correction circuit is used to add the second inverse-signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal assertion after setting the second inverse interpolator flip event flag.

10. A method for correcting nonlinearity error in the flip integral of a phase interpolator, comprising: Detect when a positive flip event of the phase interpolator occurs and when a negative flip event of the phase interpolator occurs; as well as When a positive flip event or a negative flip event of the phase interpolator is detected, a signed predistortion correction is added to the phase fraction of the voltage-controlled oscillator (VCO) clock cycle of the phase interpolator.

11. The method of claim 10, wherein: Detecting whether a positive flip event of the phase interpolator has occurred includes comparing the actual phase integer Δ value between the current accumulated phase integer value and the immediately preceding accumulated phase integer value with the expected phase integer Δ value, and indicating that a positive flip event of the phase interpolator has occurred when the actual phase integer Δ value is equal to the expected phase integer Δ value plus 1; and Detecting whether a reverse flip event of the phase interpolator has occurred includes comparing the actual phase integer Δ value between the current cumulative phase integer value and the immediately preceding cumulative phase integer value with the expected phase integer Δ value, and the phase interpolator reverse flip event occurring when the actual phase integer Δ value is equal to the expected phase integer Δ value minus 1.

12. The method according to claim 11, wherein: Comparing the actual phase integer Δ value between the current accumulated phase integer value and the immediately preceding accumulated phase integer value with the expected phase integer Δ value, and indicating a positive flip event of the phase interpolator when the actual phase integer Δ value equals the expected phase integer Δ value plus 1, includes subtracting the current accumulated phase integer value from the immediately preceding accumulated phase integer value and comparing the difference with the expected phase integer Δ value plus 1; and Comparing the actual phase integer Δ value between the current cumulative phase integer value and the immediately preceding cumulative phase integer value with the expected phase integer Δ value, and indicating the occurrence of a reverse flip event of the phase interpolator when the actual phase integer Δ value is equal to the expected phase integer Δ value minus 1, includes subtracting the current cumulative phase integer value from the immediately preceding cumulative phase integer value and comparing the difference with the expected phase integer Δ value minus 1.

13. The method according to claim 11, wherein: Indicating a positive flip event of the phase interpolator when the actual phase integer Δ value is equal to the expected phase integer Δ value plus 1 includes setting a positive flip event flag for the phase interpolator; as well as Indicating a phase interpolator reverse flip event when the actual phase integer Δ value is equal to the expected phase integer Δ value minus 1 includes setting a phase interpolator reverse flip event flag.

14. The method of claim 10, wherein adding the signed predistortion correction to the VCO clock cycle phase fraction comprises: When a positive flip event of the phase interpolator is detected, a first positive signed predistortion correction is added to the phase fraction of the VCO clock cycle. as well as When a reverse flip event of the phase interpolator is detected, a first reverse signed predistortion correction is added to the phase fraction of the VCO clock cycle.

15. The method of claim 14, further comprising: After the first positive band sign predistortion correction has been added to the VCO clock cycle phase fraction, the second positive band sign predistortion correction is added to the VCO clock cycle phase fraction. as well as After the first positive-signed predistortion correction has been added to the VCO clock cycle phase fraction, the second negative-signed predistortion correction is added to the VCO clock cycle phase fraction.

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