Task mapping, task control, task processing method and processing core, electronic equipment

Abstract

The present disclosure provides a task mapping method, including: determining multiple layers of second matrices according to a first matrix, each layer of the second matrix is ​​divided into at least one second sub-matrix; wherein the elements in the second matrix of the N+1th layer correspond to multiple second sub-matrices of the Nth layer one by one, and the second sub-matrix of the 1st layer is a sub-matrix of the first matrix; mapping at least one second sub-matrix in each layer of the second matrix to multiple processing cores in a multi-core system, each of the processing cores corresponds to a second sub-matrix, so that the processing core calculates the transpose of its corresponding second sub-matrix and stores the calculation result; wherein N is a positive integer. The present disclosure also provides a task control method, a task processing method, an electronic device, a processing core, and an electronic device.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a task mapping method, a task control method, a task processing method, an electronic device, a processing core, and an electronic device. Background Art

[0002] A sparse matrix is ​​a matrix in which the number of zero elements is much greater than the number of non-zero elements, and the distribution of non-zero elements is irregular. Sparse matrices are widely used in real life. In particular, sparse matrices often appear in high-performance computing and machine learning, for example, in data containing counts, data encoding of mapping categories, and subfields of machine learning such as natural language processing (NLP).

[0003] When performing operations such as transposition on a sparse matrix and storing the sparse matrix, it is necessary to store the values ​​of each element in the sparse matrix and its coordinates in the sparse matrix. However, in some related technologies, when the sparse matrix is ​​large in size, the sparse matrix requires more storage space and the amount of calculation is large, and the efficiency of operations involving sparse matrices is low. Summary of the invention

[0004] The present disclosure provides a task mapping method, a task control method, a task processing method, an electronic device, a processing core, and an electronic device.

[0005] In a first aspect, the present disclosure provides a task mapping method, comprising:

[0006] Determine multiple layers of second matrices according to the first matrix, each layer of the second matrix is ​​divided into at least one second sub-matrix; wherein the elements in the second matrix of the N+1th layer correspond one-to-one to the multiple second sub-matrices of the Nth layer, and the second sub-matrix of the 1st layer is a sub-matrix of the first matrix;

[0007] Mapping at least one second submatrix in each layer of the second matrix to a plurality of processing cores in the many-core system, each of the processing cores corresponding to a second submatrix, so that the processing core calculates the transpose of the corresponding second submatrix and stores the calculation result;

[0008] Wherein, N is a positive integer.

[0009] In some embodiments, at least one second submatrix of each layer of the second matrix includes at least one non-zero second submatrix; and the step of mapping at least one second submatrix in each layer of the second matrix to multiple processing cores in the many-core system includes:

[0010] Each non-zero second sub-matrix in each layer of the second matrix is ​​mapped to the plurality of processing cores respectively.

[0011] In some embodiments, the processing core corresponding to the N-th layer second sub-matrix is ​​the N-th layer processing core; and the step of mapping each non-zero second sub-matrix in each layer of the second matrix to the plurality of processing cores comprises:

[0012] Transmitting the first-layer non-zero second submatrix in the first-layer second matrix to the first-layer processing core, so that the first-layer processing core calculates the transpose of its corresponding first-layer non-zero second submatrix;

[0013] The first correspondence between the N-th layer processing core and the first coordinate is transmitted to the N+1-th layer processing core, so that the N+1-th layer processing core determines the second correspondence between the N-th layer processing core and the second coordinate according to the first correspondence; the first coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1-th layer second matrix; the second coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the transposed matrix of the N+1-th layer second matrix.

[0014] In some embodiments, the step of determining the multi-layer second matrix according to the first matrix includes:

[0015] Determine a target size according to the size of the first matrix, where the target size is the size of the second submatrix of each layer;

[0016] A multi-layer second matrix is ​​determined according to the first matrix and the target size.

[0017] In some embodiments, each layer of the second sub-matrix is ​​a square matrix.

[0018] In a second aspect, an embodiment of the present disclosure provides a task control method, including:

[0019] Determine a target processing core according to a mapping relationship between at least one second submatrix in the multi-layer second matrix and multiple processing cores in the many-core system; the target processing core is at least one of the multiple processing cores storing target data; the target data is a transposed matrix of a submatrix of the first matrix corresponding to task data of the task to be processed;

[0020] Transmitting the task data to the target processing core so that the target processing core reads the target data and performs operations corresponding to the task data;

[0021] Among them, the multi-layer second matrix is ​​determined according to the first matrix, and each layer of the second matrix is ​​divided into at least one second sub-matrix; the elements in the N+1th layer second matrix correspond one-to-one to multiple Nth layer second sub-matrices, and the 1st layer second sub-matrix is ​​a sub-matrix of the first matrix; each of the multiple processing cores corresponds to a second sub-matrix, and the processing core stores the calculation result obtained by calculating the transpose of the corresponding second sub-matrix; N is a positive integer.

[0022] In some embodiments, at least one second submatrix of each layer of the second matrix includes at least one non-zero second submatrix; the mapping relationship between at least one second submatrix in the multi-layer second matrix and the multiple processing cores in the many-core system is the mapping relationship between each non-zero second submatrix in each layer of the second matrix and the multiple processing cores; the processing core corresponding to the N-th layer second submatrix is ​​the N-th layer processing core; the 1st layer processing core stores the calculation result obtained by calculating the transpose of the corresponding 1st layer non-zero second submatrix; the N+1th layer processing core stores the second correspondence between the N-th layer processing core and the second coordinate determined according to the first correspondence between the N-th layer processing core and the first coordinate; the first coordinate is the coordinate of the element in the N+1th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1th layer second matrix; the second coordinate is the coordinate of the element in the N+1th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1th layer in the transposed matrix of the N+1th layer second matrix; the target processing core is one of the at least one 1st layer processing core; according to the mapping relationship between at least one second submatrix in the multi-layer second matrix and the multiple processing cores in the many-core system, the step of determining the target processing core includes:

[0023] When N is greater than 1, determining the N-1th layer processing core corresponding to the target data according to the second corresponding relationship stored in the Nth layer processing core corresponding to the target data;

[0024] When N is equal to 1, the first layer processing core storing the target data is used as the target processing core.

[0025] In some embodiments, the task control method further includes:

[0026] Determine the address of the storage space of each target calculation result in the off-chip storage according to the second corresponding relationship stored in each layer of processing cores; the target calculation result is the calculation result of calculating the transposition of the corresponding first layer non-zero second submatrix calculated by the first layer processing core and stored;

[0027] Control each first-layer processing core to write the target calculation result stored by the first-layer processing core into the off-chip storage according to the address of the storage space of the target calculation result stored by the first-layer processing core in the off-chip storage, wherein each of the target calculation results is spliced ​​into a transposed matrix of the first matrix in the off-chip storage.

[0028] In a third aspect, an embodiment of the present disclosure provides a task processing method, including:

[0029] Receiving a first correspondence between an Nth layer processing core and a first coordinate in a multi-layer second matrix;

[0030] Determine a second corresponding relationship between the Nth layer processing core and the second coordinate according to the first corresponding relationship;

[0031] Among them, each layer of the second matrix in the multi-layer second matrix is ​​divided into at least one second sub-matrix; the elements in the N+1th layer second matrix correspond one-to-one to multiple Nth layer second sub-matrices; each of the multiple processing cores in the many-core system corresponds to a second sub-matrix; the first coordinates are the coordinates of the elements in the N+1th layer second matrix corresponding to the Nth layer second submatrix in the N+1th layer second matrix; the second coordinates are the coordinates of the elements in the N+1th layer second matrix corresponding to the Nth layer second submatrix in the transposed matrix of the N+1th layer second matrix; N is a positive integer.

[0032] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including:

[0033] one or more processors;

[0034] A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the task mapping method described in the first aspect of the embodiment of the present disclosure;

[0035] One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

[0036] In a fifth aspect, an embodiment of the present disclosure provides a processing core, including:

[0037] Includes computing units and cache;

[0038] The computing unit can implement the task control method described in the second aspect of the embodiment of the present disclosure; and / or

[0039] The task processing method described in the third aspect of the embodiment of the present disclosure.

[0040] In a sixth aspect, an embodiment of the present disclosure provides an electronic device, including:

[0041] multiple processing cores; and

[0042] An on-chip network configured to exchange data between the plurality of processing cores and external data;

[0043] One or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the task control method described in the second aspect of the embodiment of the present disclosure; and / or

[0044] The task processing method according to the third aspect of the embodiment of the present disclosure

[0045] In an embodiment of the present disclosure, a solution for performing a transposition operation of a sparse matrix using a many-core system is provided, wherein a multi-layer second matrix is ​​determined based on a first matrix that needs to perform a transposition operation, and the size of the second submatrix of each layer of the second matrix is ​​much smaller than the size of the first matrix; the second submatrices of each layer of the second matrix are mapped to multiple processing cores in the many-core system to perform a transposition operation, and finally a transposition operation result of the first matrix is ​​obtained, thereby achieving a high compression rate for the coordinate dimension of the elements in the matrix and greatly reducing memory overhead; the calculation result of the transposition operation is stored in each processing core of the many-core system, without having to be written to an off-chip storage such as a memory, and also avoiding repeated data movement, thereby improving the efficiency of transposition operations of ultra-large-scale sparse matrices.

[0046] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0048] Figure 1 is a flowchart of a task mapping method in an embodiment of the present disclosure;

[0049] Figure 2 is a schematic diagram of mapping a multi-layer second matrix to a processing core in an embodiment of the present disclosure;

[0050] Figure 3 is a flowchart of some steps in another task mapping method in an embodiment of the present disclosure;

[0051] Figure 4 is a flowchart of some steps in another task mapping method in an embodiment of the present disclosure;

[0052] Figure 5 is a flowchart of some steps in another task mapping method in an embodiment of the present disclosure;

[0053] Figure 6 is a flow chart of a task control method in an embodiment of the present disclosure;

[0054] Figure 7 is a flowchart of some steps in another task control method in an embodiment of the present disclosure;

[0055] Figure 8 is a flowchart of some steps in another task control method in an embodiment of the present disclosure;

[0056] Fig. 9 is a flowchart of a task processing method in an embodiment of the present disclosure;

[0057] Fig.10 is a block diagram of a composition of an electronic device provided by an embodiment of the present disclosure;

[0058] Fig.11 is a block diagram of a processing core provided by an embodiment of the present disclosure;

[0059] Fig.12 It is a block diagram of a composition of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0061] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0062] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0064] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0065] The inventors of the present disclosure have found that in some related technologies, the larger the scale of the sparse matrix, the more bits are needed to store the coordinates of each element in the sparse matrix. For example, storing the coordinates of the elements in a 10 billion-dimensional matrix requires 35 bits (bit) in each row and column. For ultra-large-scale sparse matrices, not only a large amount of storage space is required to store the coordinates of the elements, but also the speed of performing operations involving sparse matrices is relatively slow. In addition, in some related technologies, after performing the transposition operation of the sparse matrix, the result of the transposition operation needs to be transferred to the memory (such as a double data rate synchronous dynamic random access memory (DDR)), and the transposed matrix of the complete sparse matrix is ​​spliced ​​in the memory; when performing subsequent operations, the transposed matrix of the sparse matrix needs to be read from the memory. The above-mentioned process of repeatedly moving data further reduces the efficiency of operations involving sparse matrices.

[0066] In view of this, firstly, refer to Figure 1 The present disclosure provides a task mapping method, comprising:

[0067] In step S110, multiple layers of second matrices are determined according to the first matrix, and each layer of the second matrix is ​​divided into at least one second sub-matrix; wherein the elements in the second matrix of the N+1th layer correspond one-to-one to the multiple second sub-matrices of the Nth layer, and the second sub-matrix of the 1st layer is a sub-matrix of the first matrix;

[0068] In step S120, at least one second sub-matrix in each layer of the second matrix is ​​mapped to multiple processing cores in the many-core system, each processing core corresponds to a second sub-matrix, so that the processing core calculates the transpose of its corresponding second sub-matrix and stores the calculation result; wherein N is a positive integer.

[0069] The embodiment of the present disclosure provides a solution for performing a transposition operation of a sparse matrix using a many-core system. In the embodiment of the present disclosure, the many-core system can be composed of a single chip, and the chip has multiple processing cores. The processing core is the smallest computing unit in the many-core system that can be independently scheduled and has complete computing capabilities; the many-core system can also be composed of multiple chips, and each chip can have multiple processing cores. The embodiment of the present disclosure does not specifically limit this.

[0070] It should be noted that in the embodiments of the present disclosure, multiple processing cores in the many-core system can run program instructions independently or work together to speed up the program execution speed by using the parallel computing capability and provide multi-tasking capabilities. It should also be noted that in the embodiments of the present disclosure, each processing core in the many-core system has an independent cache that can store data such as calculation results obtained by the processing core executing operations.

[0071] In the embodiment of the present disclosure, steps S110 to S120 are intended to calculate the transpose of the first matrix, wherein the first matrix is ​​a sparse matrix. In the multi-layer second matrix determined by step S110, the first-layer second matrix is ​​the first matrix. The multiple first-layer second sub-matrices obtained by dividing the first-layer second matrix are sub-matrices of the first matrix obtained by dividing the first matrix according to the same rule.

[0072] As an optional implementation, each layer of the second matrix is ​​a real number matrix, wherein the elements in the second matrix are all real numbers. For example, if the second submatrix of the Nth layer corresponding to the element in the second matrix of the N+1th layer is a non-zero matrix, the element is 1; if the second submatrix of the Nth layer corresponding to the element in the second matrix of the N+1th layer is a zero matrix, the element is 0. Other numerical values ​​can also be used as elements in the second matrix, and the embodiments of the present disclosure do not specifically limit this.

[0073] like Figure 2 As shown, the first matrix is ​​divided into 16 4*4 sub-matrices, corresponding to the first layer second matrix; the second layer second matrix includes 16 elements, which correspond to the 16 sub-matrices of the first matrix one by one. It should be noted that the sub-matrices obtained by dividing the first matrix can be non-zero matrices or zero matrices. When the first matrix as a sparse matrix is ​​relatively sparse, the number of zero matrices obtained by dividing the first matrix can be greater than the number of non-zero matrices. The second sub-matrix obtained by dividing each layer of the second matrix can be a non-zero matrix or a zero matrix.

[0074] It should be noted that, in step S110, when there are a total of M layers of second matrices and the 1st layer of second matrix is ​​the first matrix, the 1st layer of second matrix, the 2nd layer of second matrix, ..., the M-1th layer of second matrix are divided into multiple second sub-matrices; the Mth layer of second matrix is ​​divided into one second sub-matrix, that is, the Mth layer of second sub-matrix is ​​the Mth layer of second matrix itself.

[0075] In the embodiment of the present disclosure, the multi-layer second sub-matrix is ​​mapped to the multiple processing cores of the many-core system respectively through step S120, and the processing core calculates the transpose of the corresponding second sub-matrix and stores the calculation result. According to the matrix operation rule, in the embodiment of the present disclosure, the transpose of the second sub-matrix of each layer is calculated by the multiple processing cores in the many-core system respectively, and the transpose of the first matrix can be obtained.

[0076] As an optional implementation, in a pre-compiled manner, the multiple processing cores in step S120 have been configured with the operator, parameter and other operation instructions required for calculating the transposition of the second sub-matrix. For example, the processing core can determine how large a transposition operation is to be calculated. The second sub-matrix is ​​transmitted to the processing core via the on-chip network (NOC) in the form of a data stream.

[0077] It should be noted that in the embodiments of the present disclosure, the size of the second submatrix of each layer is smaller than the size of the first matrix, and the storage space required to store the second submatrix of each layer and the result of the transposition operation in the many-core system is much smaller than the storage space required to store the first matrix and the result of the transposition operation, and the amount of calculation of each processing core when performing the transposition operation of the second submatrix is ​​also much smaller than the amount of calculation when performing the transposition operation of the first matrix. Figure 2 As shown, the 16*16 first matrix is ​​divided into 16 4*4 sub-matrices, corresponding to the first-layer second matrix; the second-layer second matrix is ​​also a 4*4 matrix. Storing the coordinates of the elements in the 16*16 first matrix requires 4 bits for each row and column, while the processing core requires 2 bits for each row and column to store the coordinates of the elements in a 4*4 sub-matrix. The hierarchical matrix transposition scheme of the disclosed embodiment, in which multiple first processing cores calculate the transposition of the sub-matrix and the second processing core calculates the transposition of the block matrix, can achieve a high compression rate for the coordinate dimensions of the elements in the matrix, and can greatly reduce memory overhead.

[0078] In the task mapping method provided in the embodiment of the present disclosure, a solution is provided for performing transposition operation of sparse matrices using a many-core system, wherein a multi-layer second matrix is ​​determined according to a first matrix that needs to perform transposition operation, and the scale of the second submatrix of each layer of the second matrix is ​​much smaller than the scale of the first matrix; the second submatrices of each layer of the second matrix are mapped to multiple processing cores in the many-core system to perform transposition operation, and finally the transposition operation result of the first matrix is ​​obtained, thereby achieving a high compression rate for the coordinate dimension of the elements in the matrix and greatly reducing the memory overhead; the calculation result of the transposition operation is stored in each processing core of the many-core system, without having to be written to off-chip storage such as memory, and also avoiding repeated data movement, thereby improving the efficiency of transposition operation of ultra-large-scale sparse matrices.

[0079] In the embodiment of the present disclosure, when at least one second sub-matrix in each layer of the second matrix is ​​respectively mapped to multiple processing cores in the many-core system through step S120, all second sub-matrices in each layer of the second matrix can be mapped to multiple processing cores in the many-core system; or non-zero second sub-matrices in each layer of the second matrix can be mapped to multiple processing cores in the many-core system. It should be noted that, when the first matrix is ​​a sparse matrix, the sub-matrix of the first matrix includes multiple zero matrices; when determining a multi-layer second matrix, if the second sub-matrix of the Nth layer corresponding to the element in the second matrix of the N+1th layer is a non-zero matrix, the element is 1; if the second sub-matrix of the Nth layer corresponding to the element in the second matrix of the N+1th layer is a zero matrix, the element is 0. Therefore, the second sub-matrix of each layer of the second matrix includes non-zero matrices and / or zero matrices. In step S120, mapping the non-zero second sub-matrix in each layer of the second matrix to multiple processing cores in the many-core system can further reduce the occupancy of storage resources and computing resources. Figure 2 An optional implementation of mapping the non-zero second sub-matrices in each layer of the second matrix to multiple processing cores in a many-core system is shown.

[0080] Accordingly, in some embodiments, reference Figure 3 , at least one second sub-matrix of each layer of the second matrix includes at least one non-zero second sub-matrix; step S120 includes:

[0081] In step S121, each non-zero second sub-matrix in each layer of the second matrix is ​​mapped to the plurality of processing cores respectively.

[0082] In the embodiment of the present disclosure, the processing core corresponding to the second submatrix of the Nth layer is the processing core of the Nth layer. The second submatrix of the first layer is a submatrix of the first matrix. The processing core of the first layer calculates the submatrix of the first matrix and stores the transposed matrix of the submatrix of the first matrix; the processing core of the N+1th layer determines the coordinates in the transposed matrix of the second matrix of the N+1th layer corresponding to the processing core of the Nth layer after transposition based on the coordinates in the second matrix of the N+1th layer corresponding to the processing core of the Nth layer before transposition. When the subsequent operation requires the transposed operation result of the first matrix, the processing core of the first layer storing the transposed matrix of the second submatrix of the first layer, that is, the transposed matrix of the submatrix of the first matrix, can be determined layer by layer according to the correspondence between the processing cores and the coordinates stored in the processing cores of each layer.

[0083] Accordingly, in some embodiments, the processing core corresponding to the second sub-matrix of the Nth layer is the processing core of the Nth layer; Figure 4 , step S121 includes:

[0084] In step S121a, the first-layer non-zero second submatrix in the first-layer second matrix is ​​transmitted to the first-layer processing core, so that the first-layer processing core calculates the transpose of its corresponding first-layer non-zero second submatrix;

[0085] In step S121b, the first correspondence between the N-th layer processing core and the first coordinate is transmitted to the N+1-th layer processing core, so that the N+1-th layer processing core determines the second correspondence between the N-th layer processing core and the second coordinate according to the first correspondence; the first coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1-th layer second matrix; the second coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the transposed matrix of the N+1-th layer second matrix.

[0086] In the embodiment of the present disclosure, the sizes of the second sub-matrices of each layer may be the same or different, and the embodiment of the present disclosure does not impose any special limitation on this.

[0087] Accordingly, in some embodiments, reference Figure 5 , step S110 includes:

[0088] In step S111, a target size is determined according to the size of the first matrix, where the target size is the size of the second sub-matrix of each layer;

[0089] In step S112, a multi-layer second matrix is ​​determined according to the first matrix and the target size.

[0090] In the embodiment of the present disclosure, there is no special limitation on the size of the second sub-matrix, and the size of the second sub-matrix can be determined according to the computing power, storage size, and demand for computing efficiency of the many-core system.

[0091] The embodiment of the present disclosure does not impose any special limitation on the second sub-matrix. In some embodiments, each layer of the second sub-matrix is ​​a square matrix.

[0092] Second, refer to Figure 6 , the present disclosure provides a task control method, including:

[0093] In step S210, a target processing core is determined according to a mapping relationship between at least one second sub-matrix in the multi-layer second matrix and multiple processing cores in the many-core system; the target processing core is at least one of the multiple processing cores storing target data; the target data is at least one transposed matrix of a sub-matrix of the first matrix corresponding to the task data of the task to be processed;

[0094] In step S220, the task data is transmitted to the target processing core, so that the target processing core reads the target data and performs operations corresponding to the task data;

[0095] Among them, the multi-layer second matrix is ​​determined according to the first matrix, and each layer of the second matrix is ​​divided into at least one second sub-matrix; the elements in the N+1th layer second matrix correspond one-to-one to multiple Nth layer second sub-matrices, and the 1st layer second sub-matrix is ​​a sub-matrix of the first matrix; each of the multiple processing cores corresponds to a second sub-matrix, and the processing core stores the calculation result obtained by calculating the transpose of the corresponding second sub-matrix; N is a positive integer.

[0096] In the embodiment of the present disclosure, after the multiple processing cores calculate the transposition of the second sub-matrix, the result of the transposition operation is stored in the processing core. When the many-core system executes a task to be processed involving the result of the transposition operation, the control core executes steps S210 to S220, transfers the task data of the task to be processed to the target processing core, and the target processing core executes the operation corresponding to the task data. The embodiment of the present disclosure does not specifically limit the operation corresponding to the task data. For example, the transposed matrix of the sub-matrix of the first matrix and the matrix multiplication operation of the task data, and the matrix addition / subtraction operation.

[0097] The control core may be any processing core in the multi-core system. In the embodiment of the present disclosure, the control core may be any processing core other than the multiple processing cores that calculate the transposition of the second sub-matrix and store the calculation results; or it may be one of the multiple processing cores that calculate the transposition of the second sub-matrix and store the calculation results. The embodiment of the present disclosure does not specifically limit this. For example, when there are a total of M layers of second matrices, and the first layer of the second matrix is ​​the first matrix, the Mth layer of the processing core corresponding to the Mth layer of the second matrix is ​​the control core.

[0098] In the task control method provided by the embodiment of the present disclosure, the calculation result of the transposition operation is stored in each processing core of the many-core system. When it is necessary to execute a pending task involving the transposition operation, the task data of the pending task is transmitted to the target processing core, and the target processing core executes the operation corresponding to the task data. It is not necessary to first transmit the transposed matrix of the sub-matrix of the first matrix calculated by each processing core to an off-chip storage such as a memory, and then read the transposed result of the first matrix from the off-chip storage, thereby avoiding repeated data transfer and improving the efficiency of the ultra-large-scale sparse matrix transposition operation.

[0099] In some embodiments, at least one second submatrix of each layer of the second matrix includes at least one non-zero second submatrix; the mapping relationship between at least one second submatrix in the multi-layer second matrix and the multiple processing cores in the many-core system is the mapping relationship between each non-zero second submatrix in each layer of the second matrix and the multiple processing cores; the processing core corresponding to the N-th layer second submatrix is ​​the N-th layer processing core; the 1st layer processing core stores the calculation result obtained by calculating the transpose of the corresponding 1st layer non-zero second submatrix; the N+1th layer processing core stores the second correspondence between the N-th layer processing core and the second coordinate determined according to the first correspondence between the N-th layer processing core and the first coordinate; the first coordinate is the coordinate of the element in the N+1th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1th layer second matrix; the second coordinate is the coordinate of the element in the N+1th layer second matrix corresponding to the N-th layer non-zero second submatrix in the transposed matrix of the N+1th layer second matrix; the target processing core is one of the at least one 1st layer processing core; refer to Figure 7 , step S210 includes:

[0100] In step S211, when N is greater than 1, the N-1th layer processing core corresponding to the target data is determined according to the second corresponding relationship stored in the Nth layer processing core corresponding to the target data;

[0101] In step S212, when N is equal to 1, the first layer processing core storing the target data is used as the target processing core.

[0102] It should be noted that, when there are a total of M layers of second matrices, and the first layer of second matrices is the first matrix, starting from the Mth layer of processing cores, when N is greater than 1, the processing cores of each layer corresponding to the target data are determined layer by layer by iteratively executing step S211 until N is equal to 1, and the first layer of processing cores storing the target data is used as the target processing core. That is, when N is greater than 1, step S211 is executed once, and N is reduced by 1; if N is still greater than 1 after being reduced by 1, step S211 is continued to be executed; if N is equal to 1 after being reduced by 1, step S212 is executed.

[0103] In the embodiment of the present disclosure, the control core may further control the multiple processing cores to output the results of the transposition operation in the multiple processing cores to an off-chip storage such as a memory. In subsequent calculations, the transposition result of the first matrix may be obtained from the off-chip storage. It should be noted that when the results of the transposition operation in the multiple processing cores are output to an off-chip storage such as a memory, they are directly stored as the transposed matrix of the first matrix.

[0104] It should be noted that, when the non-zero second sub-matrices in each layer of the second matrix are mapped to multiple processing cores in the many-core system, the zero matrices in the sub-matrices of each first matrix need to be supplemented when the results of the transposition operation in the multiple processing cores are output to an off-chip storage such as a memory. The control core determines the address of the results of the transposition operation stored in each processing core in the off-chip storage, thereby ensuring that each processing core can be spliced ​​into a transposed matrix of the first matrix after writing the results of the stored transposed elements to the off-chip storage.

[0105] Accordingly, in some embodiments, reference Figure 8 , the task mapping method further includes:

[0106] In step S231, the address of the storage space of each target calculation result in the off-chip storage is determined according to the second corresponding relationship stored in each layer of processing cores; the target calculation result is the calculation result of the first layer processing core calculating the transposition of the corresponding first layer non-zero second submatrix and storing it;

[0107] In step S232, each first-layer processing core is controlled to write the target calculation result stored by the first-layer processing core into the off-chip storage according to the address of the storage space of the target calculation result stored by the first-layer processing core in the off-chip storage, wherein each of the target calculation results is spliced ​​into a transposed matrix of the first matrix in the off-chip storage.

[0108] Thirdly, refer to Fig. 9 , the present disclosure provides a task processing method, including:

[0109] In step S310, a first correspondence between an Nth layer processing core and a first coordinate in a multi-layer second matrix is ​​received;

[0110] In step S320, a second corresponding relationship between the Nth layer processing core and the second coordinate is determined according to the first corresponding relationship;

[0111] Among them, each layer of the second matrix in the multi-layer second matrix is ​​divided into at least one second sub-matrix; the elements in the N+1th layer second matrix correspond one-to-one to multiple Nth layer second sub-matrices; each of the multiple processing cores in the many-core system corresponds to a second sub-matrix; the first coordinates are the coordinates of the elements in the N+1th layer second matrix corresponding to the Nth layer second submatrix in the N+1th layer second matrix; the second coordinates are the coordinates of the elements in the N+1th layer second matrix corresponding to the Nth layer second submatrix in the transposed matrix of the N+1th layer second matrix; N is a positive integer.

[0112] In the task processing method provided by the embodiment of the present disclosure, the processing core of the many-core system can determine the coordinates in the transposed matrix of the second matrix of the N+1th layer corresponding to the processing core of the Nth layer after transposition based on the coordinates in the second matrix of the N+1th layer corresponding to the processing core of the Nth layer before transposition, so that the many-core system can determine multiple layers of second matrices according to the first matrix that needs to perform the transposition operation, and map the second sub-matrices of each layer of the second matrix to multiple processing cores in the many-core system to perform the transposition operation, and finally obtain the transposition operation result of the first matrix, so as to achieve a higher compression rate of the coordinate dimension of the elements in the matrix and greatly reduce the memory overhead; the calculation result of the transposition operation is stored in the processing core of the many-core system without being written to off-chip storage such as memory, and it also avoids repeated data movement, thereby improving the efficiency of ultra-large-scale sparse matrix transposition operations.

[0113] Fourthly, refer to Fig.10 , an embodiment of the present disclosure provides an electronic device, including:

[0114] One or more processors 101;

[0115] A memory 102 storing one or more programs, which, when executed by one or more processors, enables the one or more processors to implement the task mapping method described in the first aspect of the embodiment of the present disclosure;

[0116] One or more I / O interfaces 103 are connected between the processor and the memory and are configured to implement information exchange between the processor and the memory.

[0117] Among them, the processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU) and the like; the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus) and the like.

[0118] In some embodiments, the processor 101 , the memory 102 , and the I / O interface 103 are connected to each other via a bus 104 , and further connected to other components of the computing device.

[0119] Fifth, refer to Fig.11 , the present disclosure provides a processing core, including:

[0120] It includes a computing unit 201 and a cache 202;

[0121] The computing unit 201 can implement the task control method described in the second aspect of the embodiment of the present disclosure; and / or the task processing method described in the third aspect of the embodiment of the present disclosure.

[0122] Sixth, refer to Fig.12 , an embodiment of the present disclosure provides an electronic device, including:

[0123] Multiple processing cores 301; and

[0124] An on-chip network 302 configured to exchange data between the plurality of processing cores 301 and external data;

[0125] One or more instructions are stored in one or more of the processing cores 301, and one or more of the instructions are executed by one or more of the processing cores 301, so that one or more of the processing cores 301 can execute the task control method described in the second aspect of the embodiment of the present disclosure; and / or the task processing method described in the third aspect of the embodiment of the present disclosure.

[0126] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0127] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A task mapping method, comprising: Determine multiple layers of second matrices according to the first matrix, each layer of the second matrix is ​​divided into at least one second sub-matrix; wherein the elements in the second matrix of the N+1th layer correspond one-to-one to the multiple second sub-matrices of the Nth layer, and the second sub-matrix of the 1st layer is a sub-matrix of the first matrix; Mapping at least one second submatrix in each layer of the second matrix to a plurality of processing cores in the many-core system, each of the processing cores corresponding to a second submatrix, so that the processing core calculates the transpose of the corresponding second submatrix and stores the calculation result; Wherein, N is a positive integer; Each layer of the second matrix is ​​divided into at least one second sub-matrix, including: when there are a total of M layers of second matrices and the first layer of the second matrix is ​​the first matrix, each layer of the second matrix from the first layer to the M-1th layer of the second matrix is ​​divided into multiple second sub-matrices, and the Mth layer of the second matrix is ​​divided into one second sub-matrix, M is a positive integer, N<M.

2. The task mapping method according to claim 1, wherein: At least one second sub-matrix of each layer of the second matrix includes at least one non-zero second sub-matrix; The step of mapping at least one second sub-matrix in each layer of the second matrix to a plurality of processing cores in the many-core system comprises: Each non-zero second sub-matrix in each layer of the second matrix is ​​mapped to the plurality of processing cores respectively.

3. The task mapping method according to claim 2, wherein: The processing core corresponding to the second submatrix of the Nth layer is the processing core of the Nth layer; The step of mapping each non-zero second sub-matrix in each layer of the second matrix to the plurality of processing cores comprises: Transmitting the first-layer non-zero second submatrix in the first-layer second matrix to the first-layer processing core, so that the first-layer processing core calculates the transpose of its corresponding first-layer non-zero second submatrix; The first correspondence between the N-th layer processing core and the first coordinate is transmitted to the N+1-th layer processing core, so that the N+1-th layer processing core determines the second correspondence between the N-th layer processing core and the second coordinate according to the first correspondence; the first coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1-th layer second matrix; the second coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the transposed matrix of the N+1-th layer second matrix.

4. The task mapping method according to any one of claims 1 to 3, wherein: The step of determining a multi-layer second matrix according to the first matrix comprises: Determine a target size according to the size of the first matrix, where the target size is the size of the second submatrix of each layer; A multi-layer second matrix is ​​determined according to the first matrix and the target size.

5. The task mapping method according to any one of claims 1 to 3, wherein: The second sub-matrix of each layer is a square matrix.

6. A task control method, comprising: Determine a target processing core according to a mapping relationship between at least one second sub-matrix in the multi-layer second matrix and a plurality of processing cores in the many-core system; The target processing core is at least one of the plurality of processing cores storing target data; the target data is a transposed matrix of a submatrix of a first matrix corresponding to task data of a task to be processed; Transmitting the task data to the target processing core so that the target processing core reads the target data and performs operations corresponding to the task data; The multi-layer second matrix is ​​determined according to the first matrix, and each layer of the second matrix is ​​divided into at least one second sub-matrix; the elements in the N+1th layer of the second matrix correspond one-to-one to multiple Nth layer second sub-matrices, and the 1st layer of the second sub-matrix is ​​a sub-matrix of the first matrix; each of the multiple processing cores corresponds to a second sub-matrix, and the processing core stores a calculation result obtained by calculating the transpose of the corresponding second sub-matrix; N is a positive integer; Each layer of the second matrix is ​​divided into at least one second sub-matrix, including: when there are a total of M layers of second matrices and the first layer of the second matrix is ​​the first matrix, each layer of the second matrix from the first layer to the M-1th layer of the second matrix is ​​divided into multiple second sub-matrices, and the Mth layer of the second matrix is ​​divided into one second sub-matrix, M is a positive integer, N<M.

7. The task control method according to claim 6, wherein: At least one second submatrix of each layer of the second matrix includes at least one non-zero second submatrix; the mapping relationship between at least one second submatrix in the multi-layer second matrix and the multiple processing cores in the many-core system is the mapping relationship between each non-zero second submatrix in each layer of the second matrix and the multiple processing cores; The processing core corresponding to the second submatrix of the Nth layer is the processing core of the Nth layer; the processing core of the first layer stores the calculation result obtained by calculating the transposition of the corresponding non-zero second submatrix of the first layer; the processing core of the N+1th layer stores the second corresponding relationship between the processing core of the Nth layer and the second coordinate determined according to the first corresponding relationship between the processing core of the Nth layer and the first coordinate; The first coordinates are coordinates of the elements in the second matrix of the N+1th layer corresponding to the non-zero second submatrix of the Nth layer in the second matrix of the N+1th layer; the second coordinates are coordinates of the elements in the second matrix of the N+1th layer corresponding to the non-zero second submatrix of the Nth layer in the transposed matrix of the second matrix of the N+1th layer; the target processing core is one of the at least one processing core of the first layer; According to the mapping relationship between at least one second sub-matrix in the multi-layer second matrix and multiple processing cores in the many-core system, the step of determining the target processing core includes: When N is greater than 1, determining the N-1th layer processing core corresponding to the target data according to the second corresponding relationship stored in the Nth layer processing core corresponding to the target data; When N is equal to 1, the first layer processing core storing the target data is used as the target processing core.

8. The task control method according to claim 7, wherein: The task control method further includes: Determine the address of the storage space of each target calculation result in the off-chip storage according to the second corresponding relationship stored in each layer of processing cores; the target calculation result is the calculation result of calculating the transposition of the corresponding first layer non-zero second submatrix calculated by the first layer processing core and stored; Control each first-layer processing core to write the target calculation result stored by the first-layer processing core into the off-chip storage according to the address of the storage space of the target calculation result stored by the first-layer processing core in the off-chip storage, wherein each of the target calculation results is spliced ​​into a transposed matrix of the first matrix in the off-chip storage.

9. A task processing method, comprising: Receiving a first correspondence between an Nth layer processing core and a first coordinate in a multi-layer second matrix; Determine a second corresponding relationship between the Nth layer processing core and the second coordinate according to the first corresponding relationship; Among them, each layer of the second matrix in the multi-layer second matrix is ​​divided into at least one second sub-matrix; the elements in the N+1th layer second matrix correspond one-to-one to multiple Nth layer second sub-matrices; each of the multiple processing cores in the many-core system corresponds to a second sub-matrix; the first coordinate is the coordinate of the element in the N+1th layer second matrix corresponding to the Nth layer second sub-matrix in the N+1th layer second matrix; the second coordinate is the coordinate of the element in the N+1th layer second matrix corresponding to the Nth layer second sub-matrix in the transposed matrix of the N+1th layer second matrix; N is a positive integer; the multi-layer second matrix is ​​determined according to the first matrix corresponding to the task data of the task to be processed; the Nth layer processing core is the processing core corresponding to the Nth layer second sub-matrix; Each layer of the second matrix is ​​divided into at least one second sub-matrix, including: when there are a total of M layers of second matrices and the first layer of the second matrix is ​​the first matrix, each layer of the second matrix from the first layer to the M-1th layer of the second matrix is ​​divided into multiple second sub-matrices, and the Mth layer of the second matrix is ​​divided into one second sub-matrix, M is a positive integer, N<M.

10. An electronic device, comprising: one or more processors; A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the task mapping method according to any one of claims 1 to 5; One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

11. A processing core comprising: Includes computing units and cache; The computing unit is capable of implementing the task control method according to any one of claims 6 to 8; and / or The task processing method according to claim 9.

12. An electronic device comprising: Multiple processing cores; as well as An on-chip network configured to exchange data between the plurality of processing cores and external data; One or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the task control method according to any one of claims 6 to 8; and / or The task processing method according to claim 9.

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