Method, system, and readable medium for tracking instances within a sequence of video frames

Abstract

Disclosed is a machine learning framework for use in a semi-supervised environment to perform instance tracking in an image frame sequence, specifically providing a method and system for tracking instances within a video frame sequence. The method comprises the following steps: processing image frames through a backbone network to generate a set of feature maps, processing the set of feature maps by one or more prediction heads, and analyzing embedded features corresponding to a set of instances in two or more image frames in the video frame sequence to establish a one-to-one correlation between instances in different image frames. The one or more prediction heads include an embedding head configured to generate a set of embedded features corresponding to one or more instances of an object identified in the image frame. The method may also include training one or more prediction heads using a set of annotated image frames and / or a plurality of unlabeled video frame sequences.

Description

[0001] Claim priority

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 135,478, filed on January 8, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to a technology for tracking instances in a video frame sequence, and more particularly to a method, system, and readable medium for tracking instances in a video frame sequence. Background Art

[0004] Instance segmentation refers to analyzing images or frames in a video in order to assign labels to various objects in the image. For example, an image can be analyzed to classify background objects and foreground objects in the image such that each pixel belongs to a group of pixels associated with the background or the foreground. In addition, separate objects in the foreground of an image can be labeled with separate classifications, for example to distinguish different people in an image or to label people and cars separately as separate instances of different objects in the image. Segmentation masks that track multiple instances across multiple frames of a video have been intensively studied but still face two fundamental challenges: (1) the need for large-scale frame-by-frame annotations and (2) the complexity of the currently used two-stage methods.

[0005] Many existing approaches to this challenge utilize machine learning algorithms that rely on fully supervised learning techniques. To train these algorithms, a set of training data consisting of fully annotated image frames from videos is required. Because video annotation, especially on a per-frame basis, requires extensive manual labor, fully supervised learning techniques become a challenging problem.

[0006] Self-supervised methods have also been developed to learn pixel-level video correspondences from large sets of unlabeled videos. The learned correspondences can be used to track any fine-grained attributes (e.g., segmentation masks, keypoints, and / or textures) on a per-pixel basis; however, these methods are semantically agnostic, meaning that they do not distinguish between instances of different objects. In other words, a video can be processed to create a segmentation map for each frame, but there is no attempt to track different objects in each frame from one frame to the next, nor is there any attempt to establish correspondence between an instance of an object in one frame and an instance of the same object in another frame, even though the appearance or pose of the object may change over time.

[0007] Each of these techniques suffers from certain limitations. Therefore, there is a need for improved automated techniques for tracking instances across sequences of video frames. Summary of the Invention

[0008] Embodiments of the present disclosure relate to methods and systems for tracking instances within a video frame sequence. A machine learning framework is defined and trained in a semi-supervised manner using a set of annotated image frames and / or a set of unlabeled video frame sequences. Embedded features for each instance in a video frame sequence can be predicted and utilized to track unique instances across the video frame sequence.

[0009] According to a first aspect of the present disclosure, a method is provided, comprising the steps of processing an image frame by a backbone network to generate a set of feature maps, processing the set of feature maps by one or more prediction heads, and analyzing the embedded features corresponding to a set of instances in two or more image frames in the video frame sequence to establish a one-to-one correlation between the instances in different image frames. The one or more prediction heads include an embedding head configured to generate a set of embedded features corresponding to one or more instances of an object identified in the image frame. The method further comprises training the one or more prediction heads using a set of annotated image frames and / or a plurality of unlabeled video frame sequences.

[0010] In an embodiment of the first aspect, the one or more prediction heads further comprise: a classification head configured to predict the locations of zero or more instances of each of a plurality of object classes in the image; and a mask head configured to predict a pixel-level segmentation mask for each instance in the image.

[0011] In an embodiment of the first aspect, the embedding head comprises a keypoint embedding head, the keypoint embedding head comprising an encoder-decoder structure, wherein the encoder-decoder structure comprises an encoder and a decoder, the encoder comprises a convolutional layer, and the decoder comprises a deconvolutional layer.

[0012] In an embodiment of the first aspect, the one or more prediction heads include a classification head and a shape regression head configured to estimate a pose estimate for each instance based on a plurality of keypoints.

[0013] In an embodiment of the first aspect, the backbone network comprises a feature pyramid network, and wherein the set of feature maps comprises a plurality of feature maps of different spatial resolutions.

[0014] In an embodiment of the first aspect, the method further comprises training the one or more prediction heads using a set of annotated image frames and / or a plurality of unlabeled video frame sequences.

[0015] In an embodiment of the first aspect, training the embedding head comprises: minimizing an instance contrastive loss term.

[0016] In an embodiment of the first aspect, training the embedding head further comprises: enforcing maximum entropy regularization on the similarity matrix.

[0017] In an embodiment of the first aspect, training the embedding head comprises minimizing a loop loss term computed based on a forward affinity matrix and a backward affinity matrix corresponding to the sequence of video frames.

[0018] According to a second aspect of the present disclosure, a system for tracking instances within a sequence of video frames is provided. The system includes: a non-transitory computer-readable memory and at least one processor configured to implement multiple neural networks. The neural network includes: a backbone network configured to process image frames and generate a set of feature maps, and one or more prediction heads configured to process the set of feature maps generated by the backbone network. The one or more prediction heads include an embedding head configured to generate a set of embedded features corresponding to one or more instances of an object identified in the image frame.

[0019] In an embodiment of the second aspect, the one or more prediction heads further comprise: a classification head configured to predict the locations of zero or more instances of each of a plurality of object classes in the image; and a mask head configured to predict a pixel-level segmentation mask for each instance in the image.

[0020] In an embodiment of the second aspect, the embedding head comprises a keypoint embedding head, the keypoint embedding head comprising an encoder-decoder structure, wherein the encoder-decoder structure comprises an encoder and a decoder, the encoder comprises a convolutional layer, and the decoder comprises a deconvolutional layer.

[0021] In an embodiment of the second aspect, the one or more prediction heads include a classification head and a shape regression head configured to estimate a pose estimate for each instance based on a plurality of keypoints.

[0022] In an embodiment of the second aspect, the backbone network comprises a feature pyramid network, and wherein the set of feature maps comprises a plurality of feature maps of different spatial resolutions.

[0023] In an embodiment of the second aspect, the method further comprises training the one or more prediction heads using a set of annotated image frames and / or a plurality of unlabeled video frame sequences.

[0024] In an embodiment of the second aspect, training the embedding head comprises: minimizing an instance contrastive loss term and enforcing maximum entropy regularization on the similarity matrix.

[0025] In an embodiment of the second aspect, training the embedding head comprises minimizing a loop loss term computed based on a forward affinity matrix and a backward affinity matrix corresponding to the sequence of video frames.

[0026] In an embodiment of the second aspect, at least one processor comprises a parallel processing unit.

[0027] In an embodiment of the second aspect, the system is included in an autonomous vehicle.

[0028] According to a third aspect of the present disclosure, a non-transitory computer-readable medium is provided, which stores instructions that, in response to being executed by one or more processors, cause a computing system to track instances within a video frame sequence by performing the method of the first aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present system and method for tracking instances in a sequence of video frames is described in detail below with reference to the accompanying drawings, in which:

[0030] Figure 1A A machine learning framework according to some embodiments is shown;

[0031] Figure 1B A machine learning framework according to other embodiments is shown;

[0032] Figure 2 shows a flowchart of a method for performing instance tracking across a sequence of image frames according to some embodiments;

[0033] Figure 3 shows a keypoint embedding head included in the machine learning framework of FIG1 according to some embodiments;

[0034] Figure 4 shows an example parallel processing unit suitable for implementing some embodiments of the present disclosure;

[0035] Figure 5A is suitable for use in implementing some embodiments of the present disclosure Figure 4 A conceptual diagram of the processing system implemented by the PPU;

[0036] Figure 5B An exemplary system is shown in which the various architecture and / or functionality of the various previous embodiments may be implemented;

[0037] Figure 5C Components of an exemplary system that can be used to train and utilize machine learning in at least one embodiment are shown;

[0038] Figure 6A is suitable for implementing some embodiments of the present disclosure. Figure 4 A conceptual diagram of the graphics processing pipeline implemented by the PPU;

[0039] Figure 6B An exemplary game streaming system suitable for implementing some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0040] This disclosure describes a machine learning framework for learning distinct representations of different instances in a sequence of video frames. Specifically, a prediction head is proposed that includes multiple convolutional layers followed by a set of normalization layers and is configured to take feature maps from one or more fully connected networks as input. The machine learning framework is trained using only annotated (i.e., labeled) image datasets and optionally unlabeled video sequences.

[0041] Instance segmentation involves identifying and classifying all objects in an image while semantically segmenting each instance of the object at the pixel level. Objects in an image belong to a fixed set of semantic categories, but the number of instances of each object varies. For example, an image may include multiple objects, at least one of which is classified as a dog. However, multiple dogs in the same image, while sharing the common classification of belonging to the same type of object, are each separate instances. These dogs may look identical or share some similar features, but even identical objects at different locations in the image may be separate instances.

[0042] Recent instance segmentation techniques can be divided into two groups: top-down and bottom-up paradigms. Top-down methods first detect bounding boxes for each object and then segment instance masks within each bounding box. Bottom-up methods learn affinity relationships by pushing away the embedding vectors of pixels belonging to different instances and pulling together the embedding vectors of pixels belonging to the same instance, assigning an embedding vector to each pixel. Post-processing (e.g., clustering based on the embedding vectors) is then required to separate the various instances identified in the image.

[0043] SOLO is an instance segmentation solution that uses a bottom-up approach that is spatially variable and directly predicts both the semantic category and the segmentation of an object instance at each corresponding location. SOLO is described in "Solo: Segmenting object bylocations" by Wang et al. (Eur. Conf. Comput. Vis., 2020), which is incorporated herein by reference in its entirety. SOLO uses a fully connected network that feeds into parallel prediction heads, the first for predicting the semantic category associated with each location in an S x S grid, and the second for predicting an instance mask for each location. The denser the selected grid, the greater the number of individual instances of objects that can be predicted in the image.

[0044] The framework described in SOLO can be adapted to the immediate problem of tracking instances across a sequence of video frames. It should be understood that the SOLO framework is only trained to perform instance segmentation on a single frame and is not trained to track instances as they move across frames (i.e., change instance position) and change appearance over time (due to instance motion). Therefore, the instance tracking problem applies not only to tracking different instances of multiple object classes across different locations in a particular frame, but also to tracking the same instance across different locations in multiple frames.

[0045] Conventional techniques for supervised learning of instance segmentation networks treat this problem as a multi-class classification problem. However, in the current case, because the training dataset lacks ground truth association labels (i.e., frame-by-frame image annotations), the network is instead trained to learn a feature map (e.g., an embedding tensor) that distinguishes different instances and is robust to appearance changes caused by the motion of instances in the video. Once trained, the network can be used to track any object instance by searching for the most similar object in subsequent frames using its embedded features.

[0046] Instance segmentation is a core technique used in many autonomous driving applications. Autonomous vehicles may include a machine learning framework configured to process images captured by one or more image sensors included in the vehicle. The techniques described herein can be used to track instances of objects captured in video sequences to perform tasks such as collision avoidance. Instance segmentation can also be used in other types of applications, such as safety or sports applications.

[0047] Figure 1A FIG. 1 shows a machine learning framework 100 according to some embodiments. Figure 1A As shown, the framework 100 includes a backbone network coupled to a plurality of prediction heads. In one embodiment, the backbone network is a feature pyramid network (FPN) 110. FPN 110 may include a plurality of convolutional layers arranged in a pyramid form, wherein each level of the pyramid includes one or more layers and generates a feature map at a specific resolution. The feature map may be downsampled (e.g., by a stride operation or a pooling layer) at each level of the pyramid to produce a feature map with a smaller spatial resolution than the original input image. In one embodiment, FPN 110 may include skip connections and a top-down structure with an upsampling layer, as described in Lin et al. in “Feature Pyramid Networks for Object Detection” (Comp. Vis. And Pattern Recognition, 2016), the entire contents of which are incorporated herein by reference.

[0048] The FPN 110 takes an input image 102 and generates a set of feature maps at different spatial resolutions and a fixed number of channels (e.g., 256 channels). For example, an input image of 256 x 256 pixels may generate a set of feature maps with spatial resolutions of 256 x 256, 128 x 128, 64 x 64, 32 x 32, and 16 x 16, each with 256 channels. It should be understood that the above image sizes are merely examples, and different embodiments may implement different configurations of the FPN 110.

[0049] This set of feature maps is then passed to multiple prediction heads. Figure 1A As shown, the prediction head includes a classification head 112, a mask head 114, and an embedding head 116. The classification head 112 includes multiple convolutional layers (e.g., 7 convolutional layers) that generate feature maps with C channels, each of which is S×S in size, representing the initial division of the image spatial domain into a grid of cells. In some embodiments, the classification head 112 may also include an interpolation layer between or after each convolutional layer. The feature map generated by the classification head 112 represents a prediction of the location of instances of C classes of objects in the image frame. More specifically, the image is divided into an S×S grid and the output of the classification head 112 provides a prediction of whether each cell in the grid is associated with an object of a particular class. Therefore, the output of the classification head 112 is a map of S×S×C values ​​(e.g., between 0 and 1) representing the confidence level that the grid cells of the image contain objects of each corresponding class. In one embodiment, the size of C is fixed to 256, which provides a fixed number of classes for objects in the image. In some embodiments, the output of the classification head 112 is analyzed using a softmax function to determine which class of object is located in each cell of the grid.

[0050] It should be understood that the selected grid (i.e., S 2 ) limits the total number of instances of various objects that can be detected within the image. A single channel of the output of the classification head 112 is a map of values ​​that indicates which cells in the grid contain objects corresponding to a particular class. Creating a grid that is too coarse limits the total number of objects that can be identified in the image. However, creating a grid that is too fine increases the complexity of the framework 100, requiring more processing power to process the image. In addition, a different grid size can be used for each level of the feature map pyramid generated by the FPN 110. By using a set of feature maps with the spatial resolution of the pyramid structure rather than a set of feature maps at a single scale, objects of different sizes are more likely to be predicted correctly. It should be understood that a different instance of the classification head 112 can be instantiated for each level of the pyramid to process feature maps with the spatial resolution corresponding to that instance of the classification head 112.

[0051] The mask head 114 predicts a pixel-wise segmentation mask for each instance of the object located in each grid. The mask head 114 may also be composed of multiple convolutional layers and / or interpolation layers. The output of the mask head 114 is a set of H x W x S 2 The mask head 114 is a set of feature maps that predicts a pixel-wise segmentation mask for each instance of an object identified in a particular grid location. Similarly, a different instance of the mask head 114 can be instantiated for each level of the pyramid in the set of feature maps generated by the FPN 110. It should be understood that in one embodiment, the segmentation masks at each level of the pyramid can be upsampled to the original resolution of the image. In one embodiment, the set of feature maps provided as input to the mask head 114 are augmented with spatial information (i.e., x and y pixel coordinate locations). These two additional channels are concatenated to the set of feature maps output by the FPN 110 and provide at least one convolutional layer in the mask head 114 with additional spatial information that is only explicitly included in the feature map structure.

[0052] The classification head 112 and the mask head 114 may be trained using a training dataset comprising image frames with annotations. The annotations may refer to a segmentation mask for each of one or more instances of an object identified in the image, and a classification associated with each instance.

[0053] In addition to the classification head 112 and the mask head 114, which provide the identity of the class of each instance and the corresponding pixel-level correspondences (i.e., segmentation maps) for each identified instance, the framework 100 also includes another prediction head for tracking instances across a sequence of frames. To track instances across a sequence of video frames, an embedding vector is predicted for each identified instance, and the similarity of the embedding vectors of instances identified in separate frames is used to predict correspondences between instances across a sequence of video frames.

[0054] In one embodiment, the embedding head 116 provides tracking features that: (1) distinguish different instances within an image, and (2) are consistent across the instance variations typically present in a video sequence. The structure of the embedding head 116 is similar to the classification head 112, including multiple convolutional layers. However, as described in more detail below, the embedding head 116 is trained using a combination of center and contrastive losses.

[0055] In one embodiment, the embedding head 116 is implemented by four convolutional layers with 256 output channels. The convolutional layers are followed by one or more group normalization layers. It should be understood that in some embodiments, the embedding head 116 can be designed with more or fewer convolutional layers, and the group normalization layers can be omitted or replaced with other types of layers.

[0056] The central representation of instance i is obtained by averaging all embedded features for the given instance, given as follows:

[0057]

[0058] where Ω i is the set of grid cells in the image, N i is Ω i The number of grid cells in , f q is the feature vector of a specific unit q. Then the center loss that minimizes the L1 distance is defined as:

[0059]

[0060] The goal of minimizing the center loss term during training forces the embedding feature vectors of the same instance but located in different cells of the grid to be similar. However, the embedding feature vectors of different instances also need to be different in order to have strong discriminative power. Therefore, a contrast term is also defined to push the center representations of all instances further apart. Specifically, a dense similarity matrix is ​​calculated as follows:

[0061]

[0062] In Equation 3, the variables i and j refer to the different instances identified in the image, where the total number of instances of the object identified in the image is K. In order to push the embedding vectors of different instances apart, the elements on the diagonal of the matrix are encouraged to be larger than the off-diagonal elements. The cross entropy loss is then defined as follows:

[0063]

[0064] where I is the identity matrix. The total instance contrastive loss is the combination of the sum of the center loss and the cross entropy loss for each instance, given as:

[0065]

[0066] where λ is a parameter for the relative strength of the contrastive loss term.

[0067] Once the embedding head 116 is trained to predict embedding features for different instances identified in a grid cell, the center representations can be used to track instances across frames by comparing each center representation predicted in one frame with the center representation in another frame. Tracking can also be improved by utilizing information from the classification head 112 during training, as discussed below using non-maximum suppression techniques.

[0068] In one embodiment, the center representation of each instance, along with the classification and segmentation masks, can be stored in a data structure in memory as each frame of video is processed. Once multiple video frames have been processed, the center representations of instances in the frame sequence are compared using, for example, cosine similarity values ​​to identify instance correlations across the video frame sequence.

[0069] Tracking solely via instance contrastive loss is based on the assumption that any instance in the current frame also exists in adjacent frames. However, this fails to identify newly appearing instances (because they enter subsequent frames) or instances in one frame that are occluded or out of view in subsequent frames. When computing similarity scores based on the instance's embedded features, a newly appearing instance may be matched with one or more existing instances, and therefore, cross-frame predictions may result in incorrect matches. One technique to address this issue is to apply an entropy maximization term in addition to minimizing the instance contrastive loss term.

[0070] The entropy term is defined as follows:

[0071]

[0072] Where K is the number of instances in the image and S(i,j) is the dense similarity matrix described in Equation 3. A high entropy value H indicates uniform output probability and is effective when using the total instance contrastive loss term When enforced, each instance is encouraged to be equally dissimilar to all other instances. Therefore, in addition to minimizing the instance contrastive loss term, an additional objective of maximizing the entropy term can be enforced during training.

[0073] When a new instance is successfully detected, the embedding features of the new instance are compared with the embedding features of the existing K instances. The maximum entropy term forces the similarity scores of all existing instances to be equally low, so when all similarity scores are below a threshold, it is easy to assign a new identity to the newly discovered instance.

[0074] Figure 1B A machine learning framework 100 is shown in accordance with some embodiments. Figure 1A The machine learning framework 100 can be trained entirely based on a training dataset that includes only annotated images. For example, the instance contrastive loss term and the maximum entropy term used to train the parameters of the embedding head 116 rely only on the analysis of a single image and the similarity of the embedded features of each instance in the image compared to the similarity scores of other instances identified in the same image. However, there is no guarantee that training performed on a collection of images will result in continuous and coherent tracking over time. In some embodiments, it is possible to improve tracking by training the machine learning framework 100 using a training dataset that includes sequences of unlabeled video frames. Self-supervised video correspondence learning can be used to regularize the tracking of instances predicted across a sequence of video frames.

[0075] like Figure 1BAs shown, the machine learning framework 100 can be extended to be applied to both input images 102 and input videos 104, where the input image 102 may include a single frame including annotations of instances in the frame, and the input video 104 may include multiple frames in a video frame sequence but lack any ground truth annotation information. Each of the frames of the input image 102 and / or the input video 104 is processed by a backbone network that is trained on the input image 102 and / or the input video 104. Figure 1B 104. The FCN 150 is described as a fully convolutional network (FCN) 150. The FCN 150 may be shared (i.e., the structure and parameters of the network are common to all instances of the FCN 150) and is used to process individual frames in a sequence of frames of the input image 102 and the input video 104. In one embodiment, the FCN 150 is implemented as a feature pyramid network, as described above in Figure 1A The FPN 110 is described.

[0076] Figure 1B The machine learning framework 100 includes the classification head 112 and the mask head 114, as described above. However, the embedding head 116 can be separated into a pair of embedding heads: an image embedding head 152 and a video embedding head 154. The image embedding head 152 can be similar to the embedding head 116 described above. The video embedding head 154 is similar in structure to the image embedding head 152, but can be trained using different techniques.

[0077] Specifically, valid grid cells can be identified based on the output of the classification head 112 by performing non-maximum suppression (NMS) on matches with higher classification responses. Grid-cell-level video correspondences can be trained within valid grid cells by a cycle consistency loss factor. Specifically, given a set of frames randomly sampled from a video frame sequence, the cross-instance affinity is defined as Where P and Q are the number of instances identified in each of the two frames of the video. is the transition probability that the i-th instance at time t matches the j-th instance at time t+1. The long-distance correspondence given by the chain rule is defined as follows:

[0078]

[0079] Ideally, if the video sequence is reversed and instances are tracked from time t+k to time t, then the i-th instance should return to its original position in the first frame. Reverse affinity matrix And the corresponding long-distance correspondence follows a similar equation 7. Then the cycle loss term based on the long-distance correspondence of both the forward affinity matrix and the backward affinity matrix is ​​defined as follows:

[0080]

[0081] It is found that when the image dataset and the video dataset used to train the machine learning framework 100 share a domain (e.g., where the video sequence includes annotated keyframes but most frames are not annotated), then the unannotated video frame sequence can be used and a cyclic loss term can be added to the objective of minimizing the instance contrastive loss term and / or enforcing a maximum entropy objective to train the image embedding head 152. However, in the case where the image dataset and the video dataset used for training do not share a domain (i.e., the video sequence is not annotated and the annotated image data is unrelated to the video sequence), then a separate and distinct video embedding head 154 can be trained with a cyclic loss term. Figure 1B The dashed line in indicates that the image embedding head 152 is not used to process the video sequence when there is a domain gap in the training dataset. It should be understood that training via the video embedding head 154 using unlabeled videos will also help improve the training of the backbone network (such as FPN 110). Even if the video embedding head 154 is not used (i.e., disabled) during inference, the backbone network will produce better features for processing by the image embedding head 152 by jointly training with the video embedding head 154 using unlabeled videos.

[0082] Figure 2 A flow chart of a method 200 for performing instance tracking across a sequence of image frames is shown, according to some embodiments. The method 200 can be performed by software (i.e., a process or application), hardware, or some combination of software and hardware. In one embodiment, the method 200 is performed at least in part by processing various layers of the machine learning framework 100 on a parallel processing unit (e.g., PPU 400 described below).

[0083] At step 202, a machine learning framework is trained using a set of annotated images and optionally a set of unlabeled videos. In one embodiment, each annotated image includes an image, a per-pixel segmentation map of one or more instances of the image, and a classifier for each instance of the segmentation map. Each unlabeled video includes a sequence of image frames, without including annotations or other semantic information (e.g., segmentation maps) for the image frames.

[0084] In one embodiment, the machine learning framework is trained using an instance contrastive loss function that is a combination of a center loss and a contrastive loss. The loss function can also include a term that applies maximum entropy regularization, which helps detect when new objects appear in subsequent image frames of the video. Finally, the loss function includes a cross-entropy loss term associated with a per-instance affinity matrix, which helps ensure that the correspondence between instances is the same in the forward and reverse time directions.

[0085] At step 204, each image frame in the sequence of image frames is processed by a backbone network to generate a set of feature maps. In one embodiment, the backbone network includes FPN 110, and the set of feature maps includes a plurality of feature maps of different sizes or resolutions.

[0086] At step 206, the set of feature maps is processed by one or more prediction heads to generate at least one of a segmentation mask, a classifier, an instance-level embedded feature, and / or a keypoint-level embedded feature. In one embodiment, instances of multiple objects of different classes can be identified in an image frame. A segmentation mask is estimated for each instance to predict pixel-level associations for each instance in the image frame. In another embodiment, a set of keypoints (e.g., three-dimensional (3D) points) is estimated for each instance of the object.

[0087] In one embodiment, an embedding head 116 is provided to process the set of feature maps and generate instance-level embedded features. The embedding head 116 is trained to estimate an embedded feature associated with each instance identified in the image by the classification head 112. In another embodiment, a keypoint embedding head 300 is provided to process the set of feature maps and generate keypoint-level embedded features. The keypoint embedding head 300 is trained to estimate an embedded feature associated with each keypoint associated with one or more instances of an object in the image frame.

[0088] In step 208, the embedded features are processed to generate instance-level correspondences for the image frame sequence. The instance-level correspondences assign semantic labels to different instances in the image frame sequence and track the same instance in multiple image frames.

[0089] Figure 3 The pose tracking prediction head of the machine learning framework 100 is shown in accordance with some embodiments. Figure 1A The machine learning framework 100 can be further adapted to predict and track the poses of different humans or other objects (e.g., animals) that are instances of the same class. Pose tracking, or tracking the locations of key points of an object, is slightly different from instance segmentation in that it requires not only determining which pixels belong to a particular instance by estimating a segmentation map for the instance, but also locating the predicted locations of one or more key points within the instance's footprint. Compared to instance segmentation, pose tracking requires the framework 100 to learn finer-grained feature representations to distinguish different human instances in different frames.

[0090] In one embodiment, the framework 100 can be adapted to include a keypoint embedding head 300. Unlike the embedding head 116, the keypoint embedding head 300 is designed to learn distinguishing features of different keypoints associated with instances of an object. PointSetAnchors are defined that define the keypoint pose of an instance of a given class. For example, a set of 17 keypoints can be defined for the pose of a human object, where the 17 keypoints represent the positions of 17 different joints of the human body (e.g., neck, shoulder, wrist, etc.). The purpose of the keypoint embedding head 300 is to learn embedding features that represent a unique set of keypoints for a given instance in an image frame, so that the keypoints associated with each instance can be tracked across a sequence of image frames based on the correlation of the embedded features.

[0091] The keypoint embedding head 300 concatenates a set of feature maps from the FPN 110 with the predicted heatmaps of keypoint locations. Figure 3 As shown, the set of feature maps is also processed by a separate prediction head that is configured to generate a predicted heat map. The separate prediction head is depicted as a set of convolutional layers 310 (e.g., 4 convolutional layers) followed by an aggregation layer 320. The connected inputs are then fed to a keypoint embedding head 300, which includes an encoder-decoder structure. In one embodiment, the encoder 330 includes a convolutional layer and the decoder includes a deconvolutional layer 340. The encoder-decoder structure predicts keypoint-level embedding features 350. In addition, the heat map can also be used to identify the location of each keypoint-level embedding feature corresponding to a specific joint position.

[0092] The keypoint embedding head 300 is then trained using the same instance contrastive loss term as defined in Equation 4 above. More specifically, the IC loss calculation is repeated 17 times, corresponding to each of the 17 keypoints. In addition, the IC loss calculation can also be applied to the average embedding features of all keypoints for a given instance. The keypoint embedding head 300 can be added to the classification head and the shape regression head, as described in more detail in Wei et al., "Point-Set Anchors for Object Detection, Instance Segmentation and Pose Estimation", (Eur. Conf. Comput. Vis., 2020), the entire contents of which are incorporated herein by reference.

[0093] Instance tracking or pose tracking can be incorporated into various application architectures. Instance tracking is particularly useful in autonomous driving applications. For example, being able to identify and track hazards (e.g., other cars, pedestrians, etc.) captured using one or more image sensors located on a vehicle can significantly help collision avoidance algorithms and improve the safety factor of self-driving features. Instance tracking or pose tracking is also useful in other applications, such as security (e.g., tracking people on a casino floor) or sports (e.g., tracking players' movements on a field).

[0094] The machine learning framework 100 is typically implemented as a computer program executed by one or more processors. For example, each layer of the fully connected network can be implemented on a processor, such as a central processing unit (CPU) or a parallel processing unit (PPU), such as a graphics processing unit (GPU) or a vector processing unit (VPU). In some embodiments, the machine learning framework can be implemented as a service accessible via a network (e.g., a cloud-based network). In other embodiments, the machine learning framework can be implemented in a local computer system, such as on a desktop computer, a mobile device, or an autonomous vehicle. A more detailed description of an exemplary system for implementing at least a portion of the machine learning framework is set forth below.

[0095] Parallel processing architecture

[0096] Figure 4 A parallel processing unit (PPU) 400 is shown according to one embodiment. The PPU 400 can be used to implement any portion of the method 200 described above. For example, the PPU 400 can be used to generate an image embedding by executing instructions for encoding an image frame. In addition, the PPU 400 can be used to process at least one of the image embedding or the video embedding to produce the output of the machine learning framework described above.

[0097] In one embodiment, the PPU 400 is a multi-threaded processor implemented on one or more integrated circuit devices. The PPU 400 is a latency-hiding architecture designed to process many threads in parallel. A thread (e.g., an execution thread) is an instantiation of an instruction set configured to be executed by the PPU 400. In one embodiment, the PPU 400 is a graphics processing unit (GPU) that is configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data to generate two-dimensional (2D) image data for display on a display device. In other embodiments, the PPU 400 can be used to perform general-purpose computations. Although an exemplary parallel processor is provided herein for illustrative purposes, it should be specifically noted that such a processor is described for illustrative purposes only and that any processor may be used to supplement and / or replace the processor.

[0098] One or more PPUs 400 can be configured to accelerate thousands of high-performance computing (HPC), data center, cloud computing, and machine learning applications. PPUs 400 can be configured to accelerate numerous deep learning systems and applications for autonomous vehicles, simulations, computational graphics such as ray or path tracing, deep learning, high-precision speech, image, and text recognition systems, intelligent video analysis, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analysis, astronomy, molecular dynamics simulations, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations, among others.

[0099] like Figure 4 As shown, the PPU 400 includes an input / output (I / O) unit 405, a front-end unit 415, a scheduler unit 420, a work distribution unit 425, a hub 430, a crossbar switch (Xbar) 470, one or more general processing clusters (GPCs) 450, and one or more memory partitioning units 480. The PPU 400 can be connected to a host processor or other PPUs 400 via one or more high-speed NVLink 410 interconnects. The PPU 400 can be connected to a host processor or other peripheral devices via interconnect 402. The PPU 400 can also be connected to a local memory 404 including multiple memory devices. In one embodiment, the local memory can include multiple dynamic random access memory (DRAM) devices. The DRAM devices can be configured as a high-bandwidth memory (HBM) subsystem, in which multiple DRAM dies are stacked within each device.

[0100] The NVLink 410 interconnect enables the system to scale and include one or more PPUs 400 in conjunction with one or more CPUs, supporting cache coherency between the PPU 400 and the CPU, and CPU mastering. Data and / or commands can be sent by the NVLink 410 through the hub 430 to or from other units of the PPU 400, such as one or more copy engines, video encoders, video decoders, power management units, etc. (not explicitly shown). Figure 5B NVLink 410 is described in more detail.

[0101] I / O unit 405 is configured to send and receive communications (e.g., commands, data, etc.) from a host processor (not shown) via interconnect 402. I / O unit 405 can communicate with the host processor directly via interconnect 402, or through one or more intermediary devices such as a memory bridge. In one embodiment, I / O unit 405 can communicate with one or more other processors, such as one or more PPUs 400, via interconnect 402. In one embodiment, I / O unit 405 implements a Peripheral Component Interconnect Express (PCIe) interface for communicating over a PCIe bus, and interconnect 402 is a PCIe bus. In alternative embodiments, I / O unit 405 can implement other types of known interfaces for communicating with external devices.

[0102] I / O unit 405 decodes data packets received via interconnect 402. In one embodiment, the data packets represent commands configured to cause PPU 400 to perform various operations. I / O unit 405 transmits the decoded commands to various other units of PPU 400 as directed by the commands. For example, some commands may be transmitted to front-end unit 415. Other commands may be transmitted to hub 430 or other units of PPU 400, such as one or more copy engines, video encoders, video decoders, power management units, etc. (not explicitly shown). In other words, I / O unit 405 is configured to route communications between and among the various logical units of PPU 400.

[0103] In one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 400 for processing. The workload may include a number of instructions and the data to be processed by those instructions. A buffer is an area of ​​memory that is accessible (e.g., read / write) by both the host processor and the PPU 400. For example, the I / O unit 405 may be configured to access a buffer in system memory connected to the interconnect 402 via a memory request transmitted over the interconnect 402. In one embodiment, the host processor writes a command stream into the buffer and then transmits a pointer to the start of the command stream to the PPU 400. The front end unit 415 receives pointers to one or more command streams. The front end unit 415 manages the one or more streams, reads commands from these streams, and forwards the commands to the various units of the PPU 400.

[0104] The front-end unit 415 is coupled to a scheduler unit 420, which configures the various GPCs 450 to process the tasks defined by the one or more streams. The scheduler unit 420 is configured to track state information related to the various tasks managed by the scheduler unit 420. The state may indicate which GPC 450 the task is assigned to, whether the task is active or inactive, the priority associated with the task, and the like. The scheduler unit 420 manages the execution of the multiple tasks on the one or more GPCs 450.

[0105] Scheduler unit 420 is coupled to work distribution unit 425, which is configured to dispatch tasks for execution on GPCs 450. Work distribution unit 425 can track a number of scheduled tasks received from scheduler unit 420. In one embodiment, work distribution unit 425 manages a pending task pool and an active task pool for each GPC 450. When a GPC 450 completes execution of a task, the task is evicted from the active task pool of GPC 450, and one of the other tasks from the pending task pool is selected and scheduled for execution on GPC 450. If an active task on a GPC 450 has become idle, for example, while waiting for a data dependency to be resolved, the active task can be evicted from GPC 450 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on GPC 450.

[0106] In one embodiment, the host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 400. In one embodiment, multiple computing applications are executed simultaneously by the PPU 400, and the PPU 400 provides isolation, quality of service (QoS), and independent address spaces for the multiple computing applications. An application can generate instructions (e.g., API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 400. The driver kernel outputs the tasks to one or more streams being processed by the PPU 400. Each task can include one or more related groups of threads, referred to herein as warps. In one embodiment, a warp includes 32 related threads that can execute in parallel. Cooperative threads can refer to multiple threads that include instructions to perform tasks and can exchange data through shared memory. These tasks can be assigned to one or more processing units within the GPC 450, and instructions are scheduled for execution by at least one warp.

[0107] Work distribution unit 425 communicates with the one or more GPCs 450 via XBar 470. XBar 470 is an interconnect network that couples many units of PPU 400 to other units of PPU 400. For example, XBar 470 can be configured to couple work distribution unit 425 to a specific GPC 450. Although not explicitly shown, one or more other units of PPU 400 can also be connected to XBar 470 via hub 430.

[0108] Tasks are managed by a scheduler unit 420 and dispatched to GPCs 450 by a work distribution unit 425. GPCs 450 are configured to process tasks and generate results. The results can be consumed by other tasks within the GPC 450, routed to a different GPC 450 via XBar 470, or stored in memory 404. The results can be written to memory 404 via a memory partition unit 480, which implements a memory interface for reading data from and writing data to memory 404. The results can be transferred to another PPU 400 or CPU via NVLink 410. In one embodiment, a PPU 400 includes a number U of memory partition units 480, which is equal to the number of separate and distinct memory devices coupled to the memory 404 of the PPU 400. Each GPC 450 may include a memory management unit to provide virtual address to physical address translation, memory protection, and arbitration of memory requests. In one embodiment, the memory management unit provides one or more translation lookaside buffers (TLBs) for performing virtual to physical address translations in memory 404 .

[0109] In one embodiment, the memory partition unit 480 includes a raster operations (ROP) unit, a level 2 (L2) cache, and a memory interface coupled to the memory 404. The memory interface can implement a 32-bit, 64-bit, 128-bit, or 1024-bit data bus for high-speed data transfer. The PPU 400 can connect to up to Y memory devices, such as a high-bandwidth memory stack or graphics double data rate, version 5, synchronous dynamic random access memory, or other types of persistent storage. In one embodiment, the memory interface implements an HBM2 memory interface, and Y is equal to half of U. In one embodiment, the HBM2 memory stack is located on the same physical package as the PPU 400, providing significant power and area savings compared to conventional GDDR5 SDRAM systems. In one embodiment, each HBM2 stack includes four memory dies and Y is equal to 4, where each HBM2 stack includes two 129-bit channels per die, for a total of 8 channels with a data bus width of 1024 bits.

[0110] In one embodiment, memory 404 supports single-error correction, double-error detection (SECDED) error correction code (ECC) to protect data. ECC provides higher reliability for computing applications that are sensitive to data corruption. Reliability is particularly important in large-scale cluster computing environments where PPU 400 processes very large data sets and / or runs applications for extended periods of time.

[0111] In one embodiment, the PPU 400 implements a multi-level memory hierarchy. In one embodiment, the memory partitioning unit 480 supports unified memory that provides a single unified virtual address space for the CPU and PPU 400 memory, allowing data sharing between virtual memory systems. In one embodiment, the frequency with which the PPU 400 accesses memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU 400 that is accessing them more frequently. In one embodiment, NVLink 410 supports address translation services, allowing the PPU 400 to directly access the CPU's page tables and providing the PPU 400 with full access to the CPU's memory.

[0112] In one embodiment, the copy engine transfers data between multiple PPUs 400 or between a PPU 400 and a CPU. The copy engine can generate page faults for addresses that are not mapped in the page table. The memory partition unit 480 can then repair the page faults, map these addresses into the page table, and then the copy engine can perform the transfer. In conventional systems, memory is fixed (e.g., non-pageable) for multiple copy engine operations between multiple processors, significantly reducing the amount of available memory. In the event of a hardware page fault, the address can be passed to the copy engine without worrying about whether the memory page is resident, and the copy process is transparent.

[0113] Data from memory 404 or other system memory can be retrieved by memory partition unit 480 and stored in L2 cache 460, which is located on-chip and shared between various GPCs 450. As shown, each memory partition unit 480 includes a portion of the L2 cache associated with the corresponding memory 404. Low-level caches can then be implemented in various units within GPC 450. For example, each of the processing units within GPC 450 can implement a level 1 (L1) cache. The L1 cache is private memory dedicated to a particular processing unit. L2 cache 460 is coupled to memory interface 470 and XBar 470, and data from the L2 cache can be retrieved and stored in each of the L1 caches for processing.

[0114] In one embodiment, the processing units within each GPC 450 implement a SIMD (Single Instruction, Multiple Data) architecture, in which each thread in a thread group (e.g., a warp) is configured to process a different set of data based on the same instruction set. All threads in a thread group execute the same instructions. In another embodiment, the processing units implement a SIMT (Single Instruction, Multiple Thread) architecture, in which each thread in a thread group is configured to process a different set of data based on the same instruction set, but in which individual threads in a thread group are allowed to diverge during execution. In one embodiment, a program counter, call stack, and execution state are maintained for each warp, enabling concurrency between warps and serial execution within a warp when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, enabling equal concurrency between all threads within and between warps. When execution state is maintained for each individual thread, threads executing the same instruction can be aggregated and executed in parallel for maximum efficiency.

[0115] Cooperative Groups is a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, allowing for richer and more efficient expressions of parallel decompositions. The cooperative launch API supports synchronization between thread blocks used to execute parallel algorithms. Conventional programming models provide a single simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, programmers often prefer to define thread groups at a granularity smaller than a thread block in the form of a collective group-wide function interface, and synchronize within the defined group to allow for greater performance, design flexibility, and software reuse.

[0116] Cooperative Groups enables programmers to explicitly define groups of threads at sub-block and multi-block granularity (as small as a single thread), and perform collective operations such as synchronization on the threads in the cooperative group. This programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local context without having to make assumptions about aggregation. The cooperative group primitives enable new cooperative parallelism patterns, including producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0117] Each processing unit includes a large number (e.g., 128, etc.) of different processing cores (e.g., functional units), which can be fully pipelined, single-precision, double-precision, and / or mixed-precision, and include a floating-point arithmetic logic unit (ALU) and an integer ALU. In one embodiment, the ALU implements the IEEE 754-2008 standard for floating-point arithmetic. In one embodiment, the cores include 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0118] The Tensor Core is configured to perform matrix operations. In particular, the Tensor Core is configured to perform deep learning matrix arithmetic, such as GEMM (matrix-matrix multiplication), which is used for convolution operations during neural network training and inference. In one embodiment, each Tensor Core operates on a 4x4 matrix and performs matrix multiplication and accumulation operations, D = A × B + C, where A, B, C, and D are 4x4 matrices.

[0119] In one embodiment, the matrix multiplication inputs A and B can be integer, fixed-point, or floating-point matrices, while the accumulation matrices C and D can be integer, fixed-point, or floating-point matrices of equal or higher bit width. In one embodiment, the Tensor Core uses 32-bit integer accumulation to operate on 1-bit, 4-bit, or 8-bit integer input data. 8-bit integer matrix multiplication requires 1024 operations and results in a full-precision product, which is then accumulated with other intermediate products using 32-bit integer addition for 8x8x16 matrix multiplication. In one embodiment, the Tensor Core uses 32-bit floating-point accumulation to operate on 16-bit floating-point input data. 16-bit floating-point multiplication requires 64 operations and results in a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition for 4x4x4 matrix multiplication. In practice, the Tensor Core is used to perform much larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. APIs such as the CUDA 9 C++ API expose specialized matrix load, matrix multiply and accumulate, and matrix store operations for efficient use with Tensor Cores from CUDA-C++ programs. At the CUDA level, the warp-level interface takes a 16x16 matrix across all 32 threads of the warp.

[0120] Each processing unit may also include M special function units (SFUs) that perform special functions (e.g., attribute evaluation, inverse square root, etc.). In one embodiment, the SFUs may include tree traversal units configured to traverse a hierarchical tree data structure. In one embodiment, the SFUs may include texture units configured to perform texture map filtering operations. In one embodiment, the texture units are configured to load texture maps (e.g., 2D texture element arrays) from memory 404 and sample these texture maps to generate sampled texture values ​​for shader programs executed by the processing units. In one embodiment, the texture maps are stored in a shared memory that may include or contain an L1 cache. The texture units implement texture operations such as filtering operations using mip maps (e.g., texture maps with varying levels of detail). In one embodiment, each processing unit includes two texture units.

[0121] Each processing unit also includes N load-store units (LSUs) that implement load and store operations between the shared memory and the register file. Each processing unit includes an interconnect network that connects each of the cores to the register file and connects the LSUs to the register file and the shared memory. In one embodiment, the interconnect network is a crossbar switch that can be configured to connect any of the cores to any register in the register file and to connect the LSUs to memory locations in the register file and the shared memory.

[0122] Shared memory is an on-chip memory array that allows data storage and communication between processing units and between threads within a processing unit. In one embodiment, shared memory includes 128KB of storage capacity and is located on the path from each processing unit to memory partition unit 480. Shared memory can be used to cache reads and writes. One or more of shared memory, L1 cache, L2 cache, and memory 404 serves as a backing store.

[0123] Combining data cache and shared memory functionality into a single memory block provides the best overall performance for both types of memory access. The capacity can be used as a cache by programs that don't use the shared memory. For example, if the shared memory is configured to use half of its capacity, texture and load / store operations can use the remaining capacity. This integration into shared memory enables the shared memory to serve as a high-throughput conduit for streaming data, while providing high-bandwidth and low-latency access to frequently reused data.

[0124] When configured for general-purpose parallel computing, a simpler configuration can be used than for graphics computing. In particular, the fixed-function graphics processing units are bypassed, creating a much simpler programming model. In this general-purpose parallel computing configuration, the work distribution unit 425 dispatches and distributes thread blocks directly to the processing units within the GPC 450. Threads execute the same program in the computation using a unique thread ID to ensure that each thread generates a unique result using the processing units that execute the program and perform the computation, shared memory for communication between threads, and LSUs that read and write global memory through the shared memory and memory partition unit 480. When configured for general-purpose parallel computing, the processing units can also write commands that the scheduler unit 420 can use to start new work on the processing units.

[0125] Each of the PPUs 400 may include one or more processing cores and / or components thereof, such as a tensor core (TC), a tensor processing unit (TPU), a pixel vision core (PVC), a ray tracing (RT) core, a vision processing unit (VPU), a graphics processing cluster (GPC), a texture processing cluster (TPC), a streaming multiprocessor (SM), a tree traversal unit (TTU), an artificial intelligence accelerator (AIA), a deep learning accelerator (DLA), an arithmetic logic unit (ALU), an application-specific integrated circuit (ASIC), a floating point unit (FPU), an input / output (I / O) element, a peripheral component interconnect (PCI) or a peripheral component interconnect express (PCIe) element, and / or the like, and / or be configured to perform its functions.

[0126] The PPU 400 may be included in a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., a wireless, handheld device), a personal digital assistant (PDA), a digital camera, a vehicle, a head-mounted display, a handheld electronic device, etc. In one embodiment, the PPU 400 is implemented on a single semiconductor substrate. In another embodiment, the PPU 400 is included in a system-on-chip (SoC) along with one or more other devices such as an additional PPU 400, a memory 404, a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), etc.

[0127] In one embodiment, PPU 400 may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to interface with a PCIe slot on a desktop computer's motherboard. In another embodiment, PPU 400 may be an integrated graphics processing unit (iGPU) or a parallel processor included in a chipset on the motherboard. In another embodiment, PPU 400 may be implemented in reconfigurable hardware. In another embodiment, portions of PPU 400 may be implemented in reconfigurable hardware.

[0128] Exemplary Computing System

[0129] As developers expose and exploit greater parallelism in applications such as artificial intelligence computing, systems with multiple GPUs and CPUs are being used across industries. High-performance GPU-accelerated systems with tens to thousands of compute nodes are deployed in data centers, research facilities, and supercomputers to solve increasingly large problems. As the number of processing devices within high-performance systems increases, communication and data transmission mechanisms need to scale to support the increased bandwidth.

[0130] Figure 5A According to one embodiment, using Figure 4 Conceptual diagram of a processing system 500 implemented by a PPU 400. The exemplary system 500 may be configured to implement Figure 2 The processing system 500 includes a CPU 530 , a switch 510 , and multiple PPUs 400 and respective memories 404 .

[0131] NVLink 410 provides a high-speed communication link between each of the PPUs 400. Figure 5B 4 shows a specific number of NVLink 410 and interconnect 402 connections, but the number of connections to each PPU 400 and CPU 530 may vary. Switch 510 forms an interface between interconnect 402 and CPU 530. PPU 400, memory 404, and NVLink 410 may be located on a single semiconductor platform to form a parallel processing module 525. In one embodiment, switch 510 supports two or more protocols to interface between various connections and / or links.

[0132] In another embodiment (not shown), NVLink 410 provides one or more high-speed communication links between each PPU 400 and the CPU 530, and the switch 510 forms an interface between the interconnect 402 and each PPU 400. The PPUs 400, memory 404, and interconnect 402 may be located on a single semiconductor platform to form a parallel processing module 525. In yet another embodiment (not shown), the interconnect 402 provides one or more communication links between each PPU 400 and the CPU 530, and the switch 510 forms an interface between each PPU 400 using NVLink 410 to provide one or more high-speed communication links between the PPUs 400. In another embodiment (not shown), NVLink 410 provides one or more high-speed communication links between the PPUs 400 and the CPU 530 through the switch 510. In yet another embodiment (not shown), the interconnect 402 directly provides one or more communication links between each PPU 400. One or more of the NVLink 410 high-speed communication links may be implemented as a physical NVLink interconnect or as an on-chip or on-die interconnect using the same protocol as NVLink 410 .

[0133] In the context of this specification, a single semiconductor platform may refer to a single semiconductor-based integrated circuit manufactured on a die or chip. It should be noted that the term single semiconductor platform may also refer to a multi-chip module with increased connectivity that simulates on-chip operation and makes significant improvements over conventional bus implementations. Of course, the various circuits or devices may also be located individually in the semiconductor platform or in various combinations thereof as desired by the user. Alternatively, the parallel processing module 525 may be implemented as a circuit board substrate, and each PPU 400 and / or memory 404 may be a packaged device. In one embodiment, the CPU 530, switch 510, and parallel processing module 525 are located on a single semiconductor platform.

[0134] In one embodiment, the signaling rate of each NVLink 410 is 20-25 Gigabits / second, and each PPU 400 includes six NVLink 410 interfaces (e.g., Figure 5A As shown in FIG, each PPU 400 includes five NVLink 410 interfaces. Each NVLink 410 provides a data transfer rate of 25 GBytes / second in each direction, and six links provide 400 GBytes / second. NVLink 410 can be as follows: Figure 5A Shown is used exclusively for PPU-to-PPU communications, or for some combination of PPU-to-PPU and PPU-to-CPU when the CPU 530 also includes one or more NVLink 410 interfaces.

[0135] In one embodiment, NVLink 410 allows direct load / store / atomic access from the CPU 530 to the memory 404 of each PPU 400. In one embodiment, NVLink 410 supports coherency operations, allowing data read from memory 404 to be stored in the cache hierarchy of the CPU 530, reducing cache access latency for the CPU 530. In one embodiment, NVLink 410 includes support for Address Translation Services (ATS), allowing the PPU 400 to directly access the page tables within the CPU 530. One or more of NVLinks 410 can also be configured to operate in a low-power mode.

[0136] Figure 5B An exemplary system 565 is illustrated in which various architectures and / or functionalities of various previous embodiments may be implemented. The exemplary system 565 may be configured to implement Figure 2 One or more methods shown in .

[0137] As shown, a system 565 is provided that includes at least one central processing unit 530 connected to a communication bus 575. The communication bus 575 can directly or indirectly couple one or more of the following devices: main memory 540, network interface 535, CPU 530, display device 545, input device 560, switch 510, and parallel processing system 525. The communication bus 575 can be implemented using any suitable protocol and can represent one or more links or buses, such as an address bus, a data bus, a control bus, or a combination thereof. The communication bus 575 can include one or more bus or link types, such as an Industry Standard Architecture (ISA) bus, an Extended Industry Standard Architecture (EISA) bus, a Video Electronics Standards Association (VESA) bus, a Peripheral Component Interconnect (PCI) bus, a Peripheral Component Interconnect Express (PCIe) bus, HyperTransport, and / or another type of bus or link. In some embodiments, there are direct connections between components. As an example, the CPU 530 can be directly connected to the main memory 540. Additionally, the CPU 530 can be directly connected to the parallel processing system 525. Where there is a direct or point-to-point connection between components, communication bus 575 may include a PCIe link to implement the connection. In these examples, a PCI bus need not be included in system 565.

[0138] Although the use of lines Figure 5CThe different blocks of 525 are shown as being connected via a communication bus 575, but this is not intended to be limiting and is provided for clarity. For example, in some embodiments, presentation components such as display device 545 may be considered I / O components, such as input device 560 (e.g., if the display is a touch screen). As another example, CPU 530 and / or parallel processing system 525 may include memory (e.g., main memory 540 may represent a storage device in addition to parallel processing system 525, CPU 530, and / or other components). In other words, Figure 5C The term computing device is illustrative only. No distinction is made between categories such as "workstation," "server," "laptop," "desktop," "tablet," "client device," "mobile device," "handheld device," "game console," "electronic control unit (ECU)," "virtual reality system," and / or other device or system types, as all are expected to be in the Figure 5C within the range of computing devices.

[0139] The system 565 also includes a main memory 540. Control logic (software) and data are stored in the main memory 540, which can take the form of a variety of computer-readable media. Computer-readable media can be any available media that can be accessed by the system 565. Computer-readable media can include volatile and non-volatile media and removable and non-removable media. By way of example and not limitation, computer-readable media can include computer storage media and communication media.

[0140] Computer storage media may include volatile and nonvolatile media and / or removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules, and / or other data types. For example, main memory 540 may store computer-readable instructions (e.g., representing programs and / or program elements) such as an operating system. Computer storage media may include, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by system 565. As used herein, computer storage media does not include the signals themselves.

[0141] Computer storage media may embody computer-readable instructions, data structures, program modules, or other data types in a modulated data signal such as a carrier wave or other transport mechanism, and include any information delivery media. The term "modulated data signal" may refer to a signal that has one or more of its characteristics set or changed in such a manner as to encode information into the signal. By way of example and not limitation, computer storage media may include wired media such as a wired network or a direct-wired connection, and wireless media such as acoustic, RF, infrared, and other wireless media. Any combination of the above should also be included within the scope of computer-readable media.

[0142] When executed, the computer program enables the system 565 to perform various functions. The CPU 530 can be configured to execute at least some of the computer-readable instructions to control one or more components of the system 565 to perform one or more of the methods and / or processes described herein. Each of the CPUs 530 can include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) capable of processing numerous software threads simultaneously. Depending on the type of system 565 implemented, the CPU 530 can include any type of processor, and can include different types of processors (e.g., a processor with fewer cores for mobile devices, and a processor with more cores for servers). For example, depending on the type of system 565, the processor can be an Advanced RISC Machine (ARM) processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). In addition to one or more microprocessors or supplementary coprocessors such as mathematical coprocessors, the system 565 can include one or more CPUs 530.

[0143] In addition to or in lieu of the CPU 530, the parallel processing module 525 can be configured to execute at least some of the computer-readable instructions to control one or more components of the system 565 to perform one or more of the methods and / or processes described herein. The parallel processing module 525 can be used by the system 565 to render graphics (e.g., 3D graphics) or perform general-purpose computations. For example, the parallel processing module 525 can be used for general-purpose computations on a GPU (GPGPU). In embodiments, the CPU 530 and / or the parallel processing module 525 can perform any combination of the methods, processes, and / or portions thereof, either separately or in conjunction.

[0144] System 565 also includes input device 560, parallel processing system 525, and display device 545. Display device 545 may include a display (e.g., a monitor, a touch screen, a television screen, a head-up display (HUD), other display types, or a combination thereof), speakers, and / or other presentation components. Display device 545 may receive data from other components (e.g., parallel processing system 525, CPU 530, etc.) and output the data (e.g., images, video, sound, etc.).

[0145] The network interface 535 can enable the system 565 to be logically coupled to other devices, including input devices 560, display devices 545, and / or other components, some of which can be embedded in (e.g., integrated into) the system 565. Illustrative input devices 560 include microphones, mice, keyboards, joysticks, game pads, game controllers, satellite dishes, scanners, printers, wireless devices, and the like. The input devices 560 can provide a natural user interface (NUI) that processes user-generated mid-air gestures, voice, or other physiological input. In some instances, the input can be transmitted to an appropriate network element for further processing. The NUI can implement voice recognition, stylus recognition, facial recognition, biometric recognition, gesture recognition on and adjacent to the screen, mid-air gestures, head and eye tracking, and touch recognition associated with the display of the system 565 (as described in more detail below). The system 565 can include a depth camera for gesture detection and recognition, such as a stereo camera system, an infrared camera system, an RGB camera system, touch screen technology, and combinations thereof. Additionally, system 565 may include an accelerometer or gyroscope (e.g., as part of an inertial measurement unit (IMU)) to enable motion detection. In some examples, the output of the accelerometer or gyroscope may be used by system 565 to render immersive augmented or virtual reality.

[0146] In addition, the system 565 can be coupled to a network (e.g., a telecommunications network, a local area network (LAN), a wireless network, a wide area network (WAN) such as the Internet, a peer-to-peer network, a cable network, etc.) for communication purposes through the network interface 535. The system 565 can be included in a distributed network and / or cloud computing environment.

[0147] The network interface 535 may include one or more receivers, transmitters, and / or transceivers that enable the system 565 to communicate with other computing devices via an electronic communication network including wired and / or wireless communications. The network interface 535 may include components and functionality that enable communication over any of a number of different networks, such as wireless networks (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communication over Ethernet or InfiniBand), low-power wide-area networks (e.g., LoRaWAN, SigFox, etc.), and / or the Internet.

[0148] System 565 may also include a secondary storage device (not shown). The secondary storage device includes, for example, a hard disk drive and / or a removable storage drive representing a floppy disk drive, a tape drive, a compact disk drive, a digital versatile disk (DVD) drive, a recording device, or a universal serial bus (USB) flash memory. The removable storage drive reads from and / or writes to the removable storage unit in a well-known manner. System 565 may also include a hardwired power supply, a battery power supply, or a combination thereof (not shown). The power supply can provide power to system 565 to enable the components of system 565 to operate.

[0149] Each of the aforementioned modules and / or devices can even be located on a single semiconductor platform to form system 565. Alternatively, the various modules can be placed individually or in various combinations of semiconductor platforms as desired by the user. Although various embodiments have been described above, it should be understood that they are presented by way of example only and not limitation. Therefore, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

[0150] Sample network environment

[0151] A network environment suitable for implementing embodiments of the present disclosure may include one or more client devices, servers, network attached storage (NAS), other backend devices, and / or other device types. The client devices, servers, and / or other device types (e.g., each device) may be configured to: Figure 5A The processing system 500 and / or Figure 5B 565 , for example, each device may include similar components, features, and / or functionality of the processing system 500 and / or the exemplary system 565 .

[0152] The components of a network environment can communicate with each other via a network, which can be wired, wireless, or a combination thereof. A network can include multiple networks or networks of networks. For example, a network can include one or more wide area networks (WANs), one or more local area networks (LANs), one or more public networks, such as the Internet, and / or a public switched telephone network (PSTN), and / or one or more private networks. Where the network includes a wireless telecommunications network, components such as base stations, communication towers, or even access points (among other components) can provide wireless connectivity.

[0153] Compatible network environments may include one or more peer-to-peer network environments, in which case the server may not be included in the network environment, and one or more client-server network environments, in which case one or more servers may be included in the network environment. In a peer-to-peer network environment, the functionality described herein with respect to the server may be implemented on any number of client devices.

[0154] In at least one embodiment, the network environment may include one or more cloud-based network environments, distributed computing environments, combinations thereof, and the like. The cloud-based network environment may include a framework layer, a job scheduler, a resource manager, and a distributed file system implemented on one or more servers, which may include one or more core network servers and / or edge servers. The framework layer may include software supporting the software layer and / or a framework for one or more applications in the application layer. The software or application may include web-based service software or applications, respectively. In an embodiment, one or more of the client devices may use web-based service software or applications (e.g., by accessing the service software and / or application via one or more application programming interfaces (APIs)). The framework layer may be, but is not limited to, a free, open source software web application framework type that can, for example, use a distributed file system for large-scale data processing (e.g., "big data").

[0155] A cloud-based network environment can provide cloud computing and / or cloud storage that implements the computing and / or data storage functionality (or one or more portions thereof) described herein. Any of these different functions can be distributed across multiple locations from a central or core server (e.g., a central or core server in one or more data centers, which can be distributed across states, regions, countries, the world, etc.). If the connection to the user (e.g., a client device) is relatively close to an edge server, the core server can assign at least a portion of the functionality to the edge server. A cloud-based network environment can be private (e.g., limited to a single organization), public (e.g., available to many organizations), and / or a combination thereof (e.g., a hybrid cloud environment).

[0156] Client devices may include Figure 5B The example processing system 500 and / or Figure 5C At least some of the components, features, and functionality of the exemplary system 565 of FIG. By way of example and not limitation, the client device may be embodied as a personal computer (PC), a laptop, a mobile device, a smartphone, a tablet, a smartwatch, a wearable computer, a personal digital assistant (PDA), an MP3 player, a virtual reality headset, a global positioning system (GPS) or device, a video player, a video camera, a surveillance device or system, a vehicle, a boat, a spacecraft, a virtual machine, a drone, a robot, a handheld communication device, a hospital device, a gaming device or system, an entertainment system, a vehicle computer system, an embedded system controller, a remote control, an appliance, a consumer electronic device, a workstation, an edge device, any combination of these delineated devices, or any other suitable device.

[0157] Machine Learning

[0158] Deep neural networks (DNNs) developed on processors like the PPU 400 are already being used in a wide variety of use cases, from self-driving cars to faster drug discovery, from automatic image captioning from online image databases to intelligent real-time language translation in video chat applications. Deep learning is a technique that models the neural learning processes of the human brain, continuously learning, getting smarter, and delivering more accurate results faster over time. A child is initially taught by an adult to correctly identify and classify a variety of different shapes, and eventually is able to identify shapes without any guidance. Similarly, a deep learning or neural learning system needs to be trained in object recognition and classification so that it becomes smarter and more efficient at identifying basic objects, occluded objects, and so on, while also attributing context to objects.

[0159] At the simplest level, neurons in the human brain view various inputs, assign a level of importance to each of these inputs, and pass outputs to other neurons to react. Artificial neurons, or perceptrons, are the most basic model of a neural network. In one example, a perceptron can receive one or more inputs representing various features of the object it is being trained to recognize and classify, and each of these features is assigned a weight based on its importance in defining the object's shape.

[0160] Deep neural network (DNN) models include multiple layers of many connected nodes (such as perceptrons, Boltzmann machines, radial basis functions, convolutional layers, etc.), which can be trained with huge amounts of input data to quickly solve complex problems with high accuracy. In one example, the first layer of a DNN model breaks down an input image of a car into different segments and looks for basic patterns such as lines and angles. The second layer assembles these lines to find higher-level patterns such as wheels, windshields, and mirrors. The next layer identifies the type of vehicle, and the final layers generate tags for the input image, identifying the model of a specific car brand.

[0161] Once trained, a DNN can be deployed and used to identify and classify objects or patterns in a process called inference. Examples of inference (the process by which a DNN extracts useful information from a given input) include identifying handwritten digits on a check deposited at an ATM, identifying images of friends in photos, delivering movie recommendations to over 50 million users, identifying and classifying different types of cars, pedestrians, and road hazards in self-driving cars, or translating human language in real time.

[0162] During training, data flows through the DNN in a forward propagation phase until a prediction is produced indicating a label that corresponds to the input. If the neural network does not label the input correctly, the error between the correct label and the predicted label is analyzed, and the weights are adjusted for each feature during a backpropagation phase until the DNN correctly labels the input, as well as other inputs in the training dataset. Training complex neural networks requires a large amount of parallel computing performance, including floating-point multiplication and addition supported by the PPU400. Inference, which is less computationally intensive than training, is a latency-sensitive process in which the trained neural network is applied to new inputs it has not seen before in order to classify images, detect emotions, identify recommendations, recognize and translate languages, and generally reason about new information.

[0163] Neural networks rely heavily on matrix math operations, and complex, multi-layer networks require massive floating-point performance and bandwidth for both efficiency and speed. Leveraging thousands of processing cores optimized for matrix math operations and delivering tens to hundreds of TFLOPS of performance, the PPU 400 is a computing platform capable of delivering the performance required for deep neural network-based artificial intelligence and machine learning applications.

[0164] In addition, images generated using one or more of the techniques disclosed herein can be used to train, test, or certify DNNs for recognizing objects and environments in the real world. Such images can include scenes of roadways, factories, buildings, urban environments, rural environments, humans, animals, and any other physical objects or real-world environments. Such images can be used to train, test, or certify DNNs employed in machines or robots to manipulate, process, or modify physical objects in the real world. In addition, such images can be used to train, test, or certify DNNs employed in autonomous vehicles to navigate and move the vehicle in the real world. In addition, images generated using one or more of the techniques disclosed herein can be used to communicate information to users of such machines, robots, and vehicles.

[0165] Figure 5C Components of an example system 555 that can be used to train and utilize machine learning in accordance with at least one embodiment are shown. As will be discussed, various components can be provided by a single computing system or various combinations of computing devices and resources, which can be under the control of a single entity or multiple entities. Furthermore, various aspects can be triggered, initiated, or requested by different entities. In at least one embodiment, the training of a neural network can be directed by a vendor associated with a vendor environment 506, while in at least one embodiment, training can be requested by a customer or other user who can access the vendor environment via a client device 502 or other such resource. In at least one embodiment, training data (or data to be analyzed by the trained neural network) can be provided by a vendor, a user, or a third-party content provider 524. In at least one embodiment, a client device 502 can be, for example, a vehicle or object to be navigated on behalf of a user, who can submit requests and / or receive instructions to facilitate device navigation.

[0166] In at least one embodiment, the request can be submitted via at least one network 504 for receipt by the provider environment 506. In at least one embodiment, the client device can be any suitable electronic and / or computing device that enables a user to generate and send such a request, such as, but not limited to, a desktop computer, a laptop computer, a computer server, a smartphone, a tablet computer, a game console (portable or otherwise), a computer processor, computing logic, and a set-top box. The one or more networks 504 may include any suitable network for transmitting the request or other such data, and may include, for example, the Internet, an intranet, an Ethernet network, a cellular network, a local area network (LAN), a wide area network (WAN), a personal area network (PAN), an ad hoc network with direct wireless connections between peers, and the like.

[0167] In at least one embodiment, a request may be received at interface layer 508, which in this example may forward the data to training and inference manager 532. Training and inference manager 532 may be a system or service comprising hardware and software for managing services and requests corresponding to data or content. In at least one embodiment, training and inference manager 532 may receive a request to train a neural network and may provide the requested data to training module 512. In at least one embodiment, if the request is unspecified, training module 512 may select an appropriate model or neural network to use and may use the associated training data to train the model. In at least one embodiment, the training data may be a batch of data stored in training data repository 514, received from client device 502, or obtained from third-party vendor 524. In at least one embodiment, training module 512 may be responsible for the training data. The neural network may be any suitable network, such as a recurrent neural network (RNN) or a convolutional neural network (CNN). Once the neural network is trained and successfully evaluated, the trained neural network may be stored, for example, in model repository 516, which may store different models or networks for users, applications, services, and the like. In at least one embodiment, there may be multiple models for a single application or entity, which may be utilized based on a number of different factors.

[0168] In at least one embodiment, at a later point in time, a request for content (e.g., a path determination) or data determined or influenced at least in part by a trained neural network may be received from client device 502 (or another such device). The request may include, for example, input data to be processed using the neural network to obtain one or more inferences or other output values, classifications, or predictions, or for at least one embodiment, the input data may be received by interface layer 508 and directed to inference module 518, although a different system or service may also be used. In at least one embodiment, if not already locally stored to inference module 518, inference module 518 may obtain a suitable trained network from model repository 516, such as a trained deep neural network (DNN) as discussed herein. Inference module 518 may provide data as input to the trained network, which may then generate one or more inferences as output. For example, this may include a classification of the input data instance. In at least one embodiment, the inferences may then be transmitted to client device 502 for display or other communication to the user. In at least one embodiment, user context data may also be stored in a user context data repository 522, which may include data about the user that can be used as network input for generating inferences or determining data to be returned to the user after obtaining an instance. In at least one embodiment, related data, including at least some of the input or inference data, may also be stored in a local database 534 for use in processing future requests. In at least one embodiment, a user may use account information or other information to access resources or functionality in the provider environment. In at least one embodiment, if permitted and available, user data may also be collected and used to further train a model to provide more accurate inferences for future requests. In at least one embodiment, requests for a machine learning application 526 executing on a client device 502 may be received through a user interface, and results may be displayed through the same interface. The client device may include resources such as a processor 528 and memory 562 for generating requests and processing results or responses, as well as at least one data storage element 552 for storing data for the machine learning application 526.

[0169] In at least one embodiment, processor 528 (or the processor of training module 512 or inference module 518) will be a central processing unit (CPU). However, as described above, resources in such environments may utilize GPUs to process data for at least certain types of requests. GPUs, such as PPU 400, have thousands of cores and are designed to handle massively parallel workloads, making them popular in deep learning for training neural networks and generating predictions. While using GPUs for offline building allows for faster training of larger and more complex models, generating predictions offline means that request-time input features cannot be used, or predictions must be generated for all feature permutations and stored in lookup tables to service real-time requests. If the deep learning framework supports CPU mode, and the model is small and simple enough that feedforward execution can be performed on the CPU with reasonable latency, a service on a CPU instance can host the model. In this case, training can be performed offline on the GPU, and inference can be performed in real time on the CPU. If a CPU approach is not feasible, the service can run on a GPU instance. However, because GPUs have different performance and cost characteristics than CPUs, running a service that offloads runtime algorithms to a GPU may require a different design than a CPU-based service.

[0170] In at least one embodiment, video data may be provided from the client device 502 for enhancement in the vendor environment 506. In at least one embodiment, the video data may be processed for enhancement on the client device 502. In at least one embodiment, the video data may be streamed from a third-party content provider 524 and enhanced by the third-party content provider 524, the vendor environment 506, or the client device 502. In at least one embodiment, video data may be provided from the client device 502 for use as training data in the vendor environment 506.

[0171] In at least one embodiment, supervised and / or unsupervised training can be performed by the client device 502 and / or the vendor environment 506. In at least one embodiment, a set of training data 514 (e.g., classified or labeled data) is provided as input for use as training data. In one embodiment, the set of training data can be used in a generative adversarial training configuration to train a generator neural network.

[0172] In at least one embodiment, the training data may include images of at least one human subject, avatar, or character on which the neural network is to be trained. In at least one embodiment, the training data may include instances of at least one type of object on which the neural network is to be trained, as well as information identifying the type of object. In at least one embodiment, the training data may include a collection of images, each image including a representation of a type of object, wherein each image also includes or is associated with labels, metadata, classifications, or other information identifying the type of object represented in the corresponding image. Various other types of data may also be used as training data, including text data, audio data, video data, and the like. In at least one embodiment, the training data 514 is provided as training input to the training module 512. In at least one embodiment, the training module 512 may be a system or service comprising hardware and software, such as one or more computing devices executing a training application for training a neural network (or other model or algorithm, etc.). In at least one embodiment, the training module 512 receives an instruction or request indicating the type of model to be used for training. In at least one embodiment, the model may be any suitable statistical model, network, or algorithm useful for such a purpose, including artificial neural networks, deep learning algorithms, learning classifiers, Bayesian networks, and the like. In at least one embodiment, the training module 512 can select an initial model or other untrained model from an appropriate repository and train the model using the training data 514, thereby generating a trained model (e.g., a trained deep neural network) that can be used to classify similar types of data or generate other such inferences. In at least one embodiment where training data is not used, an initial model can still be selected to train the input data of each training module 512.

[0173] In at least one embodiment, the model can be trained in several different ways, which may depend in part on the type of model selected. In at least one embodiment, a training data set can be provided to a machine learning algorithm, where the model is a model artifact created by the training process. In at least one embodiment, each instance of the training data contains a correct answer (e.g., a classification) that can be called a target or target attribute. In at least one embodiment, the learning algorithm finds patterns in the training data that map the input data attributes to the target (the answer to be predicted), and the machine learning model is the output that captures these patterns. In at least one embodiment, the machine learning model can then be used to obtain predictions for new data for which the target is not specified.

[0174] In at least one embodiment, the training and inference manager 532 can select from a set of machine learning models including binary classification, multi-class classification, generative, and regression models. In at least one embodiment, the type of model to use can depend at least in part on the type of target to be predicted.

[0175] Graphics processing pipeline

[0176] In one embodiment, the PPU 400 comprises a graphics processing unit (GPU). The PPU 400 is configured to receive commands specifying a shader program for processing graphics data. Graphics data can be defined as a set of primitives such as points, lines, triangles, quadrilaterals, triangle strips, and the like. Typically, a primitive includes data specifying the number of vertices for the primitive (e.g., in a model-space coordinate system) and attributes associated with each vertex of the primitive. The PPU 400 can be configured to process the graphics primitives to generate a frame buffer (e.g., pixel data for each of the pixels of a display).

[0177] An application writes model data (e.g., attributes and vertex sets) for a scene to a memory such as system memory or memory 404. The model data defines each of the objects that may be visible on the display. The application then makes an API call to the driver kernel, requesting that the model data be rendered and displayed. The driver kernel reads the model data and writes commands to the one or more streams to perform operations to process the model data. These commands may reference different shader programs to be implemented on the processing units within PPU 400, including one or more of a vertex shader, a hull shader, a domain shader, a geometry shader, and a pixel shader. For example, one or more of the processing units may be configured to execute a vertex shader program that processes a number of vertices defined by the model data. In one embodiment, these different processing units may be configured to execute different shader programs concurrently. For example, a first subset of processing units may be configured to execute a vertex shader program, while a second subset of processing units may be configured to execute a pixel shader program. The first subset of processing units processes the vertex data to generate processed vertex data, and writes the processed vertex data to L2 cache 460 and / or memory 404. After the processed vertex data is rasterized (e.g., transformed from three-dimensional data to two-dimensional data in screen space) to generate fragment data, the second subset of processing units executes a pixel shader to generate processed fragment data, which is then blended with other processed fragment data and written to a frame buffer in memory 404. The vertex shader program and the pixel shader program can be executed concurrently, processing different data from the same scene in a pipelined manner until all model data for the scene is rendered to the frame buffer. The contents of the frame buffer are then transmitted to the display controller for display on a display device.

[0178] Figure 6A According to one embodiment, Figure 44. A conceptual diagram of a graphics processing pipeline 600 implemented by a PPU 400 of FIG. The graphics processing pipeline 600 is an abstract flow diagram of the processing steps implemented to generate a 2D computer-generated image from 3D geometric data. As is well known, pipeline architectures can perform long-latency operations more efficiently by dividing the operations into multiple stages, where the output of each stage is coupled to the input of the next subsequent stage. Thus, the graphics processing pipeline 600 receives input data 601 that is passed from one stage of the graphics processing pipeline 600 to the next stage to generate output data 602. In one embodiment, the graphics processing pipeline 600 may represent a graphics processing pipeline composed of API-defined graphics processing pipeline. As an option, graphics processing pipeline 600 can be implemented within the functional and architectural context of the previous figures and / or one or more of any subsequent figures.

[0179] like Figure 6A As shown, graphics processing pipeline 600 includes a pipeline architecture comprising multiple stages. These stages include, but are not limited to, a data assembly stage 610, a vertex shading stage 620, a primitive assembly stage 630, a geometry shading stage 640, a viewport scale, cull, and clip (VSCC) stage 650, a rasterization stage 660, a fragment shading stage 670, and a raster operation stage 680. In one embodiment, input data 601 includes commands that configure a processing unit to implement the stages of graphics processing pipeline 600 and configure geometric primitives (e.g., points, lines, triangles, quads, triangle strips, or fans, etc.) to be processed by these stages. Output data 602 may include pixel data (e.g., color data), which is copied to a frame buffer or other type of surface data structure in memory.

[0180] The data assembly stage 610 receives input data 601, which specifies vertex data for high-level surfaces, primitives, etc. The data assembly stage 610 collects the vertex data in temporary storage or queues, for example, by receiving a command from a host processor including a pointer to a buffer in memory and reading the vertex data from the buffer. The vertex data is then passed to the vertex shading stage 620 for processing.

[0181] The vertex shading stage 620 processes vertex data by executing a set of operations (e.g., a vertex shader or program) once for each vertex. A vertex may be specified, for example, as a 4-coordinate vector (e.g., ) associated with one or more vertex attributes (e.g., color, texture coordinates, surface normal, etc.).<x,y,z,w> ). The vertex shading stage 620 can manipulate various vertex attributes, such as position, color, texture coordinates, etc. In other words, the vertex shading stage 620 performs operations on the vertex coordinates or other vertex attributes associated with the vertex. Such operations typically include lighting operations (e.g., modifying the color attribute of a vertex) and transformation operations (e.g., modifying the coordinate space of a vertex). For example, a vertex can be specified using coordinates in an object coordinate space, which is transformed by multiplying the coordinates by a matrix that converts the coordinates from the object coordinate space to world space or normalized-device-coordinate (NCD) space. The vertex shading stage 620 generates transformed vertex data that is passed to the primitive assembly stage 630.

[0182] The primitive assembly stage 630 collects the vertices output by the vertex shading stage 620 and groups the vertices into geometric primitives for processing by the geometry shading stage 640. For example, the primitive assembly stage 630 can be configured to group every three consecutive vertices into geometric primitives (e.g., triangles) for transmission to the geometry shading stage 640. In some embodiments, particular vertices can be reused for consecutive geometric primitives (e.g., two consecutive triangles in a triangle strip can share two vertices). The primitive assembly stage 630 transmits the geometric primitives (e.g., a collection of associated vertices) to the geometry shading stage 640.

[0183] The geometry shading stage 640 processes geometric primitives by executing a set of operations (e.g., a geometry shader or program) on the geometric primitives. A tessellation operation can generate one or more geometric primitives from each geometric primitive. In other words, the geometry shading stage 640 can subdivide each geometric primitive into a finer mesh of two or more geometric primitives for processing by the rest of the graphics processing pipeline 600. The geometry shading stage 640 passes the geometric primitives to the viewport SCC stage 650.

[0184] In one embodiment, the graphics processing pipeline 600 may operate within a streaming multiprocessor, and the vertex shading stage 620, primitive assembly stage 630, geometry shading stage 640, fragment shading stage 670, and / or hardware / software associated therewith may perform processing operations sequentially. In one embodiment, once the sequential processing operations are completed, the viewport SCC stage 650 may utilize the data. In one embodiment, primitive data processed by one or more stages in the graphics processing pipeline 600 may be written to a cache (e.g., an L1 cache, a vertex cache, etc.). In this case, in one embodiment, the viewport SCC stage 650 may access the data in the cache. In one embodiment, the viewport SCC stage 650 and the rasterization stage 660 are implemented as fixed-function circuitry.

[0185] The viewport SCC stage 650 performs viewport scaling, culling, and clipping of geometric primitives. Each surface being rendered is associated with an abstract camera position. The camera position represents the position of the viewer viewing the scene and defines a viewing frustum that surrounds the objects of the scene. The viewing frustum can include a viewing plane, a back plane, and four clipping planes. Any geometric primitive that is completely outside the viewing frustum can be culled (e.g., discarded) because it will not contribute to the final rendered scene. Any geometric primitive that is partially inside the viewing frustum and partially outside the viewing frustum can be clipped (e.g., transformed into a new geometric primitive that is enclosed within the viewing frustum). In addition, each geometric primitive can be scaled based on the depth of the viewing frustum. All potentially visible geometric primitives are then passed to the rasterization stage 660.

[0186] The rasterization stage 660 converts 3D geometric primitives into 2D fragments (e.g., capable of being used for display, etc.). The rasterization stage 660 can be configured to use the vertices of the geometric primitives to set a set of plane equations from which various attributes can be interpolated. The rasterization stage 660 can also calculate a coverage mask for multiple pixels, which indicates whether one or more sample positions of the pixel intercept the geometric primitive. In one embodiment, a z test can also be performed to determine whether the geometric primitive is occluded by other geometric primitives that have been rasterized. The rasterization stage 660 generates fragment data (e.g., interpolated vertex attributes associated with a specific sample position for each covered pixel), which is passed to the fragment shading stage 670.

[0187] The fragment shading stage 670 processes the fragment data by executing a set of operations (e.g., a fragment shader or program) on each of the fragments. The fragment shading stage 670 can generate pixel data (e.g., color values) for the fragment, such as by performing lighting operations or sampling a texture map using the fragment's interpolated texture coordinates. The fragment shading stage 670 generates pixel data, which is passed to the raster operations stage 680.

[0188] The raster operations stage 680 may perform various operations on the pixel data, such as performing alpha tests, stencil tests, and blending the pixel data with other pixel data corresponding to other fragments associated with the pixel. When the raster operations stage 680 has completed processing the pixel data (e.g., output data 602), the pixel data may be written to a render target, such as a frame buffer, a color buffer, etc.

[0189] It should be appreciated that one or more additional stages may be included in graphics processing pipeline 600 in addition to or in place of one or more of the above-described stages. Various implementations of the abstract graphics processing pipeline may implement different stages. Furthermore, in some embodiments, one or more of the above-described stages may be excluded from the graphics processing pipeline (such as geometry shading stage 640). Other types of graphics processing pipelines are contemplated as being within the scope of the present disclosure. Furthermore, any stage of graphics processing pipeline 600 may be implemented by one or more dedicated hardware units within a graphics processor such as PPU 400. Other stages of graphics processing pipeline 600 may be implemented by programmable hardware units such as processing units within PPU 400.

[0190] The graphics processing pipeline 600 can be implemented via an application program executed by a host processor, such as a CPU. In one embodiment, a device driver can implement an application programming interface (API) that defines various functions that can be utilized by the application program to generate graphics data for display. A device driver is a software program that includes multiple instructions that control the operation of the PPU 400. The API provides an abstraction for programmers, allowing them to utilize specialized graphics hardware, such as the PPU 400, to generate graphics data without requiring them to utilize the specific instruction set of the PPU 400. An application program can include API calls that are routed to the device driver of the PPU 400. The device driver interprets the API calls and performs various operations in response to the API calls. In some cases, the device driver can perform operations by executing instructions on the CPU. In other cases, the device driver can perform operations at least in part by initiating operations on the PPU 400 using an input / output interface between the CPU and the PPU 400. In one embodiment, the device driver is configured to implement the graphics processing pipeline 600 using the hardware of the PPU 400.

[0191] Various programs may be executed within the PPU 400 to implement the various stages of the graphics processing pipeline 600. For example, a device driver may launch a kernel on the PPU 400 to execute the vertex shading stage 620 on one processing unit (or multiple processing units). The device driver (or the initial kernel executed by the PPU 400) may also launch other kernels on the PPU 400 to execute other stages of the graphics processing pipeline 600, such as the geometry shading stage 640 and the fragment shading stage 670. Additionally, some of the stages of the graphics processing pipeline 600 may be implemented on fixed unit hardware, such as a rasterizer or data assembler implemented within the PPU 400. It should be appreciated that the results from one kernel may be processed by one or more intermediate fixed-function hardware units before being processed by subsequent kernels on the processing unit.

[0192] The images generated by applying one or more of the techniques disclosed herein can be displayed on a monitor or other display device. In some embodiments, the display device can be directly coupled to the system or processor that generates or renders the image. In other embodiments, the display device can be indirectly coupled to the system or processor, for example, via a network. Examples of such networks include the Internet, mobile telecommunications networks, WIFI networks, and any other wired and / or wireless networking systems. When the display device is indirectly coupled, the image generated by the system or processor can be streamed to the display device via the network. Such streaming allows, for example, a video game or other application that renders an image to be executed on a server, a data center, or in a cloud-based computing environment, and the rendered image is transmitted and displayed on one or more user devices (e.g., computers, video game consoles, smart phones, other mobile devices, etc.) that are physically separated from the server or data center. Therefore, the techniques disclosed herein can be applied to enhance the images being streamed, and enhance services that stream images, such as NVIDIA GeForce Now (GFN), Google Stadia, etc.

[0193] Sample game streaming system

[0194] Figure 6B FIG. 6 is a diagram illustrating an example system of a game streaming system 605 according to some embodiments of the present disclosure. Figure 6B Includes one or more game servers 603 (which may include Figure 5A The example processing system 500 and / or Figure 5B ), one or more clients 604 (which may include components, features, and / or functionality similar to the exemplary system 565 of Figure 5A The example processing system 500 and / or Figure 5B 5 and / or similar components, features, and / or functionality to the exemplary system 565 of FIG. ...

[0195] In system 605, for a game session, one or more client devices 604 may simply receive input data in response to input from one or more input devices, send the input data to one or more game servers 603, receive encoded display data from the one or more game servers 603, and display the display data on a display 624. In this way, more computationally intensive calculations and processing are offloaded to one or more game servers 603 (e.g., rendering of the game session's graphical output, particularly ray or path tracing, is performed by one or more GPUs of the one or more game servers 603). In other words, the game session is streamed from one or more game servers 603 to one or more client devices 604, thereby reducing the graphics processing and rendering requirements of the one or more client devices 604.

[0196] For example, with respect to instantiation of a game session, client device 604 may be displaying a frame of the game session on display 624 based on display data received from one or more game servers 603. Client device 604 may receive input from one of the one or more input devices and, in response, generate input data. Client device 604 may send the input data to one or more game servers 603 via communication interface 621 and over one or more networks 606 (e.g., the Internet), and one or more game servers 603 may receive the input data via communication interface 618. One or more CPUs may receive the input data, process the input data, and send the data to a GPU, which causes the GPU to generate a rendering of the game session. For example, the input data may represent the movement of a user character in the game, firing a weapon, reloading, passing a ball, steering a vehicle, and so on. Rendering component 612 may render the game session (e.g., representing the results of the input data), and rendering capture component 614 may capture the rendering of the game session as display data (e.g., as image data capturing a rendered frame of the game session). The rendering of the game session may include ray or path traced lighting and / or shading effects calculated using one or more parallel processing units (e.g., GPUs, which may further employ the use of one or more dedicated hardware accelerators or processing cores to perform ray or path tracing techniques) of one or more game servers 603. The encoder 616 may then encode the display data to generate encoded display data, and the encoded display data may be sent to the client device 604 via the communication interface 618 over one or more networks 606. The client device 604 may receive the encoded display data via the communication interface 621, and the decoder 622 may decode the encoded display data to generate display data. The client device 604 may then display the display data via the display 624.

[0197] It should be noted that the techniques described herein may be included in executable instructions stored in a computer-readable medium, which are used by or in conjunction with a processor-based instruction execution machine, system, device, or apparatus. Those skilled in the art will appreciate that for some embodiments, various different types of computer-readable media may be included for storing data. As used herein, "computer-readable medium" includes one or more of any suitable media for storing executable instructions of a computer program, such that an instruction execution machine, system, apparatus, or device can read (or retrieve) instructions from the computer-readable medium and execute these instructions to implement the described embodiments. Suitable storage formats include one or more of electronic, magnetic, optical, and electromagnetic formats. A non-exhaustive list of conventional exemplary computer-readable media includes: portable computer disks; random access memory (RAM); read-only memory (ROM); erasable programmable read-only memory (EPROM); flash memory devices; and optical storage devices, including portable compact disks (CDs), portable digital video disks (DVDs), and the like.

[0198] It should be understood that the arrangement of the components shown in the drawings is for illustrative purposes, and other arrangements are possible. For example, one or more of the elements described herein can be implemented as electronic hardware components in whole or in part. Other elements can be implemented in software, hardware, or a combination of software and hardware. Moreover, some or all of these other elements can be combined, some can be omitted completely, and additional components can be added while still realizing the functions described herein. Therefore, the subject matter described herein can be implemented in many different variations, and all such variations are expected to be within the scope of the claims.

[0199] For the ease of understanding theme described herein, many aspects are described according to action sequence.Those skilled in the art will recognize that various actions can be performed by dedicated circuit or circuit system, by the program instruction of one or more processors or by the combination of the two.This paper does not expect to mean that the particular order that is described for carrying out this sequence must be followed for the description of any action sequence.All methods described herein can be performed in any appropriate order, unless this paper indicates otherwise or otherwise obviously contradicts with context.

[0200] The use of the terms "a," "an," "the," and similar designations in the context of describing the subject matter (especially in the context of the claims below) should be interpreted to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. The use of the term "at least one" (e.g., at least one of A and B) followed by a list of one or more items should be interpreted to mean one item (A or B) selected from the listed items, or any combination of two or more of the listed items (A and B), unless otherwise indicated herein or clearly contradicted by the context. In addition, the foregoing description is for illustrative purposes only and not for limiting purposes, as the scope of protection sought is defined by the claims set forth hereafter along with their equivalents. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended solely to better illustrate the subject matter and does not constitute a limitation on the scope of the subject matter, unless otherwise stated. The use of "based on" and other similar phrases in both the claims and the written specification to indicate a condition that brings about a result is not intended to exclude any other condition that brings about that result. The language in the specification should not be interpreted as indicating that any unclaimed element is essential to the implementation of the claimed invention.

Claims

1. A method for tracking an instance within a sequence of video frames, the method comprising: The image frame is processed by the backbone network to generate a set of feature maps; processing the set of feature maps by one or more prediction heads, wherein the one or more prediction heads include an embedding head configured to generate a set of embedded features corresponding to one or more instances of an object identified in the image frame; as well as The embedded features corresponding to a set of instances in two or more image frames of the video frame sequence are analyzed to establish a one-to-one correlation between the instances in the different image frames, wherein the central representations of the instances in the video frame sequence are compared to identify instance correlations across the video frame sequence, and wherein the central representation of the instance is obtained by averaging all the embedded features to a given instance.

2. The method of claim 1 , wherein the one or more prediction heads further comprise: a classification head configured to predict locations of zero or more instances of each of a plurality of object classes in the image; as well as A mask head is configured to predict a pixel-wise segmentation mask for each instance in the image.

3. The method of claim 1, wherein the embedding head comprises a keypoint embedding head, the keypoint embedding head comprises an encoder-decoder structure, wherein the encoder-decoder structure comprises an encoder and a decoder, the encoder comprises a convolutional layer, and the decoder comprises a deconvolutional layer.

4. The method of claim 3, wherein the one or more prediction heads include a classification head and a shape regression head, the shape regression head configured to estimate a pose estimate for each instance based on a plurality of key points.

5. The method of claim 1, wherein the backbone network comprises a feature pyramid network, and wherein the set of feature maps comprises a plurality of feature maps of different spatial resolutions.

6. The method of claim 1 , further comprising: The one or more prediction heads are trained using a set of annotated image frames and / or a plurality of unlabeled video frame sequences.

7. The method of claim 6, wherein training the embedding head comprises: Minimize the instance contrastive loss term.

8. The method of claim 7, wherein training the embedding head further comprises: Enforces maximum entropy regularization on the similarity matrix.

9. The method of claim 6, wherein training the embedding head comprises: Minimize the loop loss term computed based on the forward affinity matrix and the backward affinity matrix corresponding to the sequence of video frames.

10. A system for tracking an instance within a sequence of video frames, comprising: non-transitory computer-readable memory; and At least one processor configured to implement a plurality of neural networks, the plurality of neural networks comprising: a backbone network configured to process image frames and generate a set of feature maps; and One or more prediction heads configured to process the set of feature maps generated by the backbone network, wherein the one or more prediction heads include an embedding head configured to generate a set of embedded features corresponding to one or more instances of an object identified in the image frame, wherein the embedded features corresponding to a set of instances in two or more image frames of the video frame sequence are analyzed to establish a one-to-one correlation between instances in different image frames, wherein central representations of instances in the video frame sequence are compared to identify instance correlations across the video frame sequence, and wherein the central representation of an instance is obtained by averaging all the embedded features to a given instance.

11. The system of claim 10, wherein the one or more prediction heads further comprise: a classification head configured to predict locations of zero or more instances of each of a plurality of object classes in the image; as well as A mask head is configured to predict a pixel-wise segmentation mask for each instance in the image.

12. The system of claim 10, wherein the embedding head comprises a keypoint embedding head, the keypoint embedding head comprises an encoder-decoder structure, wherein the encoder-decoder structure comprises an encoder and a decoder, the encoder comprises a convolutional layer, and the decoder comprises a deconvolutional layer.

13. The system of claim 12, wherein the one or more prediction heads include a classification head and a shape regression head configured to estimate a pose estimate for each instance based on a plurality of keypoints.

14. The system of claim 10, wherein the backbone network comprises a feature pyramid network, and wherein the set of feature maps comprises a plurality of feature maps of different spatial resolutions.

15. The system of claim 10, wherein the one or more prediction heads are trained using a set of annotated images and a plurality of unlabeled video frame sequences.

16. The system of claim 10, wherein training the embedding head comprises: Minimizes the instance contrastive loss term and enforces maximum entropy regularization on the similarity matrix.

17. The system of claim 10, wherein training the embedding head comprises: Minimize the loop loss term computed based on the forward affinity matrix and the backward affinity matrix corresponding to the sequence of video frames.

18. The system of claim 10, wherein the at least one processor comprises a parallel processing unit.

19. The system of claim 10, wherein the system is included in an autonomous vehicle.

20. A non-transitory computer-readable medium storing instructions that, in response to execution of the instructions by one or more processors, cause a computing system to track instances within a sequence of video frames by: The image frame is processed by the backbone network to generate a set of feature maps; processing the set of feature maps by one or more prediction heads, wherein the one or more prediction heads include an embedding head configured to generate a set of embedded features corresponding to one or more instances of an object identified in the image frame; as well as The embedded features corresponding to a set of instances in two or more image frames of the video frame sequence are analyzed to establish a one-to-one correlation between the instances in the different image frames, wherein the central representations of the instances in the video frame sequence are compared to identify instance correlations across the video frame sequence, and wherein the central representation of the instance is obtained by averaging all the embedded features to a given instance.

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