Access management methods, memory devices, electronic devices, and controllers

Abstract

This invention provides a method for managing access to a memory device via a universal asynchronous transceiver (UART) connection. The method may include: receiving a set of intermediate commands corresponding to a set of operation commands via a UART connection between a memory device and a host device using a UART of a memory controller, wherein the host device converts the set of operation commands into the set of intermediate commands before transmitting the set of intermediate commands to the memory controller via the UART connection; converting the set of intermediate commands into the set of operation commands according to a command mapping table; using the set of operation commands to access non-volatile memory for the host device; and transmitting a response to the host device via the UART connection.

Description

Technical Field

[0001] This invention relates to memory control, and more particularly to a method and apparatus for managing access to a memory device via a universal asynchronous receiver-transmitter (UART) connection. Background Technology

[0002] Memory devices may include flash memory for storing data, and managing access to flash memory is quite complex. During the preliminary phase, such as the design phase (e.g., one of several pilot run phases), prior to mass production, access test operations may need to be performed on the memory device to develop one or more flash memory access algorithms. However, some problems may arise. Taking a universal flash storage (UFS) device as an example, in the preliminary phase of a UFS device, some communication features may be poorly designed (e.g., the UFS device may not support UFS communication at this stage), which may delay the testing schedule for access test operations. However, no suitable solution has been found in the prior art; therefore, an innovative method and related architecture are needed to solve these problems without introducing side effects or in a way that is unlikely to introduce side effects. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a method and apparatus for managing access to a memory device using a universal asynchronous transceiver connection, in order to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a method for access management of a memory device via a universal asynchronous transceiver (UART) connection, wherein the method can be applied to a memory controller of the memory device, the memory device may include the memory controller and a non-volatile (NV) memory, and the NV memory may include at least one NV memory element (e.g., one or more NV memory elements). The method may include: receiving a set of intermediate commands corresponding to a set of operation commands via a UART connection between the memory device and a host device using a UART of the memory controller, wherein the host device converts the set of operation commands into the set of intermediate commands before transmitting the set of intermediate commands to the memory controller via the UART connection; converting the set of intermediate commands into the set of operation commands according to a command mapping table, wherein the command mapping table is located in the memory device; using the set of operation commands to access the NV memory for the host device; and transmitting a response to the host device via the UART connection.

[0005] In addition to the methods described above, the present invention also provides a memory device, which includes a non-volatile memory and a controller. The non-volatile memory is used to store information, and may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements). The controller is coupled to the non-volatile memory and is used to control the operation of the memory device. Furthermore, the controller includes processing circuitry for controlling the controller according to multiple host commands from a host device, so as to allow the host device to access the non-volatile memory through the controller. The controller further includes a transmission interface circuit for communicating with a host device. Specifically, the transmission interface circuit includes a universal asynchronous transceiver (UART), wherein the UART has a set of terminals each coupled to a corresponding set of terminals of a UART on the host device, forming a UART connection between the memory device and the host device. For example, the controller uses the UART to receive an intermediate command corresponding to a set of operation commands via the UART connection, wherein the host device converts the set of operation commands into the set of intermediate commands before transmitting the set of intermediate commands to the controller via the UART connection; the controller converts the set of intermediate commands into the set of operation commands according to a command mapping table, wherein the command mapping table is located in the memory device; and the controller uses the set of operation commands to access non-volatile memory for the host device and to transmit a response to the host device via the UART connection.

[0006] According to some embodiments, a related electronic device is also provided. The electronic device may include the aforementioned memory device, and may further include a host device coupled to the memory device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor and for providing power to the at least one processor and the memory device. Furthermore, the memory device may provide storage space for the host device.

[0007] In addition to the methods described above, the present invention also provides a controller for a memory device, wherein the memory device includes a controller and a non-volatile memory. The non-volatile memory may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements). Furthermore, the controller includes processing circuitry for controlling the controller according to a plurality of host commands from a host device, so as to allow the host device to access the non-volatile memory through the controller. The controller further includes a transmission interface circuit for communicating with a host device. Specifically, the transmission interface circuit includes a universal asynchronous transceiver (UART), wherein the UART has a set of terminals each coupled to a corresponding set of terminals of a UART on the host device, forming a UART connection between the memory device and the host device. For example, the controller uses the UART to receive an intermediate command corresponding to a set of operation commands via the UART connection, wherein the host device converts the set of operation commands into the set of intermediate commands before transmitting the set of intermediate commands to the controller via the UART connection; the controller converts the set of intermediate commands into the set of operation commands according to a command mapping table, wherein the command mapping table is located in the memory device; and the controller uses the set of operation commands to access non-volatile memory for the host device and to transmit a response to the host device via the UART connection.

[0008] According to some embodiments, a memory controller of a memory device can control the operation of the memory device according to the method, and the memory device can be installed in an electronic device that includes at least a portion (e.g., a portion or all) of the electronic device. For example, the device may include the memory device, or for example, the device may include all of the electronic device.

[0009] The method and apparatus of the present invention ensure that at any stage of the different phases of the memory device, whether the stage represents a mass production phase or an initial phase prior to mass production, such as a design phase (e.g., a pilot phase of multiple pilot phases), the memory device can operate as required by the host device. Furthermore, at any stage, the host device and the memory device can communicate with each other via a universal asynchronous transceiver connection according to a new protocol provided by the present invention. For example, in the initial phase, regardless of whether the communication characteristics of the memory device for the host device are complete, the memory device can access the non-volatile memory for the host device in various ways as required by the host device. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0011] Figure 2 This is a schematic diagram of a control scheme for a method of managing access to a memory device using a universal asynchronous transceiver connection according to an embodiment of the present invention.

[0012] Figure 3 This is a flowchart illustrating a method for managing access to a memory device using a universal asynchronous transceiver connection, according to an embodiment of the present invention.

[0013] Figure 4 This is an example schematic diagram of the timing diagrams of a host device 50 and a memory device 100 according to an embodiment of the present invention.

[0014] Figure 5 This is a schematic diagram of some related signals corresponding to the READ PAGE operation of the READ PAGE command according to an embodiment of the present invention.

[0015] Figure 6 This is a schematic diagram of a general asynchronous transceiver in an electronic device.

[0016] Figure 7 This is a schematic diagram illustrating an example of a byte transmission format for a general asynchronous transceiver connection.

[0017] Figure 8 This is a flowchart of a method for managing access to a memory device using a universal asynchronous transceiver connection, according to an embodiment of the present invention.

[0018] [Symbol Explanation]

[0019] 10: Electronic devices

[0020] 50: Main unit

[0021] 52: Processor

[0022] 54: Power Supply Circuit

[0023] 56,116: Random Access Memory

[0024] 58,118: Transmission interface circuit

[0025] 58U, 118U, 600: General Purpose Asynchronous Transceiver

[0026] 100: Memory device

[0027] 110: Memory controller

[0028] 112: Microprocessor

[0029] 112C: Program Code

[0030] 112M: Read-Only Memory

[0031] 114: Control Logic Circuit

[0032] 116,120T: Command Mapping Table

[0033] 120: Non-volatile memory

[0034] 122-1~122-N non-volatile memory elements

[0035] S10, S11, S12A, S12B, S12C, S13B, S13C, S14B, S14C, S15B, S15C, S16B, S16C, S17B, S17C, S18: Steps

[0036] DQ[7:0],RDY,ARDY: Signals

[0037] 610: Clock Generator

[0038] 620T: Transmission Circuit

[0039] 620R: Receiver circuit

[0040] 630T: Transmission buffer circuit

[0041] 630R: Receiver buffer circuit

[0042] 810, 812, 814, 816, 818A, 818B: Steps Detailed Implementation

[0043] Figure 1This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors), collectively referred to as processor 52, a power supply circuit 54, at least one random access memory (RAM), such as one or more random access memories (e.g., dynamic random access memory (DRAM) or static random access memory (SRAM)), collectively referred to as random access memory 56 (for simplicity, denoted as "RAM"), and a transmission interface circuit 58, wherein processor 52 and random access memory 56 may be coupled to each other via a bus and may be coupled to the power supply circuit 54 to obtain power. Processor 52 can be used to control the operation of the host device 50. The power supply circuit 54 can provide power to the processor 52, random access memory 56, transmission interface circuit 58 and memory device 100, and output one or more drive voltages to the memory device 100, wherein the memory device 100 can provide storage space to the host device 50, and can obtain one or more drive voltages from the host device 50 as power for the memory device 100. Examples of host device 50 may include, but are not limited to: multi-functional mobile phones, tablets, wearable devices, and personal computers, such as desktop computers and laptops. Examples of storage device 100 may include, but are not limited to: portable storage devices (e.g., memory cards conforming to SD / MMC, CF, MS, XD, or UFS specifications, solid-state drives (SSDs), and different types of embedded storage devices (e.g., embedded storage devices conforming to generic flash storage specifications or embedded multimedia card (eMMC) specifications). According to this embodiment, storage device 100 may include a controller, such as a memory controller 110, and may further include non-volatile (NV) memory 120 (for simplicity, ...). Figure 1 The controller accesses the non-volatile memory 120, which is used to store information. The non-volatile memory 120 may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), such as multiple non-volatile memory elements 122-1, 122-2, ..., and 122-NS (for simplicity, ...). Figure 1The non-volatile memory 120 can be a flash memory, and the multiple non-volatile memory elements 122-1, 122-2, ..., and 122-NS can be multiple flash memory wafers or multiple flash memory dies, but the present invention is not limited thereto.

[0044] like Figure 2 As shown, the memory controller 110 may include a processing circuit (e.g., a microprocessor 112), a storage unit (e.g., a read-only memory (ROM) 112M; for simplicity, it is labeled "ROM"), a control logic circuit 114, a random access memory 116 (e.g., which may be implemented by static random access memory; for simplicity, it is labeled "RAM"), and a transmission interface circuit 118, wherein at least a portion (e.g., some or all) of the above components can be coupled to each other via a bus. Random access memory 116 can be used to provide internal storage space (e.g., temporarily storing information) to memory controller 110, but the invention is not limited thereto. Furthermore, in this embodiment, read-only memory 112M is used to store program code 112C, and microprocessor 112 is used to execute program code 112C to control access to non-volatile memory 120. It should be noted that program code 112C can also be stored in random access memory 116 or any type of memory. In addition, control logic circuitry 114 can be used to control non-volatile memory 120. Control logic circuitry 114 may include an error correction code (ECC) circuit (not shown). Figure 1 It can perform error correction code encoding and decoding to protect data and / or perform error correction. The transmission interface circuit 118 may conform to a specific communication specification (such as Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIE) specification, Embedded Multimedia Card specification, or Universal Flash Storage specification), and can communicate according to the specific communication specification. For example, the transmission interface circuit 118 may communicate between the memory device 100 and the transmission interface circuit 58 according to the specific communication specification, and the transmission interface circuit 58 may communicate between the host device 50 and the transmission interface circuit 118 according to the specific communication specification.

[0045] In this embodiment, the host device 50 can transmit multiple host commands and corresponding logical addresses to the memory controller 110 to indirectly access the non-volatile memory 120 within the memory device 100. The memory device 100 receives the multiple host commands and logical addresses, converts the multiple host commands into memory operation commands (for simplicity, these can be referred to as operation commands), and further controls the non-volatile memory 120 with the operation commands to read or write / program memory cells or data pages at specific physical addresses within the non-volatile memory 120, where the physical address corresponds to the logical address. For example, the memory controller 110 can generate or update at least one logical-to-physical (H2F) address mapping table to manage the relationship between physical addresses and logical addresses. The non-volatile memory 120 can store a global logical-to-physical address mapping table to provide the memory controller 110 with the ability to control the memory device 100 to access data in the non-volatile memory 120.

[0046] To better understand, the global logic-to-physical address mapping table may be located in a predetermined region within the non-volatile memory element 122-1, such as the system region. However, the invention is not limited thereto. For example, the global logic-to-physical address mapping table may be divided into multiple region logic-to-physical address mapping tables, and these multiple region logic-to-physical address mapping tables may be stored in one or more of the non-volatile memory elements 122-1, 122-2, ..., and 122-N, particularly in the non-volatile memory elements 122-1, 122-2, ..., and 122-N respectively. When needed, the memory controller 110 may load at least a portion (e.g., part or all) of the global logic-to-physical address mapping table into the random access memory 116 or other memory. For example, the memory controller 110 may load a region logic-to-physical address mapping table of multiple region logic-to-physical address mapping tables into the random access memory 116 as a temporary logic-to-physical address mapping table therein to access data in the non-volatile memory 120 according to the region logic-to-physical address mapping table, but the invention is not limited thereto.

[0047] Furthermore, the aforementioned at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N}) may contain multiple blocks, wherein the smallest unit for the memory controller 110 to perform a data erasure operation on the non-volatile memory 120 may be a block, and the smallest unit for the memory controller 110 to perform a data write operation on the non-volatile memory 120 may be a page, but the invention is not limited thereto. For example, any non-volatile memory element 122-n (where “n” can represent any integer in the interval [1, N]) among the non-volatile memory elements 122-1, 122-2, ..., and 122-N may contain multiple blocks, and one of the multiple blocks may contain and record a specific number of pages, wherein the memory controller 110 may access a specific page within a specific block of the multiple blocks according to the block address and the page address. For example, the non-volatile memory element 122-n may include multiple planes, one of which may contain a set of blocks (e.g., the multiple blocks described above), and the memory controller 110 may specify a plane among the multiple planes according to a plane number to access a page within a block of that plane. As the total number of blocks increases, the storage space of the non-volatile memory 120 can become larger. Many technologies can be used to manufacture the non-volatile memory 120, such as 2D / planar NAND flash memory technology, which arranges memory cells in a single layer; and 3D NAND flash memory technology, which arranges memory cells in a multi-layered vertical stack. According to some embodiments, the non-volatile memory 120 may be implemented as a 2D / planar NAND flash memory structure with memory cells arranged in a single layer. According to some embodiments, the non-volatile memory 120 can be implemented as a 3D reverse gate flash memory structure with vertically stacked multilayer memory cells, in which case the storage space of the non-volatile memory 120 can become very large.

[0048] According to this embodiment, the transmission interface circuit 118 may include a universal asynchronous transceiver 118U (referred to as "UART" for simplicity), and the transmission interface circuit 58 may include a universal asynchronous transceiver 58U, wherein either the universal asynchronous transceiver 118U or the universal asynchronous transceiver 58U may include sub-circuits (e.g., transceivers, transmitters, etc.). When needed, a set of terminals {RX, TX, GND} of the Universal Asynchronous Transceiver 118U can be coupled to a set of terminals {TX, RX, GND} of the Universal Asynchronous Transceiver 58U to form a Universal Asynchronous Transceiver ART connection between the memory device 100 (e.g., the memory controller 110 therein) and the host device 50. The Universal Asynchronous Transceiver ART connection may include a connection between the set of terminals {RX, TX, GND} of the synchronous transceiver 118U and the set of terminals {TX, RX, GND} of the Universal Asynchronous Transceiver 58U.

[0049] according to Figure 1 In the illustrated architecture, host device 50 (e.g., processor 52) and memory device 100 (e.g., memory controller 110) can communicate with each other via a Universal Asynchronous Receiver / Transmitter (UART) connection according to a new protocol provided by the present invention. This protocol can be considered a Universal Asynchronous Receiver / Transmitter (UART) protocol, and the related communications performed by host device 50 (e.g., processor 52) and memory device 100 (e.g., memory controller 110) via the UART connection can be referred to as UART communication. According to this protocol, a single UART command (CMD) may include a command code and multiple arguments, and one or more of the multiple arguments may carry one or more operation command representatives indicating one or more operation commands (e.g., the aforementioned one or more operation commands concerning the non-volatile memory 120). Furthermore, the host device 50 (e.g., processor 52) may perform command mapping according to command mapping table 56T to convert one or more operation commands into one or more operation command representatives, and the memory device 100 (e.g., memory controller 110) may perform command mapping according to another command mapping table (e.g., a reverse command mapping table corresponding to the opposite direction of command mapping, such as either command mapping table 116T or 120T) to convert one or more operation command representatives into one or more operation commands.

[0050] For example, processor 52 may pre-store a command mapping table in a storage device (e.g., a hard disk drive, HDD) within host device 50, and load the command mapping table from that storage device into random access memory 56 as command mapping table 56T for use as periodic command mapping in general asynchronous transceiver communication. In addition, memory controller 110 may pre-store command mapping table 120T in non-volatile memory 120 (e.g., non-volatile memory element 122-1), and load command mapping table 120T from non-volatile memory 120 into random access memory 116 as command mapping table 116T for use as periodic command mapping in general asynchronous transceiver communication. When host device 50 accesses memory device 100 (e.g., writes data to or reads data from memory device 100), host device 50 (e.g., processor 52) can convert a set of operation commands (e.g., one or more operation commands) into a set of intermediate commands (e.g., one or more operation command representatives) according to command mapping table 56T, and transmit the set of intermediate commands to memory device 100 (e.g., memory controller 110 therein) via a universal asynchronous transceiver connection, especially receiving a response (e.g., an acknowledgment message (ACK) or returned data) from memory device 100 (e.g., memory controller 110 therein) via the universal asynchronous transceiver connection. When the memory device 100 receives the set of intermediate commands from the host device 50, the memory device 100 (e.g., memory controller 110) can convert the set of intermediate commands (e.g., one or more operation command representatives) into the set of operation commands (e.g., one or more operation commands) according to the command mapping table 116T, and use the set of operation commands to access the non-volatile memory 120 for the host device 50, especially to transmit the response (e.g., acknowledgment message or returned data) to the host device 50 via a general asynchronous transceiver connection.

[0051] For better understanding, the command mapping table 120T may be located in a predetermined area within the non-volatile memory element 122-1, such as a system area. However, the invention is not limited thereto. For example, the command mapping table 120T may be stored in another predetermined area within the non-volatile memory element 122-1, such as another system area. As another example, the command mapping table 120T may be stored in any of the non-volatile memory elements 122-1, 122-2, ..., and 122-N.

[0052] Figure 2This is a schematic diagram of a control scheme for a method of managing access to a memory device using a universal asynchronous transceiver connection according to an embodiment of the present invention, wherein the method can be applied to Figure 1 In the architecture shown, the host device 50 (e.g., processor 52) and the memory device 100 (e.g., memory controller 110) are particularly relevant. Figure 2 The host UART and device UART in the middle part of the architecture shown can respectively represent Figure 1 The general-purpose asynchronous transceiver 58U and general-purpose asynchronous transceiver 118U shown are illustrated. Figure 2 The host platform in the upper part of the architecture shown can represent Figure 1 The processor 52, random access memory 56, etc. shown, and Figure 2 The inverse and gate flash memory in the lower part of the architecture shown can represent Figure 1 The non-volatile memory 120 is shown. Furthermore, one or more program codes running on processor 52 may include an operating system (OS), multiple drivers, multiple applications, etc., and the multiple applications may include a host application, such as a host application running on a main platform. Additionally, one or more program codes running on microprocessor 112 (e.g., program code 112C loaded from read-only memory 112M and / or in-system programming (ISP) code loaded from non-volatile memory 120) may include a control application program interface (API) and a device application, wherein the control application program interface can perform hardware-level control at the hardware layer of memory controller 110 for the device application.

[0053] For a Universal Asynchronous Transceiver (UART) connection, host device 50 (e.g., processor 52) may transmit one or more first UART commands (labeled "commands" next to the down arrow for brevity) to memory device 100 during access to memory device 100, particularly during the writing of data to memory device 100, to transmit an additional payload, such as write data, to memory device 100 (e.g., one or more first UART commands may indicate a write request from host device 50). Furthermore, memory device 100 (e.g., memory controller 110) may transmit one or more second UART commands (labeled "commands" next to the up arrow for brevity) to host device 50 in response, particularly when memory device 100 operates in response to a read request from host device 50 (e.g., one or more first UART commands may indicate a read request from host device 50), to transmit an additional payload, such as read data, to host device 50.

[0054] For example, under the control of the main application, the host device 50 (e.g., processor 52) can convert the set of operation commands (e.g., one or more operation commands) into the set of intermediate commands (e.g., one or more operation command representatives) according to the command mapping table 56T, and transmit the set of intermediate commands to the memory device 100 via a universal asynchronous transceiver connection, particularly receiving responses (e.g., acknowledgment messages or returned data) from the memory device 100 via the universal asynchronous transceiver connection for further processing. As another example, under the control of the device application, the memory device 100 (e.g., memory controller 110) can convert the set of intermediate commands (e.g., one or more operation command representatives) into the set of operation commands (e.g., one or more operation commands) according to the command mapping table 116T, and use the set of operation commands to access the non-volatile memory 120 for the host device 50, particularly transmitting responses (e.g., acknowledgment messages or returned data) to the host device 50 via a universal asynchronous transceiver connection. For the sake of brevity, a similar description of this embodiment will not be repeated in detail here.

[0055] Table 1

[0056]

[0057] Table 1 illustrates the basic format of a single general asynchronous transceiver command used by an electronic device 10 according to an embodiment of the present invention. The command packet of the general asynchronous transceiver command may contain 16 bytes, such as bytes 0 to byte F, which have been assigned hexadecimal values ​​0x0 to 0xF respectively. However, the present invention is not limited thereto. In some embodiments, the bytes in this basic format may be assigned any of the values ​​of some other types, such as decimal values ​​0 to 15.

[0058] The basic format of a single general-purpose asynchronous transceiver command may include multiple fields as listed below: #1, #2, ..., and #6.

[0059] (1) Field #1 (e.g., byte 0 and byte 1) is used to carry the command code;

[0060] (2) Field #2 (e.g., byte 2 and byte 3) is used to carry the first argument Arg1;

[0061] (3) Field #3 (e.g., byte 4 and byte 7) is used to carry the second argument Arg2;

[0062] (4) Field #4 (e.g., byte 8 and byte B) is used to carry the third argument Arg3;

[0063] (5) Field #5 (e.g., byte C and byte D) is used to carry the fourth argument Arg4; and

[0064] (6) Field #6 (e.g., byte E and byte F) is used to carry the checksum of bytes 0 through byte D.

[0065] However, the invention is not limited thereto. In some embodiments, this basic format may vary; for example, the checksum in field #6 may be replaced by any other type of checksum information to ensure the correctness of general asynchronous transceiver commands. In another example, the number of arguments in this basic format may vary. In some examples, the number of fields in this basic format and / or the byte count of each field in this basic format may vary.

[0066] Table 2

[0067]

[0068] Table 2 illustrates some examples of general asynchronous transceiver commands used by the electronic device 10 according to an embodiment of the present invention. For better understanding, the relevant command codes and related information (e.g., auxiliary information), such as arguments Arg1, Arg2, Arg3, etc., are also shown in Table 2. The first three examples of general asynchronous transceiver commands (labeled "UART commands" in Table 2 for simplicity) may include:

[0069] (1) lower-level command-input (which may represent a command to input a lower-level command), such as the “CMD In” command (which may be represented by the command code “CI”), is used to input lower-level commands, such as operation command representatives indicating operation commands, from the host device 50 into the memory device 100.

[0070] (2) Data-input commands (which can represent a command for data input), such as the “Data In” command (which can be represented by the command code “DI”), are used to input data from the host device 50 into the memory device 100, wherein the fourth argument Arg4 of this command can carry the transmission-unit count (denoted as “CNT” for simplicity) of the data to be input into the memory device 100 as requested by this command, such as a load count; and

[0071] (3) data-output commands (which can represent a command for data output), such as the “Data Out” command (which can be represented by the command code “DO”), are used to output data from the memory device 100 to the host device 50, wherein the fourth argument Arg4 of this command can carry the transmission unit count (marked as “CNT” for simplicity) of the data to be output from the memory device 100 as requested by this command, such as a load count;

[0072] These commands can serve as examples of one or more first general asynchronous transceiver commands.

[0073] Furthermore, the last three examples of general asynchronous transceiver commands may include:

[0074] (1) A ready-for-command-receiving command (which may represent a command to be ready to receive a command), such as the “Ready for CMD” command (which may be represented by the command code “RC”), is used to instruct the memory device 100 to be ready to receive a general asynchronous transceiver command from the host device 50, wherein the fourth argument Arg4 of this command may carry an error (ERR) code when needed.

[0075] (2) A ready-for-data-input command (which can represent a command to prepare input data), such as the "Ready for Input" command (which can be represented by the command code "RI"), is used to instruct memory device 100 to prepare to input data from host device 50 to memory device 100, wherein the fourth argument Arg4 of this command can carry an error code when needed; and

[0076] (3) The ready-for-data-output command (which can represent a command to prepare for output data), such as the “Ready for Output” command (which can be represented by the command code “RO”), is used to instruct the memory device 100 to prepare to input data to the host device 50, wherein the fourth argument Arg4 of this command can carry an error code when needed.

[0077] These commands can be examples of one or more second generic asynchronous transceiver commands, and can be responses from memory device 100 to host device 50 (e.g., generic asynchronous transceiver response (UART response)).

[0078] Command codes can indicate different host-and-device interaction types. Therefore, when memory device 100 (e.g., memory controller 110) receives one of the commands "CMD In", "Data In", and "DataOut", memory device 100 (e.g., memory controller 110) can determine the corresponding host-and-device interaction type (e.g., a corresponding type among the types "CI" of command code "CI", "DI" of command code "DI", and "DO" of command code "DO"). Similarly, when host device 50 (e.g., processor 52) receives one of the commands "Ready for CMD", "Ready for Input", and "Ready for Output", host device 50 (e.g., processor 52) can determine the corresponding host-and-device interaction type (e.g., a corresponding type among the types "RC" of command code "RC", "RI" of command code "RI", and "RO" of command code "RO"). Furthermore, when needed, higher-order mechanisms in electronic device 10 (such as either the main application or the device application) can determine (e.g., define) the arguments Arg1, Arg2, Arg3, and Arg4. For data-input commands (e.g., the “DataIn” command), the transmission unit count (denoted as “CNT” for brevity) carried by the fourth argument Arg4 of this command, such as the payload count, can indicate how many 512-bit (512B) payloads should be transmitted by this command, wherein the total amount of data to be input to memory device 100 is measured in units of 512 bits (e.g., each payload has 512 bits). For data-output commands (e.g., the “Data Out” command), the transmission unit count (denoted as “CNT” for brevity) carried by the fourth argument Arg4 of this command, such as a payload count, can indicate how many 512-byte payloads should be transmitted by this command, where the total amount of data to be output from memory device 100 is measured in units of 512 bytes (e.g., 512 bytes per payload). For any response from memory device 100 to host device 50 (e.g., a generic asynchronous transceiver response), an error code can represent a failure code, specifically indicating an error (e.g., data verification failure or command execution failure).

[0079] Figure 3This is a flowchart illustrating a method for managing access to a memory device using a universal asynchronous transceiver connection according to an embodiment of the present invention. For example, host device 50 and memory device 100 can be considered as the host end and device end, respectively; therefore, for simplicity, some related steps in this workflow can be labeled "host" and "device," respectively. Furthermore, the device application can be implemented using memory test firmware (MTFW) code, where the initialization of the memory test firmware code can be considered as memory test firmware initialization, but the present invention is not limited thereto.

[0080] In step S10, the memory device 100 (e.g., memory controller 110) may perform memory test firmware initialization (for brevity, denoted as "MTFW initialization").

[0081] In step S11, the memory device 100 (e.g., memory controller 110) may wait for a general asynchronous transceiver command from the host device 50.

[0082] In step S12A, the host device 50 (e.g., processor 52) can transmit lower-level command-input commands, such as the “CMD In” command (labeled “CI” for brevity), to the memory device 100 via a general asynchronous transceiver connection.

[0083] In step S12B, the host device 50 (e.g., processor 52) can transmit data-input commands, such as the “Data In” command (labeled “DI” for brevity), to the memory device 100 via a general asynchronous transceiver connection, wherein the data-input command (e.g., the “Data In” command) may carry its own payload count.

[0084] In step S12C, the host device 50 (e.g., processor 52) can transmit data-output commands, such as “Data Out” commands (denoted as “DO” for brevity), to the memory device 100 via a general asynchronous transceiver connection, wherein the data-output commands (e.g., “Data Out” commands) may carry their own payload count.

[0085] In step S13B, the memory device 100 (e.g., memory controller 110) can check whether any error has occurred. If so, proceed to step S18; otherwise, proceed to step S14B.

[0086] In step S13C, the memory device 100 (e.g., memory controller 110) can check whether any error has occurred. If so, proceed to step S18; otherwise, proceed to step S14C.

[0087] In step S14B, the memory device 100 (e.g., memory controller 110) can transmit ready-for-data-input commands, such as the “Ready for Input” command (labeled “RI” for brevity), to the host device 50 via a general asynchronous transceiver connection.

[0088] In step S14C, the memory device 100 (e.g., memory controller 110) can transmit ready-for-data-output commands, such as the “Ready for Output” command (labeled “RO” for brevity), to the host device 50 via a general asynchronous transceiver connection.

[0089] In step S15B, the host device 50 (e.g., processor 52) may transfer the relevant payload to the memory device 100.

[0090] In step S15C, the memory device 100 (e.g., memory controller 110) may transfer the relevant payload to the host device 50.

[0091] In step S16B, the memory device 100 (e.g., memory controller 110) can check whether any error has occurred. If so, proceed to step S18; otherwise, proceed to step S17B.

[0092] In step S16C, the memory device 100 (e.g., memory controller 110) can check whether any error has occurred. If so, proceed to step S18; otherwise, proceed to step S17C.

[0093] In step S17B, the memory device 100 (e.g., memory controller 110) can check whether the payload transfer is complete. If yes, proceed to step S18; otherwise, proceed to step S14B.

[0094] In step S17C, the memory device 100 (e.g., memory controller 110) can check whether the payload transfer is complete. If yes, proceed to step S18; otherwise, proceed to step S14C.

[0095] In step S18, the memory device 100 (e.g., memory controller 110) can transmit ready-for-command-receiving commands, such as the “Ready for CMD” command (labeled “RC” for brevity), to the host device 50 via a general asynchronous transceiver connection.

[0096] To better understand this method, it can be used... Figure 3 The workflow shown is for illustrative purposes only; however, the invention is not limited thereto. According to certain embodiments, one or more steps may be performed within [the specified timeframe]. Figure 3 Add, delete, or modify in the workflow shown.

[0097] Table 3

[0098]

[0099] Table 3 illustrates the basic format of a single Universal Asynchronous Receiver / Transmitter (UART) payload used by an electronic device 10 according to an embodiment of the present invention. The payload packet of the UART payload may contain 514 bytes (e.g., bytes 0 to 513), which have been assigned decimal values ​​0 to 513 respectively. However, the present invention is not limited thereto. In some embodiments, the bytes in this basic format may be assigned values ​​of any of some other types, such as hexadecimal values ​​0x0000 to 0x0201.

[0100] The basic format of a single general-purpose asynchronous transceiver payload may include several fields #1 and #2 as listed below:

[0101] (1) Field #1 (e.g., bytes 0 to byte 511) is used to carry payload (e.g., the payload mentioned in either step S15B or step S15C); and

[0102] (2) Field #2 (e.g., byte 512 and byte 513) is used to carry the checksum of bytes 0 to byte 511;

[0103] However, the invention is not limited thereto. In some embodiments, this basic format may vary; for example, the checksum in field #2 may be replaced by any other type of checksum information to ensure the correctness of the generic asynchronous transceiver payload. In some examples, the number of fields in this basic format and / or the respective byte count of the fields in this basic format may vary.

[0104] Figure 4This is an example schematic diagram of the timing diagrams of a host device 50 and a memory device 100 according to an embodiment of the present invention. For example, the host device 50 and the memory device 100 can be considered as a host end and a device end, respectively. Therefore, for simplicity, in... Figure 4 The terms "host" and "device" can be respectively labeled as "host" and "device". For better understanding, assume that the first general asynchronous transceiver command transmitted from host device 50 to memory device 100 via a general asynchronous transceiver connection is a lower-level command-input command, such as the "CMD In" command (labeled "CI" for brevity), and assume that the associated response (e.g., a second general asynchronous transceiver command) transmitted from memory device 100 to host device 50 is a ready-for-command-receiving command, such as the "Ready for CMD" command (labeled "RC" for brevity), but the invention is not limited thereto. In some embodiments, the first general asynchronous transceiver command and the associated response (e.g., the second general asynchronous transceiver command) may vary.

[0105] For the host-side time frame of host device 50 (hereinafter referred to as "host time frame" for simplicity), host device 50 (e.g., processor 52) can transmit a first general asynchronous transceiver command, such as a "CMD In" command (hereinafter referred to as "CI" for simplicity), to memory device 100 via a general asynchronous transceiver connection, and wait for a response from memory device 100 (e.g., a second general asynchronous transceiver command), and receive a response from memory device 100 via the general asynchronous transceiver connection, such as a "Ready for CMD" command (hereinafter referred to as "RC" for simplicity). Subsequently, the process concerning the first and second general asynchronous transceiver commands on the host side will end. For the device-side time frame of the memory device 100 (hereinafter referred to as "device time frame" for brevity), the memory device 100 (e.g., memory controller 110) may wait for a first generic asynchronous transceiver command (hereinafter referred to as "CMD") from the host device 50 and receive such commands, such as the "CMD In" command (hereinafter referred to as "CI"), via a generic asynchronous transceiver connection. The microprocessor 112 running device applications (e.g., firmware, such as memory test firmware) may also operate in response to the first generic asynchronous transceiver command, thus making the microprocessor 112 busy. Subsequently, the memory device 100 (e.g., memory controller 110) can transmit responses, such as a “Ready for CMD” command (denoted as “RC” for brevity), to the host device 50 via a general asynchronous transceiver connection, and wait for another first general asynchronous transceiver command (denoted as “CMD” for brevity) from the host device 50.

[0106] According to the above embodiments, the basic architecture of the new protocol has been established. In any of the multiple stages of the memory device 100, regardless of whether the stage represents a mass production stage or a preliminary stage prior to mass production, such as a design stage (e.g., a pilot stage of multiple pilot stages), the memory device 100 (e.g., memory controller 110) can operate as required by the host device 50. Furthermore, in any of these stages, the host device 50 (e.g., processor 52) and the memory device 100 (e.g., memory controller 110) can communicate with each other via a universal asynchronous transceiver connection according to the new protocol provided by the present invention. For example, in the preliminary stage, regardless of whether the communication characteristics of the memory device 100 for the host device 50 are complete, the memory device 100 (e.g., memory controller 110) can access the non-volatile memory 120 for the host device 50 in various ways as required by the host device 50.

[0107] Since one or more programs running on microprocessor 120 can be implemented via in-system programming code loaded from nonvolatile memory 120, the manufacturer of memory controller 110 and / or the manufacturer of memory device 100 can use general asynchronous transceiver communication between host device 50 (e.g., processor 52) and memory device 100 (e.g., memory controller 110) to update the in-system programming code in nonvolatile memory 120, thereby updating the control application programming interface and / or device applications within one or more programs. Therefore, the new protocol provided by this invention is quite helpful to the relevant work of the manufacturers mentioned above at any stage of memory device 100.

[0108] Table 4

[0109] Operation commands Arg1 CMD1 0x0000 CMD2 0x0001 CMD3 0x0010 CMD4 0x0011 CMD5 0x0100 … …

[0110] Table 4 illustrates an example of command mapping according to an embodiment of the present invention, wherein for simplicity, the symbol “…” indicates that certain contents of Table 4 can be omitted. The host device 50 (e.g., processor 52) can perform command mapping according to command mapping table 56T to convert one or more operation commands (e.g., one or more operation commands such as operation commands CMD1, CMD2, CMD3, CMD4, CMD5, etc. in Table 4) into one or more operation command representatives (e.g., one or more operation command representatives such as operation command representatives 0x0000, 0x0001, 0x0010, 0x0011, 0x0100, etc. in Table 4), and the memory device 100 (e.g., memory controller). Device 110 can perform command mapping according to its own command mapping table, such as command mapping table 116T and command mapping table 120T, to convert one or more operation command representatives (e.g., one or more operation command representatives 0x0000, 0x0001, 0x0010, 0x0011, 0x0100, etc. in Table 4) into one or more operation commands (e.g., one or more operation commands CMD1, CMD2, CMD3, CMD4, CMD5, etc. in Table 4). According to this embodiment, the first argument Arg1 can be configured to carry any of the operation command representatives 0x0000, 0x0001, 0x0010, 0x0011, 0x0100, etc. in Table 4, but the invention is not limited to this. For example, when needed, any of the other arguments among Arg1, Arg2, Arg3, etc. can be configured to carry an operation command representative.

[0111] Taking a read request as an example of an access request from host device 50, let's assume:

[0112] (1) Operation command CMD1 can represent command latch enable (CLE) command (for brevity, it can be referred to as "CLE"), wherein one or more subsequent arguments (e.g., a single subsequent argument, such as the second argument Arg2) can carry the related operation command READ MODE command 00h (e.g. 0x00), READ PAGE command 00h~30h (e.g. {0x00,0x30}) command sequence ending command 30h (e.g. 0x30), etc.;

[0113] (2) The operation command CMD2 can represent the address latch enable (ALE) command (for brevity, it can be referred to as “ALE”), in which one or more subsequent arguments (e.g. multiple subsequent arguments, such as the second argument Arg2 and the third argument Arg3) can carry the associated address with a predetermined number of bytes (e.g., 5 bytes or 6 bytes).

[0114] (3) The operation command CMD3 can represent the Wait-Ready-or-Busy (Wait-RB) command (for brevity, it can be referred to as "WaitRB"); and

[0115] (4) The operation command CMD4 can represent a DMA-Read command, wherein one or more subsequent arguments (e.g., a single subsequent argument, such as the second argument Arg2) can carry a sector count of a predetermined number of bytes (e.g., one or more bytes).

[0116] However, the present invention is not limited thereto. In some embodiments, the meanings of the operation commands CMD1, CMD2, CMD3, CMD4, CMD5, etc. in Table 4, as well as the information carried by the related subsequent arguments (e.g., the second argument Arg2 or the third argument Arg3), may vary.

[0117] Since the command mapping table 56T can store multiple command mapping relationships between the operation commands CMD1, CMD2, CMD3, CMD4, CMD5, etc. shown in Table 4, and the operation command representatives 0x0000, 0x0001, 0x0010, 0x0011, 0x0100, etc., the host device 50 (e.g., processor 52) can perform command mapping according to the command mapping table 56T to obtain any one of the multiple command mapping relationships. For example, the group of operation commands may include a series of operation commands as listed below:

[0118] (1){CLE,0x00};

[0119] (2){ALE,0x0000000100}, where the predetermined number of bytes in the relevant address can represent 5 bytes;

[0120] (3){CLE,0x30};

[0121] (4){WaitRB}; and

[0122] (5) {DMA-Read,0x08}, which can represent a direct memory access (DMA) read operation to read 8 segments (e.g., 8 kilobytes (KB)), where a predetermined number of bytes in the relevant segment count can represent 1 byte.

[0123] However, the present invention is not limited thereto. After command mapping is performed according to command mapping table 56T, host device 50 (e.g., processor 52) can obtain the set of intermediate commands, such as a series of operation commands represented as follows:

[0124] (1){0x0000,0x00};

[0125] (2){0x0001,0x0000000100};

[0126] (3){0x0000,0x30};

[0127] (4){0x0010}; and

[0128] (5){0x0011,0x08};

[0129] However, the present invention is not limited thereto. Therefore, the host device 50 (e.g., processor 52) may transmit a series of operation commands representing a series of general asynchronous transceiver commands, as listed below:

[0130] (1){"CI",{0x0000,0x00000000,0x00000000,0x0000,CHECKSUM(1)};

[0131] (2){"CI",{0x0001,0x0000000000000100,0x0000,CHECKSUM(2)};

[0132] (3){"CI",{0x0000,0x00000030,0x00000000,0x0000,CHECKSUM(3)};

[0133] (4){“CI”,{0x0010,0x00000000,0x00000000,0x0000,CHECKSUM(4)}; and

[0134] (5){"CI",{0x0011,0x00000008,0x00000000,0x0000,CHECKSUM(5)};

[0135] CHECKSUM(1), CHECKSUM(2), ..., and CHECKSUM(5) can represent the checksums carried in field #6 of the respective generic asynchronous transceiver commands of this series, and the numbers printed in italics as shown above can represent dummy digits. However, the invention is not limited thereto, and in some embodiments, the arrangement of dummy digits and / or the individual values ​​of the dummy digits may vary.

[0136] Since each of the command mapping table 116T and the command mapping table 120T can store multiple command mapping relationships between the operation commands CMD1, CMD2, CMD3, CMD4, CMD5, etc. shown in Table 4 and the operation command representatives 0x0000, 0x0001, 0x0010, 0x0011, 0x0100, etc., the memory device 100 (e.g., the memory controller 110) can perform command mapping according to either the command mapping table 116T or the command mapping table 120T to obtain any one of the multiple command mapping relationships, especially to obtain the set of operation commands (e.g., the series of operation commands mentioned above), and use the series of operation commands to access (e.g., read) the non-volatile memory 120 for the host device 50. For the sake of brevity, a similar description of this embodiment will not be repeated in detail here.

[0137] According to another embodiment, each of the aforementioned virtual numbers can be replaced by 0xF, and the host device 50 (e.g., processor 52) can transmit a series of operation commands representing another version of a series of general asynchronous transceiver commands, as listed below:

[0138] (1){"CI",{0x0000,0xFFFFFF00,0xFFFFFFFF,0xFFFF,CHECKSUM(1)};

[0139] (2){"CI",{0x0001,0xFFFFFF0000000100,0xFFFF,CHECKSUM(2)};

[0140] (3){"CI",{0x0000,0xFFFFFF30,0xFFFFFFFF,0xFFFF,CHECKSUM(3)};

[0141] (4){"CI",{0x0010,0xFFFFFFFF,0xFFFFFFFF,0xFFFF,CHECKSUM(4)}; and

[0142] (5){"CI",{0x0011,0xFFFFFF08,0xFFFFFFFF,0xFFFF,CHECKSUM(5)};

[0143] CHECKSUM(1), CHECKSUM(2), ..., and CHECKSUM(5) can represent the checksums carried in field #6 of the respective generic asynchronous transceiver commands of this series, and the numbers printed in italics as shown above can represent virtual numbers. However, the invention is not limited thereto, and for the sake of brevity, similar descriptions of this embodiment will not be repeated in detail here.

[0144] Figure 5 This is a schematic diagram of some related signals corresponding to the READ PAGE operation of the READ PAGE command 00h to 30h (e.g., {0x00.0x30}) according to an embodiment of the present invention. The signals DQ[7:0], RDY and ARDY can be used as an example of a set of signals between the memory controller 110 and the non-volatile memory 120, but the present invention is not limited thereto.

[0145] Memory device 100 (e.g., memory controller 110) can operate as required by host device 50, particularly by receiving a series of generic asynchronous transceiver commands to obtain a series of operation command representatives, translating the series of operation command representatives into a series of operation commands according to either command mapping tables 116T and 120T, and using the series of operation commands to access (e.g., read) non-volatile memory 120 for host device 50. For better understanding, Figure 5 The cycle type sequence {CLE,ALE,ALE,ALE,ALE,ALE,ALE,CLE} shown at the top can indicate some control cycles (e.g., 7 consecutive cycles). For example, in 7 consecutive cycles starting from a certain cycle (e.g., cycles #0, #1, ..., and #6 starting from cycle #0), the memory controller 100 can assert the CLE signal in this group of signals in cycles #0 and #6 (set the CLE signal to the enabled state), and de-assert the CLE signal in this group of signals in cycles #1, #2, ..., and #5 (e.g., set the CLE signal to the disabled state), and assert the ALE signal in this group of signals in cycles #1, #2, ..., and #5 (e.g., set the ALE signal to the enabled state), and de-assert the ALE signal in this group of signals in cycles #0 and #6 (e.g., set the ALE signal to the disabled state).

[0146] Furthermore, the byte sequence {00h,C1,C2,R1,R2,R3,30h} (e.g., 7 bytes {0x00,0x00,0x01,0x00,0x00,0x00,0x30}) carried by the signal DQ[7:0] on the bus between memory control 110 and non-volatile memory 120 can represent the command byte 00h indicating the READ MODE command 00h, the five address bytes {C1,C2,R1,R2,R3} indicating the read address (e.g., the respective bytes {0x00,0x00,0x00,0x01,0x00} of the relevant address 0x0000000100 of the operation command CMD2 transmitted in reverse order), and the instruction READ MODE command 00h. The command byte 30h at the end of the command sequence 00h to 30h of the PAGE command may contain a column address, such as column bytes {C1, C2}, and a row address, such as row bytes {R1, R2, R3}, but the invention is not limited thereto. Following this, there may be state transitions for signals RDY and ARDY.

[0147] Furthermore, the subsequent cycle type sequence {DOUT, DOUT, DOUT, ...} can indicate some data output cycles. During the data output cycle, the memory controller 110 can obtain data bytes Dn, Dn+1, Dn+2, etc. from the non-volatile memory 120 via the signal DQ[7:0] to prepare the read data to be returned to the host device 50. Therefore, in response to the read request, the memory device 100 (e.g., the memory controller 110) can return the read data to the host device 50. For the sake of brevity, a similar description of this embodiment will not be repeated in detail here.

[0148] Figure 6 This is an example schematic diagram of a universal asynchronous transceiver in electronic device 10, wherein either universal asynchronous transceiver 58U or universal asynchronous transceiver 118U (e.g., each universal asynchronous transceiver) can be transmitted via... Figure 6The general asynchronous transceiver 600 is implemented using the architecture shown. The general asynchronous transceiver 600 may include a clock generator 610, a transmission circuit 620T, a transmission buffer circuit 630T, a receiving circuit 620R, and a receiving buffer circuit 630R. The clock generator 610 generates a clock CLK as a reference for data transmission. The transmission circuit 620T is coupled to the clock generator 610, the transmission buffer circuit 630T is coupled to the transmission circuit 620T, the receiving circuit 620R is coupled to the clock generator 610, and the receiving buffer circuit 630R is coupled to the receiving circuit 620R. The transmission circuit 620T and the receiving circuit 620R can be implemented using shift registers, etc., and the transmission buffer circuit 630T and the receiving buffer circuit 630R can be implemented using registers, etc. However, the present invention is not limited to these. Furthermore, the receiving path and the transmission path can represent at least a portion of the connection between the set of terminals {RX,TX,GND} of the general asynchronous transceiver 118U and the set of terminals {TX,RX,GND} of the general asynchronous transceiver 58U, for example, two connections between the set of terminals {RX,TX} of the general asynchronous transceiver 118U and the set of terminals {TX,RX} of the general asynchronous transceiver 58U. For the sake of brevity, a similar description of this embodiment will not be repeated in detail here.

[0149] Figure 7 This is an example diagram illustrating a byte transmission format for a universal asynchronous transceiver (UAST) connection, where the horizontal axis represents time. A first UAST transceiver, either 118U or 58U, can transmit a byte containing data bits {D0, D1, ..., D7}, such as any byte (e.g., each byte) of all bytes commanded by the UAST transceiver, to a second UAST transceiver, either 118U or 58U, according to the byte transmission format. The second UAST transceiver can receive the byte containing data bits {D0, D1, ..., D7} according to the byte transmission format. Before transmitting this byte, the first UAST transceiver can receive a start bit S (e.g., a logic value of 0). After transmitting this byte, the first general asynchronous transceiver may selectively transmit the parity bit PB (labeled "optional" for better understanding) and the stop bit P (e.g., logic 1). For the sake of brevity, a similar description of this embodiment will not be repeated in detail here.

[0150] According to some embodiments, the general flash storage initialization process may include a series of processes, for example, such a series of processes may include:

[0151] (1) Perform M-PHY layer initialization at both ends (e.g., the general flash storage host end and the general flash storage device end);

[0152] (2) UniPro boot sequence and attribute configuration;

[0153] (3) UTP verification;

[0154] (4) Check if startup is enabled;

[0155] (5) Check whether the logical unit (LU) is ready to start;

[0156] (6) Read boot data;

[0157] (7) Set a flag; and

[0158] (8) Poll flag;

[0159] However, the present invention is not limited thereto. It should be noted that the general flash memory initialization process is very complex. In contrast, general asynchronous transceiver communication based on the new protocol provided by the present invention can be very useful at any stage of the memory device 100. For example, in cases where the memory device 100 is designed to support the general flash memory initialization process, the general flash memory initialization process typically operates during the mass production stage and / or the user stage (e.g., the stage when a user owns a product, such as memory device 100), but may not be available in the initial stage of the memory device 100 (e.g., the design stage). When needed, general asynchronous transceiver communication based on the new protocol provided by the present invention can be used in the mass production stage, user stage, or initial stage (e.g., the design stage) of the memory device 100. For the sake of brevity, a similar description of this embodiment will not be repeated in detail here.

[0160] According to some embodiments, the Universal Flash Storage Protocol Information Unit (UPIU) may include multiple fields, and processing may be required for these multiple fields to properly configure them to ensure correct control. Examples of these multiple fields may include, but are not limited to:

[0161] (1) Transaction type;

[0162] (2) Flags;

[0163] (3) Logical unit number (LUN);

[0164] (4) Task tag;

[0165] (5) Command setting type;

[0166] (6) Query functions and / or task management functions;

[0167] (7) Response;

[0168] (8) Status;

[0169] (9) Total length of extra header segment (EHS);

[0170] (10) Device information;

[0171] (11) Data segment length;

[0172] (12) Trade specific fields;

[0173] (13) Additional header section field;

[0174] (14) Header E2ECRC;

[0175] (15) Data segment; and

[0176] (16) Data E2ECRC;

[0177] However, the present invention is not limited thereto. It should be noted that the processing related to Universal Flash Memory Protocol (USB) information units is very complex. In contrast, Universal Asynchronous Transceiver Communication (UART) based on the new protocol provided by the present invention can be very useful at any stage of the memory device 100. For example, in cases where the memory device 100 is designed to support USB data unit processing, USB data unit processing typically operates during the mass production stage and / or the user stage (e.g., the stage when a user owns a product, such as memory device 100), but may not be available in the initial stage (e.g., the design stage) of the memory device 100. When needed, UART based on the new protocol provided by the present invention can be used in the mass production stage, user stage, or initial stage (e.g., the design stage) of the memory device 100. For the sake of brevity, a similar description of this embodiment will not be repeated in detail here.

[0178] According to some embodiments, if the memory device 100 fails during the user phase, the user can send the memory device 100 back to a department of the manufacturer of the memory device 100 (e.g., after-sales service department) to request repair of the memory device 100. In this department of the manufacturer, the universal asynchronous transceiver communication based on the new protocol provided by the present invention is quite helpful for testing the memory device 100 and obtaining user data for the user, etc. For the sake of brevity, a similar description of this embodiment will not be repeated in detail here.

[0179] Figure 8This is a flowchart illustrating a method for managing access to a memory device using a Universal Asynchronous Transceiver (UART) connection according to an embodiment of the present invention. For better understanding, host device 50 can transmit a host command from among multiple host commands to memory device 100 according to an existing protocol (e.g., a protocol of a specific communication specification) to access memory device 100. Memory device 100 (e.g., its memory controller 110) can receive and recognize the host command from host device 50 among the multiple host commands according to an existing protocol, to access non-volatile memory 120 for host device 50. Furthermore, memory device 100 (e.g., its memory controller 110) can communicate with host device 50 via a UART connection according to a UART protocol, particularly if the UART protocol differs from existing protocols. For example, in the case where the set of terminals {RX, TX, GND} of the general asynchronous transceiver 118U is coupled to the set of terminals {TX, RX, GND} of the general asynchronous transceiver 58U to form a general asynchronous transceiver connection between the memory device 100 (e.g., the memory controller 110 therein) and the host device 50, the memory device 100 (e.g., the memory controller 110) can, according to Figure 8 Follow the workflow shown.

[0180] In step 810, when the general asynchronous transceiver 118U of the memory controller 110 is connected to the general asynchronous transceiver 58U of the host device 50 (e.g., the set of terminals {RX, TX, GND} of the general asynchronous transceiver 118U is coupled to the set of terminals {TX, RX, GND} of the general asynchronous transceiver 58U respectively), the memory device 100 (e.g., the memory controller 110) can enter the general asynchronous transceiver communication mode to perform general asynchronous transceiver communication, in particular to begin communicating with the host device 50 via the general asynchronous transceiver connection according to the general asynchronous transceiver protocol.

[0181] In step 812, the memory device 100 (e.g., memory controller 110) may check whether it has received any general asynchronous transceiver command from the host device 50. If yes, proceed to step 814; if no, proceed to step 812 again.

[0182] In step 814, the memory device 100 (e.g., memory controller 110) may selectively perform command translation, particularly when the command translation is applicable to any general asynchronous transceiver command (e.g., intermediate command), the memory device 100 (e.g., memory controller 110) may translate any general asynchronous transceiver command into an operation command.

[0183] In step 816, memory device 100 (e.g., memory controller 110) may check for the existence of any access request based on one or more recent generic asynchronous transceiver commands received from host device 50. If yes, proceed to step 818A; otherwise, proceed to step 818B again. For better understanding, memory device 100 (e.g., memory controller 110) may translate one or more recent generic asynchronous transceiver commands into a set of operation commands (e.g., the set of operation commands mentioned in one or more of the above embodiments), for example, performing the operation of step 814 once or more for one or more recent generic asynchronous transceiver commands, wherein the set of operation commands may indicate the existence of any access request.

[0184] In step 818A, the memory device 100 (e.g., memory controller 110) may use the set of operation commands (e.g., one or more operation commands) to access the non-volatile memory 120 for the host device 50.

[0185] In step 818B, the memory device 100 (e.g., memory controller 110) can transmit a response to the host device 50 via a universal asynchronous transceiver connection.

[0186] In particular, since either of the two sets of commands (i.e., the set of intermediate commands and the set of operational commands) can be translated into the other set of commands, one or more latest generic asynchronous transceiver commands can represent the set of intermediate commands (e.g., one or more operational commands can represent it), and the set of intermediate commands can correspond to the set of operational commands. The host device 50 can translate the set of operational commands into the set of intermediate commands before transmitting the set of intermediate commands to the memory controller 110 via the generic asynchronous transceiver connection to notify the memory controller 110 of any access request. Furthermore, the memory device 100 (e.g., memory controller 110) can utilize the general asynchronous transceiver 118U of the memory controller 110 to receive the set of intermediate commands (e.g., one or more operation command representatives) corresponding to the set of operation commands via the general asynchronous transceiver connection between the memory device 100 and the host device 50, and can convert the set of intermediate commands into the set of operation commands according to the command mapping table located in the memory device 100 (e.g., either command mapping table 116T or 120T). For the sake of brevity, a similar description of this embodiment will not be repeated in detail here.

[0187] To better understand, this method can be derived from... Figure 8 The workflow shown is for illustrative purposes only; however, the invention is not limited thereto. According to certain embodiments, one or more steps may be performed within [the specified timeframe]. Figure 8 Add, delete, or modify in the workflow shown.

[0188] According to some embodiments, the set of operation commands may include one or more operation commands for use by the memory controller 110 to directly control the non-volatile memory 120, and the set of intermediate commands may include one or more operation command representatives as one or more representatives of the one or more operation commands. For the sake of brevity, similar descriptions of these embodiments will not be repeated in detail here.

[0189] According to certain embodiments, the memory device 100 (e.g., memory controller 110) may operate using the universal asynchronous transceiver 118U of the memory controller 110 in accordance with the Universal Asynchronous Transceiver Protocol (UAP) to provide basic communication capabilities (e.g., UAP communication capabilities in one or more of the architectures described in the above embodiments) so that the non-volatile memory 120 may be accessed externally via a UAP connection at any of the multiple possible stages of the memory device 100. For better understanding, multiple possible stages may represent different stages of the memory device 100 described above. Therefore, multiple possible stages may include a mass production stage and at least one preliminary stage prior to the mass production stage (e.g., one or more preliminary stages, such as a design stage and / or any one of multiple pilot stages). For example, the general asynchronous transceiver 118U of the memory controller 110 may operate according to the general asynchronous transceiver protocol, such that the non-volatile memory 120 may be accessed externally to the memory device 100 via a general asynchronous transceiver connection during the aforementioned at least one preliminary stage. For the sake of brevity, similar descriptions of these embodiments will not be repeated in detail here.

[0190] According to some embodiments, the communication speed of the general asynchronous transceiver connection can be the lowest speed among at least one effective connection speed between the memory device 100 and the host device 50. For better understanding, the at least one effective connection can include any type of connection that the memory device 100 and the host device 50 can establish between the transmission interface circuit 118 and the transmission interface circuit 58. For example, the transmission interface circuit 118 and the transmission interface circuit 58 can communicate with each other at a certain stage (e.g., one or more pilot stages, mass production stages, and / or user stages) according to existing protocols (e.g., the protocol of the specific communication specification described above), and can utilize general asynchronous transceiver. Transmitter 118U and Universal Asynchronous Transmitter 58U communicate with each other in these stages according to the Universal Asynchronous Transmitter Protocol. In this case, the aforementioned at least one active connection may include an existing-protocol-based connection (e.g., a connection corresponding to the Serial Advanced Technology Annex Specification, the Universal Serial Bus Specification, or the Fast External Connection Standard Specification, respectively) and a Universal Asynchronous Transmitter connection. Although the communication speed of the Universal Asynchronous Transmitter connection may be much lower than that of the existing-protocol-based connection, the Universal Asynchronous Transmitter connection can be used as a backup connection when needed. For example, when one or more circuits within the memory device 100 fail, the transmission interface circuits 118 and 58 cannot communicate with each other according to existing protocols due to the failure. However, they can communicate with each other according to the Universal Asynchronous Transceiver Protocol (UART). In this case, the at least one active connection may include a single active connection (e.g., a UART connection). Among all the speeds of the at least one active connection, the UART connection can have the lowest or highest communication speed since it is a single connection. Similarly, in the preliminary stage (e.g., the design stage), one or more circuits within the memory device 100 may not yet be designed or properly implemented. In this case, the at least one active connection may include a single active connection (e.g., a UART connection). Likewise, the UART connection can have the lowest or highest communication speed. For the sake of brevity, similar descriptions of these embodiments will not be repeated here.

[0191] According to some embodiments, general asynchronous transceiver communication can be applied to change or update the control mechanism of memory device 100. For example, during step 818A when the host device 50 accesses non-volatile memory 120 using the set of operation commands, memory device 100 (e.g., memory controller 110) can write at least a portion (e.g., some or all) of the in-system programming code to non-volatile memory 120 to further control memory device 100. When the total length of the in-system programming code is small enough to fit entirely into a payload packet in general asynchronous transceiver communication (e.g., the total data size of the in-system programming code is less than or equal to the byte count 512 in column #1 of the basic format of a single general asynchronous transceiver payload shown in Table 3), it is sufficient to perform step 818A once to completely write the in-system programming code into the non-volatile memory 120; otherwise, it requires multiple executions of step 818A and a loop including steps 812, 814, 816, 818A, and 818B to completely write the in-system programming code into the non-volatile memory 120. For the sake of brevity, similar descriptions of these embodiments will not be repeated in detail here.

[0192] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. A method for access management of a memory device via a universal asynchronous transceiver connection, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile memory comprising at least one non-volatile memory element, the memory device being intended to be disposed in an electronic device as an internal component of the electronic device rather than the electronic device itself, the electronic device comprising a host device and the memory device, the memory device acting as a memory component of the host device without operating independently, the method comprising: using a universal asynchronous transceiver of the memory controller, the universal asynchronous transceiver being disposed in the memory controller to support direct connection of the memory device to the host device rather than indirect connection of the memory device to the host device, thereby ensuring that the memory device can operate as required by the host device to receive a set of intermediate commands corresponding to a set of operation commands between the memory device and the host device via the universal asynchronous transceiver connection at any one of different stages of the memory device, whether the any one of the different stages represents a mass production stage or a preliminary stage prior to the mass production stage; converting the set of intermediate commands to the set of operation commands according to a command mapping table, wherein the command mapping table is located in the memory device; and using the set of operation commands to access the non-volatile memory for the host device and transmitting a response to the host device via the universal asynchronous transceiver connection.

2. The method of claim 1, wherein, the set of operation commands comprises one or more operation commands for the memory controller to directly control the non-volatile memory; and the set of intermediate commands comprises one or more operation command representatives for use as the one or more operation commands.

3. The method of claim 1, wherein, the host device is capable of transmitting a host command among a plurality of host commands to the memory device to access the memory device according to an existing protocol; and the memory device communicates with the host device via the universal asynchronous transceiver connection according to a universal asynchronous transceiver protocol.

4. The method of claim 3, wherein, the universal asynchronous transceiver protocol is different from the existing protocol.

5. The method of claim 1, wherein, further comprising: starting to communicate with the host device via the universal asynchronous transceiver connection according to a universal asynchronous transceiver protocol as a result of the universal asynchronous transceiver of the memory controller being connected to a corresponding universal asynchronous transceiver of the host device.

6. The method of claim 1, wherein, further comprising: operating the universal asynchronous transceiver of the memory controller according to a universal asynchronous transceiver protocol to provide a basic communication capability for the non-volatile memory to be accessed by an external of the memory device via the universal asynchronous transceiver connection.

7. The method of claim 6, wherein, The universal asynchronous receiver-transmitter of the memory controller operates in accordance with the universal asynchronous receiver-transmitter protocol to enable the non-volatile memory to be accessed by an external of the memory device through the universal asynchronous receiver-transmitter connection during a mass production phase of the memory device.

8. The method of claim 6, wherein, The universal asynchronous receiver-transmitter of the memory controller operates in accordance with the universal asynchronous receiver-transmitter protocol to enable the non-volatile memory to be accessed by an external of the memory device through the universal asynchronous receiver-transmitter connection during at least a preliminary phase prior to a mass production phase of the memory device.

9. The method of claim 1, wherein, A communication speed of the universal asynchronous receiver-transmitter connection is a lowest speed among at least a speed of at least a connection available between the memory device and the host device.

10. The method of claim 1, wherein, The step of accessing the non-volatile memory for the host device with the set of operation commands further comprises: writing at least a portion of an in-system programming code to the non-volatile memory to further control the memory device.

11. A memory device for being disposed in an electronic device as an internal component of the electronic device rather than the electronic device itself, the electronic device comprising a host device and the memory device, the memory device serving as a memory component of the host device without operating independently, the memory device comprising: a non-volatile memory to store information, wherein the non-volatile memory includes at least one non-volatile memory element; and a controller coupled to the non-volatile memory and configured to control operation of the memory device, wherein the controller comprises: a processing circuit configured to control the controller in accordance with a plurality of host commands from the host device to allow the host device to access the non-volatile memory through the controller; and a transport interface circuit configured to communicate with the host device, wherein the transport interface circuit comprises: a universal asynchronous receiver-transmitter, wherein the universal asynchronous receiver-transmitter is provided with a set of terminals to be respectively coupled to a set of terminals of a corresponding universal asynchronous receiver-transmitter of the host device to form a universal asynchronous receiver-transmitter connection between the memory device and the host device; wherein: the controller utilizes the universal asynchronous receiver-transmitter of itself, which is provided in the controller to support the memory device to be directly connected to the host device rather than indirectly connected to the host device, to ensure that the memory device can operate in accordance with a request of the host device to receive a set of intermediate commands corresponding to a set of operation commands through the universal asynchronous receiver-transmitter connection during any one of different phases of the memory device, whether the any one of the different phases represents a mass production phase or a preliminary phase prior to the mass production phase, wherein the host device converts the set of operation commands to the set of intermediate commands before transmitting the set of intermediate commands to the controller through the universal asynchronous receiver-transmitter connection; the controller converts the set of intermediate commands to the set of operation commands in accordance with a command mapping table, wherein the command mapping table is located in the memory device; and and The controller utilizes the set of operation commands to access the non-volatile memory for the host device, and transmits a response to the host device through the universal asynchronous receiver-transmitter connection.

12. An electronic device comprising the memory device of claim 11, characterized in that, And further comprising: The host device is coupled to the memory device, wherein the host device comprises: At least one processor to control the operation of the host device; And A power supply circuit coupled to the at least one processor and to provide power to the at least one processor and the memory device. Wherein the memory device provides storage space for the host device.

13. A controller of a memory device, the memory device comprising the controller and a non-volatile memory comprising at least one non-volatile memory element, the memory device is intended to be disposed in an electronic device as an internal component of the electronic device rather than the electronic device itself, the electronic device comprising a host device and the memory device, the memory device serving as a memory component of the host device without operating independently, the controller comprising: a processing circuit to control the controller in accordance with a plurality of host commands from the host device to allow the host device to access the non-volatile memory through the controller; And A transmission interface circuit to communicate with the host device, wherein the transmission interface circuit comprises: A universal asynchronous receiver-transmitter, wherein the universal asynchronous receiver-transmitter is provided with a set of terminals to be coupled to a corresponding set of terminals of a universal asynchronous receiver-transmitter of the host device respectively to form a universal asynchronous receiver-transmitter connection between the memory device and the host device; Wherein: The controller utilizes the universal asynchronous receiver-transmitter of itself, the universal asynchronous receiver-transmitter is provided in the controller to support the memory device to be connected to the host device directly rather than indirectly, thereby ensuring that in any one of different stages of the memory device, whether the any one of the different stages represents a mass production stage or a preliminary stage before the mass production stage, the memory device can operate according to the requirements of the host device to receive a set of intermediate commands corresponding to a set of operation commands through the universal asynchronous receiver-transmitter connection, wherein the host device converts the set of operation commands to the set of intermediate commands before transmitting the set of intermediate commands to the controller through the universal asynchronous receiver-transmitter connection; The controller converts the set of intermediate commands to the set of operation commands according to a command mapping table, wherein the command mapping table is located in the memory device; And The controller utilizes the set of operation commands to access the non-volatile memory for the host device, and transmits a response to the host device through the universal asynchronous receiver-transmitter connection.

Images