Packed data alignment plus compute instruction, processor, method, and system

Abstract

A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands, a second set of one or more source packed data operands, at least one data element offset, the first set to include a first data element, the second set to include a second data element. An execution unit is to store a result packed data operand in response to the instruction, the result packed data operand to include result data elements each having a value of an operation performed with a pair of the first set of data elements of the source packed data operands and the second set of data elements of the source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to offset any corresponding lack of alignment between the data elements of each pair in the first and second sets of source packed data operands.

Description

Technical Field

[0001] The embodiments described herein generally relate to processors. In particular, the embodiments described herein generally relate to processors having a single instruction, multiple data (SIMD) architecture. Background Technology

[0002] Many processors employ a Single Instruction Multiple Data (SIMD) architecture. In a SIMD architecture, multiple data elements can be packaged into a single register or memory location as packaged data or SIMD data. Within packaged or SIMD data, the bits of the register or memory location can be logically divided into a sequence of data elements. For example, a 128-bit wide packaged data register can have two 64-bit data elements, four 32-bit data elements, eight 16-bit data elements, or sixteen 8-bit data elements. Packaged data or SIMD instructions can be used to perform simultaneous and parallel operations on multiple data elements or pairs of corresponding data elements within the packaged or SIMD data. The processor may have parallel or SIMD execution logic (e.g., one or more SIMD execution units) in response to packaged data or SIMD instructions to perform simultaneous and parallel operations on the packaged or SIMD data. Attached Figure Description

[0003] The invention can be best understood by referring to the following description and the accompanying drawings used to illustrate embodiments. In the drawings:

[0004] Figure 1 This is a block diagram of an embodiment of a processor that operates to execute packed data alignment and calculation instructions.

[0005] Figure 2 This is a block flowchart illustrating an embodiment of a method for executing packaged data alignment and calculation instructions.

[0006] Figure 3 This is a block diagram illustrating a first embodiment of the data alignment and calculation operation.

[0007] Figure 4 This is a block diagram of an example embodiment of a runtime unit that operates to perform packaged data alignment and computation operations.

[0008] Figure 5 This is a block diagram illustrating a second embodiment of the data alignment and calculation operation.

[0009] Figure 6 This is a block diagram illustrating a third embodiment of the data alignment and calculation operation.

[0010] Figure 7 This is a block diagram of a detailed example embodiment of a processor suitable for implementing embodiments of the present invention.

[0011] Figure 8A This is a block diagram illustrating an embodiment of an ordered pipeline and an embodiment of a register renaming out-of-order issue / run pipeline.

[0012] Figure 8B This is a block diagram of an embodiment of a processor core, which includes a front-end unit coupled to a runtime engine unit, and both the front-end unit and the runtime engine unit are coupled to a memory unit.

[0013] Figure 9A This is a block diagram of an embodiment of a single processor core, its connection to the on-die interconnect network, and a local subset of its Level 2 (L2) cache.

[0014] Figure 9B yes Figure 9A A block diagram of an embodiment of a processor core portion.

[0015] Figure 10 This is a block diagram of an embodiment of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics.

[0016] Figure 11 This is a block diagram of a first embodiment of a computer architecture.

[0017] Figure 12 This is a block diagram of a second embodiment of a computer architecture.

[0018] Figure 13 This is a block diagram of a third embodiment of a computer architecture.

[0019] Figure 14 This is a block diagram of the fourth embodiment of the computer architecture.

[0020] Figure 15 This is a block diagram illustrating the use of a software instruction converter according to an embodiment of the present invention for converting binary instructions in a source instruction set into binary instructions in a target instruction set. Detailed Implementation

[0021] This document discloses packaged data alignment and computation instructions, processors for running these instructions, methods executed by the processor while processing or running the instructions, and systems that combine one or more processors to process or run the instructions. Numerous specific details (e.g., specific instruction operations, data formats, processor configurations, microarchitectural details, operation sequences, etc.) are set forth in the following description. However, embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0022] In some embodiments, packed data aligned addition instructions can be executed in a processor with a SIMD architecture. In a SIMD architecture, parallel or SIMD execution logic (e.g., one or more SIMD execution units) is typically designed to perform operations on data elements of packed or SIMD data that are aligned with each other to a specific data element. As an example, a SIMD adder unit can be designed to add corresponding data elements in the first and second source packed data that are at the same relative data element position. Similarly, a wide variety of other types of SIMD execution units (e.g., SIMD multiplication units, SIMD comparison units, SIMD shift units, etc.) can be designed to operate on corresponding data elements in the first and second source packed data that are at the same relative data element position. Such operations on corresponding data elements are sometimes referred to as “vertical” SIMD operations.

[0023] Other SIMD execution units are not limited to operating only on corresponding data elements and / or performing only "vertical" SIMD operations. Instead, some SIMD execution units can operate on non-corresponding data elements. As an example, an execution unit executing a complex multiplication instruction can operate to multiply both corresponding and non-corresponding data elements (e.g., diagonal data elements) and combine the products. However, SIMD execution units are typically designed to operate on data elements in the source packed data that have a specific, fixed, and invariant relative data element alignment. Without the packed data alignment plus computation instructions disclosed herein, if an operation is expected on data elements that do not yet exhibit a specific, fixed, and invariant relative data element alignment, one or more packed data alignment operations typically need to be performed before the SIMD execution unit can operate on the intended data elements. For example, an initial shift, rotation, shift-merge, or other packed data alignment instruction can be performed on the first source packed data operand to shift or align the data elements of the first source packed data operand before executing another instruction to perform an operation on the shifted or aligned data elements of the first source packed data operand.

[0024] However, the need to execute one or more separate packed data alignment instructions may tend to have one or more disadvantages. One potential disadvantage is that the one or more packed data alignment instructions are separate instructions, which may tend to take additional time to execute (e.g., one or more clock cycles) and / or may tend to use additional resources (e.g., fetch units, decoders, execution units, etc.) and thus increase power consumption. Another potential disadvantage is that packed data alignment instructions typically store their results back into architectural registers (e.g., packed data registers), which may render the registers unavailable for storing other data. Advantageously, the packed data alignment plus computation instructions disclosed herein can combine packed data alignment operations and computation operations within the same single instruction execution limit. This can help avoid the need to execute separate packed data alignment and computation instructions, and thus generally contributes to improved performance, increased availability of architectural registers, etc.

[0025] Figure 1 This is a block diagram of an embodiment of a processor 100 that operates to execute packaged data alignment and computation instructions 102. In some embodiments, the processor may be a general-purpose processor (e.g., a general-purpose microprocessor or central processing unit (CPU) of the type used in desktop computers, laptop computers, or other computers). Alternatively, the processor may be a special-purpose processor. Examples of suitable special-purpose processors include, but are not limited to, digital signal processors (DSPs), image processors, graphics processors, network processors, communication processors, cryptographic processors, coprocessors, embedded processors, and controllers (e.g., microcontrollers). The processor may have any of a variety of Complex Instruction Set Computing (CISC) architectures, Reduced Instruction Set Computing (RISC) architectures, Very Long Instruction Word (VLIW) architectures, hybrid architectures, or combinations of different architectures (e.g., different cores may have different architectures). In one particular example embodiment, the processor may be a DSP used as an image processor unit, but the scope of the invention is not so limited.

[0026] During operation, processor 100 may receive packed data aligned plus calculation instructions 102. For example, the instructions may be received from memory via a bus or other interconnect. The instructions may represent macro instructions, assembly language instructions, machine code instructions, or other instructions or control signals of the processor's instruction set. In some embodiments, the packed data aligned plus calculation instructions may explicitly specify (e.g., through one or more fields or bit sets) or otherwise indicate (e.g., implicitly) a first set of one or more source packed data operands 112 that will contain a first plurality of data elements (e.g., labeled as data elements A1 to A4 in the illustrated example), may explicitly specify or otherwise indicate a second set of one or more source packed data operands that will contain a second plurality of data elements (e.g., labeled as data elements B1 to B8 in the illustrated embodiment), and may explicitly specify or otherwise indicate a destination storage location 118 where the result packed data operand 120 will be stored. As an example, the instructions may have source and / or destination operand specification fields to explicitly specify the register, memory location, or other storage location of the operands. Alternatively, one or more of these operands, although not explicitly expressed (e.g., implicit or implied by the opcode of an instruction), may optionally be implicit or implied by the instruction. For example, the processor may understand from the opcode that a particular fixed register or other storage location is to be used for one of these operands. In one aspect, although this is not required, the data of the source operand may be received from an input / output device (e.g., a network interface, a digital image acquisition device, a video input device, a wireless interface, an audio input device, etc.).

[0027] As shown, in some embodiments, the packing data alignment plus calculation instruction may also explicitly specify or otherwise indicate at least one data element offset 122. As will be further explained below, at least one data element offset can be used to perform a packing data alignment operation to align source packing data operands in first and second sets of source packing data operands. At least one data element offset may represent various different types of offsets in different embodiments. To name only a few examples, suitable offsets include, but are not limited to, specifying or indicating the number of data elements, specifying or indicating the number of bits (e.g., in increments of data element size), selecting one of a predetermined number of data elements, selecting one of a predetermined number of bits (e.g., in increments of data element size), specifying or indicating a rotation amount (e.g., in increments of data element size) in a data element or bit, and specifying or indicating a shift amount (e.g., in increments of data element size) in a data element or bit. As shown, in some embodiments, at least one data element offset may optionally be stored in a general-purpose register or other scalar register 124. Alternatively, the immediate value of the instruction may optionally be used to provide at least one data element offset, or a combination of such methods may optionally be used. Advantageously, such embodiments allow instructions to indicate flexible or variable offsets (e.g., in one aspect, the offset can be any of -4, -3, -2, -1, 0, 1, 2, 3, or 4 data element offset positions, where negative integers (e.g., -2) are used to indicate the offset in one direction and non-negative integers (e.g., 2) are used to indicate the offset in the opposite direction). In other embodiments, a fixed offset may optionally be implicit for instructions (e.g., their opcodes) rather than being flexibly or variablely indicated through the non-opcode field of the instruction.

[0028] Refer again Figure 1The processor includes a decoding unit or decoder 104. The decoding unit can receive and decode packetized data-aligned addition instructions. The decoding unit can output one or more relatively low-level instructions or control signals (e.g., one or more microinstructions, microoperations, microcode entry points, decoding instructions, or control signals, etc.) that reflect or represent relatively high-level packetized data-aligned addition instructions and / or obtain the one or more relatively low-level instructions or control signals from the higher-level packetized data-aligned addition instructions. In some embodiments, the decoding unit may include: one or more input structures (e.g., ports, interconnects, interfaces) for receiving packetized data-aligned addition instructions; instruction recognition and decoding logic coupled thereto for recognizing and decoding the packetized data-aligned addition instructions; and one or more output structures coupled thereto (e.g., ports, interconnects, interfaces) for outputting lower-level instructions or control signals. The decoding unit can be implemented using various different mechanisms, including but not limited to microcode read-only memory (ROM), lookup tables, hardware implementations, programmable logic arrays (PLAs), and other mechanisms suitable for implementing the decoding unit.

[0029] In some embodiments, instead of directly providing the packet data alignment and calculation instructions to the decoding unit, an instruction emulator, translator, transformer, interpreter, or other instruction conversion module may be optionally used. Various types of instruction conversion modules can be implemented in software, hardware, firmware, or a combination thereof. In some embodiments, the instruction conversion module may be located external to the processor, such as on a separate die and / or in memory (e.g., as a static, dynamic, or runtime emulation module). As an example, the instruction conversion module may receive packet data alignment and calculation instructions (which may belong to a first instruction set) and may emulate, translate, transform, interpret, or otherwise convert the packet data alignment and calculation instructions into one or more corresponding intermediate instructions or control signals, which may belong to a second, different instruction set. One or more intermediate instructions or control signals of the second instruction set may be provided to the decoding unit (e.g., decoding unit 104), which may decode them into one or more lower-level instructions or control signals executable by the processor's native hardware (e.g., one or more execution units).

[0030] Refer again Figure 1The processor 100 also includes a set of packed data registers 108. Each of these packed data registers may represent an on-die storage location, which operates to store packed data or SIMD data. This packed or SIMD data may represent “spatial” SIMD, where elements are received together via a bus or other interconnect, stored together as packed or SIMD data in a register (where interruptions may occur in the carry chain of data elements), etc. The packed data registers may represent architecture-visible or architectural registers visible to software and / or a programmer, and / or registers indicated by instructions of the processor's instruction set to identify operands. These architectural registers contrast with other non-architectural registers in a given microarchitecture (e.g., temporary registers, reorder registers, retirement registers, etc.). Packed data registers may be implemented in different ways in different microarchitectures and are not limited to any particular type of design. Examples of suitable types of registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, and combinations thereof.

[0031] In some embodiments, a first set of one or more source packed data operands 112 may optionally be stored in a first set of one or more packed data registers 110 (e.g., a single register may be used to store a single operand or different packed data registers may be used to store each of two different operands), and a second set of one or more source packed data operands 116 may optionally be stored in a second set of one or more packed data registers 114 (e.g., a single register may be used to store a single operand or different packed data registers may be used to store each of two different operands). In some embodiments, destination storage location 118 may optionally be a third packed data register. Alternatively, memory locations or other storage locations may optionally be used for one or more of these operands. Furthermore, in some embodiments, a source / destination packed data register used for one of the source packed data operands may optionally be reused as a destination storage location for storing a result packed data operand. For example, instructions may specify a source / destination register and the processor may implicitly or implicitly understand that the source / destination register is initially intended to be used to retrieve a source operand and subsequently the result operand is to be stored in the source / destination register, thereby overwriting the source operand. Additionally, in some embodiments, the instructions may specify a set of data operands that are packed from only one or more sources (e.g., set 112 instead of set 116).

[0032] Refer again Figure 1The execution unit 106 is coupled to the decoding unit 104. The execution unit may receive one or more decoded or otherwise converted instructions or control signals representing or derived from a packed data alignment and addition instruction. The execution unit is coupled, for example, to first and second sets of source packed data operands 112, 116 via coupling to the packed data register 108. The execution unit may receive the first and second sets of source packed data operands. The execution unit operates in response to and / or due to a packed data alignment and addition instruction (e.g., in response to one or more instructions or control signals decoded therefrom) to store the resulting packed data operand 120 in the destination storage location 118 indicated by the instruction.

[0033] In some embodiments, the resulting packaged data operands may contain multiple resulting data elements (e.g., labeled data elements R1 to R4 in the illustrated example). In some embodiments, each of the resulting data elements may have a value representing an operation performed using data elements from a first set of source packaged data operands 112 and data elements from a second set of source packaged data operands 116. For example, as shown in the illustrated example embodiment, R1 may have a value representing an operation (OP) performed using data element A1 from the first set of source packaged data operands and a non-corresponding data element B4 from the second set of source packaged data operands. Similarly, R2 may have a value representing an operation (OP) performed using A2 and B5, R3 may have a value representing an operation (OP) performed using A3 and B6, and R4 may have a value representing an operation (OP) performed using A4 and B7. This example offset applied to the positions of the three data elements of operand 116 is merely an illustrative example.

[0034] In some embodiments, such as when at least one data element offset collectively or cumulatively reaches at least one (leastone) non-zero data element offset, the data elements in each pair may be non-corresponding data elements in the source operands. For example, A1 and B4 are in non-corresponding data element positions in the first and second sets of the source packed data operands (i.e., in the first and second sets of the source packed data operands, A1 is in a data element position corresponding to B1 but not to B4). Similarly, A2 and B5, A3 and B6, and A4 and B7 are each in non-corresponding data element positions in the first and second sets of the source packed data operands.

[0035] The execution unit may apply at least one data element offset to at least one corresponding data element in the first and second sets of source packed data operands, and the at least one data element offset may negate, eliminate, cancel, or otherwise offset any lack of correspondence between pairs of data elements in the first and second sets of source packed data operands. Applying at least one data element offset to at least one data element in the first and second sets of source packed data operands may make each pair of data elements correspond (e.g., the same relative data element position) or align them in intermediate or microarchitecture registers or circuitry within the execution unit. In some embodiments, non-corresponding data element positions may differ based on at least one data element offset indicated by a packed data alignment plus calculation instruction. In the case of a single non-zero offset, non-corresponding data elements may differ by a non-zero offset. For example, in the illustrated example embodiment, non-corresponding data element positions differ by three data element positions. For example, B4 may be rotated, shifted, or otherwise moved or offset by three data element positions (which, depending on the implementation, may be toward the least or most significant bit position) such that it will be in the data element position corresponding to A1. In some embodiments, the difference of these three data element positions (in this particular example) may be equal to a single data element offset of the three data element positions. In other embodiments, in the case of two offsets, non-corresponding data elements may differ by two offsets or be different based on a combination of the two offsets or the application of the two offsets. For example, the positional difference of the three data elements illustrated (in this particular example) may be equal to the difference between the first data element offset of the first set to be applied to one or more source packaged data operands and the second data element offset of the second set to be applied to one or more source packaged data operands. As an example, A1 is not shown as having been moved in the illustration, which can be performed using a zero data element offset of the first set to be applied to the packaged data operands and a three data element offset of the second set to be applied to the packaged data operands. In other embodiments, the non-corresponding data element positions may differ based on other differences between positive or negative data element offsets, such as the difference between negative four and four data element positions (i.e., -4, -3, -2, -1, 0, 1, 2, 3, 4), the difference between negative two and two data element positions (i.e., -2, -1, 0, 1, 2), the difference between zero and four data element positions (i.e., 0, 1, 2, 3, 4), the difference between zero and two data element positions (i.e., 0, 1, 2), the difference between zero and one data element positions, the difference between negative six and six data element positions, the difference between zero and six data element positions, etc.

[0036] In the illustrated embodiments, specific examples of source and result operands are shown and described, but the scope of the invention is not so limited. In the illustrated example embodiments, a first set of source packaged data operands optionally has at least four data elements, a second set of source packaged data operands optionally has eight data elements, and a result packaged data operand optionally has four data elements, but in other embodiments fewer or more data elements may optionally be used for these operands. As another illustrative example, each of the first and second sets of source packaged data operands may optionally have sixty-four data elements, and the result packaged data operand may optionally have half that number or thirty-two data elements. In other embodiments, other numbers of data elements disclosed herein are also suitable. Moreover, for ease of illustration, the result data element is physically larger than the source data element, but the result data element may have the same or different number of bits as the source data element. Furthermore, the data elements of the first and second sets of source packaged data operands may have the same or different number of bits. In some embodiments, the result packaged data operand may be a pair Figure 3-6 Any of those shown and described herein, including variations and alternative embodiments thereof.

[0037] The execution unit and / or processor may include specific or particular logic (e.g., transistors, integrated circuit systems, or other hardware potentially combined with firmware (e.g., instructions stored in non-volatile memory) and / or software) that operates to execute packed data aligned addition calculation instructions and / or to store results in response to and / or due to packed data aligned addition calculation instructions (e.g., in response to one or more instructions or control signals decoded from packed data aligned addition calculation instructions). In some embodiments, the execution unit may include one or more input structures (e.g., ports, interconnects, interfaces) for receiving source operands, a packed data aligned circuit system or logic (e.g., shift or rotate circuit system or logic) for performing arithmetic operations on the source operands, an arithmetic or logical operation circuit system or logic coupled thereto for performing arithmetic or logical operations on aligned intermediate operands and generating result operands, and one or more output structures (e.g., ports, interconnects, interfaces) coupled thereto for outputting the result operands. In some embodiments, the execution unit may include... Figure 4 The circuit systems or logic, or variations or alternatives thereof, shown and described are illustrative examples of suitable microarchitectural arrangements, but the scope of the invention is not so limited. In some embodiments, the operating unit may be contained within the image processor unit of the digital signal processor and used to process the pixels of an image, but the scope of the invention is not so limited.

[0038] To avoid confusion, a relatively simple processor 100 is shown and described. However, the processor may optionally include other processor components. For example, various different embodiments may include... Figure 7 And / or various combinations and configurations of the components shown and described in Figures 8-10. All components of the processor can be coupled together to allow them to operate as intended.

[0039] Figure 2 This is a block flowchart illustrating an embodiment of method 230 for executing packaged data alignment and computation instructions. In various embodiments, the method may be executed by a processor, instruction processing device, or other digital logic device. In some embodiments, Figure 2 The method can be derived from Figure 1 The processor executes and / or executes within it. This article is for Figure 1 The components, features, and specific optional details described in the processor description can also be optionally applied to Figure 2 The method. Alternative sites, Figure 2 The method can be executed by and / or within different processors or devices. Furthermore, Figure 1 The processor can execute with Figure 2 Those different methods.

[0040] The method includes receiving a packed data alignment and calculation instruction at block 231. In various aspects, the instruction may be received at the processor or a portion thereof (e.g., instruction fetch unit, decode unit, bus interface unit, etc.). In various aspects, the instruction may be received from external and / or off-die sources (e.g., from the processor, interconnect, etc.) or from on-processor and / or on-die sources (e.g., from the instruction cache, instruction queue, etc.). The packed data alignment and calculation instruction may specify or otherwise indicate a first set of one or more source packed data operands containing a first plurality of data elements, may specify or otherwise indicate a second set of one or more source packed data operands containing a second plurality of data elements, may specify or otherwise indicate an offset of at least one data element, and may specify or otherwise indicate a destination storage location.

[0041] At block 232, the resulting packaged data operand may be stored in the destination storage location in response to and / or due to a packaged data alignment plus calculation instruction. The resulting packaged data operand may contain multiple resulting data elements. In some embodiments, each of the resulting data elements may have a value representing an operation performed using data elements in a first set of a pair of source packaged data operands and non-corresponding data elements in a second set of source packaged data operands. In some embodiments, each pair of non-corresponding data elements is located at a non-corresponding data element position in the first and second sets of the source packaged data operands. In some embodiments, the non-corresponding data element position differs based on at least one data element offset indicated by the packaged data alignment plus calculation instruction. In some embodiments, the method may be performed using a digital signal processor during pixel filtering during image processing, but the scope of the invention is not so limited.

[0042] The illustrated method involves architectural operations (e.g., those visible from a software perspective). In other embodiments, the method may optionally include one or more microarchitectural operations. As an example, instructions may be fetched out of order, decoded, scheduled, and source operands may be accessed. The execution unit may perform microarchitectural operations to implement instructions (e.g., shifting, rotating, or otherwise moving data elements based on at least one offset), etc.

[0043] Figure 3 This is a block diagram illustrating a first example embodiment of a packed data alignment and calculation operation 348 that can be performed in response to a first example embodiment of a packed data alignment and calculation instruction 302. The instruction includes an operation code or opcode 336. The opcode may represent multiple bits or one or more fields operable to identify the instruction and / or operation to be performed (e.g., packed data alignment and specific type of calculation operation (e.g., averaging, multiplication, addition, shifting, etc.)).

[0044] The instruction may also optionally include a first source specification field (SRC1) 338 for specifying the first source packaged data operand 312-1 and a second source specification field (SRC2) 340 for specifying the second source packaged data operand 312-2. The first and second source packaged data operands represent a first set of source packaged data operands. The instruction may also optionally include a third source specification field (SRC3) 342 for specifying the third source packaged data operand 316-1 and a fourth source specification field (SRC4) 344 for specifying the fourth source packaged data operand 316-2. The third and fourth source packaged data operands represent a second set of source packaged data operands. The instruction may also optionally include a destination specification field (DEST) 346 for specifying the destination storage location of the packaged data operand 320 in which the result to be stored is located.

[0045] As an example, each of the source and destination specification fields may contain bits (typically but not necessarily contiguous) used to explicitly specify the address, memory location, or other storage location of the register to which the associated operand is stored. Alternatively, in another embodiment, any of the specification fields may be optionally omitted, and the register or other storage location may be optionally implicit or implied by instructions. For example, it may be inherent or understood (though not explicitly expressed) to use a fixed register for one of the operands when decoding the opcode. As another example, instead of having a destination specification field, one of the source specification fields may represent the source / destination specification field used to specify the source / destination register. The source packed data operand may be initially stored in the source / destination register, and then it may be implicit or inherent to reuse the source / destination register to store the resulting packed data operand on top of the initial source packed data operand.

[0046] The instruction also indicates at least one data element offset. In the illustrated example embodiment, the instruction has: a first offset specification field 322-1, specifying or otherwise indicating a first offset to correspond to and be applied to a first set of source packed data operands (operations 312-1, 312-2 in this embodiment); and an optional second offset specification field 322-2, specifying or otherwise indicating an optional second offset to correspond to or be applied to a second set of source packed data operands (operations 316-1, 316-2 in this embodiment). In some embodiments, bits in each of these offset specification fields may specify or otherwise indicate a register (e.g., a general-purpose register or other scalar register) or other storage location where the value of the offset is stored. In other embodiments, bits in each of these offset specification fields may specify the value of the offset, or otherwise encode or indicate the value of the offset (e.g., have values ​​for selecting among a plurality of predetermined offsets). In some embodiments, the immediate value of the instruction may optionally have a first and optional second offset. Combinations of methods are also suitable.

[0047] In the illustrated example embodiment, the first offset indicates an offset of one data element position, and the second offset indicates an offset of two data element positions, but this is merely an illustrative example. In other embodiments, each of the first and second offsets can be any of the following data element positions: -8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 7, or 8. In other embodiments, fewer or more data element offsets may optionally be supported. In other embodiments, the instruction may have only a single offset specification field to provide a single offset. Additionally, in other embodiments, one or more offsets may optionally be implicit or inherent to the instruction (e.g., opcode) and be immutable or fixed. Other embodiments of the packed data alignment plus calculation instruction may optionally omit some of the described fields, add additional fields (e.g., add fields associated with a specific type of operation (e.g., to provide the shift amount, indicate whether saturation is performed, etc.)), and may rearrange the fields differently within the instruction.

[0048] Examples of suitable sets of source operands are shown in the description, but the scope of the invention is not limited to these specific source operands. Specifically, a first source packed data operand 312-1 (e.g., indicated by SRC1) has four packed data elements A1-A4, and a second source packed data operand 312-2 (e.g., indicated by SRC2) has four packed data elements A5-A8. Similarly, a third source packed data operand 316-1 (e.g., indicated by SRC3) has four packed data elements B1-B4, and a fourth source packed data operand 316-2 (e.g., indicated by SRC4) has four packed data elements B5-B8. In other embodiments, the source packed data operands may optionally contain different numbers of packed data elements. Typically, the number of data elements in each source packed data operand may be equal to the bit-based size of the source packed data operand divided by the bit-based size of a single data element. In various embodiments, each source packaged data operand can be 64-bit, 128-bit, 256-bit, 512-bit, or 1024-bit, but the scope of the invention is not limited thereto. In various embodiments, each data element can be 8-bit, 16-bit, 32-bit, or 64-bit, but the scope of the invention is not limited thereto. In various embodiments, each operand can contain four, eight, sixteen, thirty-two, or sixty-four data elements, but the scope of the invention is not limited thereto. It is not required that the operands have the same number of data elements. Typically, the number of data elements in an operand is a power of 2, but this is not required.

[0049] In the illustrated example embodiment, the least significant data element is on the left and the most significant data element is on the right, but the reverse arrangement is also possible. Data elements in the first set of operands 312-1 and 312-2 and the second set of operands 316-1 and 316-2 that are in the same relative data element position are in corresponding positions and / or are corresponding data elements. For example, A1 and B1 are corresponding data elements, A2 and B2 are corresponding data elements, and so on. In contrast, A2 and B3 are in non-corresponding data element positions and / or A2 and B3 are non-corresponding data elements. Furthermore, the first and second source packaged data operands can be logically cascaded or otherwise considered together, such that A5 and B5 correspond but A5 and B1 do not, such that A7 and B7 correspond but A7 and B3 do not, and so on.

[0050] Packed data alignment and calculation operation 348 can be performed in response to an embodiment of packed data alignment and calculation instruction 302. This may involve retrieving or otherwise receiving source operands from registers or other storage locations associated with the source operands and providing them to execution unit 306. At least one offset indicated by the instruction (in this embodiment, a first offset and an optional second offset) may also be provided to the execution unit. The execution unit can operate in response to the packed data alignment and calculation instruction to generate a result packed data operand 320 and store it in a destination storage location (e.g., indicated by DEST). The result packed data operand may contain multiple result data elements. In the illustrated example embodiment, the result packed data operand has four result data elements, but other embodiments may have fewer or more result data elements than four. In some embodiments, each of the resulting data elements may have the value of an operation (OP) performed using data elements in a first set of at least one pair of source packaged data operands (e.g., operands 312-1, 312-2) and non-corresponding data elements in a second set of source packaged data operands (e.g., operands 316-1, 316-2), wherein each pair of non-corresponding data elements is in a non-corresponding data element position in the first and second sets of source packaged data operands. For example, in the illustrated example embodiment, the first resulting data element may have the value of an operation (OP) performed on A2 and B3, the second resulting data element may have the value of an operation (OP) performed on A3 and B4, the third resulting data element may have the value of an operation (OP) performed on A4 and B5, and the fourth resulting data element may have the value of an operation (OP) performed on A5 and B6.

[0051] In some embodiments, each pair of non-corresponding data elements may be located in non-corresponding data element positions in the first and second sets of source packed data operands, differing based on at least one data element offset indicated by an instruction (e.g., a first offset 322-1 and a second offset 322-2). The non-corresponding data element positions may be such that a unit operation is performed to apply the first and second offsets to the source operands in response to a packed data alignment plus calculation instruction, and, within the execution limits of the packed data alignment plus calculation instruction, brings the non-corresponding data element into the corresponding data element position. For example, B3 may be offset or otherwise moved into the corresponding data element position relative to A2 (e.g., moved into the same relative data element bit position) by applying a first offset 322-1 of a data element position to the first and second source packed data operands (e.g., their logical concatenation) and by applying a second offset 322-2 of two data element positions to the third and fourth source packed data operands (e.g., their logical concatenation). In the illustrated example embodiment, the first offset is one data element position, and the second offset is two data element positions; therefore, applying the first and second offsets together shifts or moves the relative position of the data element by one data element position. The two offsets work together to make A2 and B3 corresponding data elements, A3 and B4 corresponding data elements, A5 and B6 corresponding data elements, and so on, within the operating unit. Data element offsets can be applied in different ways in different embodiments, such as as shifts, as rotations, as shift-merge operations, etc. Note that B2 and B3 (and the like) will typically not be corresponding data elements in the architecturally visible packed data registers; instead, once accessed from the packed data registers, they will be carried over to corresponding data elements in temporary / intermediate non-architecturally visible registers within the internal circuitry and / or the operating unit.

[0052] The execution unit can operate to perform a wide variety of different types of operations (OPs) on aligned data elements. The scope of the invention is not limited to any particular known type of such operation (OP). Examples of suitable types of operations include, but are not limited to, arithmetic operations (e.g., addition, subtraction, multiplication, division, multiply-accumulate, multiply-accumulate, dot product, etc.), logical operations (e.g., shift, rotation, logical AND, logical OR, logical XOR, logical AND NOT, etc.), other operations (e.g., comparison, square root, inverse square root, bit counting, bit inversion, saturate to half width, etc.), and combinations thereof. In some embodiments, the execution unit may perform “vertical” SIMD computation operations only on corresponding data elements in the same relative data element position (e.g., utilizing a “vertical” SIMD lane or a portion of the execution unit), but the scope of the invention is not so limited. For example, the execution unit can perform packed addition, packed subtraction, packed multiplication, packed division, packed averaging, packed saturated half-width, packed square root, packed inverse square root, packed shift, packed rotation, packed logical AND, packed logical OR, packed logical XOR, packed logical ANDNOT, packed comparison, or similar operations only on the corresponding data elements in the first and second sets of the source operands.

[0053] In some embodiments, the execution unit can perform a combination of vertical and non-vertical SIMD computation operations involving combinations of corresponding and non-corresponding data elements. As an example, the execution unit can perform complex multiplication, which involves adding two products of corresponding and non-corresponding data elements. Various other examples of such more detailed vertical-to-non-vertical SIMD operations are also suitable. In any case, data elements are aligned to the positions where the execution unit intends or is designed to perform operations on the intended set of data elements. Advantageously, alignment operations can allow the reuse or utilization of a wide variety of existing vertical and / or vertical and non-vertical SIMD execution units or logic without requiring the execution of separate packing data alignment instructions (e.g., shift-merge instructions) to achieve the same packing data alignment. In certain example embodiments, the operation can be one of multiplication, addition, averaging, and multiply-accumulate, but the scope of the invention is not so limited.

[0054] Figure 4 This is a block diagram of an example embodiment of a runtime unit that operates to perform packaged data alignment and computation operations. The runtime unit can be used to perform the various operations described herein (e.g., Figure 3 and 5 The running unit includes a first alignment unit 460 and a second alignment unit 467. The running unit also includes a vertical SIMD calculation unit 466.

[0055] The first alignment unit is coupled to receive a first set of one or more source packed data operands, which in the illustrated embodiment include a first source packed data operand 412-1 and a second source packed data operand 412-2. The first alignment unit includes a first cascade and rotation unit CR1, a second cascade and rotation unit CR2, and a third cascade and rotation unit CR3. CR1 operates to perform a right rotation (although shown to the left in the description) toward the least significant bit position of the zero data element position and outputs a zero data element offset intermediate operand 461-0. Because the zero data element position is rotated, the CR1 unit can optionally be replaced by a simpler cascade unit. CR2 operates to perform a right rotation toward the least significant bit position of one data element position and outputs a data element offset intermediate operand 461-1. CR2 operates to perform a right rotation toward the least significant bit positions of two data element positions and outputs two data element offset intermediate operands 461-2. Each of the intermediate operands 461 can be provided as input to a first multiplexer (MUX) or other selector unit 464. In other embodiments, additional and / or different numbers of data element positions may optionally be supported. For example, in an alternative embodiment, five or nine different data element offset intermediate operands may optionally be generated and input to the selector unit. Furthermore, in other embodiments, shifting may optionally be used instead of rotation. The first data element offset 422-1 indicated by the instruction may be input to the selector unit 464 and can be used to select one of the inputs. In this example embodiment, the first data element offset is a data element position, so a data element offset intermediate operand 461-1 can be selected and output as the first selected operand 465.

[0056] The second alignment unit 467 is coupled to receive a second set of one or more source packed data operands, which in the illustrated embodiment include a third source packed data operand 416-1 and a fourth source packed data operand 416-2. The second alignment unit includes a fourth cascade and rotation unit CR4, a fifth cascade and rotation unit CR5, and a sixth cascade and rotation unit CR6. CR4 operates to perform a right rotation (although shown to the left in the description) toward the least significant bit position of the zero data element position and outputs a zero data element offset intermediate operand 468-0. Because the zero data element position is rotated, the CR4 unit can optionally be replaced by a simpler cascade unit. CR5 operates to perform a right rotation toward the least significant bit position of one data element position and outputs a data element offset intermediate operand 468-1. CR6 operates to perform a right rotation toward the least significant bit positions of two data element positions and outputs two data element offset intermediate operands 468-2. Each of the intermediate operands 468 can be provided as input to a second multiplexer (MUX) or other selector unit 469. In other embodiments, additional and / or different numbers of data element positions may optionally be supported. For example, in an alternative embodiment, five or nine different data element offset intermediate operands may optionally be generated and input to the selector unit. Moreover, in other embodiments, shifting may optionally be used instead of rotation. The second data element offset 422-2 indicated by the instruction may be input to the second selector unit 469 and may be used to select one of the inputs. In this example embodiment, the second data element offset is two data element positions, so two data element offset intermediate operands 461-2 can be selected and output as the second selected operand 470.

[0057] Both the first selected operand 465 and the second selected operand 470 can be input to the vertical SIMD computation unit 466 (e.g., a SIMD addition unit, a SIMD multiplication unit, etc.). The vertical SIMD computation unit can operate to perform vertical SIMD computation operations on the corresponding data elements of the first and second selected operands. Any of the previously described operation types is suitable, such as packed addition, multiplication, averaging, division, or other operations described herein. The vertical SIMD computation unit can output and store the result packed data operand 420. In the illustrated example embodiment, because the first offset is one data element position and the second offset is two data element positions, the result packed data operand can have a first result data element with the values ​​of the operations performed on A2 and B3, a second result data element with the values ​​of the operations performed on A3 and B4, a third result data element with the values ​​of the operations performed on A4 and B5, and a fourth result data element with the values ​​of the operations performed on A5 and B6.

[0058] This is merely an illustrative example of a suitable operating unit. In other embodiments, the first and second alignment units may instead perform shift-merge operations based on corresponding offsets rather than multiple shift and selection operations. In other embodiments, a single variable shift or rotation unit may shift or rotate the operand based on an offset rather than creating multiple possibilities and selecting one of them. Furthermore, in other embodiments, if only a single data element offset is desired, only one of the first and second alignment units may be optionally included.

[0059] Figure 5 This is a block diagram illustrating a second example embodiment of a packaged data alignment and calculation operation 548 that can be performed in response to a packaged data alignment and calculation instruction 502. Figure 5 The instructions and operations have the same Figure 3 There are certain similarities between the instructions and operations. To avoid confusion, the main description will be... Figure 5 The different instructions and / or additional features of the operation without repeating all about Figure 3 The instructions and operations may have similar or common characteristics, details, variations, and alternatives. However, to understand the previously described... Figure 3 The characteristics, details, variations, and alternatives of the instructions and operations can also be optionally applied. Figure 5 Instructions and operations, unless otherwise specified or obvious.

[0060] Instruction 502 includes opcode 536, a first source specification field (SRC1) 538 for specifying the first source packaged data operand 512, a second source specification field (SRC2) 540 for specifying the second source packaged data operand 516-1, and a third source specification field (SRC3) 542 for specifying the third source packaged data operand 516-2. In this embodiment, with Figure 3 In contrast to the two source packaged data operands in the embodiment, the first source packaged data operand 512 is a first set of single-source packaged data operands. The second and third source packaged data operands 516 represent a second set of two source packaged data operands. The instructions may also optionally include a destination specification field (DEST) 546 for specifying the destination storage location of the packaged data operand 520 in which the result is to be stored. Each of these fields and operands may have the characteristics, details, variations, and alternatives described previously.

[0061] In this embodiment, with Figure 3In contrast to the two data element offsets in the embodiment, the instruction further indicates only a single data element offset. The instruction has a single offset specification field 522 for specifying or otherwise indicating a single offset to correspond to and be applied to the second set of source packed data operands (operations 516-1 and 516-2 in this embodiment). The data element offset and its specification field may have the characteristics, details, variations, and alternatives described previously. Various situations exist where it is useful to perform relative offsets only between the second and third source packed data operands and the first source packed data operand without shifting or moving any data elements of the first source packed data operand. A single data element offset is sufficient to achieve this. Moreover, applying only a single data element offset can help reduce the complexity of the execution unit, for example, by eliminating one of the alignment units (e.g., eliminating...). Figure 4 (The first alignment unit in the diagram). In the illustrated example embodiment, a single offset indicates an offset of three data element positions, but this is merely an illustrative example. In other embodiments, a single offset can be any of -4 to 4, 0 to 4, -2 to 2, 0 to 2, or some other number of data element positions, depending on the specific implementation. As before, the offset can be specified as the number of data elements, the number of bits, the amount of shift, the amount of rotation, or the like. Alternatively, in other embodiments, a second data element offset may be optionally used, if intended. In alternative embodiments, a fixed offset may be optionally used instead of the offset specification field, and may be implicit for opcodes, as previously described.

[0062] In the illustrated embodiment, the first set of one or more source packed data operands has only a single first source packed data operand 512 (e.g., indicated by SRC1), which in this example embodiment has four packed data elements A1-A4. A second source packed data operand 516-1 (e.g., indicated by SRC2) has four packed data elements B1-B4, and a third source packed data operand 516-2 (e.g., indicated by SRC3) has four packed data elements B5-B8. Because only the second and third source packed data elements are offset in the illustrated example embodiment, there is no need for additional data elements to replace or substitute them, as indicated by... Figure 3 The data element A5 shown in the diagram represents the data element lost due to the offset of the first source packed data operand. Other numbers of data elements can, conversely, be used as previously described. Additionally, in the illustrated embodiment, the second set of source packed data operands has second and third source packed data operands, but in another embodiment, a single source packed data operand with more data elements than the first source packed data operand (e.g., up to twice or at least one more, depending on the supported offset) can be optionally used.

[0063] Data elements in the second set of the first source packaged data operand 512 and the second and third source packaged data operands 516-1 and 516-2 that are in the same relative data element position are in corresponding positions and / or are corresponding data elements. For example, A1 and B1 correspond, A4 and B4 correspond, and so on. In contrast, A1 and B4 are in non-corresponding data element positions and / or A1 and B4 are non-corresponding data elements in the source operands. Furthermore, the first and second source packaged data operands can be logically cascaded or otherwise considered together such that A1 and B5 do not correspond.

[0064] A second embodiment of the packing data alignment and calculation operation 548 can be executed in response to a second embodiment of the packing data alignment and calculation instruction 502. The execution unit can operate in response to the packing data alignment and calculation instruction to generate a result packing data operand 520 and store it in a destination storage location. In the illustrated example embodiment, the result packing data operand has four result data elements, but other embodiments may have fewer or more result data elements than four. In some embodiments, each of the result data elements may have the value of an operation (OP) performed using data elements from a first set of at least one pair of source packing data operands (e.g., a single source packing data operand 512) and non-corresponding data elements from a second set of source packing data operands (e.g., second and third source packing data operands 516-1, 516-2). Each pair of non-corresponding data elements may be in a non-corresponding data element position in the first source packing data operand and the second and third packing data operands. For example, in the illustrated example embodiment, the first result data element may have the value of an operation (OP) performed on A1 and B4, the second result data element may have the value of an operation (OP) performed on A2 and B5, the third result data element may have the value of an operation (OP) performed on A3 and B6, and the fourth result data element may have the value of an operation (OP) performed on A4 and B7. This is merely an illustrative example.

[0065] As before, in some embodiments, each pair of non-corresponding data elements may be in non-corresponding data element positions within the source packed data operands, differing based on a single data element offset. The non-corresponding data element positions may be such that the execution unit operates to apply a single data element offset to the second and third source packed data operands in response to a packed data alignment plus calculation instruction, and, within the execution limits of the packed data alignment plus calculation instruction, brings the non-corresponding data element into the corresponding data element position. For example, B4 may be offset or otherwise moved by three data element positions such that it corresponds to A1 (e.g., having the same relative data element position) by applying a single data element offset of 522 to the second and third source packed data operands (e.g., their logical concatenation). The execution unit may operate to perform any of various types of operations (OPs) on the aligned data elements as previously described. In some embodiments, the execution unit may perform "vertical" SIMD calculation operations only on the corresponding data elements. In other embodiments, the execution unit may perform combinations of vertical and non-vertical SIMD calculation operations involving combinations of corresponding and non-corresponding data elements.

[0066] Figure 6 This is a block diagram illustrating a third example embodiment of a packaged data alignment and calculation operation 648 that can be performed in response to a third example embodiment of a packaged data alignment and calculation instruction 602. Figure 6 The instructions and operations have the same Figure 3 There are certain similarities between the instructions and operations. To avoid confusion, the main description will be... Figure 6 The different instructions and / or additional features of the operation, without repeating information about Figure 3 All possible similar or common characteristics, details, variations, and alternatives of the instructions and operations. However, to understand the previously described... Figure 3 The characteristics, details, variations, and alternatives of the instructions and operations can also be optionally applied. Figure 6 Instructions and operations, unless otherwise specified or obvious.

[0067] Instruction 602 includes opcode 636, a first source specification field (SRC1) 638 for specifying a first source packaged data operand 612, and a second source specification field (SRC2) 640 for specifying a second source packaged data operand 616. In this embodiment, the first source packaged data operand 612 represents a first set of single-source packaged data operands. Similarly, the second source packaged data operand 616 represents a second set of single-source packaged data operands. The instruction may also optionally include a destination specification field (DEST) 646 for specifying the destination storage location where the resulting packaged data operand 620 is to be stored. Each of these fields and operands may have the characteristics, details, variations, and alternatives described above.

[0068] In this embodiment, the instructions also specify a first data element offset 622-1 and a second data element offset 622-2. The first data element offset corresponds to and is to be applied to the first source packed data operand 612, and the second data element offset corresponds to and is to be applied to the second source packed data operand 616. In other embodiments, a single data element offset may be used if desired (e.g., as in union). Figure 5 (Described). Data element offsets and their canonical fields may have the characteristics, details, variations, and alternatives described previously. In the illustrated example embodiment, the first data element offset indicates an offset from the zero data element position, and the second data element offset is an offset from three data element positions, but this is merely an illustrative example. In other embodiments, each of the data element offsets (independent of each other) may be any one of -4 to 4, 0 to 4, -2 to 2, 0 to 2, or some other number of data element positions (e.g., a larger number of offsets may also be used if more data elements are present), depending on the specific implementation. As before, each data element offset may be specified as the number of data elements, the number of bits, the amount of shift in a bit or data element, the amount of rotation in a bit or data element, or the like.

[0069] In the illustrated example embodiment, the first source packed data operand 612 (e.g., indicated by SRC1) has eight packed data elements A1-A8. The second source packed data operand 616 (e.g., indicated by SRC2) has eight packed data elements B1-B8. In other embodiments, alternatively, other numbers of data elements may be used. Data elements in the same relative data element positions in the first source packed data operand 612 and the second source packed data operand 616 are in corresponding positions and / or are corresponding data elements. For example, A1 and B1 correspond, A7 and B7 correspond, and so on. In contrast, A1 and B4 are in non-corresponding data element positions and / or A1 and B4 are non-corresponding data elements in the source operands. In the illustrated embodiment, each of the source operands has more data elements than the resulting packed data operand (e.g., twice as many data elements in this example).

[0070] A third embodiment of the packing data alignment and calculation operation 648 can be executed in response to a third embodiment of the packing data alignment and calculation instruction 602. The execution unit, in response to the packing data alignment and calculation instruction, can operate to generate a result packing data operand 620 and store it in a destination storage location. In the illustrated example embodiment, the result packing data operand has four result data elements, but other embodiments may have fewer or more result data elements. In some embodiments, each of the result data elements may have the value of an operation (OP) performed using at least one pair of data elements in the first source packing data operand 612 and non-corresponding data elements in the second source packing data operand 616. Each pair of non-corresponding data elements may be in a non-corresponding data element position in the first and second source packing data operands. For example, in the illustrated example embodiment, the first result data element may have values ​​of operations (OPs) performed on A1 and B4, the second result data element may have values ​​of operations (OPs) performed on A2 and B5, the third result data element may have values ​​of operations (OPs) performed on A3 and B6, and the fourth result data element may have values ​​of operations (OPs) performed on A4 and B7. This is merely an illustrative example. In other illustrative examples, the first offset may be one, three (e.g., the same as the second offset), four, ten, etc.

[0071] As before, in some embodiments, each pair of non-corresponding data elements may be located in non-corresponding data element positions within the first and second source packed data operands, where the non-corresponding positions differ based on the application of the first and second data element offsets. The non-corresponding data element positions may be such that the running unit operates to apply the first and second data element offsets, respectively, to the first and second source packed data operands to make the non-corresponding data elements correspond. For example, B4 may be offset or otherwise moved by three data element positions so that it corresponds to A1 (e.g., having the same relative data element position). The running unit may operate to perform any of various types of operations (OPs) on the aligned data elements as previously described. In some embodiments, the running unit may perform "vertical" SIMD computation operations only on corresponding data elements. In other embodiments, the running unit may perform combinations of vertical and non-vertical SIMD computation operations involving combinations of corresponding and non-corresponding data elements.

[0072] In some embodiments, the instructions disclosed herein can be used in image filtering in image processing, but the scope of the invention is not so limited. In filtering, it is very common to compute a resulting filtered pixel from a given input pixel and one or more pixels adjacent to that given input pixel. As an example, a given pixel in a row of pixels can be filtered using neighboring pixels on either side of that given pixel (e.g., using a normalized convolution 1, 2, 1 coefficient filter). Implementing filters in SIMD vector processors is traditionally accomplished by iteratively aligning data, each time followed by a SIMD operation. In imaging and vision, such filters are frequently used in two-dimensional (2D) forms of sizes such as 3x3, 5x5, and 7x7, which may involve nine, twenty-five, and forty-nine alignment operations, respectively, each potentially a separate packing data alignment instruction (unless the instructions disclosed herein are used). Especially when implemented in embedded digital signal processors or other typically resource-constrained environments, the cost of performing additional alignment operations in a cycle and / or the additional register space required to store intermediate results of alignment instructions can significantly impact overall efficiency.

[0073] In many of the embodiments described above, different sets of operations on one or more source packaged data are shown and described (e.g., Figure 1(Sets 112 and 116 in the original text). In some uses and implementations, the same data (e.g., a single set of one or more source packed data operands) can be used for operations. One way to achieve this is to specify the same register or other storage location for two sets of one or more source packed data operands. For example, an instruction may specify a pair of registers R1 and R2 for set 112 and may also specify registers R1 and R2 for set 116. Alternatively, a single set of one or more packed data operands (e.g., set 112) may be specified by an instruction (e.g., registers R1 and R2 may be specified) and it may be implicit or implied by an instruction (e.g., its opcode) to use a single set of source packed data operand 112 for the first and second sets of source packed data operands 112 and 116. Additional source specification fields (e.g., SRC2, SRC3) may be omitted from the instructions. In some embodiments, the data elements of all source operands may optionally all be pixels in the same row of pixels of the image. For example, in pixel filtering in image processing to average a pixel with its neighborhood (e.g., to achieve normalized convolution of pixels using filter coefficients 1, 2, 1), and in various other applications, it is often useful to offset different copies or replicas of the same set of source packed data operands multiple times with different offsets applied to each copy or replica (e.g., zero, one, and two data element offsets applied to three replicas in the case of normalized convolution of pixels using filter coefficients 1, 2, 1). Therefore, the alternative embodiments disclosed above can indicate only a single set (e.g., 112) of one or more source packed data operands and implicitly or inherently reuse copies or replicas of that indicated set (e.g., instead of explicit set 116).

[0074] Figure 7This is a block diagram of a detailed example embodiment of a processor 700 suitable for implementing embodiments of the present invention. The processor includes at least one core 780 capable of executing embodiments of packed data-aligned addition instructions. The core includes a branch prediction unit 781 for predicting branches in the program flow. The branch prediction unit is coupled to an instruction prefetch unit 782. The instruction prefetch unit may prefetch or otherwise receive instructions, including packed data-aligned addition instructions, from memory (e.g., via memory unit 790). A Level 1 (L1) instruction cache 783 is coupled to the instruction prefetch unit. The L1 instruction cache may cache or otherwise store instructions, including packed data-aligned addition instructions. The processor also includes an L1 data cache 791 for caching or otherwise storing data, including data elements and / or operands of instructions. The processor may also optionally include a Level 2 (L2) cache 792. The L2 cache may be dedicated to a core or shared by the core and one or more other optional cores (not shown). The L2 cache may store data and instructions, including packed data-aligned addition instructions. The instruction fetch unit 784 is coupled to the L1 instruction cache, the L2 cache, and the decoding unit 704. The instruction fetch unit can fetch or otherwise receive instructions containing packed data aligned and computed instructions (e.g., from the L1 instruction cache or the L2 cache), and can provide instructions to the decoding unit. The decoding unit can decode instructions containing packed data aligned and computed instructions, as described elsewhere herein.

[0075] The processor also includes one or more register file units 788. These register file units may contain various types of registers, such as packed data registers, general-purpose registers, status or flag registers, control or configuration registers, etc. In embodiments where the core optionally supports out-of-order (OOO) execution, the core may also optionally include a register renaming / allocator unit 785 coupled to the register file unit for allocating resources and performing register renaming on registers (e.g., packed data registers associated with packed data-aligned plus compute instructions). Furthermore, for OOO execution, the core may optionally include one or more scheduler units 786 coupled to a decoding unit, a renaming / allocator unit, and one or more execution units 706, 789. The scheduler unit can schedule one or more operations associated with decoded instructions, which include one or more operations decoded from packed data-aligned plus compute instructions, for execution on the execution units. The core may optionally have multiple different types of execution units, such as integer execution units, floating-point execution units, vector execution units, one or more memory access units 789, and the like. For OOO operation, the core may optionally include a quit or commit unit 787 coupled to the run unit, register file unit, and rename / allocator unit. The quit or commit unit can operate to quit or commit instructions.

[0076] It should be understood that this is merely an illustrative example of a suitable processor. In alternative embodiments, the processor may contain fewer or more components. Examples of other components that may be optionally included are one or more instruction and / or data translation back buffers (TLBs), one or more reordering buffers (ROBs), reservation stations, address generation units, debugging units, performance monitoring units, and power management units. Furthermore, the processor may optionally have multiple cores (e.g., at least two, at least four, at least eight, at least thirty, etc.). In some cases, all cores may have the same components as core 780 and support the same instruction set as core 780. Alternatively, at least some of the cores may have different components and / or may support different instruction sets.

[0077] Exemplary core architectures, processors, and computer architectures

[0078] Processor cores can be implemented in different ways for different purposes and in different processors. For example, such core implementations can include: 1) general-purpose ordered cores intended for general-purpose computing; 2) high-performance general-purpose out-of-order cores intended for general-purpose computing; and 3) dedicated cores primarily intended for graphics and / or scientific (throughput) computing. Different processor implementations can include: 1) CPUs containing one or more general-purpose ordered cores and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) coprocessors containing one or more dedicated cores primarily intended for graphics and / or scientific (throughput) computing. Such different processors result in different computer system architectures that can include: 1) coprocessors on a separate chip from the CPU; 2) coprocessors on a separate die in the same package as the CPU; 3) coprocessors on the same die as the CPU (in which case such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or dedicated cores); and 4) systems-on-a-chip that may contain the described CPU (sometimes referred to as dedicated cores or dedicated processors), the coprocessors described above, and additional functionality on the same die. The example core architecture is then described, followed by a description of exemplary processors and computer architectures.

[0079] Exemplary nuclear architecture

[0080] Ordered and disordered kernel diagrams

[0081] Figure 8A This is a block diagram illustrating an exemplary ordered pipeline and an exemplary register renaming, out-of-order output / run pipeline according to an embodiment of the present invention. Figure 8B This is a block diagram illustrating an exemplary embodiment of an ordered architecture core to be included in a processor according to an embodiment of the present invention, and an exemplary register renaming, out-of-order issuance / running architecture core. Figure 8A The dashed boxes in -B illustrate ordered pipelines and ordered cores, while the optional dashed boxes illustrate register renaming, out-of-order output / run pipelines, and cores. Given that the ordered aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0082] exist Figure 8A In the processor pipeline 800, there are fetch stage 802, length decoding stage 804, decoding stage 806, allocation stage 808, renaming stage 810, scheduling (also known as dispatch or issue) stage 812, register read / memory read stage 814, run stage 816, write-back / memory write stage 818, exception handling stage 822 and commit stage 824.

[0083] Figure 8BThe processor core 890 is shown, which includes a front-end unit 830 coupled to a runtime engine unit 850, and both are coupled to a memory unit 870. Core 890 can be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. Alternatively, core 890 can be a dedicated core, such as a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, or the like.

[0084] Front-end unit 830 includes branch prediction unit 832 coupled to instruction cache unit 834, which is coupled to instruction translation back buffer (TLB) 836, which is coupled to instruction fetch unit 838, which is coupled to decode unit 840. Decoding unit 840 (or decoder) can decode instructions and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as outputs, which are decoded from or otherwise reflect or derived from the original instructions. Decoding unit 840 can be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. In one embodiment, core 890 includes microcode ROM or other medium storing microcode for certain macro instructions (e.g., in decoding unit 840 or otherwise within front-end unit 830). Decoding unit 840 is coupled to rename / allocator unit 852 in execution engine unit 850.

[0085] The runtime engine unit 850 includes a rename / allocator unit 852, which is coupled to a set of retirement units 854 and one or more scheduler units 856. Scheduler units 856 represent any number of different schedulers, including reservation stations, central instruction windows, etc. Scheduler units 856 are coupled to physical register file units 858. Each physical register file unit 858 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating-point numbers, packed integers, packed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., instruction pointer, which is the address of the next instruction to be executed), etc. In one embodiment, physical register file unit 858 includes vector register units, write mask register units, and scalar register units. These register units can provide architectural vector registers, vector mask registers, and general-purpose registers. The physical register file unit 858, overlaid with the retirement unit 854, illustrates various methods for implementing register renaming and out-of-order execution (e.g., using a reorder buffer and a retirement register file; using a future heap, a history buffer, and a retirement register file; using register mapping and a register pool; etc.). The retirement unit 854 and the physical register file unit 858 are coupled to a run cluster 860. The run cluster 860 comprises a set of one or more run units 862 and a set of one or more memory access units 864. Run units 862 can perform various operations (e.g., shift, addition, subtraction, multiplication) on various types of data (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some embodiments may include many run units dedicated to a particular function or set of functions, other embodiments may include only one or more run units, all of which perform all functions. Because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / packed integer / packed floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each with its own scheduler unit, physical register file unit, and / or run cluster—and in the case of separate memory access pipelines, some embodiments are implemented where only the run cluster of that pipeline has memory access unit 864), scheduler unit 856, physical register file unit 858, and run cluster 860 are shown as possibly multiple. It should also be understood that, in the case of using separate pipelines, one or more of these pipelines may be issued / run out of order and the remainder are ordered.

[0086] A set of memory access units 864 is coupled to memory unit 870, which includes a data TLB unit 872 coupled to data cache unit 874, which is coupled to level 2 (L2) cache unit 876. In an exemplary embodiment, memory access unit 864 may include a load unit, a memory address unit, and a memory data unit, each of which is coupled to the data TLB unit 872 in memory unit 870. Instruction cache unit 834 is further coupled to level 2 (L2) cache unit 876 in memory unit 870. L2 cache unit 876 is coupled to one or more other cache levels and ultimately to main memory.

[0087] As an example, the exemplary register renaming out-of-order issue / run kernel architecture can implement pipeline 800 as follows: 1) Instruction fetch 838 executes fetch and length decoding stages 802 and 804; 2) Decoding unit 840 executes decoding stage 806; 3) Rename / allocator unit 852 executes allocation stage 808 and rename stage 810; 4) Scheduler unit 856 executes scheduling stage 812; 5) Physical register file unit 858 and memory unit 870 execute register read / memory read stage 814; run cluster 860 executes run stage 816; 6) Memory unit 870 and physical register file unit 858 execute write-back / memory write stage 818; 7) Various units may be involved in exception handling stage 822; and 8) Retirement unit 854 and physical register file unit 858 execute commit stage 824.

[0088] Core 890 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions); the MIPS instruction set of MIPS Technologies, Sunnyvale, California; the ARM instruction set of ARM Holdings, Sunnyvale, California (with optional additional extensions, such as NEON)) that contain the instructions described herein. In one embodiment, Core 890 includes logic supporting packaged data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packaged data.

[0089] It should be understood that a core can support multithreading (running two or more parallel operations or sets of threads) and can do so in a variety of ways, including time-sliced ​​multithreading, simultaneous multithreading (in the case of a single physical core providing logical cores for each thread, that physical core is multithreading simultaneously), or a combination thereof (e.g., time-sliced ​​fetch and decode followed by simultaneous multithreading, such as in Intel® Hyperthreading technology).

[0090] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can also be used in ordered architectures. While the illustrated embodiment of the processor also includes separate instruction and data cache units 834 / 874 and a shared L2 cache unit 876, alternative embodiments may have a single internal cache for both instructions and data, such as a level 1 (L1) internal cache, or a multi-level internal cache. In some embodiments, the system may include a combination of internal caches and external caches outside the core and / or processor. Alternatively, all caches may be outside the core and / or processor.

[0091] Specific exemplary ordered nuclear architecture

[0092] Figure 9A -B illustrates a more specific exemplary ordered core architecture block diagram, where the core will be one of several logic blocks in a chip (which contain other cores of the same type and / or different types). The logic blocks communicate via a high-bandwidth interconnect network (e.g., a ring network) with some fixed-function logic, memory I / O interfaces, and other necessary I / O logic, depending on the application.

[0093] Figure 9A This is a block diagram of a single processor core according to an embodiment of the invention, along with its connection to the on-die interconnect network 902 and a local subset of its Level 2 (L2) cache 904. In one embodiment, the instruction decoder 900 supports the x86 instruction set with Packed Data Instruction Set Extensions. The L1 cache 906 allows low-latency access to the cache memory into the scalar and vector units. Although in one embodiment (for design simplification), the scalar unit 908 and the vector unit 910 use separate register sets (scalar register 912 and vector register 914, respectively) and data transferred between them is written to memory and then read back from the Level 1 (L1) cache 906, alternative embodiments of the invention may use different methods (e.g., using a single register set or including a communication path that allows data to be transferred between two register sets without being written back and read back).

[0094] The local subset of L2 cache 904 is part of the global L2 cache, divided into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset of L2 cache 904. Data read by a processor core is stored in its L2 cache subset 904 and can be accessed quickly in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 904 and flushed from other subsets if necessary. A ring network ensures consistency for shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logical blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide in each direction.

[0095] Figure 9B This is an embodiment of the present invention. Figure 9A An expanded diagram of the processor core. Figure 9B The document includes the L1 data cache 906A portion containing L1 cache 904, and further details regarding vector unit 910 and vector register 914. Specifically, vector unit 910 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 928), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports mixed register input using swizzle unit 920, numerical conversion using value conversion units 922A-B, and copying on memory input using copy unit 924. Write mask register 926 allows predicating vector writes.

[0096] Processor with integrated memory controller and graphics

[0097] Figure 10 This is a block diagram of a processor 1000 that, according to an embodiment, may have more than one core, may have an integrated memory controller, and may have integrated graphics. Figure 10 The solid-line box diagram illustrates processor 1000, which has a single core 1002A, a system agent 1010, and a set of one or more bus controller units 1016, while the dashed-line box diagram illustrates alternative processor 1000, which has multiple cores 1002A-N, a set of one or more integrated memory controller units 1014 among the system agent units 1010, and special-purpose logic 1008.

[0098] Therefore, different implementations of processor 1000 can include: 1) a CPU, where dedicated logic 1008 is integrated graphics and / or scientific (throughput) logic (which may contain one or more cores), and cores 1002A-N are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, where cores 1002A-N are a large number of dedicated cores primarily intended for graphics and / or scientific (throughput); and 3) a coprocessor, where cores 1002A-N are a large number of general-purpose ordered cores. Thus, processor 1000 can be a general-purpose processor, coprocessor, or dedicated processor, such as a network or communication processor, compression engine, graphics processor, GPGPU (General-Purpose Graphics Processing Unit), a high-throughput multi-core (MIC) coprocessor (containing 30 or more cores), an embedded processor, or the like. The processor can be implemented on one or more chips. Processor 1000 can be part of one or more substrates and / or can be implemented using any of many process technologies (e.g., BiCMOS, CMOS, or NMOS) on one or more substrates.

[0099] The memory hierarchy includes one or more levels of cache within the core, a set of one or more shared cache units 1006, and external memory (not shown) coupled to a set of integrated memory controller units 1014. The set of shared cache units 1006 may contain one or more intermediate-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, the last-level cache (LLC), and / or combinations thereof. Although in one embodiment, ring-based interconnect units 1012 interconnect integrated graphics logic 1008, the set of shared cache units 1006, and system agent units 1010 / integrated memory controller units 1014, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, consistency between one or more cache units 1006 and cores 1002-AN is maintained.

[0100] In some embodiments, one or more of the cores 1002A-N are multithreaded. System agent 1010 includes those components that coordinate and operate the cores 1002A-N. System agent unit 1010 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or include the logic and components required for regulating the power states of the cores 1002A-N and the integrated graphics logic 1008. The display unit is used to drive one or more externally connected displays.

[0101] From the perspective of the instruction set architecture, the 1002A-N cores can be homogeneous or heterogeneous; that is, two or more cores in the 1002A-N cores can run the same instruction set, while others can run only a subset of that instruction set or a different instruction set.

[0102] Exemplary computer architecture

[0103] Figure 11-15 This is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktop computers, handheld PCs, personal digital assistants, engineered workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, many types of systems or electronic devices capable of incorporating processors and / or other operating logic as disclosed herein are generally suitable.

[0104] Now for reference Figure 11 The diagram illustrates a block diagram of a system 1100 according to an embodiment of the present invention. The system 1100 may include one or more processors 1110, 1115 coupled to a controller hub 1120. In one embodiment, the controller hub 1120 includes a graphics memory controller hub (GMCH) 1190 and an input / output hub (IOH) 1150 (which may be on a separate chip); the GMCH 1190 includes memory and a graphics controller, to which a memory 1140 and a coprocessor 1145 are coupled; the IOH 1150 couples an input / output (I / O) device 1160 to the GMCH 1190. Alternatively, one or both of the memory and the graphics controller are integrated within the processor (as described herein), with the memory 1140 and the coprocessor 1145 directly coupled to the processor 1110 and the controller hub 1120 on a single chip having the IOH 1150.

[0105] The optional nature of the additional processor 1115 is in Figure 11 The text uses broken lines for indication. Each processor 1110, 1115 may contain one or more of the processing cores described herein and may be a version of processor 1000.

[0106] The memory 1140 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of both. In at least one embodiment, the controller hub 1120 communicates with the processors 1110, 1115 via a multipoint bus (e.g., front-side bus (FSB)), a point-to-point interface (e.g., fast path interconnect (QPI)), or a similar connection 1195.

[0107] In one embodiment, the coprocessor 1145 is a general-purpose processor, such as a high-throughput MIC processor, network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, the controller hub 1120 may include an integrated graphics accelerator.

[0108] In terms of the spectrum of advantages (which include architecture, microarchitecture, thermal, power consumption characteristics and the like), various differences can exist between physical resources 1110 and 1115.

[0109] In one embodiment, processor 1110 executes instructions that control general-type data processing operations. Coprocessor instructions may be embedded within instructions. Processor 1110 identifies these coprocessor instructions as types that should be executed by the attached coprocessor 1145. Therefore, processor 1110 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 1145 on the coprocessor bus or other interconnect. Coprocessor 1145 receives and executes the received coprocessor instructions.

[0110] Now for reference Figure 12 The diagram shown is a block diagram of a first more specific exemplary system 1200 according to an embodiment of the present invention. (See also...) Figure 12 As shown, the multiprocessor system 1200 is a point-to-point interconnect system and includes a first processor 1270 and a second processor 1280 coupled via a point-to-point interconnect 1250. Each of processors 1270 and 1280 may be a version of processor 1000. In one embodiment of the invention, processors 1270 and 1280 are processors 1110 and 1115, respectively, and coprocessor 1238 is coprocessor 1145. In another embodiment, processors 1270 and 1280 are processor 1110 and coprocessor 1145, respectively.

[0111] Processors 1270 and 1280 are shown, each including an integrated memory controller (IMC) unit 1272 and 1282, respectively. Processor 1270 also includes point-to-point (PP) interfaces 1276 and 1278 as part of its bus controller unit; similarly, a second processor 1280 includes PP interfaces 1286 and 1288. Processors 1270 and 1280 can exchange information via point-to-point (PP) interface 1250 using PP interface circuits 1278 and 1288. Figure 12 As shown, IMC 1272 and 1282 couple the processor to the corresponding memory, namely memory 1232 and memory 1234, which may be portions of the main memory locally attached to the corresponding processor.

[0112] Processors 1270 and 1280 can each exchange information with chipset 1290 via individual PP interfaces 1252 and 1254 using point-to-point interface circuits 1276, 1294, 1286, and 1298. Chipset 1290 may optionally exchange information with coprocessor 1238 via high-performance interface 1239. In one embodiment, coprocessor 1238 is a dedicated processor, such as a high-throughput MIC processor, network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

[0113] A shared cache (not shown) may be contained in either processor or outside of both processors, but connected to the processors via a PP interconnect, such that if the processors are placed in a low-power mode, the local cache information of either or both processors can be stored in the shared cache.

[0114] Chipset 1290 may be coupled to first bus 1216 via interface 1296. In one embodiment, first bus 1216 may be a peripheral component interconnect (PCI) bus, or a bus such as a PCI Express bus or another third-generation I / O interconnect bus, but the scope of the invention is not so limited.

[0115] As in Figure 12 As shown, various I / O devices 1214, along with a bus bridge 1218, can be coupled to a first bus 1216, which in turn couples the first bus 1216 to a second bus 1220. In one embodiment, one or more additional processors 1215, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (e.g., a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array, or any other processor, are coupled to the first bus 1216. In one embodiment, the second bus 1220 may be a low pin count (LPC) bus. Various devices can be coupled to the second bus 1220, including, for example, a keyboard and / or mouse 1222, a communication device 1227, and a storage unit 1228, such as a disk drive or other mass storage device, which in one embodiment may contain instruction / code and data 1230. Furthermore, audio I / O 1224 can be coupled to the second bus 1220. Note that other architectures are possible. For example, instead of… Figure 12 The point-to-point architecture allows the system to implement multi-point bus or other similar architectures.

[0116] Now for reference Figure 13 The diagram shown is a block diagram of a second, more specific, exemplary system 1300 according to an embodiment of the present invention. Figure 12 and Figure 13 Similar elements in the model have similar reference numerals, and Figure 12 Some aspects have already been from Figure 13 Omitted to avoid confusion Figure 13 Other aspects.

[0117] Figure 13 The processors 1270 and 1280 illustrated may include integrated memory and I / O control logic (“CL”) 1272 and 1282, respectively. Therefore, CL 1272 and 1282 include an integrated memory controller unit and I / O control logic. Figure 13 The diagram shows that not only are memories 1232 and 1234 coupled to CLs 1272 and 1282, but I / O device 1314 is also coupled to control logic 1272 and 1282. Legacy I / O device 1315 is coupled to chipset 1290.

[0118] Now for reference Figure 14 The diagram shown is a block diagram of a SoC 1400 according to an embodiment of the present invention. Figure 10 Similar components in the model have similar reference figures. Furthermore, the dashed box is an optional feature on more advanced SoCs. Figure 14 In this embodiment, interconnect unit 1402 is coupled to: application processor 1410, which includes a shared cache unit 1006 and a set of one or more cores 132A-N; system agent unit 1010; bus controller unit 1016; integrated memory controller unit 1014; a set of one or more coprocessors 1420, which may include integrated graphics logic, image processor, audio processor, and video processor; static random access memory (SRAM) unit 1430; direct memory access (DMA) unit 1432; and display unit 1440 for coupling to one or more external displays. In one embodiment, coprocessor 1420 includes a dedicated processor, such as a network or communication processor, compression engine, GPGPU, high-throughput MIC processor, embedded processor, or the like.

[0119] Embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention can be implemented as computer programs or program code running on programmable systems, including at least one processor, a storage system (containing volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0120] Program code (e.g. in) Figure 12The code 1230 shown in the diagram can be applied to input instructions to perform the functions described herein and generate output information. This output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes, for example, any system having a processor; a digital signal processor (DSP); a microcontroller; an application-specific integrated circuit (ASIC); or a microprocessor.

[0121] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code can also be implemented in assembly or machine language. In fact, the mechanisms described in this article are not limited to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0122] One or more aspects of at least one embodiment can be implemented by representative instructions stored on a machine-readable medium representing various logic within a processor, which, when read by a machine, causes the machine to manufacture the logic to perform the techniques described herein. Such a representation (referred to as an "IP core") can be stored on a tangible machine-readable medium and supplied to various customers or manufacturing facilities for loading onto the manufacturing machine that actually manufactures the logic or processor.

[0123] Such machine-readable storage media may include, but is not limited to, non-transitory tangible arrangements of articles made or formed by a machine or device, including storage media such as hard disks, any other type of disk (including floppy disks, optical disks, CD-ROMs, CD-RWs, and magneto-optical disks), such as read-only memory (ROM), random access memory (RAM) (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase-change memory (PCM), semiconductor devices of magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

[0124] Therefore, embodiments of the present invention also include non-transitory tangible machine-readable media containing instructions or design data, such as a hardware description language (HDL), that defines the structures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

[0125] Simulation (including binary translation, code transformation, etc.)

[0126] In some cases, an instruction translator can be used to translate instructions from a source instruction set into a target instruction set. For example, an instruction translator can translate (e.g., using static binary translation, dynamic binary translation, which includes dynamic compilation), transform, emulate, or otherwise translate instructions into one or more other instructions to be processed by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on-processor, off-processor, or partially on-processor and partially off-processor.

[0127] Figure 15 This is a block diagram contrasting the use of a software instruction converter according to an embodiment of the present invention with the conversion of binary instructions in a source instruction set into binary instructions in a target instruction set. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 15 A program employing a high-level language 1502 is shown to be compiled using an x86 compiler 1504 to generate x86 binary code 1506, which can be natively executed by a processor having at least one x86 instruction set core 1516. A processor having at least one x86 instruction set core 1516 represents any processor capable of performing substantially the same functions as an Intel processor having at least one x86 instruction set core in order to achieve substantially the same results as an Intel processor having at least one x86 instruction set core by: compatibly running or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) a version of object code for an application or other software intended to run on an Intel processor having at least one x86 instruction set core. The x86 compiler 1504 represents a compiler operable to generate x86 binary code 1506 (e.g., object code) capable of running on a processor having at least one x86 instruction set core 1516 with or without additional linking processing. Similarly, Figure 15A program using high-level language 1502 is shown to be compiled using alternative instruction set compiler 1508 to generate alternative instruction set binary code 1510, which can be natively executed by a processor without at least one x86 instruction set core 1514 (e.g., a processor with a core running the MIPS instruction set of MIPS Technologies, Sunnyvale, California, and / or the ARM instruction set of ARM Holdings, Sunnyvale, California). Instruction converter 1512 is used to translate x86 binary code 1506 into code that can be natively executed by a processor without an x86 instruction set core 1514. This translated code is unlikely to be identical to the alternative instruction set binary code 1510 because an instruction converter with this capability is difficult to manufacture; however, the translated code will perform general operations and consists of instructions from the alternative instruction set. Thus, instruction converter 1512 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without an x86 instruction set processor or core to run x86 binary code 1506 through emulation, simulation, or any other process.

[0128] right Figure 3-7 Any components, features, and details described may also be optionally applied. Figure 1-2 Any of the components, features, and details described herein may also be optionally applied to any of the methods, which in embodiments may be performed by and / or utilizing such a device. Any of the processors described herein may be included in the computer systems disclosed herein (e.g., Figure 11-14 Any of the following. In some embodiments, the computer system may include dynamic random access memory (DRAM). Alternatively, the computer system may include flash memory or a class of non-volatile memory that does not require refreshing. The instructions disclosed herein can be executed on any of the processors shown herein (having any of the microarchitectures shown herein) or on any of the systems shown herein.

[0129] In the description and claims, the terms “coupled” and / or “connected” may be used together with their derivatives. These terms are not intended to be synonyms for each other. Rather, in embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” can mean that two or more elements are in direct physical or electrical contact with each other. However, “coupled” can also mean that two or more elements are not in direct contact with each other, but still operate or interact with each other. For example, a running unit may be coupled to a register and / or a decoding unit through one or more intervening components. In the figures, arrows are used to illustrate connections and couplings.

[0130] The term “and / or” may be used. As used herein, the term “and / or” means one or the other or both (e.g., A and / or B means A or B or both A and B).

[0131] In the foregoing description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. However, other embodiments may be practiced without some of these specific details. The scope of the invention is defined not by the specific examples provided above but solely by the claims below. In other instances, well-known circuits, structures, devices, and operations are shown in block diagram form or not in detail to avoid obscuring the understanding of the description. Where deemed appropriate, reference numerals or the ends of reference numerals are repeated in the figures to indicate corresponding or similar elements, which may optionally have similar or identical characteristics, unless otherwise specified or obvious.

[0132] Certain operations may be performed by hardware components or may be embodied in machine-operable or circuit-operable instructions, which can be used to cause and / or result in a machine, circuit, or hardware component (e.g., a processor, a portion of a processor, circuitry, etc.) programmed with the instructions to perform the operation. Operations may also optionally be performed by a combination of hardware and software. The processor, machine, circuit, or hardware may contain a specific or particular circuit system or other logic (e.g., hardware potentially combined with firmware and / or software) that operates to execute and / or process instructions and store results in response to those instructions.

[0133] Some embodiments involve manufacturing articles (e.g., computer program products) that include machine-readable media. The media may contain mechanisms employing information provided in a machine-readable form (e.g., stored). The machine-readable media may provide or have instructions or sequences of instructions stored thereon that, if executed by a machine and / or operated by a machine, cause the machine to perform and / or cause the machine to perform one or more operations, methods, or techniques disclosed herein.

[0134] In some embodiments, a machine-readable medium may comprise a non-transitory machine-readable storage medium. For example, a non-transitory machine-readable storage medium may comprise a floppy disk, optical storage medium, optical disk, optical data storage device, CD-ROM, magnetic disk, magneto-optical disk, read-only memory (ROM), programmable ROM (PROM), erasable and programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), flash memory, phase-change memory, phase-change data storage material, non-volatile memory, non-volatile data storage device, non-transitory memory, non-transitory data storage device, or the like. A non-transitory machine-readable storage medium does not consist of transient propagating signals. In some embodiments, the storage medium may comprise a tangible medium containing a solid material.

[0135] Examples of suitable machines include, but are not limited to, general-purpose processors, special-purpose processors, digital logic circuits, integrated circuits, or the like. Other examples of suitable machines include computer systems or other electronic devices that include processors, digital logic circuits, or integrated circuits. Examples of such computer systems or electronic devices include, but are not limited to, desktop computers, portable computers, notebook computers, tablet computers, netbooks, smartphones, cellular phones, servers, network devices (e.g., routers and switches), mobile internet devices (MIDs), media players, smart TVs, internet access devices, set-top boxes, and video game controllers.

[0136] Throughout this specification, references such as "one embodiment," "embodiment," "one or more embodiments," and "some embodiments" indicate that specific features may be included in the practice of the invention but are not necessarily required to be. Similarly, in the description, to streamline this disclosure and facilitate understanding of the various inventive aspects, various features are sometimes combined in a single embodiment, figure, or description thereof. However, this disclosed approach is not to be construed as reflecting an intention that the invention requires more features than specifically recited in each claim. Rather, as reflected in the following claims, the inventive aspect lies in having fewer features than all of a single disclosed embodiment. Thus, the claims following the detailed description are specifically combined with this detailed description, wherein each claim relies on itself as a separate embodiment of the invention.

[0137] Example Implementation

[0138] The following example is an alternative embodiment. The details in this example may be used anywhere in one or more embodiments.

[0139] Example 1 is a processor or other device that includes a decoding unit for decoding a packed data alignment and addition instruction. The packed data alignment and addition unit indicates a first set of one or more source packed data operands, a second set of one or more source packed data operands, an offset of at least one data element, and a destination storage location. The first set contains a first plurality of data elements, and the second set contains a second plurality of data elements. The device also includes an execution unit coupled to the decoding unit. The execution unit, in response to the packed data alignment and addition instruction, stores a resulting packed data operand in the destination storage location. The resulting packed data operand contains a plurality of resulting data elements, each having a value representing an operation performed using data elements from a pair of source packed data operands in the first and second sets. The execution unit applies at least one data element offset to at least one corresponding data element in each of the first and second sets of source packed data operands. The at least one data element offset cancels out any lack of correspondence between each pair of data elements in the first and second sets of source packed data operands.

[0140] Example 2 includes the processor of Example 1, wherein the decoding unit decodes an instruction that indicates a single data element offset corresponding only to a second set of one or more source-packed data operands. Optionally, each pair of data elements has a corresponding deficiency to be offset by at least one data element offset.

[0141] Example 3 includes the processor of Example 1, wherein the decoding unit is to decode an instruction that indicates a first data element offset corresponding to a first set of one or more source packed data operands and a second data element offset corresponding to a second set of one or more source packed data operands.

[0142] Example 4 includes the processor of Example 3, wherein each pair of data elements has a corresponding deficiency that is to be offset by applying a first data element offset to a first set of one or more source packed data operands and applying a second data element offset to a second set of one or more source packed data operands.

[0143] Example 5 includes the processor of Example 1, wherein the decoding unit is to decode an instruction that indicates a first set of source packed data operands that includes a first source packed data operand and a second source packed data operand, and a second set of source packed data operands that includes a third source packed data operand and a fourth source packed data operand.

[0144] Example 6 includes the processor of Example 1, wherein the decoding unit is to decode an instruction that indicates a first set of one or more source-packed data operands to contain only a single first source-packed data operand and a second set of source-packed data operands to contain a second source-packed data operand and a third source-packed data operand.

[0145] Example 7 includes the processor of Example 6, wherein the resulting packaged data operand may optionally contain the same number of data elements as each of the first source packaged data operand and the second source packaged data operand.

[0146] Example 8 includes the processor of Example 1, wherein the decoding unit is to decode an instruction that indicates a first set of one or more source-packed data operands containing only a single first source-packed data operand and a second set of one or more source-packed data operands containing only a single second source-packed data operand, and wherein the execution unit is to store a result-packed data operand that optionally has fewer data elements compared to the second source-packed data operand.

[0147] Example 9 includes a processor of any of Examples 1 to 8, wherein the decoding unit is to decode an instruction that indicates a data element offset capable of having at least one data element offset of any of a plurality of different data element offset values.

[0148] Example 10 includes a processor of any one of Examples 1 to 8, wherein the decoding unit is to decode an instruction that indicates a data element offset having the capability of at least one data element offset having: (1) an offset in the direction toward the least significant bit position of any one of at least and two data element positions; (2) an offset of the zero data element position; and (3) an offset in the direction toward the most significant bit position of any one of at least and two data element positions.

[0149] Example 11 includes a processor of any one of Examples 1 to 8, wherein the decoding unit is to decode an instruction that indicates a data element offset having the capability of at least one data element offset having any of the following capabilities: (1) an offset in the direction toward the least significant bit position of any one of at least one, two, three, and four data element positions; (2) an offset of the zero data element position; and (3) an offset in the direction toward the most significant bit position of any one of at least one, two, three, and four data element positions.

[0150] Example 12 includes a processor of any one of Examples 1 to 8, wherein the execution unit, in response to an instruction, is to store a result-packed data operand, which shall have result data elements, each having a value of an operation performed using the pair of data elements, wherein the operation may optionally be one of addition, subtraction, multiplication, division, and averaging.

[0151] Example 13 includes a processor of any of Examples 1 through 8, wherein the execution unit performs vertical single instruction multiple data (SIMD) operations on each pair of data elements in response to the decoding of instructions.

[0152] Example 14 includes a processor of any of Examples 1 to 8, wherein the decoding unit is to decode an instruction, which optionally has an immediate value indicating the offset of at least one data element.

[0153] Example 15 includes a processor of any one of Examples 1 to 8, wherein the decoding unit is to decode an instruction that optionally instructs a scalar register to store a value that indicates a data element offset of at least one data element offset.

[0154] Example 16 includes a processor from any of Examples 1 to 8, and further includes an image processor unit with a digital signal processor having an operating unit.

[0155] Example 17 includes a processor of any of Examples 1 through 8, further including an optional branch prediction unit for predicting branches. The processor may also include an optional instruction prefetch unit coupled to the branch prediction unit to prefetch instructions containing packed data-aligned addition instructions. The processor may also include an optional Level 1 (L1) instruction cache coupled to the instruction prefetch unit to store instructions. The processor may also include an optional L1 data cache for storing data. The processor may also include an optional Level 2 (L2) cache for storing both data and instructions. The processor may also include an instruction fetch unit coupled to a decode unit, the L1 instruction cache, and the L2 cache to fetch packed data-aligned addition instructions from one of the L1 and L2 caches and provide the packed data-aligned addition instructions to the decode unit. The processor may also include an optional register renaming unit for renaming registers. The processor may also include an optional scheduler for scheduling one or more operations decoded from packed data-aligned addition instructions for execution. The processor may also include an optional commit unit, which is used to commit the results of the execution of the packing data alignment and calculation instructions.

[0156] Example 18 is a method in a processor that includes receiving a packed data alignment plus calculation instruction. The packed data alignment plus calculation instruction may indicate a first set of one or more source packed data operands containing a first plurality of data elements, a second set of one or more source packed data operands containing a second plurality of data elements, an offset of at least one data element, and a destination storage location. The method further includes storing a resulting packed data operand in the destination storage location in response to the packed data alignment plus calculation instruction. The resulting packed data operand contains a plurality of resulting data elements, each having a value obtained by performing an operation using a pair of data elements from the first set of source packed data operands and data elements from the second set of source packed data operands. Each pair of data elements is located at a non-corresponding data element position in the first and second sets of source packed data operands. The non-corresponding data element position is different based on the offset of at least one data element indicated by the packed data alignment plus calculation instruction.

[0157] Example 19 includes the method of Example 18, wherein receiving includes receiving an instruction indicating an offset of only a single data element, and wherein the positions of non-corresponding data elements differ from that single data element offset.

[0158] Example 20 includes the method of Example 18, wherein the receive includes a receive instruction indicating a first data element offset corresponding to a first set of one or more source packed data operands, and a second data element offset corresponding to a second set of one or more source packed data operands. Non-corresponding data element positions may optionally differ between the first and second data element offsets.

[0159] Example 21 includes the method of Example 18, wherein the receive includes a receive instruction that indicates both a first source packaged data operand and a second source packaged data operand of a first set of source packaged data operands, and indicates both a third source packaged data operand and a fourth source packaged data operand of a second set of source packaged data operands.

[0160] Example 22 includes the method of Example 18, wherein the receive includes a receive instruction indicating a data element offset, which can be any of a plurality of different data element offset values.

[0161] Example 23 includes a method of any of Examples 18 to 22, wherein the storage includes storage result data elements, each having a value of an operation performed using the pair of data elements, wherein the operation may optionally be one of addition, subtraction, multiplication, division, and averaging.

[0162] Example 24 includes the method of any of Examples 18 to 22, and further includes performing an operation as a vertical single instruction multiple data (SIMD) operation using the pair of data elements.

[0163] Example 25 includes the method of any of Examples 18 to 22, which is executed using a digital signal processor during pixel filtering during image processing.

[0164] Example 26 is a system for processing instructions, comprising an interconnect and a processor coupled to the interconnect. The processor receives a packing data alignment plus computation instruction that indicates a first set of one or more source packing data operands, a second set of one or more source packing data operands, an offset of at least one data element, and a destination storage location. The first set contains a first plurality of data elements, and the second set contains a second plurality of data elements. In response to the instruction, the processor stores a resulting packing data operand in the destination storage location. The resulting packing data operand contains a plurality of resulting data elements, each having a value from an operation performed using data elements from a pair of source packing data operands in the first and second sets. The processor applies at least one data element offset to at least one corresponding data element in each of the first and second sets of source packing data elements. The at least one data element offset cancels out any lack of correspondence between pairs of data elements in each of the first and second sets of source packing data operands. The system also includes dynamic random access memory (DRAM) coupled to the interconnect. The DRAM stores an instruction set to perform a pixel filtering algorithm. When executed by the processor, the instruction set causes the processor to execute multiple instances of the packing data alignment plus computation instruction, each with a different offset.

[0165] Example 27 includes the system of Example 26, wherein the instruction indicates a first data element offset, which can be any of a plurality of distinct values. Each pair of data elements may optionally be in non-corresponding data element positions in the first and second sets of the source operands.

[0166] Example 28 is a manufactured article comprising a non-transitory machine-readable storage medium storing packing data alignment and calculation instructions. The instructions indicate a first set of one or more source packing data operands, a second set of one or more source packing data operands, an offset of at least one data element, and a destination storage location. The first set contains a first plurality of data elements, and the second set contains a second plurality of data elements. If executed by a machine, the instructions cause the machine to perform an operation comprising storing a resulting packing data operand in the destination storage location. The resulting packing data operand contains a plurality of resulting data elements, each having a value obtained by performing an operation using a pair of data elements from the first set of source packing data operands and data elements from the second set of source packing data operands. Each pair of data elements is located at a non-corresponding data element position in the first and second sets of source packing data operands. The non-corresponding data element position is different based on the offset of at least one data element indicated by the packing data alignment and calculation instructions.

[0167] Example 29 contains the manufactured article of Example 28, wherein the instructions are to indicate a data element offset having the capability of at least one data element offset having any of the following: (1) an offset in the direction toward the least significant bit position of any of at least one and two data element positions; (2) an offset of the zero data element position; and (3) an offset in the direction toward the most significant bit position of any of at least one and two data element positions.

[0168] Example 30 includes a processor or other device comprising a decoding unit for decoding a packed data alignment and addition instruction. The packed data alignment and addition instruction indicates a first set of one or more source packed data operands, a second set of one or more source packed data operands, an offset of at least one data element, and a destination storage location. The first set contains a first plurality of data elements, and the second set contains a second plurality of data elements. The processor also includes a running unit coupled to the decoding unit. The running unit, in response to the packed data alignment and addition instruction, stores a resulting packed data operand in the destination storage location. The resulting packed data operand contains a plurality of resulting data elements, each having a value from an operation performed using a pair of data elements from the first set of source packed data operands and non-corresponding data elements from the second set of source packed data operands. Each pair of non-corresponding data elements is located at a non-corresponding data element position in the first and second sets of source packed data operands. The non-corresponding data element position is different based on the offset of at least one data element indicated by the packed data alignment and addition instruction.

[0169] Example 31 is a processor or other device that performs or operates on a method to perform any of Examples 18 to 25.

[0170] Example 32 is a processor or other device that includes components for performing the methods of any one of Examples 18 to 25.

[0171] Example 33 is a manufactured article comprising an optional non-transitory machine-readable medium that optionally stores or otherwise provides instructions which, if executed by a processor, computer system, electronic device or other machine and / or, when executed by a processor, computer system, electronic device or other machine, cause a machine to perform any of the methods in Examples 18 to 25.

[0172] Example 34 is a processor or other device that is roughly as described herein.

[0173] Example 35 is a processor or other device that operates to perform any of the methods described herein.

[0174] Example 36 is a processor or other device that executes (e.g., has components to execute or operations to execute) any packaged data alignment plus computation instructions as described herein.

[0175] Example 37 is a computer system or other electronic device that includes a processor having a decoding unit to decode instructions of a first instruction set. The processor also has one or more execution units. The electronic device further includes a storage device coupled to the processor. The storage device stores the first instruction, which may be any of the packed data-aligned plus computation instructions disclosed herein and belongs to a second instruction set. The storage device also stores instructions to translate the first instruction into one or more instructions of the first instruction set. The one or more instructions of the instruction set, when executed by the processor, cause the processor to have architectural effects as specified by the first instruction.

Claims

1. A processor comprising: a decode unit to decode a packed data aligned add compute instruction, the packed data aligned add compute instruction to indicate a first source packed data operand, to indicate a second source packed data operand, and to indicate a destination operand, the first source packed data operand to contain a first plurality of data elements, the second source packed data operand to contain a second plurality of data elements, the destination operand to contain a plurality of result data elements, the packed data aligned add compute instruction to contain an immediate field to indicate a data element offset value; and an execution unit coupled with the decode unit, the execution unit, in response to the packed data aligned add compute instruction, to store a result packed data operand in a destination storage location, the result packed data operand to contain a plurality of result data elements each to have a value corresponding to an operation performed with a pair of a data element of the first plurality of data elements and a data element of the second plurality of data elements, the execution unit to include: an alignment unit to select, based on the data element offset value, the data element of the second plurality of data elements to pair with the data element of the first plurality of data elements to perform the operation to produce a corresponding result data element.

2. The processor of claim 1, wherein, the operation performed for at least some of the pairs of data elements of the first plurality of data elements and the second plurality of data elements comprises a non- vertical single instruction multiple data (SIMD) operation.

3. The processor of claim 2, wherein, the operation performed for one or more of the pairs of data elements of the first plurality of data elements and the second plurality of data elements comprises a vertical SIMD operation.

4. The processor of claim 2 or 3, wherein, the SIMD operation comprises a multiply-accumulate or dot-product operation.

5. The processor of any one of claims 1 to 3, wherein, the second plurality of data elements are to be stored in a register coupled with the execution unit.

6. The processor of claim 5, further comprising: a blending unit to blend the register input to the execution unit.

7. The processor of any one of claims 1 to 3, wherein, a size of data elements in the first plurality of data elements and the second plurality of data elements is 16 bits, 32 bits, or 64 bits.

8. The processor of any one of claims 1 to 3, wherein, the data elements in each pair are to have a corresponding deficiency to be offset by selecting one or more data elements of the second plurality of data elements to pair with one or more data elements of the first plurality of data elements.

9. The processor of claim 8, wherein, the corresponding deficiency comprises a different relative data element position.

10. The processor of any one of claims 1 to 3, wherein, the packed data aligned add compute instruction to indicate a second data element offset value to be applied to data elements of the first plurality of data elements.

11. The processor of any one of claims 1 to 3, wherein, the result packed data operand to contain a same number of data elements as each of the first source packed data operand and the second source packed data operand.

12. The processor of any one of claims 1 to 3, wherein, the decode unit and execution unit are components of a core of a plurality of cores, the processor further comprising: a shared cache shared by the plurality of cores; a scheduler to schedule instructions for execution on cores of the plurality of cores; and a memory interface to couple the plurality of cores to a memory.

13. The processor of claim 1, wherein, The alignment unit includes a multiplexer to select the data elements of the second plurality of data elements to pair with the data elements of the first plurality of data elements based on the data element offset values.

14. A processor (100) comprising: a decode unit (104) to decode a packed data alignment plus compute instruction (102) that specifies or implicitly indicates, in one or more fields of the instruction, a first set (112) of one or more source packed data operands, a second set (116) of one or more source packed data operands, a first data element offset (122, 322-1) to be applied to the first set (112) of one or more source packed data operands, a second data element offset (122, 322-2) to be applied to the second set (116) of one or more source packed data operands, and a destination storage location (118), the first set to include a first plurality of data elements, the second set to include a second plurality of data elements; and an execution unit (106), coupled with the decode unit (104), the execution unit (106) to, responsive to the packed data alignment plus compute instruction (102): perform a packed data alignment operation to align the first plurality of data elements with the second plurality of data elements using the first and second data element offsets (122, 322-1; 122, 322-2) by offsetting each data element of the first plurality of data elements by the first data element offset (122, 322-1) and offsetting each data element of the second plurality of data elements by the second data element offset (122, 322-2); perform a compute operation on the aligned first and second plurality of data elements; and store a result packed data operand (120) in the destination storage location (118), the result packed data operand (120) to include a plurality of result data elements each to have a value of the compute operation performed with a pair of aligned data elements, the pair of aligned data elements corresponding to a data element of the first set (112) of source packed data operands and a data element of the second set (116) of source packed data operands.

15. The processor (100) of claim 14, wherein, The decode unit (104) to decode the instruction (102) that specifies or indicates the first set (112) of source packed data operands and the second set (116) of source packed data operands, the first set to include a first source packed data operand and a second source packed data operand, the second set to include a third source packed data operand and a fourth source packed data operand.

16. The processor (100) of claim 14, wherein, The decode unit (104) is to decode the instruction (102) that specifies or indicates the first set (112) of one or more source packed data operands to include only a single first source packed data operand and the second set (116) of one or more source packed data operands.

17. The processor (100) of claim 14, wherein, The decode unit (104) is to decode the instruction (102) that specifies or indicates the first set (112) of one or more source packed data operands to include only a single first source packed data operand and the second set (116) of one or more source packed data operands to include only a single second source packed data operand, and wherein the execution unit (106) is to store the result packed data operand (120) to have fewer data elements than the second source packed data operand.

18. The processor (100) according to any one of claims 14 to 17, wherein The decode unit (104) is to decode the instruction (102) that specifies or indicates the first data element offset and the second data element offset, each of the first data element offset and the second data element offset can be any of: an offset in a direction toward a least significant bit position of either one of at least one and two data element positions; an offset of zero data element positions; and an offset in a direction toward a most significant bit position of either one of at least one and two data element positions. The execution unit (106) is to store, responsive to the instruction (102), the result packed data operand (120) to have the result data elements, each result data element to have a value of a computational operation performed on the pair of data elements, wherein the computational operation is one of addition, subtraction, multiplication, division, and average.

19. The processor (100) according to any one of claims 14 to 17, wherein The execution unit (106) is to perform, responsive to the instruction (102) being decoded, a vertical single instruction multiple data (SIMD) operation on the data elements of each pair.

20. The processor (100) according to any one of claims 14 to 17, wherein The decode unit (104) is to decode the instruction (102) that specifies or indicates the first set (112) of one or more source packed data operands to include only a single first source packed data operand and the second set (116) of one or more source packed data operands to include only a single second source packed data operand, and wherein the execution unit (106) is to store the result packed data operand (120) to have fewer data elements than the second source packed data operand.

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