An acceleration method and computing device suitable for integrated circuit design simulation and verification

Abstract

The present invention provides an acceleration method suitable for integrated circuit design simulation and verification, which precompiles IC digital integrated circuit design files to meet segmentation needs. Calling a first compiler to perform hierarchical processing and segmentation on the design file can reduce the level and depth of the operation path, and the second compiler continues to compile the operation task to become an executable binary program. The binary program runs in each processor of the operation server in the form of multi-threads or multi-processes. At the same time, data and communication-related instructions are executed during the operation process, which can realize data interaction between individual operation tasks and realize the decomposition and final integration of the operation tasks. Compared with the existing integrated circuit design, the technical solution of the present invention is flatter in structure, and the level and depth of the operation path are greatly reduced. The new topological structure makes it easier to design segmentation and compilation of multi-threads and multi-processes, and can further improve the running speed.

Description

Technical Field

[0001] The present invention belongs to the field of electronic design acceleration and simulation verification, and in particular relates to a verification method and a computing device suitable for integrated circuit simulation acceleration and simulation. Background Art

[0002] Emulators have been available for more than 20 years and are widely used in VLSI design. Emulators are mainly divided into two types based on the core computing components of hardware implementation: one is based on FPGA, such as the Zebu system from Synopsy; the other is based on a custom processor, such as the Palladium system from Cadence. Both have their pros and cons. Emulators based on FPGA are usually low-cost and run faster. However, due to the limitations of FPGA architecture, when the user's design volume increases, the running speed of FPGA-based emulators will drop rapidly. At the same time, due to the influence of the compilation speed of FPGA itself, the compilation time of FPGA-based systems is often longer. Traditional emulators based on dedicated processors can usually compile quickly and run at a relatively high speed, but the system price is high, the system consumes a lot of energy during operation, and the degree of dedicated maintenance is high.

[0003] In order to solve the problem of reduced simulation speed when large-scale design load is applied, a Chinese invention patent with publication number "CN104111871B" discloses a method for dynamic load balancing in circuit simulation, the specific scheme of which is as follows: "identify a plurality of circuit simulation tasks to be executed; determine an execution duration estimate corresponding to the performance of the plurality of simulation tasks; allocate the plurality of simulation tasks to a plurality of processors according to the execution duration estimate of each simulation task; execute the plurality of simulation tasks in parallel on the plurality of processors; divide the plurality of simulation tasks into corresponding plurality of subtasks; The corresponding plurality of subtasks are stored in a task queue; the corresponding plurality of subtasks in the task queue are assigned to a plurality of processors so that the processing is consistent with the simulation time of the corresponding plurality of subtasks. The above prior art divides the simulation task into a plurality of subtasks according to the execution time, and assigns each subtask to a plurality of processors to execute the simulation task in parallel, so as to improve the execution speed of the simulation task; however, the problem of the prior art is that when in an ultra-large integrated circuit design environment, various logics are intertwined to form a very large circuit topology diagram, which will make it difficult to effectively carry out the division of the simulation task. Based on this problem, the Chinese invention patent with the publication number "CN113822004A" proposes a verification method and system for integrated circuit simulation acceleration and simulation, such as Figure 1As shown, topological transformation of circuit design can reduce the level and depth of circuit design topological structure, make it easier to split and compile multiple tasks, and improve the running speed. The invention patent technical solution with publication number "CN113822004A" is as follows: Figure 2 As shown: topology transformation; receiving the original circuit design, generating a corresponding old value storage logic for the original storage logic in the original circuit design, after the corresponding original storage logic completes the operation, assigning the operation value to the corresponding old value storage logic, and replacing the original storage logic in the next logic operation step of the original storage logic with the old value storage logic, traversing the original circuit design through the above replacement logic, and generating a transformed circuit design; design segmentation; dividing the transformed circuit design into multiple operation tasks, and assigning each operation task to multiple processors for execution, and each processor is provided with a connection channel for data interaction; wherein the operation task includes one or more design units in the transformed circuit design, and load balancing is performed on each operation task based on the load of the design unit. However, after the circuit topology transformation, there will still be a relatively large and tightly coupled part in the design, and the amount of operation is still large, and there is actually still room for decomposition. For example, a large decoding circuit or arbitration circuit. If such a part is placed in a CPU to run, the amount of operation on this CPU will be too large, and other CPUs will have to wait for this CPU to perform the operation during the operation. Such imbalance or inconsistent CPU loads will lead to a waste of CPU computing resources and a decrease in operating speed. Summary of the invention

[0004] The technical problem to be solved by the present invention is: how to balance the execution load between the CPUs and improve the computing speed and efficiency of simulation and emulation verification.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] The present invention provides an acceleration method suitable for integrated circuit design simulation and verification, comprising the following steps:

[0007] S101, read the design file of the IC digital integrated circuit;

[0008] S102, precompiling the acquired design file according to the settings;

[0009] S103, after analyzing and flattening the precompiled design file; calling the first compiler to perform hierarchical processing and segmentation on the design file; outputting a group of operation tasks, each of which represents a part of the logic in the original circuit design;

[0010] S104, compiling the computing task by calling a second compiler to generate a binary program of the computing task;

[0011] S105. The binary program of the computing task is run in the computing server in the form of multiple threads or multiple processes. Instructions related to data exchange and communication are inserted into each thread or process. By executing relevant instructions, data interaction between various computing tasks is realized.

[0012] Preferably, the S103 specifically includes the following steps:

[0013] S601: topological transformation, generating a corresponding old value storage logic from each original storage logic in the integrated circuit design, assigning the operation value to the corresponding old value storage logic after the corresponding original storage logic completes the operation, and replacing the original storage logic in the next logic operation step of the original storage logic with the old value storage logic, traversing the original circuit design through the above replacement logic, and generating a topological structure diagram of the integrated circuit design after topological transformation, wherein the integrated circuit design topological structure diagram includes at least one combinational logic;

[0014] S602: Preliminary segmentation: Based on the integrated circuit design topology structure diagram, a second integrated circuit design topology structure diagram with equivalent functions is generated. In the second integrated circuit design topology structure diagram, each segmented part is not related to each other, and each segmented part forms a subgraph; any subgraph is selected, and the amount of calculation of the combinational logic operation in the subgraph is estimated and accumulated as the amount of calculation of the subgraph; if the amount of calculation of a subgraph exceeds a set threshold, the subgraph is transferred to step S603 for further segmentation, otherwise, it is considered that the amount of calculation of the subgraph has met the requirements and no segmentation is performed;

[0015] S603: Classifying the subgraphs, performing classification processing on the subgraphs, and classifying according to the order of the operation nodes in the subgraphs;

[0016] S604: Segment the subgraph, and divide the operation in the subgraph into at least two operation tasks, each operation task including at least one operation logic.

[0017] Preferably, the step S603 is specifically as follows:

[0018] Extract each combinational logic operation in the subgraph as an operation node and the corresponding signal relationship, calculate the order of each combinational logic operation, and classify them according to the order. The operation at each level only depends on the operation results that occurred earlier than it.

[0019] Preferably, the step S604 is specifically as follows:

[0020] The subgraph is prepared for segmentation, and each level of operation in the subgraph is divided into at least two operation tasks. According to the operation path and the amount of operation from the first level operation to the last level operation, the operation tasks with equivalent amount of operation are divided and segmented, and each operation task contains at least one operation logic.

[0021] Preferably, the pre-compilation in step S102 includes: converting the design file into a required data structure, and performing operations on various parameters.

[0022] Preferably, the computing tasks of each subgraph are respectively assigned to different computing units in the computing server.

[0023] Preferably, the computing unit may be a CPU, a GPU, a FPGA, etc.

[0024] A computing device, comprising:

[0025] A memory storing a plurality of instructions;

[0026] at least one processor, configured to execute the plurality of instructions so that the computing device executes the acceleration method suitable for integrated circuit design simulation and verification; and

[0027] A display device displays a related graphic display interface.

[0028] A non-volatile computer-readable storage medium stores a set of instructions for a computing device, which can enable the computing device to execute an acceleration method suitable for integrated circuit design simulation and verification.

[0029] The present invention has the following beneficial effects:

[0030] 1. The present invention provides an acceleration method suitable for integrated circuit design simulation and verification. By precompiling the IC digital integrated circuit design file to meet the segmentation requirements, calling the first compiler to perform hierarchical processing and segmentation on the design file can reduce the level and depth of the operation path. The second compiler continues to compile the operation task and turns it into an executable binary program. The binary program runs in each processor of the operation server in the form of multi-threads or multi-processes. At the same time, since there are data and communication related instructions executed during the operation process, data interaction between individual operation tasks can be realized, and the decomposition and final integration of the operation tasks can be realized. Compared with the existing integrated circuit design, the acceleration method suitable for integrated circuit design simulation and verification of the present invention is flatter in structure, and the level and depth of the operation path are greatly reduced. The new topological structure makes it easier to design segmentation and compilation of multi-threads and multi-processes, and can further improve the running speed.

[0031] 2. Further, the present invention provides an acceleration method suitable for integrated circuit design simulation and verification. In large-scale integrated circuit design, it is a complex network diagram from a graphical point of view, which makes it impossible to effectively divide the computing tasks. The present application reduces the dependency and coupling between the various computing nodes (combinatorial logic operations, storage logic operations) in the original design file by setting a topological transformation. The design after the topological transformation is flatter in structure than the original design, and the level and depth of the computing path are significantly reduced, which can better meet the design segmentation and compilation of multi-threads or multi-processes, and at the same time improve the speed of design simulation and verification. Because various computing logics are intertwined, the integrated circuit design collection is flatter in structure than the original integrated circuit design, and the level and depth of the computing path are greatly reduced. The new topological structure makes it easier to design segmentation and compilation for multi-threads and multi-processes, and can further improve the running speed. When the computational amount of a subgraph exceeds the set threshold, the computational amount of the surface subgraph may be too large. By preliminarily segmenting the subgraph, it is possible to avoid the situation where the computational amount of a certain subgraph is much larger than that of another subgraph, and realize the balanced allocation of the computing resources of the processor. For subgraphs with large computational load, the subgraphs are classified according to the order of computational nodes and further divided into smaller computational particles.

[0032] 3. Furthermore, the present invention provides an acceleration method suitable for integrated circuit design simulation and verification. The methods are graded according to the order of the combinational logic operations. The operations at each level only depend on the results of operations that occurred earlier than it. Therefore, the operations at the same level can be performed in parallel, effectively improving the computing efficiency.

[0033] 4. Furthermore, the present invention provides an acceleration method suitable for integrated circuit design simulation and verification, which divides the calculation path and amount of calculation from the first-level calculation to the last-level calculation into calculation tasks with equivalent amount of calculation, so that the amount of calculation of each part after division is as equal as possible.

[0034] 5. Furthermore, the present invention provides an acceleration method suitable for integrated circuit design simulation and verification, which converts the design file into the required data structure, and performs operations on various parameters as pre-compilation to facilitate segmentation preparation.

[0035] 6. Furthermore, the present invention provides an acceleration method suitable for integrated circuit design simulation and verification, and the segmentation method is applicable to different computing units. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of a flow chart of an acceleration method suitable for integrated circuit design simulation and verification according to the present invention;

[0037] Figure 2 A schematic diagram of a design segmentation process of an acceleration method suitable for integrated circuit design simulation and verification according to the present invention;

[0038] Figure 3 An example of an original topology structure provided for an acceleration method suitable for integrated circuit design simulation and verification of the present invention;

[0039] Figure 4 The present invention is an acceleration method suitable for integrated circuit design simulation and verification for Figure 3 Schematic diagram of the topological structure after topological transformation;

[0040] Figure 5 A schematic diagram of a topological transformation of an acceleration method suitable for integrated circuit design simulation and verification according to the present invention after transformation and Leveing;

[0041] Figure 6 The present invention is a schematic diagram of an acceleration method suitable for integrated circuit design simulation and verification using a partitioning algorithm.

[0042] Description of labels:

[0043] 201 - original input; 202 - original output; 203 - sequential logic; 204 - first combination logic; 205 - second combination logic; 301 - old value storage logic; 302 - output signal. DETAILED DESCRIPTION

[0044] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] The present invention provides an acceleration method suitable for integrated circuit design simulation and verification, referring to Figure 1 As shown, the following steps are included:

[0046] S101, reading IC (integrated circuit) digital integrated circuit design files, which may be RTL and gate IC design files.

[0047] S102, precompiling the acquired design file according to the settings, wherein the precompiling mainly includes some parameter calculations and / or format conversions.

[0048] S103, after analyzing and flattening the precompiled design file, unfold it to form a topology diagram; call the first compiler to perform hierarchical processing and segmentation on the design file; output a set of operation tasks, each of which represents a part of the logic in the original circuit design. The first compiler can also be called a precompiler or a front-end compiler. The first compiler can directly process and segment the RTL without first having to go through the synthesis process from RTL to gate-level netlist like other simulators.

[0049] S104: Compile the computing task by calling a second compiler to generate a binary program of the computing task.

[0050] S105. The binary program of the computing task is run in the computing server in the form of multiple threads or multiple processes. Instructions related to data exchange and communication are inserted into each thread or process. By executing relevant instructions, data interaction between various computing tasks is realized.

[0051] Preferably, if Figure 2 As shown, the S103 specifically includes the following steps:

[0052] S601: Topological transformation, generating a corresponding old value storage logic for each original storage logic in the integrated circuit design, assigning the operation value to the corresponding old value storage logic after the corresponding original storage logic completes the operation, and replacing the original storage logic in the subsequent logic operation step of the original storage logic with the old value storage logic, traversing the original circuit design through the above replacement logic, and generating a topological structure diagram of the integrated circuit design after topological transformation, wherein the integrated circuit design topological structure diagram includes at least one combinational logic. Figure 3 This is a typical signal and logic diagram of a logic design. Input signals 1, 2, 3 are the original inputs 201 of the design, and output signals 1, 2 are the original outputs 202 of the design. The design includes a first combinational logic 204 and a second combinational logic 205, and also includes a sequential logic 203. As shown in the figure, the sequential logic can be equivalent to a register. Figure 4 The topological structure diagram after the topological transformation is shown. The original storage logic 203 generates a corresponding old value storage logic 301, such as the old value register 1 corresponds to the original memory 1, etc. The design after the topological transformation provided by the technical solution of the present application is flatter in structure than the original design, and the level and depth of the operation path are greatly reduced. The new topological structure makes it easier to design and compile multi-threading and multi-process, and can further improve the running speed.

[0053] S602: Preliminary segmentation: Based on the IC design topology diagram, generate a second IC design topology diagram with equivalent functions. In the second IC design topology diagram, each segmented part is not related to each other, and each segmented part forms a sub-graph. Select any sub-graph, estimate the amount of operation of the combinational logic operation in the sub-graph, and add them up as the amount of operation of the sub-graph. If the amount of operation of a sub-graph exceeds the set threshold, the sub-graph is transferred to step S603 for further segmentation. Otherwise, it is considered that the amount of operation of the sub-graph has met the requirements and no segmentation is performed. Figure 4As shown, after the topological transformation 601 is completed, two subgraphs have been formed, namely, combinational logic 1 and combinational logic 2, which can be placed on two computing units (such as two CPUs) for parallel computing. However, considering the diversity of integrated circuit design, it is very likely that the complexity of each subgraph is different, and it is very likely that the amount of computing of a subgraph is much larger than that of another subgraph. If this situation is not further processed, it will happen that one CPU has finished the operation and is waiting for the completion of the operation on another CPU, resulting in a waste of CPU computing resources and reducing the overall operating speed. In order to solve this problem, the invention will determine the subgraphs that need to be further segmented in step 602. The confirmation method is based on the estimation of the amount of computing of each subgraph.

[0054] S603: Leveling the subgraphs: performing leveling on the subgraphs according to the order of the operation nodes in the subgraphs. Figure 5 As shown, we first need to sort out the various operation nodes in the subgraph and the signals they use to confirm the order of each operation, and then classify them. The input signal used in the subgraph, the old value storage unit is Level 0, and then the operation of the operation logic F1 only depends on the input signal 1 and the input signal 2, so the operation logic F1 can be operated first, so it belongs to Level 1. The input of the operation logic F3 includes input signal 3, the old value register 1 and the output signal of F1. It can be judged that the operation of the operation logic F3 should be performed after the operation logic F1 is completed, so the operation logic F3 needs to be placed in Level 2, and so on. After step 603 is completed, the entire subgraph forms a structure based on Level. The biggest feature of this structure is that the operation logic or operation task at the same level only depends on the operation at a lower level, that is, the operation tasks at the same level can be operated in parallel.

[0055] S604: Segment the subgraph, and divide the operation in the subgraph into at least two operation tasks, each operation task including at least one operation logic.

[0056] Preferably, the step S603 is specifically as follows:

[0057] Extract each combinational logic operation in the subgraph as an operation node and the corresponding signal relationship, calculate the order of each combinational logic operation, and classify them according to the order. The operation at each level only depends on the operation results that occurred earlier than it.

[0058] Preferably, the step S604 is specifically as follows:

[0059] The subgraph is prepared for segmentation, and each level of operation in the subgraph is divided into at least two operation tasks. According to the operation path and operation amount from the first level operation to the last level operation, the operation tasks with equivalent operation amount are divided and segmented, and each operation task contains at least one operation logic. Figure 5 As shown, when designing and performing parallel operations, it is necessary to ensure that the results of the operations are consistent with the results of the operations on the entire integrated circuit. At the same time, considering the characteristics of the simulator itself, when further segmenting, it is necessary to ensure that any path from Level 0 to the highest level can be divided into at most two partitions. Based on this principle, there are many ways to segment the graph. Figure 5 The following is one of them. By splitting between Level 3 and Level 4, the subgraph is first divided into two parts of computing tasks. The computing tasks of the upper part include the computing logic of F1, F2, F3, F4, and F5, and the computing tasks of the lower part include the computing logic of F6, F7, F8, and F9. The two levels between which the split is made depends on the total amount of computing logic contained in the upper and lower parts. In this way, the subgraph can at least be split into two parts with equal computing volume.

[0060] when Figure 6 After the design diagram shown is divided into two parts, it can be seen that in the upper part, the calculation task formed by the combination of F1, F3, and F5 operation logics and the calculation task formed by the combination of F2 and F4 operation logics can be relatively independent. Similarly, in the lower part, the calculation of F6 operation logic, the calculation of F7 operation logic, and the calculation of F8 and F9 operation logics can also be relatively independent. So in the end, through step 604, we can put Figure 6 The designed operations in the schematic diagram are divided into five partitions 505, 506, 507, 508, and 509 or are considered as parallel operations in the operation tasks.

[0061] Preferably, the pre-compilation in step S102 includes: converting the design file into a required data structure, and performing operations on various parameters.

[0062] Preferably, the computing tasks of each subgraph are respectively assigned to different computing units in the computing server.

[0063] Preferably, the computing unit may be a CPU, a GPU, a FPGA, etc. Figure 3-6 There is continuity, and the reference numerals in the figure are only for the purpose of corresponding to the figure numbers respectively. 301, 401, 501 do not mean different registers, input signals, etc.

[0064] A computing device, comprising:

[0065] A memory stores a plurality of instructions.

[0066] at least one processor, configured to execute the plurality of instructions so that the computing device executes the acceleration method suitable for integrated circuit design simulation and verification; and

[0067] A display device displays a related graphic display interface.

[0068] A non-volatile computer-readable storage medium stores a set of instructions for a computing device, which can enable the computing device to execute an acceleration method suitable for integrated circuit design simulation and verification.

[0069] The operations described in this application can also be understood as “calculation” or replaced by “calculation”.

[0070] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An acceleration method suitable for integrated circuit design simulation and verification, characterized in that: The following steps are involved: S101, read the design file of the IC digital integrated circuit; S102, precompiling the acquired design file according to the settings; S103, analyzing and flattening the precompiled design file; Expand to form a topology diagram, call the first compiler to perform hierarchical processing and segmentation on the design file; output a set of operation tasks, each operation task represents a part of the logic in the original circuit design; S104, compiling the computing task by calling a second compiler to generate a binary program of the computing task; S105, the binary program of the computing task is run in the computing server in the form of multiple threads or multiple processes, and instructions related to data exchange and communication are inserted into each thread or process, and data interaction between various computing tasks is realized by executing relevant instructions; The S103 specifically includes the following steps: S601: topological transformation, generating a corresponding old value storage logic for each original storage logic in the integrated circuit design, assigning the operation value to the corresponding old value storage logic after the corresponding original storage logic completes the operation, and replacing the original storage logic in the next logic operation step of the original storage logic with the old value storage logic, traversing the original circuit design through the above replacement logic, and generating a topological structure diagram of the integrated circuit design after topological transformation; S602: Preliminary segmentation: Based on the integrated circuit design topology structure diagram, a second integrated circuit design topology structure diagram with equivalent functions is generated. In the second integrated circuit design topology structure diagram, each segmented part is not related to each other, and each segmented part forms a subgraph; any subgraph is selected, and the amount of calculation of the combinational logic operation in the subgraph is estimated and accumulated as the amount of calculation of the subgraph; if the amount of calculation of a subgraph exceeds a set threshold, the subgraph is transferred to step S603 for further segmentation, otherwise, it is considered that the amount of calculation of the subgraph has met the requirements and no segmentation is performed; S603: Classifying the subgraphs, performing classification processing on the subgraphs, and classifying according to the order of the operation nodes in the subgraphs; S604: Segment the subgraph, and divide the operation in the subgraph into at least two operation tasks, each operation task including at least one operation logic.

2. The acceleration method suitable for integrated circuit design simulation and verification according to claim 1, characterized in that: The step S603 is specifically as follows: Extract each combinational logic operation in the subgraph as an operation node and the corresponding signal relationship, calculate the order of each combinational logic operation, and classify them according to the order. The operation at each level only depends on the operation results that occurred earlier than it.

3. A verification method suitable for integrated circuit simulation acceleration and emulation according to claim 2, characterized in that: The step S604 is specifically as follows: The subgraph is prepared for segmentation, and each level of operation in the subgraph is divided into at least two operation tasks. According to the operation path and the amount of operation from the first level operation to the last level operation, the operation tasks with equivalent amount of operation are divided and segmented, and each operation task contains at least one operation logic.

4. The acceleration method suitable for integrated circuit design simulation and verification according to claim 1, characterized in that: The pre-compilation in step S102 includes: converting the design file into a required data structure, and performing operations on various parameters.

5. An acceleration method suitable for integrated circuit design simulation and verification according to any one of claims 1 to 3, characterized in that: The computing tasks of each subgraph are respectively assigned to different computing units in the computing server.

6. The acceleration method suitable for integrated circuit design simulation and verification according to claim 5, characterized in that: The computing unit is a CPU, a GPU or a FPGA.

7. A computing device comprising: A memory storing a plurality of instructions; At least one processor, configured to execute the plurality of instructions so that the computing device runs an acceleration method suitable for integrated circuit design simulation and verification as described in any one of claims 1 to 6; And a display device, displaying a related graphic display interface.

8. A non-volatile computer-readable storage medium, wherein the storage medium stores a set of instructions for a computing device, wherein the set of instructions enables the computing device to execute an acceleration method suitable for integrated circuit design simulation and verification as described in any one of claims 1-6.

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