IO circuit suitable for multi-level communication and control method thereof

Abstract

This application provides an I / O circuit and its control method suitable for multi-level communication, belonging to the field of electronic technology. The I / O circuit includes multiple input branches, each with a different power supply voltage. Each input branch is configured to convert a voltage level signal connected to its pin into a first voltage level signal when the input branch is selected. This first voltage level signal is adapted to the target communication level and is used to connect to the next stage circuit. Using this application can reduce the area of ​​the I / O circuit.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to an I / O circuit and its control method suitable for multi-level communication. Background Technology

[0002] I / O (In / Out) interfaces are commonly used to enable interaction and communication between internal chip circuits and the outside world. Corresponding I / O circuits are used to implement digital input, output, pull-up, and pull-down functions. Outputs can include push-pull outputs and open-drain outputs. I / O circuits consist of input and output branches, and their different functions are implemented through the configuration of internal logic.

[0003] I / O interfaces need to adapt to different communication level requirements. For example, in some applications, different I / O interfaces on a general-purpose MCU can connect to different electronic devices (such as other chips or board-level circuits) at the board level. The communication levels of these electronic devices may not be the same. Therefore, the I / O circuit needs to adapt to different communication levels according to the application. Taking communication levels VDD1 and VDD2 as an example, the power supply voltage of the input branch can be switched between VDD1 and VDD2 according to the application requirements through a power switching circuit, thereby adapting to different communication levels.

[0004] If a chip contains multiple I / O circuits that need to adapt to different communication levels, each I / O circuit requires a power switching circuit. Since the power switching circuit has a large area, it will occupy a large area of ​​the chip.

[0005] Furthermore, I / O circuits typically include ESD (Electro-Static Discharge) protection circuits. ESD protection circuits need to consider the impact of power switching circuits; to achieve equivalent ESD capability, the area of ​​the ESD discharge device needs to be increased, thus increasing the complexity of the ESD protection circuit design. Summary of the Invention

[0006] To address the problems of existing technologies, this application provides an I / O circuit and its control method suitable for multi-level communication, which avoids the use of power switching circuits and reduces area footprint. The technical solution is as follows:

[0007] According to one aspect of this application, an I / O circuit suitable for multi-level communication is provided, the I / O circuit including multiple input branches, each input branch having a different power supply voltage;

[0008] The input branch is configured to convert the level signal connected to the pin into a first level signal when the input branch is selected, wherein the first level signal is adapted to the target communication level and is used to connect to the next stage circuit.

[0009] Optionally, the input branch may further include a control module;

[0010] The control module is used to receive the enable control signal of the input branch, and is configured to enable the input branch based on the first level enable control signal when the input branch is selected; and to disable the input branch based on the second level enable control signal when the input branch is not selected.

[0011] Optionally, when the power supply voltage corresponding to the input branch is compatible with the target communication level, the enable control signal is configured to the first level;

[0012] When the power supply voltage corresponding to the input branch is not compatible with the target communication level, the enable control signal is configured to the second level.

[0013] Optionally, the control module includes a first field-effect transistor, the control terminal of which is used to receive the enable control signal.

[0014] Optionally, the input branch includes a level detection module and an input module;

[0015] The level detection module is used to output a detection signal based on the level signal connected to the pin and a set threshold.

[0016] The input module is used to convert the detection signal into the first level signal.

[0017] Optionally, the I / O circuit further includes a default state setting module;

[0018] The default state setting module is configured to connect a certain level to the input terminal of the input module when the input branch is invalid.

[0019] Optionally, the default state setting module includes a second field-effect transistor, the control terminal of which is used to receive the enable control signal or a signal opposite to the enable control signal.

[0020] Optionally, when the power supply voltage corresponding to the input branch is inconsistent with the power supply voltage applicable to the next stage circuit, the input branch may further include a level conversion module.

[0021] The level conversion module is used to convert the first level signal into a second level signal, the second level signal being compatible with the power supply voltage applicable to the next stage circuit.

[0022] According to another aspect of this application, a control method for an I / O circuit suitable for multi-level communication is provided, the I / O circuit including multiple input branches, each input branch having a different power supply voltage, the method comprising:

[0023] Based on the target communication level with the external circuit, determine the target input branch that is compatible with the target communication level;

[0024] Based on the target input branch, the level signal connected to the pin is converted into a first level signal, wherein the first level signal is adapted to the target communication level;

[0025] Connect the first level signal to the next stage circuit.

[0026] According to another aspect of this application, a chip is provided, including the aforementioned I / O circuit suitable for multi-level communication.

[0027] According to another aspect of this application, an electronic device is provided, including the aforementioned I / O circuit suitable for multilevel communication.

[0028] In this application, the I / O circuit may include multiple input branches, each with a defined power supply voltage, eliminating the need for power switching and transforming power switching into input branch selection. Compared to power switching circuits, the I / O circuit provided in this application has a simpler structure and occupies less chip area. Attached Figure Description

[0029] Further details, features, and advantages of this application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0030] Figure 1 A schematic diagram of an I / O input circuit provided according to an exemplary embodiment of this application is shown;

[0031] Figure 2 A schematic diagram of the input branch provided according to an exemplary embodiment of this application is shown;

[0032] Figure 3 A schematic diagram of a control module provided according to an exemplary embodiment of this application is shown;

[0033] Figure 4 A schematic diagram of the input branch provided according to an exemplary embodiment of this application is shown;

[0034] Figure 5 A schematic diagram of an I / O input circuit provided according to an exemplary embodiment of this application is shown;

[0035] Figure 6 A schematic diagram of an I / O input circuit provided according to an exemplary embodiment of this application is shown;

[0036] Figure 7 A schematic diagram illustrating the default state settings provided according to an exemplary embodiment of this application is shown;

[0037] Figure 8 A schematic diagram of a default state setting module provided according to an exemplary embodiment of this application is shown;

[0038] Figure 9 A schematic diagram of an I / O input circuit provided according to an exemplary embodiment of this application is shown;

[0039] Figure 10 A schematic diagram of the input branch provided according to an exemplary embodiment of this application is shown;

[0040] Figure 11 A schematic diagram of an I / O circuit provided according to an exemplary embodiment of this application is shown;

[0041] Figure 12 A flowchart of a control method provided according to an exemplary embodiment of this application is shown;

[0042] Figure 13 A structural block diagram of an exemplary electronic device that can be used to implement embodiments of this application is shown. Detailed Implementation

[0043] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0044] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc., mentioned in this application are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0045] It should be noted that the terms "a" and "a plurality of" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0046] The names of the messages or information exchanged between multiple devices in the embodiments of this application are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0047] This application provides an I / O circuit suitable for multi-level communication. This I / O circuit can be integrated into a chip or board-level circuit, or disposed in an electronic device. This I / O circuit can communicate with external circuits based on a target communication level, and includes input and output branches, with signals input or output via pins. This application mainly improves the input branch; the output branch can adopt existing structures to achieve the corresponding functions. This application does not limit the output branch and will not describe it in detail here.

[0048] Reference Figure 1 The illustrated I / O circuit diagram shows that the I / O circuit may include multiple input branches, each with a different power supply voltage, and these input branches are connected in parallel. For example, the power supply voltage VDD1 of one input branch may be 3.3V, and the power supply voltage VDD2 of another input branch may be 1.8V, or other voltage values. This embodiment does not limit the number of input branches or the specific power supply voltage values.

[0049] The following introduction will be based on one input branch; the same applies to other input branches.

[0050] An input branch can be configured to convert the level signal connected to the pin into a first level signal when the input branch is selected.

[0051] The level signal connected to the pin can be an analog signal, while the first level signal can be a digital signal.

[0052] The first level signal is compatible with the target communication level, and this first level signal is used to access the next stage circuit. Compatibility can refer to high and low level logic matching. For example, suppose the level signal connected to the pin is 1.8V. In a circuit with a power supply voltage of 1.8V, it can be determined as a high level, but in a circuit with a power supply voltage of 3.3V, it may be determined as a low level. If the correct circuit logic requires the connected 1.8V to be a high level, then in a circuit with a power supply voltage of 1.8V, the high and low level logic matches, and the circuit can operate correctly, which is compatibility. However, in a circuit with a power supply voltage of 3.3V, the high and low level logic does not match, and the circuit may perform incorrect actions, which is mismatch.

[0053] In one possible implementation, the input terminal of the input branch is connected to a pin to receive a level signal from an external circuit; the output terminal is connected to the next stage circuit to input the output level signal into the internal circuit.

[0054] When the I / O circuit is connected to an external circuit, the applicable power supply voltage for the external circuit can be determined, that is, the target communication level can be determined. Then, a target input branch that matches the target communication level can be identified through internal logic. This target input branch can then be selected. For example, a 01 signal can be used to indicate whether an input branch is selected. For instance, when there are two input branches, "01" indicates that the second input branch is selected, and "10" indicates that the first input branch is selected.

[0055] When an input branch is selected, the target input branch can be configured as valid, and the input branch (i.e. the target input branch) can work normally to convert the level signal input from the external circuit into a first level signal.

[0056] When an input branch is not selected, it can be configured to be either enabled or disabled.

[0057] Preferably, when an input branch is not selected, it is configured as invalid. When an input branch is invalid, it does not process the level signal input from the external circuit and outputs an invalid signal. This reduces the power consumption of unselected input branches.

[0058] Since there are multiple input branches, the first-level signal output by the target input branch can be connected to the next stage circuit through a multiplexer. This embodiment does not limit this. For example, the above-mentioned 01 signal can be connected to a multiplexer, and the first-level signal output by the target input branch can be selected by the multiplexer. For example, the signal of the second input branch can be selected based on the signal "01", and the signal of the first input branch can be selected based on the signal "10".

[0059] Optional, refer to Figure 2 The diagram shown illustrates the input branch, which may also include a control module. This control module can be used to control whether the input branch is valid.

[0060] The control module can be used to receive the enable control signal of the input branch, and is configured to enable the input branch based on a first level when the input branch is selected, and disable the input branch based on a second level when the input branch is not selected.

[0061] When the power supply voltage corresponding to the input branch matches the target communication level, the above-mentioned enable control signal can be configured to the first level. When the power supply voltage corresponding to the input branch does not match the target communication level, the above-mentioned enable control signal can be configured to the second level.

[0062] One input branch corresponds to one enable control signal.

[0063] In chip applications, the power supply voltage of each input branch is determined to be compatible with the target communication level based on the actual scenario. If they are compatible, the enable control signal for that input branch can be configured to a first level; if they are not compatible, the enable control signal for that input branch can be configured to a second level. For example, the first level can be high, and the second level can be the opposite of the first level, which is low. Of course, the first level can also be low and the second level can be high; this embodiment does not limit the specific enable control signal.

[0064] Furthermore, the first-level enable control signal can be connected to the target input branch to configure the target input branch as active; the second-level enable control signal can be connected to the remaining input branches to configure the remaining input branches as inactive.

[0065] Optionally, the control module can be located at the grounding terminal of the input branch to control whether the input branch is grounded. Alternatively, the control module can also be located at the power supply end of the input branch to control whether the power supply voltage is connected to the input branch. This embodiment does not limit the specific location of the control module.

[0066] Optionally, the control module may include a first field-effect transistor, the control terminal of which is used to receive an enable control signal.

[0067] For example, consider a control module located at the ground terminal and a first field-effect transistor (FET) that is an NMOS (N-Metal-Oxide-Semiconductor) transistor. (Refer to...) Figure 3 The control module diagram shown illustrates that the control terminal (gate) of the first field-effect transistor (FET) can be used to receive an enable control signal, the source can be grounded, and the drain can be connected to the ground terminal of the input branch. The first voltage level can be high. When the control terminal of the first FET is connected to a high voltage level, the FET is turned on, the input branch can be grounded to form a circuit, and it can operate normally. When the control terminal of the first FET is connected to a low voltage level, the FET is turned off, the input branch is not grounded, and it is in a high-impedance state.

[0068] Of course, the first field-effect transistor can also be a PMOS (P-Metal-Oxide-Semiconductor) transistor. This embodiment does not limit the specific type of the first field-effect transistor. In this case, the first level can be a low level, the input terminal of the first field-effect transistor can be connected to the ground terminal of the input branch, and the output terminal can be grounded.

[0069] Optional, refer to Figure 4The schematic diagram of the input branch shown can include a level detection module and an input module. The output terminal of the level detection module is connected to the input terminal of the input module.

[0070] The level detection module can be used to output a detection signal based on the level signal input to the pin and a set threshold.

[0071] The input module can be used to convert the detection signal into a first-level signal.

[0072] In one possible implementation, the input terminal of the level detection module can be connected to a pin, and the output terminal can be connected to the input terminal of the input module; the input terminal of the input module can be connected to the output terminal of the level detection module, and the output terminal can be connected to the next stage circuit, for converting the detection signal into a first level signal and connecting it to the internal circuit.

[0073] In the input branch consisting of the level detection module and the input module, the level signal input from the external circuit can be compared with a set threshold to determine whether it is higher or lower than the set threshold, thus detecting whether the level signal is high or low. This set threshold can be related to the power supply voltage of the input branch. For example, the set threshold can be half the power supply voltage; if the power supply voltage is 3V, then the set threshold can be 1.5V. If the input level signal is 1.3V, lower than the set threshold, it is considered low, and the detection signal can be low; if the input level signal is 2.5V, higher than the set threshold, it is considered high, and the detection signal can be high. This embodiment does not limit the specific set threshold.

[0074] In one specific implementation, refer to Figure 5 The input branch diagram shown illustrates that the level detection module can be composed of a pair of PMOS and NMOS transistors connected in parallel. The gate of the PMOS transistor is connected to the pin, and its source is connected to the drain of the NMOS transistor, with the drain used to receive the power supply voltage. Similarly, the gate of the NMOS transistor is connected to the pin, and its drain is connected to the source, with the source used to ground. In this configuration, the PMOS and NMOS transistors can be used to implement an inversion function; that is, when the pin is connected to a high level, the level detection module can output a low level, and when the pin is connected to a low level, the level detection module can output a high level. Correspondingly, the input module can be used to implement an inversion function, for example, by using an inverter to convert the high level output by the level detection module to a low level, and vice versa. This allows for a buffering function based on the level detection module and the input module. When the pin is connected to a high level, the first level signal output by the input branch can be a corresponding high level; when the pin is connected to a low level, the first level signal output by the input branch can be a corresponding low level.

[0075] This embodiment does not limit the specific circuit structure of the level detection module and the input module.

[0076] For example, when Figure 3 The control module shown is Figure 5 When the level detection module and input module shown are combined, they can form a structure as follows: Figure 6 The I / O circuit shown is described above. The specific implementation principle of this I / O circuit has already been explained and will not be repeated here.

[0077] Optionally, when the input branch is in a high-impedance state, the voltage level signal connected to the internal circuit may be either high or low, resulting in an unstable state that could cause leakage problems. Therefore, refer to... Figure 7 The diagram shown illustrates an I / O circuit. The I / O circuit may also include a default state setting module.

[0078] The default state setting module is configured to connect a specific voltage level to the input terminal of the input module when the input branch is invalid. Even when the input branch is in a high-impedance state, a specific voltage level can still be connected to the input terminal of the input module, allowing the input module to output a definite voltage signal, avoiding unstable states and resolving leakage problems.

[0079] Optionally, the default state setting module includes a second field-effect transistor, the control terminal of which is used to receive the above-mentioned enable control signal, or to receive a signal opposite to the above-mentioned enable control signal.

[0080] When the input branch is active, the second MOSFET can be turned off, without affecting the input signal connection to the input module. When the input branch is inactive, the second MOSFET can be turned on, connecting a specific voltage level to the input module. Therefore, the enable control signal connected to the second MOSFET may be the same as or opposite to the enable control signal connected to the input module, depending on the type of the second MOSFET. For example, when the input branch is high-level enabled, if the second MOSFET is a PMOS transistor and low-level enabled, its control terminal can be used to receive the same signal as the enable control signal of the input circuit; if the second MOSFET is an NMOS transistor and high-level enabled, its control terminal can be used to connect a signal opposite to the enable control signal of the input circuit. The same applies when the input branch is low-level enabled, and will not be elaborated further.

[0081] In one specific implementation, refer to Figure 8 The schematic diagram of the default state setting module shows that the second field-effect transistor is a PMOS transistor, with its source connected to the input terminal of the input module and its drain used to receive the power supply voltage. When the input branch is configured to be invalid, the second field-effect transistor is turned on, connecting the power supply voltage to the input module.

[0082] Of course, the level of the input module can be other values, and this embodiment does not limit the specific value of the level.

[0083] For example, when Figure 6 The IO circuit shown is Figure 8 When the default state setting modules shown are combined, they can form a configuration such as Figure 9 The I / O circuit shown is described above. The specific implementation principle of this I / O circuit has already been explained and will not be repeated here.

[0084] Optionally, when the power supply voltage corresponding to the input branch is inconsistent with the power supply voltage applicable to the next stage circuit, the input branch may also include a level conversion module.

[0085] The level conversion module is used to convert a first-level signal into a second-level signal.

[0086] The second-level signal is matched with the power supply voltage applicable to the next stage circuit so that the next stage circuit can process it. Both the first-level signal and the second-level signal are digital signals.

[0087] Reference Figure 10 The schematic diagram of the input branch shown illustrates that the input terminal of the level conversion module can be used to receive a first-level signal, and the output terminal can be used to output a second-level signal. The level conversion module can utilize existing circuit structures, as long as they can achieve level conversion. This embodiment does not limit the specific circuit structure of the level conversion module.

[0088] For example, suppose the power supply voltage of the input branch is 3V. If the first level signal is high, the corresponding voltage can be 3V; if the first level signal is low, the corresponding voltage can be 0.1V. When the power supply voltage of the next stage circuit is 1.5V, when the first level signal is high, the level conversion module can convert 3V to 1.5V, and the resulting second level signal can be used as a high level in the next stage circuit; when the first level signal is low, the level conversion module can convert 0.1V to 0.05V, and the resulting second level signal can be used as a low level in the next stage circuit.

[0089] Figure 11A specific I / O circuit diagram is shown, including an output branch and multiple parallel input branches. The implementation principle of the multiple parallel input branches has been described above and will not be repeated here. The output branch includes an output control and pull-up / pull-down control logic module, a field-effect transistor for driving, pull-up resistors, and pull-down resistors, used to connect the signal output from the internal circuit to the pin and transmit it to the external circuit. The output control logic module is used to control the output enable, output mode (push-pull output or open-drain output), output current, etc. This embodiment does not limit the circuit structure and implementation method of the output branch.

[0090] The embodiments of this application can achieve at least the following beneficial effects:

[0091] (1) The IO circuit may include multiple input branches, each with a defined power supply voltage, eliminating the need for power supply switching and converting power supply switching into selection of input branches. Compared to power supply switching circuits, the IO circuit provided in this application has a simpler structure and occupies less chip area.

[0092] (2) With the reduction of IO circuit area, the corresponding ESD protection circuit design complexity is reduced and the performance is improved, which can improve the robustness of the chip.

[0093] (3) In existing power switching schemes, the input branches used for different power supply voltages are the same. Therefore, the devices in the input branches need to be adapted to most power supply voltages, which may lead to mismatch and affect circuit performance. In the IO circuit provided in this application, the circuit structure of each input branch can be the same, and the device size can vary according to the requirements of different power domains and match the corresponding power supply voltage, which can improve the performance of the IO circuit.

[0094] This application provides a control method applicable to the aforementioned I / O circuit. The specific implementation has been described above and will not be repeated here. (Refer to...) Figure 12 The flowchart of the control method shown includes:

[0095] Step 1201: Determine the target input branch that matches the target communication level based on the target communication level with the external circuit.

[0096] Step 1202: Based on the target input branch, convert the level signal connected to the pin into a first level signal;

[0097] Step 1203: Connect the first level signal to the next stage circuit.

[0098] The first level signal is adapted to the target communication level.

[0099] Optionally, the input branch further includes a control module, the control module being used to receive an enable control signal from the input branch, and the method further includes:

[0100] The control module enables the input branch to be active when it is selected, based on a first-level enable control signal; and disables the input branch when it is not selected, based on a second-level enable control signal.

[0101] Optionally, the method further includes:

[0102] When the power supply voltage corresponding to the input branch is compatible with the target communication level, the enable control signal will be configured to the first level;

[0103] When the power supply voltage corresponding to the input branch is not compatible with the target communication level, the enable control signal will be configured to the second level.

[0104] Optionally, the control module includes a first field-effect transistor, the control terminal of which is used to receive the enable control signal.

[0105] Optionally, the input branch includes a level detection module and an input module, wherein converting the level signal connected to the pin into a first level signal includes:

[0106] The level detection module outputs a detection signal based on the level signal connected to the pin and a set threshold.

[0107] The input module converts the detection signal into the first level signal.

[0108] Optionally, the I / O circuit further includes a default state setting module, and the method further includes:

[0109] When the input branch is invalid, the default state setting module controls the input terminal of the input module to connect a certain level.

[0110] Optionally, the default state setting module includes a second field-effect transistor, the control terminal of which is used to receive the enable control signal or a signal opposite to the enable control signal.

[0111] Optionally, when the power supply voltage corresponding to the input branch is inconsistent with the power supply voltage applicable to the next stage circuit, the input branch further includes a level conversion module, and the method further includes:

[0112] The level conversion module converts the first level signal into a second level signal, which is compatible with the power supply voltage applicable to the next stage circuit.

[0113] The embodiments of this application can achieve at least the following beneficial effects:

[0114] (1) The IO circuit may include multiple input branches, each with a defined power supply voltage, eliminating the need for power supply switching and converting power supply switching into selection of input branches. Compared to power supply switching circuits, the IO circuit provided in this application has a simpler structure and occupies less chip area.

[0115] (2) With the reduction of IO circuit area, the corresponding ESD protection circuit design complexity is reduced and the performance is improved, which can improve the robustness of the chip.

[0116] (3) In existing power switching schemes, the input branches used for different power supply voltages are the same. Therefore, the devices in the input branches need to be adapted to most power supply voltages, which may lead to mismatch and affect circuit performance. In the IO circuit provided in this application, the circuit structure of each input branch can be the same, and the device size can vary according to the requirements of different power domains and match the corresponding power supply voltage, which can improve the performance of the IO circuit.

[0117] An exemplary embodiment of this application also provides a chip, including the IO circuit suitable for multilevel communication provided in the embodiments of this application.

[0118] An exemplary embodiment of this application also provides an electronic device, including: an I / O circuit suitable for multi-level communication as provided in the embodiments of this application; at least one processor; and a memory communicatively connected to the at least one processor. The memory stores a computer program executable by the at least one processor.

[0119] refer to Figure 13 The following is a structural block diagram of the electronic device 1300 that can serve as the present application, which is an example of a hardware device that can be applied to various aspects of the present application. The electronic device is intended to represent various forms of digital electronic computer devices, such as data center servers, laptops, client computers, desktop computers, workstations, personal digital assistants, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0120] like Figure 13As shown, the electronic device 1300 includes a computing unit 1301, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1302 or a computer program loaded from a storage unit 1308 into a random access memory (RAM) 1303. The RAM 1303 may also store various programs and data required for the operation of the device 1300. The computing unit 1301, ROM 1302, and RAM 1303 are interconnected via a bus 1304. An input / output (I / O) interface 1305 is also connected to the bus 1304.

[0121] Multiple components in electronic device 1300 are connected to I / O interface 1305, including: input unit 1306, output unit 1307, storage unit 1308, and communication unit 1309. Input unit 1306 can be any type of device capable of inputting information to electronic device 1300. Input unit 1306 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of electronic device. Output unit 1307 can be any type of device capable of presenting information and may include, but is not limited to, a display, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 1308 may include, but is not limited to, disk and optical disk. Communication unit 1309 allows electronic device 1300 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0122] The computing unit 1301 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1301 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Part or all of the computer program can be loaded and / or installed on the electronic device 1300 via ROM 1302 and / or communication unit 1309.

[0123] Program code can be written in any combination of one or more programming languages. This program code can be provided to the processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code can be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0124] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0125] As used in this application, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and / or apparatus (e.g., disk, optical disk, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including machine-readable media that receive machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0126] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0127] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0128] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other.

[0129] The above provides a detailed description of the I / O circuit and its control method suitable for multi-level communication provided by this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An I / O circuit suitable for multi-level communication, characterized in that, The I / O circuit includes multiple input branches, each with a different power supply voltage. The input branch is configured to convert the level signal connected to the pin into a first level signal when the input branch is selected, wherein the first level signal is adapted to the target communication level and is used to connect to the next stage circuit, and the first level signal is a digital signal; The input branch includes a level detection module and an input module. The level detection module is used to compare the level signal connected to the pin with a set threshold and output a detection signal. The input module is used to convert the detection signal into the first level signal. The set threshold is related to the power supply voltage of the input branch.

2. The I / O circuit according to claim 1, characterized in that, The input branch also includes a control module; The control module is used to receive the enable control signal of the input branch, and is configured to enable the input branch based on the first level enable control signal when the input branch is selected; and to disable the input branch based on the second level enable control signal when the input branch is not selected.

3. The I / O circuit according to claim 2, characterized in that, When the power supply voltage corresponding to the input branch is compatible with the target communication level, the enable control signal is configured to the first level; When the power supply voltage corresponding to the input branch is not compatible with the target communication level, the enable control signal is configured to the second level.

4. The I / O circuit according to claim 2, characterized in that, The control module includes a first field-effect transistor, and the control terminal of the first field-effect transistor is used to receive the enable control signal.

5. The I / O circuit according to claim 2, characterized in that, The I / O circuit also includes a default state setting module; The default state setting module is configured to connect a certain level to the input terminal of the input module when the input branch is invalid.

6. The I / O circuit according to claim 5, characterized in that, The default state setting module includes a second field-effect transistor, the control terminal of which is used to receive the enable control signal, or to receive a signal opposite to the enable control signal.

7. The I / O circuit according to claim 1, characterized in that, When the power supply voltage corresponding to the input branch is inconsistent with the power supply voltage applicable to the next stage circuit, the input branch also includes a level conversion module; The level conversion module is used to convert the first level signal into a second level signal, the second level signal being compatible with the power supply voltage applicable to the next stage circuit.

8. A control method for I / O circuits suitable for multi-level communication, characterized in that, The I / O circuit includes multiple input branches, each with a different power supply voltage. The method includes: Based on the target communication level with the external circuit, determine the target input branch that is compatible with the target communication level; The level signal connected to the pin is compared with a set threshold of the target input branch to output a detection signal. The detection signal is converted into a first level signal, wherein the first level signal is adapted to the target communication level, the first level signal is a digital signal, and the set threshold is related to the power supply voltage of the target input branch. Connect the first level signal to the next stage circuit.

9. A chip, characterized in that, Includes I / O circuits suitable for multilevel communication as described in any one of claims 1-7.

10. An electronic device, characterized in that, Includes I / O circuits suitable for multilevel communication as described in any one of claims 1-7.

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