Local Pattern Density Analysis Method of Layout

Abstract

The present invention provides a local graphic density analysis method for a layout, including: dividing a number of gates in the layout into m categories according to different channel sizes; dividing each category of gates into n inspection groups, setting the number of steps and the imbalance coefficient of each inspection group; setting the size of the inspection window of the test area corresponding to each inspection group according to the number of steps, the imbalance coefficient and the channel size; setting the control specification of the graphic density of the test area corresponding to each inspection group according to the number of steps; dividing the test area corresponding to each inspection group into multiple blocks according to the size of the inspection window, calculating the graphic density of each block, and judging whether the graphic density of each block is qualified according to the control specification. According to the method of obtaining different inspection windows and control specifications for different inspection groups of different categories of gates, the graphic density of gates in different places on the layout is flexibly calculated, so as to obtain a more accurate local graphic density.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a local pattern density analysis method of a layout. Background Art

[0002] In the semiconductor manufacturing process, layout pattern density analysis has become an important step in the analysis of many key-level mask data. The uniformity of pattern density distribution has a great impact on the etching process and chemical mechanical polishing process. In the case of uneven pattern density distribution, it is not only easy to aggravate the load effect in etching, causing the final size of some patterns to deviate from the target size, but also more likely to cause the pattern to be over-polished in the chemical mechanical polishing process.

[0003] The layout includes the gate and the graphics around the gate. The gate and the surrounding graphics may correspond to each other. With the continuous development of integrated circuit technology, the continuous reduction of process nodes, the critical size is getting smaller and smaller, and the critical size of the graphics around the gate on the layout is becoming more and more sensitive and important. Therefore, accurately calculating the local graphic density of the graphics around the gate in the layout, and therefore using the graphics around the gate as the test area to find the high-risk process blocks, is conducive to timely understanding the specific location and graphic characteristics of the high-risk process hotspots of the product, formulating corresponding countermeasures as early as possible, and successfully achieving product tape-out and mass production.

[0004] The existing pattern density analysis is to calculate the layout data of the same level mask with a fixed inspection window size and the same control specifications. For example, Figure 1 For the first type of gate 110, the test area is divided into 6 blocks 120 with an inspection window size of 50μm*50μm, and then the pattern density of each block is judged according to a certain control specification. Please refer to Figure 2 For the second type of gate 210, the test area is divided into 6 blocks 220 with the inspection window size of 50μm*50μm, and then the pattern density of each block is judged with the same control specifications as the first gate. However, because the types of gates are different, the patterns around the gates may be different, for example, Figure 1 In the example, the distribution of the pattern 130 in the test area corresponding to the first gate 110 and the pattern 230 in the test area corresponding to the second gate are different. Therefore, the density analysis method in the prior art may cause the loss and deviation of the density analysis. Summary of the invention

[0005] The object of the present invention is to provide a local graphic density analysis method for a layout, which can change the inspection window and control specifications of the corresponding test area according to the gates of different channel sizes on the layout, so as to obtain a more accurate local graphic density.

[0006] In order to achieve the above object, the present invention provides a local pattern density analysis method of a layout, which is used to analyze the pattern density (test area) of the patterns around several gates in the layout, wherein the gates all have a test area, including:

[0007] The plurality of gates in the layout are divided into m categories according to the different channel sizes, where m is a positive integer;

[0008] Divide each type of the gate into n inspection groups, and set the step number and unbalance coefficient of each inspection group, wherein n is a positive integer;

[0009] Setting the size of the inspection window of the test area corresponding to each inspection group according to the step number, the unbalance coefficient and the channel size;

[0010] Setting the control specification of the pattern density of the test area corresponding to each inspection group according to the step number; and

[0011] The test area corresponding to each inspection group is divided into a plurality of blocks according to the size of the inspection window, and the pattern density of each block is calculated, and whether the pattern density of each block is qualified is determined according to the control specification.

[0012] Optionally, in the local graphic density analysis method, the layout includes a total of m*n inspection groups.

[0013] Optionally, in the local pattern density analysis method, the method of classifying the gates into m categories according to different channel sizes includes: classifying the gates with the same channel length as the same category.

[0014] Optionally, in the local pattern density analysis method, the method of dividing each type of the gates into n inspection groups includes:

[0015] n m =[K 0 / L m ];

[0016] Among them, n m is the number of inspection groups of the mth type of gate, and K is taken 0 / L m integer; L m is the channel size of the m-th type of gate; K 0 It is a constant coefficient that is set, and its value is between 0 and 1.

[0017] Optionally, in the local pattern density analysis method, the method of setting the step number of each inspection group includes:

[0018] t m =1 / n m ;

[0019] Among them, t m is the number of steps of the m-th type of gate, n m is the number of inspection groups of the mth type of gate.

[0020] Optionally, in the local pattern density analysis method, the method of setting the imbalance coefficient of each inspection group includes:

[0021] C mi =K 2 +(1-K 2 ) / (n m -1)*(i-1);

[0022] Among them, C mi is the unbalance coefficient of the ith inspection group of the mth type of gate, K 2 is the imbalance parameter to be set, the value is set between 0 and 1, n m is the number of inspection groups of the mth type of gate, and the value of i ranges from 1 to n m .

[0023] Optionally, in the local pattern density analysis method, the method of setting the size of the inspection window of the test area corresponding to each inspection group according to the step number, the imbalance coefficient and the channel size includes:

[0024] The side length of the inspection window of the test area corresponding to each inspection group is set according to the step number, the unbalance coefficient and the channel size, and the inspection window is a square.

[0025] Optionally, in the local pattern density analysis method, the method of setting the side length of the inspection window of the test area corresponding to each inspection group according to the step number, the imbalance coefficient and the channel size includes:

[0026] W mi =C mi *i*t m *K 1 *L m ;

[0027] Among them, W mi is the side length of the inspection window of the test area corresponding to the i-th inspection group of the m-th type of gate, C mi is the unbalance coefficient of the i-th inspection group of the m-th type of gate, and the value of i ranges from 1 to n m , t m is the number of steps of the m-th type of gate, K 1 is the unit constant set, which is an integer multiple of 1000. m is the channel size of the mth type of gate.

[0028] Optionally, in the local pattern density analysis method, the method of setting the pattern density control specification of the test area corresponding to each inspection group according to the step number includes:

[0029] S mi =i*t m *S;

[0030] Among them, S mi is the control specification of the pattern density of the test area corresponding to the i-th inspection group of the m-th type of gate, i ranges from 1 to n, t m is the step number of the mth type of gate, and S is the control specification of the gate density of the set layout.

[0031] Optionally, in the local graphic density analysis method, the method of judging whether the graphic density of each block is qualified according to the control specification includes:

[0032] If the pattern density of each block is lower than the control specification of the pattern density of the inspection group to which it belongs, it is considered unqualified.

[0033] In the local graphic density analysis method of the layout provided by the present invention, gates with different channel sizes are classified, each type of gate is divided into several inspection groups, and finally different inspection windows and control specifications are obtained according to different inspection groups of different types of gates. The graphic density of the test area corresponding to different inspection groups of different gates on the layout is flexibly calculated, thereby obtaining a more accurate local graphic density. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic diagram of the calculation of the pattern density of the first type of gate in the prior art;

[0035] Figure 2 is a schematic diagram of the calculation of the pattern density of the second type of gate in the prior art;

[0036] Figure 3 is a flow chart of a local pattern density analysis method of a layout according to an embodiment of the present invention;

[0037] Figure 4 is a schematic diagram of pattern density calculation of a first inspection group of a first type of gates according to an embodiment of the present invention;

[0038] Figure 5 is a schematic diagram of pattern density calculation of a second inspection group of a first type of gates according to an embodiment of the present invention;

[0039] Figure 6 is a schematic diagram of calculating the pattern density of the inspection group of the second type of gates according to an embodiment of the present invention;

[0040] In the figure: 110 - first gate, 120 - block, 130 - graphic, 210 - second gate, 220 - block, 230 - graphic, 310 - first gate, 320 - block, 330 - graphic, 410 - second gate, 420 - block, 430 - graphic. DETAILED DESCRIPTION

[0041] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0043] Please refer to Figure 3 The present invention provides a local pattern density analysis method of a layout, which is used to analyze the pattern density of patterns around a plurality of gates in the layout, wherein the gates all have a test area, including:

[0044] S11: dividing a plurality of gates in the layout into m categories according to different channel sizes, where m is a positive integer;

[0045] S12: Divide each type of the gate into n inspection groups, and set the step number and unbalance coefficient of each inspection group, where n is a positive integer;

[0046] S13: setting the size of the inspection window of the test area corresponding to each inspection group according to the step number, the unbalance coefficient and the channel size;

[0047] S14: setting a control specification of the pattern density of the test area corresponding to each inspection group according to the step number; and

[0048] S15: Divide the test area corresponding to each inspection group into a plurality of blocks according to the size of the inspection window, calculate the graphic density of each block, and determine whether the graphic density of each block is qualified according to the control specification.

[0049] Preferably, gates with the same channel length are classified into the same category. Here, the channel size also refers to the channel length. Thus, the gates are divided into m categories, and each category of gates is divided into n inspection groups. Therefore, the layout contains a total of m*n inspection groups.

[0050] Preferably, the method of dividing each type of gate into n inspection groups includes:

[0051] n m =[K 0 / L m ];

[0052] Among them, n m is the number of inspection groups of the mth type of gate, and K is taken 0 / L m integer; L m is the channel size of the m-th type of gate; K 0 It is a constant coefficient that is set, and its value is between 0 and 1.

[0053] Preferably, the method of setting the number of steps for each inspection group includes:

[0054] t m =1 / n m ;

[0055] Among them, t m is the number of steps of the m-th type of gate, n m is the number of inspection groups of the mth type of gate. The number of steps of the same type of gate is the same, that is, the channel size L m The number of steps of pattern density between the test areas corresponding to the inspection groups after the gate is divided into inspection groups is t m .

[0056] Preferably, the method of setting the unbalance coefficient of each inspection group includes:

[0057] C mi =K 2 +(1-K 2 ) / (n m -1)*(i-1);

[0058] Among them, C mi is the unbalance coefficient of the ith inspection group of the mth type of gate, K 2 The imbalance parameter is usually set between 0 and 1. m is the number of inspection groups of the mth type of gate, and the value of i ranges from 1 to n m The imbalance factor may be different for each inspection group.

[0059] Preferably, the method of setting the size of the inspection window of the test area corresponding to each inspection group according to the number of steps, the unbalance coefficient and the channel size includes: setting the side length of the inspection window of each inspection group according to the number of steps, the unbalance coefficient and the channel size, the inspection window is a square, so that all the side lengths of the inspection window can be known, that is, the size of the inspection window can be known. The method of setting the side length of the inspection window of the test area corresponding to each inspection group according to the number of steps, the unbalance coefficient and the channel size is as follows:

[0060] W mi =C mi *i*t m *K 1 *L m ;

[0061] Among them, W mi is the side length of the inspection window of the test area corresponding to the i-th inspection group of the m-th type of gate, C mi is the unbalance coefficient of the i-th inspection group of the m-th type of gate, and the value of i ranges from 1 to n m , t m is the number of steps of the m-th type of gate, K 1 is the unit constant set, which is usually an integer multiple of 1000. m is the channel size of the mth type of gate.

[0062] Preferably, the method for setting the control specification of the pattern density of the test area corresponding to each inspection group according to the step number includes:

[0063] S mi =i*t m *S;

[0064] Among them, S mi is the control specification of the pattern density of the test area corresponding to the i-th inspection group of the m-th type of gate, i ranges from 1 to n, t m is the step number of the mth type of gate, and S is the control specification of the gate density of the set layout.

[0065] Preferably, the method of dividing the test area corresponding to each inspection group into a plurality of blocks according to the size of the inspection window includes:

[0066] The test area corresponding to each inspection group is moved rightward and upward respectively from the leftmost and bottommost corners of the test area with reference to the size of the inspection window, thereby dividing the inspection group into a plurality of blocks.

[0067] Preferably, the method of judging whether the graphic density of each block is qualified according to the control specification includes:

[0068] If the pattern density of each block is lower than the control specification of the pattern density of the inspection group, it is considered unqualified. m Control specifications S in different blocks of the group mi , for the local graph density D in 7 mi Determine whether it meets the specifications.

[0069] Next, further analysis is performed through an example.

[0070] First, set three constants K 0 =0.1, K 1 =1000, K 2 =0.8, DFM is design for manufacturability. These three parameters are derived from the actual situation in the production process and DFM analysis. They may be different for each process. The specific algorithms of these three parameters are not described in this article.

[0071] Next, the gate channel size in the product A layout is measured and counted, and it is found that there are two types of gate channel sizes, so the gates in the layout are divided into two categories, that is, m=2, where the channel size L of the first type of gate is 1 =0.05um, the channel size of the second type of gate is L 2 =0.2um. At the same time, the density specification S of the gate in the entire layout design specification is set to 10% during layout definition. Next, the size and control specifications of the inspection window are set for the gates of the two types of channel sizes respectively.

[0072] First, calculate the size and control specifications of the first type of gate inspection window. The channel size L of the first type of gate 1 =0.05um, according to the formula n m =[K 0 / L m ] Calculate the number of inspection groups of the first type of gate, n 1 =[0.1 / 0.05]=2, that is, the channel size is L 1 = 0.05um gate will be set up with two inspection groups, and then two inspection specifications will be formed.

[0073] Then, according to the formula t m =1 / n m Calculate the number of steps t 1 =1 / n 1 =1 / 2=0.5, that is, the two inspection groups of the first type of gates are both set with a step of 0.5.

[0074] Next, follow C mi =K 2 +(1-K 2 ) / (n m-1)*(i-1) calculates the unbalance coefficient of each inspection group. For the first inspection group, i=1, the balance coefficient of the first inspection group of the first type of gate is:

[0075] (C 1 ) 1 =K 2 +(1-K 2 ) / (n 1 -1)*(i-1)=0.8+(1-0.8) / 1*(1-1)=0.8;

[0076] For the second inspection group, i=2, the balance coefficient of the first inspection group of the first type of gate is:

[0077] (C 1 ) 2 =K 2 +(1-K 2 ) / (n 1 -1)*(i-1)=0.8+(1-0.8) / 1*(2-1)=1;

[0078] Next, follow W mi =C mi *i*t m *K 1 *L m Calculate the size and control specifications of the inspection window of the test area corresponding to each inspection group of the first type of gate. The side length of the inspection window of the test area corresponding to the first inspection group of the first type of gate is:

[0079] (W 1 ) 1 =(C 1 ) 1 *(1)i*t 1 *K 1 *L 1 =0.8*1*0.5*1000*0.05=20um; Figure 4 At this time, the size of the inspection window is 20um*20um, so the test area corresponding to the entire first type gate 310 is divided into 8*5 blocks 320, and the distribution of the graphics 330 contained in each block 320 may be different. In this way, the pattern density of each block 320 can be calculated, and then it can be determined whether the pattern density of each block 320 is qualified.

[0080] The control specifications of the test area corresponding to the first inspection group of the first type of gate are:

[0081] (S 1 ) 1 =(1)i*t 1 *S = 1 * 0.5 * 10% = 5%;

[0082] The side length of the inspection window of the test area corresponding to the second inspection group of the first type of gate is:

[0083] (W 1 ) 2 =(C 1 ) 2 *(1)i*t 1 *K 1 *L 1 =1*2*0.5*1000*0.05=50um; Figure 5 At this time, the size of the inspection window is 50um*50um, so the test area corresponding to the entire first type gate 310 is divided into 3*2 blocks 320, and the distribution of the graphics 330 contained in each block 320 may be different. In this way, the pattern density of each block 320 can be calculated, and then it can be determined whether the pattern density of each block 320 is qualified.

[0084] The control specifications of the test area corresponding to the second inspection group of the first type of gate are:

[0085] (S 1 ) 2 =(1)i*t 1 *S=2*0.5*10%=10%.

[0086] Please continue as Figure 4 and Figure 5 It can be seen that two inspection windows and control specifications are set for the first type of gates. If the inspection groups of the same type of gates are different, the number of blocks divided into the test area will be different, and the control specifications of the pattern density in each block will also be different. It is no longer a fixed and unique window size and control specification. In this way, even if it is the same type of gate, the pattern density obtained by dividing the inspection group is more accurate.

[0087] Next, the inspection window and control specifications of the test area corresponding to the second type of gate are calculated. Specifically, the channel size of the second type of gate is L 2 =0.2um, according to the formula n m =[K 0 / L m ] Calculate the number of inspection groups of the second type of gate, that is, n 2 =[0.1 / 0.2]=1, therefore, the second type of gate will set a check specification.

[0088] Then, according to the formula t m =1 / n m Calculate the number of steps for the inspection group of the second type of gate:

[0089] t 2 =1 / n2 =1 / 1=1, that is, the inspection group of the second gate is set in a step of 1.

[0090] Next, follow C mi =K 2 +(1-K 2 ) / (n m -1)*(i-1) calculates the unbalance coefficient of the inspection group of the second grid, and the balance coefficient of the inspection group of the second grid is:

[0091] C 2 =1;

[0092] Next, follow W mi =C mi *i*t m *K 1 *L m Calculate the size and control specifications of the inspection window of the inspection group of the second type of gate. The side length of the inspection window of the test area corresponding to the inspection group of the second type of gate is:

[0093] W 2 =C 2 *(2)i*t 2 *K 1 *L 2 =1*1*1*1000*0.2=200um; refer to Figure 6 At this time, the size of the inspection window is 200um*200um, so the test area corresponding to the second type of gate 410 is divided into two blocks 420 according to the size of the inspection window 200um*200um. The distribution of the graphics 430 contained in each block 420 may be different. Then, the graphic density of each block 420 is calculated, and it is determined whether the graphic density is qualified.

[0094] The control specifications of the test area corresponding to the inspection group of the second type of gate are:

[0095] S 2 =(2)i*t 2 *S = 1 * 1 * 10% = 10%;

[0096] Please continue to refer to Figure 4 ,It can be seen that the test area corresponding to the second type of gate has only one inspection window and inspection specification. Figures 2 to 4 It is a schematic diagram of a method for calculating the graphic density of different types of gates on the layout.

[0097] Then, according to step S15, the local pattern density of each block of the first type of gate and the second type of gate is calculated respectively. First, the first type of gate structure L is calculated. 1=0.05um corresponds to the local pattern density of the test area in the two inspection windows:

[0098] (W 1 ) 1 is 20um. In the inspection window of 20um*20um, the local pattern densities are: (D 1 ) 17 =0%, (D 1 ) 131 =0%, such as Figure 3 , two blocks are selected for calculation, the selected blocks are (D 1 ) 17 and (D 1 ) 131 ,The division and numbering of blocks are common techniques and will not be described here;

[0099] (W 1 ) 2 is 50um. In the inspection window of 50um*50um, the local pattern density is: (D 1 ) 22 = 8%, such as Figure 3 , one of the blocks is selected for calculation, the selected block is (D 1 ) 22 ;

[0100] Then, calculate the second type of gate channel size L 2 = Local pattern density of surrounding patterns of 0.2um in the inspection window:

[0101] W 2 is 200um. In the inspection window of 200um*200um, the local pattern density is: (D 2 ) 1 =8%.

[0102] Next, the pattern density of each block is determined according to the control specifications, and the gate channel size L is determined according to the specifications. 1 =Whether the surrounding pattern density of 0.05um meets the specification, that is, the local pattern density>10%:

[0103] In the 20um*20um inspection window, (D 1 ) 17 =0% (<10%), (D 1 ) 131 =0% (<10%), (D 1 ) 17 and (D 1 ) 131The local graphic density exceeds the control specification, and a warning alarm is required. For example, the block can be marked, for example, by color marking, such as Figure 2 D 17 Block and D 131 piece.

[0104] In the inspection window of 50um*50um, (D 1 ) 22 = 8% (< 20%) of the local graphics density exceeds the specification, and a warning alarm is required. For example, the block can be marked, for example, by color marking, such as Figure 3 D 22 piece.

[0105] Similarly, the gate channel size L is determined according to the specifications. 2 =Whether the surrounding pattern density of 0.2um meets the specification, that is, the local pattern density>20%, within the inspection window of 200um*200um, (D 2 ) 1 =8% (<10%) of the local pattern density exceeds the specification, and a warning alarm is required. For example, the block can be marked, for example, by color marking, such as Figure 4 D 1 piece.

[0106] In summary, in the local graphic density analysis method of the layout provided in the embodiment of the present invention, by classifying gates of different channel sizes, and then dividing each type of gates into several inspection groups, and finally obtaining different inspection windows and control specifications according to different inspection groups of different types of gates, the graphic density of the test area corresponding to different inspection groups of different gates on the layout is flexibly calculated, thereby obtaining a more accurate local graphic density.

[0107] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A local pattern density analysis method for a layout, used to analyze the pattern density of patterns around a plurality of gates in the layout, wherein the gates all have a test area, It is characterized in that include: The plurality of gates in the layout are divided into m categories according to the different channel sizes, where m is a positive integer; Divide each type of the gate into n inspection groups, and set the step number and unbalance coefficient of each inspection group, wherein n is a positive integer; Setting the size of the inspection window of the test area corresponding to each inspection group according to the step number, the unbalance coefficient and the channel size; Setting the control specification of the pattern density of the test area corresponding to each inspection group according to the step number; and Divide the test area corresponding to each inspection group into a plurality of blocks according to the size of the inspection window, calculate the pattern density of each block, and determine whether the pattern density of each block is qualified according to the control specification; The method of setting the unbalance coefficient of each inspection group comprises: C mi =K 2 +(1-K 2 ) / (n m -1)*(i-1); Among them, C mi is the imbalance coefficient of the i-th inspection group of the m-th type of gate, and K 2 is the set imbalance parameter, and its value is set between 0 and 1. n m is the number of inspection groups of the m-th type of gate, and the value of i is from 1 to n m .

2. The local pattern density analysis method according to claim 1, It is characterized in that The layout contains a total of m*n inspection groups.

3. The local pattern density analysis method according to claim 1, It is characterized in that The method of classifying the gates into m categories according to the difference in channel sizes includes: classifying the gates having the same channel length as the same category.

4. The local pattern density analysis method according to claim 1, It is characterized in that The method of dividing each type of the gate into n inspection groups includes: n m =[K 0 / L m ]; Among them, n m is the number of inspection groups of the mth type of gate, and K is taken 0 / L m integer; L m is the channel size of the m-th type of gate; K 0 It is a constant coefficient that is set, and its value is between 0 and 1.

5. The local pattern density analysis method according to claim 4, It is characterized in that The method for setting the step number of each inspection group includes: t m =1 / n m ; Among them, t m is the number of steps of the m-th type of gate, n m is the number of inspection groups of the mth type of gate.

6. The local pattern density analysis method according to claim 1, It is characterized in that The method for setting the size of the inspection window of the test area corresponding to each inspection group according to the step number, the unbalance coefficient and the channel size comprises: The side length of the inspection window of the test area corresponding to each inspection group is set according to the step number, the unbalance coefficient and the channel size, and the inspection window is a square.

7. The local pattern density analysis method according to claim 6, It is characterized in that The method of setting the side length of the inspection window of the test area corresponding to each inspection group according to the step number, the unbalance coefficient and the channel size includes: W mi =C mi *i*t m *K 1 *L m ; Among them, W mi is the side length of the inspection window of the test area corresponding to the i-th inspection group of the m-th type of gate, C mi is the unbalance coefficient of the i-th inspection group of the m-th type of gate, and the value of i ranges from 1 to n m , t m is the number of steps of the m-th type of gate, K 1 is the unit constant set, which is an integer multiple of 1000. m is the channel size of the mth type of gate.

8. The local pattern density analysis method according to claim 4, It is characterized in that The method for setting the control specification of the pattern density of the test area corresponding to each inspection group according to the step number includes: S mi =i*t m *S; Among them, S mi is the control specification of the pattern density of the test area corresponding to the i-th inspection group of the m-th type of gate, i ranges from 1 to n, t m is the step number of the mth type of gate, and S is the control specification of the gate density of the set layout.

9. The local pattern density analysis method according to claim 8, It is characterized in that The method for judging whether the pattern density of each block is qualified according to the control specification includes: If the pattern density of each block is lower than the control specification of the pattern density of the inspection group to which it belongs, it is considered unqualified.

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