Source driving circuit, display device and display driving method

Abstract

The present invention provides a source driving circuit, a display device and a display driving method. The source driving circuit of the embodiment of the present invention includes a serial-to-parallel conversion module, N first buffers, a second buffer, an operator and a digital-to-analog conversion module, wherein N is an integer greater than 1: the N first buffers are cascaded in sequence; the output end of the serial-to-parallel conversion module is connected to the input end of the first-level first buffer among the N first buffers; the output ends of the N first buffers are all connected to the input end of the operator; the output end of the operator is connected to the input end of the second buffer; the output end of the second buffer is connected to the input end of the digital-to-analog conversion module. The embodiment of the present invention improves the correlation between each pixel and the surrounding pixels during the display data optimization process, helps to improve the display effect, and the implementation cost is relatively low, which helps to reduce costs.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a source driving circuit, a display device, and a display driving method. Background Art

[0002] With the development of display technology, the requirements for display effects are getting higher and higher, while the quality of the display signal provided by the signal source is relatively fixed. In related technologies, the display effect can be optimized by performing resolution enhancement processing on the display data or by rendering the picture. However, this method usually optimizes the display data by adding a processor. However, the cost of this method is relatively high and the improvement of the display effect is relatively limited. Summary of the invention

[0003] The embodiments of the present invention provide a source driving circuit, a display device and a display driving method to reduce costs and improve the optimization effect on the display interface.

[0004] To solve the above problems, the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides a source driving circuit, including a serial-to-parallel conversion module, N first buffers, a second buffer, an operator, and a digital-to-analog conversion module, wherein N is an integer greater than 1:

[0006] The N first buffers are cascaded in sequence;

[0007] The output end of the serial-to-parallel conversion module is connected to the input end of the first-stage first buffer among the N first buffers;

[0008] The output ends of the N first buffers are all connected to the input end of the operator;

[0009] The output terminal of the operator is connected to the input terminal of the second buffer;

[0010] The output end of the second buffer is connected to the input end of the digital-to-analog conversion module.

[0011] In some embodiments, the number of data channels of the first buffer is less than the number of data channels of the second buffer.

[0012] In a second aspect, an embodiment of the present invention provides a display device, comprising a display panel and a source driving circuit as described in any one of the first aspects, wherein the source driving circuit is used to drive the display panel to display an image, the display panel comprises a plurality of sub-pixel columns, and the data channels of the second buffer correspond one-to-one to the sub-pixel columns.

[0013] In a third aspect, an embodiment of the present invention provides a display driving method, which is applied to the display device according to the second aspect, and the method comprises the following steps:

[0014] The serial-to-parallel conversion module converts the input first display data from a serial format to a parallel format, wherein the first display data is a digital data signal;

[0015] The N first buffers store the first display data in a parallel format, wherein the nth level first buffer among the N first buffers stores the first display data of the Mth row of pixels in the n+1th level first buffer when storing the first display data of the M+1th row of pixels, wherein n is a positive integer less than N, and M is a positive integer;

[0016] The operator generates second display data according to the first display data stored in the N first buffers, wherein the pixel data of each pixel in the second display data is generated according to the pixel data of a plurality of pixels in the first display data that are associated with each other;

[0017] The second buffer stores the second display data generated by the operator and sends it to the digital-to-analog conversion module;

[0018] The digital-to-analog conversion module converts the second display data in a digital data signal format into the third display data in an analog data signal format.

[0019] In some embodiments, the N first buffers store the first display data converted into a parallel format, including:

[0020] At the rising edge of the Kth latch signal, the Kth row of first display data in the Lth level first buffer is stored in the L+1th level first buffer, where K is a positive integer and L is a positive integer less than N.

[0021] In some embodiments, the operator generates the second display data according to the first display data stored in the N first buffers, including:

[0022] Between the rising edge of the Kth release signal and the rising edge of the K+1th latch signal, the operator generates the second display data according to the first display data stored in the N first buffers.

[0023] In some embodiments, the operator is turned on at a rising edge of a release signal and turned off at a rising edge of a latch signal.

[0024] In some embodiments, the plurality of pixels associated with the positions include a plurality of pixels located in adjacent rows and / or adjacent columns.

[0025] In some embodiments, the operator generates the second display data according to the first display data stored in the N first buffers, including:

[0026] Pixel data of the Xth row and the Yth column and pixel data of the Xth row and the 2Yth column in the second display data are generated according to the pixel data of the Xth row and the Yth column, the pixel data of the Xth row and the Y+1th column, the pixel data of the X+1th row and the Yth column, and the pixel data of the X+1th row and the Y+1th column in the first display data, where X and Y are positive integers.

[0027] In some embodiments, the operator generates the second display data according to the first display data stored in the N first buffers, including:

[0028] When a first difference between the pixel data in the Xth row and the Yth column and the pixel data in the Xth row and the Y+1th column in the first display data is greater than a preset pixel difference threshold, and a second difference between the pixel data in the X+1th row and the Yth column and the pixel data in the X+1th row and the Y+1th column is greater than the preset pixel difference threshold, use the pixel data in the Xth row and the Yth column in the first display data as the pixel data in the Xth row and the 2Yth column in the second display data;

[0029] When at least one of the first difference and the second difference is not greater than the preset pixel difference threshold, an average of the pixel data of the Xth row and Yth column and the pixel data of the Xth row and Y+1th column in the first display data is used as the pixel data of the Xth row and 2Yth column in the second display data.

[0030] The embodiment of the present invention designs a multi-level first buffer, uses the first buffer to store the first display data of multiple sub-pixels, and then reads the display data stored in the first buffer through the operator to process the display data. Since N first buffers are cascaded in sequence, the operator can read N lines of display data at the same time and generate a new line of display data based on multiple lines of display data, thereby improving the correlation between each pixel and the surrounding pixels during the display data optimization process, which helps to improve the display effect. At the same time, the technical solution of this embodiment mainly relies on the improvement of the source driving circuit, and the implementation cost is relatively low, which helps to reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0032] Figure 1It is a structural schematic diagram of a source driving circuit in the related art;

[0033] Figure 2 It is a schematic diagram of the corresponding relationship between display data and data channels in the related technology;

[0034] Figure 3 It is a timing diagram showing data transmission in the related art;

[0035] Figure 4 It is a schematic diagram showing the flow of data in the related art;

[0036] Figure 5A is a schematic structural diagram of a source driving circuit in one embodiment of the present invention;

[0037] Figure 5B is a schematic structural diagram of a source driving circuit in one embodiment of the present invention;

[0038] Figure 6 is a timing diagram showing data transmission in one embodiment of the present invention;

[0039] Figure 7 is a schematic diagram showing the flow of data in one embodiment of the present invention;

[0040] Figure 8 is a schematic diagram of generating second display data in one embodiment of the present invention;

[0041] Fig. 9 is another schematic diagram of generating second display data in one embodiment of the present invention;

[0042] Fig.10a is another schematic diagram of generating second display data in one embodiment of the present invention;

[0043] Fig.10b is another schematic diagram of generating second display data in one embodiment of the present invention;

[0044] Fig.10c is another schematic diagram of generating second display data in one embodiment of the present invention;

[0045] Fig.10d is another schematic diagram of generating second display data in one embodiment of the present invention;

[0046] Fig.11 Schematic diagram of image optimization results in one embodiment of the present invention. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] In the related art, a display device includes a display panel, a timing control board and a source driver circuit (also called a source driver IC), wherein the display panel generally includes a gate line (or signal line), a data line and a plurality of pixels, the data line is used to provide a data signal for each pixel, for example, it may be a display grayscale of the pixel, and the gate line is generally used to provide a switching signal for the pixel, thereby controlling the data line to transmit the data signal to each pixel.

[0049] Each pixel usually includes multiple sub-pixels of different colors. For example, a pixel may include three sub-pixels of red, green, and blue, or may include four sub-pixels of red, green, green, and blue, or may include four sub-pixels of red, green, blue, and white, etc. The specific structure of each pixel is not further limited here.

[0050] Each pixel is usually arranged according to a certain rule. For example, if the physical resolution of the display panel is 2a*2b, it means that there are 2a pixels in each row, which is called the horizontal resolution, and 2b pixels in each column, which is called the vertical resolution. In general, each sub-pixel is also arranged according to a certain rule. For example, a column of sub-pixels can be all green sub-pixels, and red sub-pixels and blue sub-pixels are arranged alternately in another column of sub-pixels.

[0051] The timing control board is used to provide a timing control signal to achieve timing control. The source drive circuit is used to convert the received digital data signal into an analog data signal that can drive the pixels of the display panel to display an image. In this way, under the control of the timing control signal and the converted analog data signal, the display panel can be controlled to display an image.

[0052] like Figure 1 As shown, a source driving circuit in the related art includes a serial-to-parallel conversion module, a buffer, a digital-to-analog conversion module and a power amplification module.

[0053] The timing control signal sends the display data added with the timing control signal to the source driving circuit. At this time, the display data is a serial data signal and a digital data signal.

[0054] The serial-to-parallel conversion module converts the serial data signal sent by the timing control board into a parallel data signal, and then outputs it through the output channel. Here, the number of output channels is consistent with the number of sub-pixel columns of the input signal, and the output channels correspond to the data channels of the buffer, the data channels of the digital-to-analog conversion module, the data channels of the power amplifier module, and the sub-pixel columns of the display panel.

[0055] It should be understood that, in this embodiment, the buffer digital-to-analog conversion module and the like can be understood to include multiple data channels, where each data channel can be understood to be a circuit structure for processing the first display data of a sub-pixel.

[0056] The buffer is responsible for the storage and transfer of row data, and in this embodiment specifically includes a first-level buffer and a second-level buffer.

[0057] The digital-to-analog conversion module combines the digital data signal with the analog voltage to generate an analog data signal. The power amplifier module is responsible for amplifying the output signal power. The amplified display data is output to the display panel, which can drive the display panel to display an image.

[0058] like Figure 2 As shown, an exemplary description is given by assuming that each pixel includes 3 sub-pixels and each source driver IC corresponds to Y display panel columns.

[0059] During implementation, the digital data signal of sub-pixel 1 of pixel 1 in a certain row transmitted by the timing control board is received by the serial-to-parallel conversion module channel 1 to the first-stage buffer channel 1, and then transmitted to the second-stage buffer channel 1. It is converted into an analog data signal in combination with the analog voltage at the digital-to-analog conversion module channel 1, and finally sent to the sub-pixel 1 of pixel 1 in the corresponding row of the display panel.

[0060] like Figure 3 As shown, during the working process, in the T1 period, the source driver IC and the timing control board perform initial clock training to make their clock signals consistent.

[0061] After the initial clock training is completed, the timing control board sends each row of data information in sequence.

[0062] The data information of a row generally includes the clock training information, control data information and display data of the row. The sending and control process of the clock training information and the control data information can refer to the relevant technology and is not further limited in this embodiment. In this embodiment, only the display data related content is further described later.

[0063] Please continue reading Figure 3 , the time for the timing control board to send a row of data is T2, which is also the time for the source driver IC to receive a row of data.

[0064] After the source driver IC recognizes that the control data information transmission is completed, it controls the serial-to-parallel conversion module to receive the display data. The serial-to-parallel conversion module transmits the received data to the first-level buffer in real time for latching. When the source driver IC recognizes that the display data of the first row has been received, it generates the first latch signal and sends the data in the first-level buffer to the second-level buffer. At the same time, the first-level buffer starts to prepare to receive the display data of the second row.

[0065] It should be understood that each data channel of the buffer directly connected to the serial-to-parallel conversion module corresponds to display data of a column of sub-pixels in the received display data, and the time when each data channel of the buffer corresponding to different columns of sub-pixels receives the display data is different.

[0066] In order to improve the processing effect on the display data, a first buffer and a second buffer are provided.

[0067] Specifically, different data channels of the first buffer can receive display data at different times, and then save and process the data in the first buffer. After the first buffer sends the processed display data to the second buffer, the second buffer sends the display data to the display panel at a specified time. At the same time, the first buffer can continue to receive the next line of display data, thereby reducing the possibility of interference with the storage and transmission process of the processed data and the subsequently received data.

[0068] More specifically, the latch signal is generally located in the clock training phase of the next row. In this embodiment, the latch action is triggered by the rising edge of the latch signal as an example for illustrative description.

[0069] When the source driver IC generates the first latch signal, the first release signal is also generated internally. The rising edge of the release signal is located before the rising edge of the first latch signal, which corresponds to the T4+T5 period, and the falling edge of the release signal is located after the rising edge of the first latch signal, which corresponds to the T6+T7 period.

[0070] The falling edge of the release signal will turn on the connection switch between the power amplifier module and the display panel, releasing the data signal in the second-stage buffer to the display panel. The rising edge will close the connection switch, stop the output, or simultaneously connect the display panel to a fixed intermediate voltage for charge sharing. Usually, the intermediate voltage is set to half of the maximum analog voltage used by the source driver IC.

[0071] That is to say, at the end of the T5 period, the rising edge of the latch signal triggers the latch operation, and at the end of the T6 period, the falling edge of the latch signal ends the latch operation, completing the latching of the display data. Next, at the end of the T7 period, the data signal in the second-stage buffer is released to the display panel under the control of the release signal, thereby driving the display panel to display the picture.

[0072] Therefore, the falling edge of the first release signal releases the first row display data signal in the second-stage buffer to the first row of the display panel to display it; the rising edge of the second release signal turns off the output of the first row display data signal; the time from the falling edge of the first release signal to the rising edge of the second release signal is the T8+T9 period, which is the time for maintaining the analog voltage of the first row display data on the data line of the display panel.

[0073] During the T10 period, the processing of the next row of display data begins with reference to the above process.

[0074] like Figure 4 As shown, according to the above process, each row of display data flows between the modules in the source driver IC. Here, each module refers to the above-mentioned serial-to-parallel conversion module, buffer, digital-to-analog conversion module and power amplifier module.

[0075] An embodiment of the present invention provides a source driving circuit.

[0076] like Figure 5A As shown, in one embodiment, the source driving circuit includes a serial-to-parallel conversion module, N first buffers, a second buffer, an operator and a digital-to-analog conversion module. Specifically, the N first buffers in this embodiment are Figure 5A The first-stage buffer to the N-th-stage buffer are shown, and the second buffer is the N+1-th-stage buffer.

[0077] The source driving circuit may further include a power amplification module. In this embodiment, N is an integer greater than 1, and may be 2, 3, 4, etc.

[0078] In this embodiment, the N first buffers are cascaded in sequence, and the output end of the serial-to-parallel conversion module is connected to the input end of the first-level first buffer among the N first buffers. It should be understood that the x-th level first buffer in this embodiment refers to Figure 5A The output ends of the N first buffers are all connected to the input end of the operator, the output end of the operator is connected to the input end of the second buffer, and the output end of the second buffer is connected to the input end of the digital-to-analog conversion module.

[0079] like Figure 5B As shown, in this embodiment, N is equal to 2 for exemplary description.

[0080] In this embodiment, the two first buffers are specifically Figure 5B The first-stage buffer and the second-stage buffer shown in FIG. Figure 5B The third stage buffer is shown.

[0081] The output ends of the first-stage buffer and the second-stage buffer are both connected to the input end of the operator, and the output end of the operator is connected to the third-stage buffer.

[0082] In some embodiments, the number of data channels of the first buffer may be equal to the number of data channels of the second buffer. In this case, the operator reads the pixel data associated with each pixel for optimization processing to obtain the optimized pixel data of the pixel, thereby optimizing the display effect.

[0083] In some other embodiments, the number of data channels of the first buffer is less than the number of data channels of the second buffer.

[0084] In this embodiment, compared with the first buffer, the second buffer has more data channels, so that the operator can obtain more columns of display data based on the display data in the first buffer, thereby realizing super-resolution processing of the display data and improving the display effect.

[0085] Exemplarily, if the row resolution of the display panel is 2a, that is, each row includes 2a pixels, each pixel includes three sub-pixels of different colors, then each row includes 6a sub-pixels in total, the number of data channels of the second buffer should be 6a, and the number of channels of the two first buffers should be less than 6a, and can be 3a by way of example, but not limited to this. Correspondingly, the number of output channels of the serial-to-parallel conversion module is 3a, the number of data channels of the operator is 6a, and the number of data channels of the digital-to-analog conversion module is 6a.

[0086] An embodiment of the present invention provides a display device, including a display panel and a source driving circuit of any of the above items, the source driving circuit is used to drive the display panel to display an image, the display panel includes multiple sub-pixel columns, and the data channel of the second buffer corresponds one-to-one to the sub-pixel columns. It should be understood that the display device can also control a timing control board, etc., which is not further limited or described here.

[0087] An embodiment of the present invention provides a display driving method, which is applied to the above-mentioned display device.

[0088] In one embodiment, the display driving method comprises the following steps:

[0089] The serial-to-parallel conversion module converts the input first display data from a serial format to a parallel format, wherein the first display data is a digital data signal;

[0090] The N first buffers store the first display data in a parallel format;

[0091] The operator generates second display data according to the first display data stored in the N first buffers, wherein the pixel data of each pixel in the second display data is generated according to the pixel data of a plurality of pixels in the first display data that are associated with each other;

[0092] The second buffer stores the second display data generated by the operator and sends it to the digital-to-analog conversion module;

[0093] The digital-to-analog conversion module converts the second display data in a digital data signal format into the third display data in an analog data signal format.

[0094] It should be understood that in the technical solution of this embodiment, the serial-to-parallel conversion module obtains serial first display data and then converts it into parallel first display data. In the first buffer, the second buffer, the operator, the digital-to-analog conversion module and other modules after the serial-to-parallel conversion module, the display data is processed in parallel in each data channel, and the same column of display data is processed sequentially in the data channel of each module.

[0095] In the technical solution of this embodiment, after the conversion is completed by the serial-to-parallel conversion module, it is input into N first buffers.

[0096] In this embodiment, when storing the first display data of the M+1th row of pixels, the nth level first buffer among N first buffers stores the first display data of the Mth row of pixels in the n+1th level first buffer, where n is a positive integer less than N and M is a positive integer.

[0097] It should be understood that a row of pixel data in this embodiment actually includes data of a plurality of sub-pixels included in each pixel in the row of pixels.

[0098] For example, when N is equal to 2, the first level first buffer (i.e. Figure 5B The first-stage buffer (shown as the first-stage buffer) first obtains the first row of display data in the first display data, and then the first-stage first buffer saves the first row of display data to the second-stage first buffer (i.e. Figure 5B The second-stage buffer is shown), and then the first-level first buffer obtains the second row of display data. At this time, the operator can simultaneously obtain the first row of display data and the second row of display data in the first display data from the first-level first buffer and the second-level first buffer.

[0099] The operator processes the read first row display data and second row display data to obtain second display data.

[0100] It is important to understand that Figure 1 In the embodiment shown, only one row of display data can be read and processed. Figure 1Compared with the illustrated embodiment, the present embodiment can read multiple lines of display data simultaneously, so that for one target sub-pixel, not only the display data of the target sub-pixel can be obtained, but also the display data of other sub-pixels associated with its position can be obtained, so that the display data can be optimized according to these associated sub-pixels.

[0101] It should be understood that the sub-pixel associated with the target sub-pixel position refers to the pixel corresponding to the target sub-pixel in the pixels associated with the target pixel position containing the target sub-pixel. For example, if the target sub-pixel is a red sub-pixel, the sub-pixel associated with it may be a red sub-pixel in the pixel adjacent to the red sub-pixel.

[0102] In this way, each sub-pixel in a pixel can be optimized according to the display data of the sub-pixel associated with the sub-pixel position, and it can also be understood that the pixel data of each pixel is optimized according to the display data of the pixel associated with the pixel position.

[0103] In some embodiments, the plurality of pixels associated with each other in position include a plurality of pixels located in adjacent rows and / or adjacent columns. That is, in this embodiment, the display effect can be optimized based on the pixels in adjacent rows or adjacent columns.

[0104] The calculated and generated second display data is first stored in the second buffer (ie Figure 5B The third-stage buffer is then sent by the second buffer to a subsequent digital-to-analog conversion module to convert the second display data in the format of a digital data signal into the third display data in the format of an analog data signal. The third display data can then be power amplified and processed as needed, and then the display panel is driven to display an image.

[0105] In this way, the embodiment of the present invention designs a multi-level first buffer, uses the first buffer to store the first display data of multiple sub-pixels, and then reads the display data stored in the first buffer through the operator to process the display data. Since N first buffers are cascaded in sequence, the operator can read N lines of display data at the same time and generate a new line of display data based on multiple lines of display data, thereby improving the correlation between each pixel and the surrounding pixels during the display data optimization process, which helps to improve the display effect. At the same time, the technical solution of this embodiment mainly relies on the improvement of the source driving circuit, and the implementation cost is relatively low, which helps to reduce costs.

[0106] In some embodiments, the N first buffers store the first display data converted into a parallel format, including:

[0107] At the rising edge of the Kth latch signal, the Kth row of first display data in the Lth level first buffer is stored in the L+1th level first buffer, where K is a positive integer and L is a positive integer less than N.

[0108] Exemplarily, when K is equal to 1 and L is equal to 1, at the rising edge of the first latch signal, the first display data of the first row in the first-level first buffer is stored in the second-level first buffer.

[0109] In some embodiments, the operator generates the second display data according to the first display data stored in the N first buffers, including:

[0110] Between the rising edge of the Kth release signal and the rising edge of the K+1th latch signal, the operator generates the second display data according to the first display data stored in the N first buffers.

[0111] When generating the second display data, between the rising edge of the first release signal and the rising edge of the second latch signal, the operator acquires the first display data in the N first buffer areas to generate the second display data.

[0112] In some embodiments, the operator is turned on at a rising edge of a release signal and turned off at a rising edge of a latch signal.

[0113] like Figure 6 and Figure 7 As shown, in the technical solution of this embodiment, the phase of the release signal corresponding to a row of display data corresponds to the latch signal moment of the next row. At the rising edge of the release signal, in addition to closing the connection between the power amplifier module and the display panel, the operation function of the operator is also turned on. At the rising edge of the latch signal, the data in the first buffer of the first level is sent to the first buffer of the next level and the operator is turned off.

[0114] like Figure 6 and Figure 7 As shown, specifically, at a rising edge of a latch signal, the first row of display data in the first level first buffer is stored in the second level first buffer, and the first level first buffer begins to prepare to store the second row of display data. As of the first rising edge of the release signal, that is, in the T5+T6 period, the first level first buffer has stored most of the second row of display data.

[0115] Next, at the rising edge of the first release signal, the operator starts to operate the first display data in the first-level first buffer and the second-level first buffer to obtain the second display data.

[0116] The generated second display data is directly latched into the second buffer, and all calculations and storages of the first row display data and the second row display data are completed before the rising edge of the second latch signal, that is, all calculations and storages of the first row display data and the second row display data are completed within the T7 period.

[0117] During the T7 period, the connection between the power amplifier module and the display panel is also turned off. Specifically, the external output of the third-stage buffer can be turned off, and the display panel can also be connected to a fixed intermediate voltage for charge sharing.

[0118] like Figure 7 As shown, by analogy, the rising edge of the second latch signal causes the second-level first buffer to latch the second-line display data sent by the first-level first buffer, and the first-level first buffer is ready to store the third-line data, while the operation function of the operator is turned off;

[0119] The first release signal falling edge sends the new first row display data stored in the third-stage buffer to the display panel; the second release signal rising edge turns off the data output of the third-stage buffer and turns on the operator at the same time.

[0120] It should be understood that, for the last column of pixels, since there is no next column of pixels, the processing process can be omitted and the impact on the display effect can be ignored.

[0121] The super-resolution processing of the first display data and N equals 2 are used as an example. Specifically, when N equals 2, two adjacent pixels are grouped together, and each pixel includes three sub-pixels. In this way, the first display data includes display data of 2a columns of pixels, that is, display data of 6a columns of sub-pixels. The generated second display data actually includes display data of 12a columns of sub-pixels.

[0122] In this embodiment, display data of a new column of sub-pixels is generated by display data of two adjacent columns of sub-pixels in the first display data, and the generated new column of sub-pixels is located between the above two adjacent columns of sub-pixels. In this way, the number of sub-pixel rows of the obtained second display data is the same as that of the first display data, and the number of sub-pixel columns of the obtained second display data is twice that of the first display data. Correspondingly, the number of pixel rows of the second display data is also the same as that of the first display data, and the number of pixel columns is twice that of the first display data.

[0123] It should be understood that for the last column of sub-pixels in the first display data, since there is no next column of sub-pixels, it is impossible to obtain a new column of sub-pixels in the second display data by referring to the above method. However, the last column of sub-pixels in the second display data can be obtained by other methods, such as directly copying the previous column of pixels, calculating interpolation, etc.

[0124] In some embodiments, the operator generates the second display data according to the first display data stored in the N first buffers, including:

[0125] Pixel data of the Xth row and the Yth column and pixel data of the Xth row and the 2Yth column in the second display data are generated according to the pixel data of the Xth row and the Yth column, the pixel data of the Xth row and the Y+1th column, the pixel data of the X+1th row and the Yth column, and the pixel data of the X+1th row and the Y+1th column in the first display data, where X and Y are positive integers.

[0126] like Figure 8 and Fig. 9 As shown, illustratively, in this embodiment, the data in the first-stage buffer channel 1 is used to perform calculations with the data in the second-stage buffer channel 1, the data in the first-stage buffer channel 4, and the data in the second-stage buffer channel 4, and the generated data is input to the third-stage buffer channel 1 and channel 4. The data in the first-stage buffer channel 4 is used to perform calculations with the data in the second-stage buffer channel 4, the data in the first-stage buffer channel 7, and the data in the second-stage buffer channel 7, and the generated data is input to the third-stage buffer channel 7 and channel 10. By analogy, the display data of each data channel can be obtained.

[0127] like Figure 8 As shown, the data in the first-order buffer channel 1, the data in the second-order buffer channel 1, the data in the first-order buffer channel 4, and the data in the second-order buffer channel 4 are actually the display data of the corresponding sub-pixels in four adjacent pixels at corresponding positions. In this way, the display data input to the third-order buffer channels 7 and 10 obtained based on these four display data can actually be understood as the display data of the corresponding sub-pixels in two adjacent pixels in the second display data.

[0128] By analogy, the display data of two adjacent sub-pixels in the second display data can be calculated through the display data of four adjacent sub-pixels in the first display data. Since each pixel is composed of multiple sub-pixels, Fig. 9 As shown, from the pixel level, it can be understood that the display data of two adjacent pixels in the second display data is determined by the display data of four adjacent pixels in the first display data.

[0129] It should be understood that the last column of pixels required for the second display data may be omitted, or may be generated with reference to the last column of pixels in the first display data, and the impact on the display effect may be ignored.

[0130] like Fig. 9As shown, in this embodiment, two levels of first buffers are set, wherein the first level first buffer stores the display data of pixel 2-1 and pixel 2-2, and the second level buffer stores the display data of pixel 1-1 and pixel 1-2.

[0131] During implementation, the display data of the four pixels are called to generate pixel 1-1* as the display data of the first row and first column in the second display data, and generate pixel 1-1** as the display data of the first row and second column in the second display data.

[0132] Similarly, pixels 1-2, 1-3, 2-2, and 2-3 in the first display data are called to generate pixel 1-2* as the display data of the first row and third column in the second display data and pixel 1-2** as the display data of the first row and fourth column in the second display data. And so on, the second display data can be obtained.

[0133] It should be understood that the above situation is only for setting two first buffers in this embodiment. If three first buffers are set, the display data of three rows of pixels can be stored simultaneously, and the operator can generate the second display data according to the first display data of the three rows of pixels.

[0134] During implementation, different numbers of first buffers may be set as required to achieve image optimization.

[0135] Obviously, more data channels may be set to call more columns of display data as needed. For example, three or more columns of first display data may be called to generate second display data with reference to the above process.

[0136] In some embodiments, the operator generates the second display data according to the first display data stored in the N first buffers, including:

[0137] When a first difference between the pixel data in the Xth row and the Yth column and the pixel data in the Xth row and the Y+1th column in the first display data is greater than a preset pixel difference threshold, and a second difference between the pixel data in the X+1th row and the Yth column and the pixel data in the X+1th row and the Y+1th column is greater than the preset pixel difference threshold, use the pixel data in the Xth row and the Yth column in the first display data as the pixel data in the Xth row and the 2Yth column in the second display data;

[0138] When at least one of the first difference and the second difference is not greater than the preset pixel difference threshold, an average of the pixel data of the Xth row and Yth column and the pixel data of the Xth row and Y+1th column in the first display data is used as the pixel data of the Xth row and 2Yth column in the second display data.

[0139] In one embodiment, the preset pixel difference threshold is set to 70. Obviously, the preset pixel threshold can be adjusted as needed and is not limited thereto.

[0140] The difference value of the pixel data is actually determined according to the pixel value of each sub-pixel included in the pixel.

[0141] like Figures 10a to 10d As shown, each sub-pixel in the first row of pixels can be processed in the following manner.

[0142] like Fig.10a As shown, in two adjacent rows, if the difference between the pixel values ​​of the two columns of sub-pixels is greater than 70, the pixel value of the first column of sub-pixels is copied to the newly generated 1*th column to maintain a high contrast ratio for images in different regions.

[0143] like Fig.10b As shown, in two adjacent rows, if the difference in pixel values ​​of two columns of sub-pixels is less than 70, the average of the pixel values ​​of the two columns of sub-pixels in the first row of pixels is calculated as the pixel value of the newly generated 1*th column of the first row. In this way, the image transition can be smoother.

[0144] like Fig.10c and Fig.10d As shown, in two adjacent rows, if the difference in pixel values ​​of two adjacent columns of sub-pixels in the first row is not greater than 70, then no matter what the relationship between the pixel values ​​of two adjacent columns of sub-pixels in the second row is, the average of the pixel values ​​of the two columns of sub-pixels in the first row of pixels is used as the pixel value of the newly generated sub-pixel in the 1*th column of the first row. In this way, the image transition can be smoother.

[0145] For the last row of pixels, since there is no next row of pixels, the average of the pixel values ​​of two adjacent columns can be used, or the pixel value of the previous row can be copied.

[0146] like Fig.11 As shown, through the above processing method, for areas with higher pixel value differences, their contrast can be maintained, and for areas with relatively lower pixel value differences, the transition effect of different areas can be improved, making the transition smoother.

[0147] The technical solution of this embodiment realizes super-resolution of the horizontal resolution of the display signal and improves the optimization effect of the display screen. When performing data expansion operations, the pixel data of adjacent columns and the data of adjacent rows can be included to optimize the expansion effect and improve the display quality. The total number of effective channels of each buffer in the technical solution of the embodiment of the present invention is the same as that of the conventional design, which reduces the cost increase. At the same time, the control of the newly added operator uses the original latch signal and release signal, which avoids the increase of control signals, does not increase the control difficulty, and helps to control costs.

[0148] It should be noted that it should be understood that the division of the above modules is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. And these modules can all be implemented in the form of software called by processing elements; they can also be all implemented in the form of hardware; some modules can also be implemented in the form of software called by processing elements, and some modules can be implemented in the form of hardware. For example, the determination module can be a separately established processing element, or it can be integrated in a chip of the above-mentioned device for implementation. In addition, it can also be stored in the memory of the above-mentioned device in the form of program code, and called and executed by a processing element of the above-mentioned device. The implementation of other modules is similar. In addition, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element described here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each module above can be completed by an integrated logic circuit of hardware in the processor element or instructions in the form of software.

[0149] For example, each module, unit, sub-unit or sub-module may be one or more integrated circuits configured to implement the above method, such as: one or more application specific integrated circuits (ASIC), or one or more microprocessors (digital signal processor, DSP), or one or more field programmable gate arrays (FPGA), etc. For another example, when a module above is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0150] The above is a preferred implementation of the embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display driving method, characterized in that: Applied to a display device, the display device includes a display panel and a source driving circuit, the source driving circuit is used to drive the display panel to display an image, the display panel includes a plurality of sub-pixel columns, the source driving circuit includes a serial-to-parallel conversion module, N first buffers, a second buffer, an operator and a digital-to-analog conversion module, wherein N is an integer greater than 1: the N first buffers are cascaded in sequence; the output end of the serial-to-parallel conversion module is connected to the input end of the first-level first buffer among the N first buffers; the output ends of the N first buffers are all connected to the input end of the operator; the output end of the operator is connected to the input end of the second buffer; the output end of the second buffer is connected to the input end of the digital-to-analog conversion module; the data channel of the second buffer corresponds to the sub-pixel column one by one, The method comprises the following steps: The serial-to-parallel conversion module converts the input first display data from a serial format to a parallel format, wherein the first display data is a digital data signal; The N first buffers store the first display data in a parallel format, wherein the nth level first buffer among the N first buffers stores the first display data of the Mth row of pixels in the n+1th level first buffer when storing the first display data of the M+1th row of pixels, wherein n is a positive integer less than N, and M is a positive integer; The operator generates second display data according to the first display data stored in the N first buffers, wherein the pixel data of each pixel in the second display data is generated according to the pixel data of a plurality of pixels in the first display data that are associated with each other; The second buffer stores the second display data generated by the operator and sends it to the digital-to-analog conversion module; The digital-to-analog conversion module converts the second display data in a digital data signal format into the third display data in an analog data signal format.

2. The method according to claim 1, characterized in that The N first buffers store the first display data converted into a parallel format, including: At the rising edge of the Kth latch signal, the Kth row of first display data in the Lth level first buffer is stored in the L+1th level first buffer, where K is a positive integer and L is a positive integer less than N.

3. The method according to claim 2, characterized in that The operator generates second display data according to the first display data stored in the N first buffers, including: Between the rising edge of the Kth release signal and the rising edge of the K+1th latch signal, the operator generates the second display data according to the first display data stored in the N first buffers.

4. The method according to claim 2 or 3, characterized in that: The operator is turned on at the rising edge of the release signal and turned off at the rising edge of the latch signal.

5. The method according to claim 1, characterized in that The plurality of pixels associated with the positions include a plurality of pixels located in adjacent rows and / or adjacent columns.

6. The method according to claim 5, characterized in that The operator generates second display data according to the first display data stored in the N first buffers, including: Pixel data of the Xth row and the Yth column and pixel data of the Xth row and the 2Yth column in the second display data are generated according to the pixel data of the Xth row and the Yth column, the pixel data of the Xth row and the Y+1th column, the pixel data of the X+1th row and the Yth column, and the pixel data of the X+1th row and the Y+1th column in the first display data, where X and Y are positive integers.

7. The method according to claim 6, characterized in that The operator generates second display data according to the first display data stored in the N first buffers, including: When a first difference between the pixel data in the Xth row and the Yth column and the pixel data in the Xth row and the Y+1th column in the first display data is greater than a preset pixel difference threshold, and a second difference between the pixel data in the X+1th row and the Yth column and the pixel data in the X+1th row and the Y+1th column is greater than the preset pixel difference threshold, use the pixel data in the Xth row and the Yth column in the first display data as the pixel data in the Xth row and the 2Yth column in the second display data; When at least one of the first difference and the second difference is not greater than the preset pixel difference threshold, an average of the pixel data of the Xth row and Yth column and the pixel data of the Xth row and Y+1th column in the first display data is used as the pixel data of the Xth row and 2Yth column in the second display data.

8. The method according to claim 1, characterized in that The number of data channels of the first buffer is smaller than the number of data channels of the second buffer.

Images