Shift register, gate drive circuit and display device

Abstract

The present invention discloses a shift register, including an input module, a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module and an energy storage module; the input module provides an input signal of an input signal terminal to a second node, the first output module provides a first power signal of a first power signal terminal to an output signal terminal under the voltage control of the second node, and the second output module provides a second power signal of a second power signal terminal to an output signal terminal under the voltage control of the first node. The first control module, the second control module, the third control module, the fourth control module and the energy storage module cooperate with each other to control the potentials of the first node, the third node and the fourth node. The shift register of the present invention can output a pulse signal whose waveform meets the requirements.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and in particular to a shift register, a gate driving circuit and a display device. Background Art

[0002] The gate driver on array (GOA) technology integrates the thin film transistor (TFT) gate switch circuit on the array substrate of the display panel to drive the display panel, thereby eliminating the wiring space of the bonding area and fan-out area of ​​the integrated circuit (IC), thereby achieving a narrow frame.

[0003] Oxide thin film transistors are gaining more and more attention due to their transparent materials, relatively simple manufacturing process and low process temperature. For oxide thin film transistors, new GOA circuits need to be designed to adapt to the low carrier mobility of oxide thin film transistors. Summary of the invention

[0004] In a first aspect, the present disclosure provides a shift register, comprising: an input module, a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module and an energy storage module;

[0005] An input module connected to the input signal terminal, the first clock signal terminal and the second node, and configured to provide an input signal of the input signal terminal to the second node under the control of the first clock signal of the first clock signal terminal;

[0006] A first output module, connected to the first power signal terminal, the second node and the output signal terminal, configured to provide the first power signal of the first power signal terminal to the output signal terminal under the voltage control of the second node;

[0007] A second output module, connected to the second power signal terminal, the first node and the output signal terminal, configured to provide the second power signal of the second power signal terminal to the output signal terminal under the voltage control of the first node;

[0008] A first control module is connected to the second power signal terminal, the second node and the first node, and is configured to provide the second power signal of the second power signal terminal to the first node under the voltage control of the second node;

[0009] A second control module is connected to the first clock signal terminal, the third node and the first node, and is configured to provide the first clock signal of the first clock signal terminal to the first node under the voltage control of the third node;

[0010] A third control module is connected to the input signal terminal, the second power signal terminal, the second clock signal terminal and the third node, and is configured to provide the second power signal of the second power signal terminal to the third node under the control of the input signal of the input signal terminal, and to provide the second power signal of the second power signal terminal to the third node under the control of the second clock signal of the second clock signal terminal;

[0011] a fourth control module connected to the first power signal terminal, the first clock signal terminal, the second power signal terminal, the second clock signal terminal and the fourth node, and configured to provide the first power signal of the first power signal terminal to the fourth node under the control of the first clock signal of the first clock signal terminal, and to provide the second power signal of the second power signal terminal to the fourth node under the control of the second clock signal of the second clock signal terminal;

[0012] The energy storage module includes a first capacitor, wherein two ends of the first capacitor are respectively connected to a third node and a fourth node.

[0013] In a second aspect, the present disclosure provides a gate drive circuit, comprising N cascaded shift registers SR(i); the output signal end of the kth shift register SR(k) is connected to the input signal end of the k+1th shift register SR(k+1); 1≤k≤N-1, N>1; at least one shift register SR(i) among the N shift registers adopts the above-mentioned shift register; 1≤i≤N.

[0014] In a third aspect, the present disclosure provides a display device, comprising the above-mentioned gate driving circuit.

[0015] The embodiments of the present disclosure provide a shift register, a gate drive circuit and a display device. The shift register includes an input module, a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module and an energy storage module. The input module provides an input signal of an input signal end to a second node, the first output module provides a first power signal of a first power signal end to an output signal end under the voltage control of the second node, the second output module provides a second power signal of a second power signal end to an output signal end under the voltage control of the first node, the first control module and the second control module control the voltage of the first node, the third control module controls the voltage of the third node, and the fourth control module controls the voltage of the fourth node. The cooperation of the four control modules and the energy storage module can make the node potential jump in time, thereby outputting a pulse signal with a waveform that meets the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0017] Figure 1 A schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure;

[0018] Figure 2 A schematic diagram of an equivalent circuit of a shift register provided by an embodiment of the present disclosure;

[0019] Figure 3 A schematic diagram of an equivalent circuit of another shift register provided in an embodiment of the present disclosure (including a second capacitor and a third capacitor);

[0020] Figure 4 A schematic diagram of an equivalent circuit of another shift register provided by an embodiment of the present disclosure (including the tenth transistor);

[0021] Figure 5 A signal timing diagram of a shift register provided by an embodiment of the present disclosure;

[0022] Figure 6 A schematic diagram of a cascade structure of a gate drive circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0024] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0025] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0026] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0027] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The source and drain of a transistor are symmetrical, and the functions of the "source" and "drain" are sometimes interchanged when using transistors with opposite polarities or when the current direction changes during circuit operation. In the disclosed embodiment, one of the source and the drain is referred to as the first electrode, the other of the source and the drain is referred to as the second electrode, and the gate is referred to as the control electrode.

[0028] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0029] In the following examples, the driving transistor is described as an N-type thin film transistor, and other transistors have the same or different types as the driving transistor according to the circuit design. Similarly, in other embodiments, the driving transistor may also be shown as a P-type thin film transistor. It can be understood by those skilled in the art that the technical solution of the present disclosure can also be implemented by changing the types of other transistors accordingly and inverting each driving signal and level signal (and / or performing other additional adaptive modifications).

[0030] The present disclosure provides a shift register, such as Figure 1 As shown, a shift register provided by an embodiment of the present disclosure includes: an input module 10, a first output module 20, a second output module 30, a first control module 40, a second control module 50, a third control module 60, a fourth control module 70 and an energy storage module 80;

[0031] An input module connected to the input signal terminal IN, the first clock signal terminal CK1 and the second node N2, and configured to provide an input signal of the input signal terminal to the second node under the control of the first clock signal of the first clock signal terminal;

[0032] A first output module, connected to the first power signal terminal VGH, the second node N2 and the output signal terminal OUT, configured to provide the first power signal of the first power signal terminal to the output signal terminal under the voltage control of the second node;

[0033] A second output module, connected to the second power signal terminal VGL, the first node N1 and the output signal terminal OUT, configured to provide the second power signal of the second power signal terminal to the output signal terminal under the voltage control of the first node;

[0034] A first control module connected to the second power signal terminal VGL, the second node N2 and the first node N1, and configured to provide a second power signal of the second power signal terminal to the first node under the voltage control of the second node;

[0035] A second control module is connected to the first clock signal terminal CK1, the third node N3 and the first node N1, and is configured to provide the first clock signal of the first clock signal terminal to the first node under the voltage control of the third node;

[0036] a third control module connected to the input signal terminal IN, the second power signal terminal VGL, the second clock signal terminal CK2 and the third node N3, and configured to provide the second power signal of the second power signal terminal to the third node under the control of the input signal of the input signal terminal, and to provide the second power signal of the second power signal terminal to the third node under the control of the second clock signal of the second clock signal terminal;

[0037] a fourth control module connected to the first power signal terminal VGH, the first clock signal terminal CK1, the second power signal terminal VGL, the second clock signal terminal CK2 and the fourth node N4, and configured to provide the first power signal of the first power signal terminal to the fourth node under the control of the first clock signal of the first clock signal terminal, and to provide the second power signal of the second power signal terminal to the fourth node under the control of the second clock signal of the second clock signal terminal;

[0038] The energy storage module includes a first capacitor C1, wherein two ends of the first capacitor are respectively connected to a third node and a fourth node.

[0039] The shift register provided in the above embodiment includes an input module, a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module and an energy storage module; the input module provides the input signal of the input signal end to the second node, the first output module provides the first power signal of the first power signal end to the output signal end under the voltage control of the second node, the second output module provides the second power signal of the second power signal end to the output signal end under the voltage control of the first node, the first control module and the second control module control the voltage of the first node, the third control module controls the voltage of the third node, and the fourth control module controls the voltage of the fourth node. Through the cooperation of the four control modules and the energy storage module, the node potential can jump in time, shorten the time of the rising edge and falling edge of the output pulse signal, so that the output waveform meets the requirements.

[0040] Figure 2 An equivalent circuit diagram of a shift register is provided.

[0041] like Figure 2 As shown, in some exemplary embodiments, the input module includes a first transistor T1, a control electrode of the first transistor is connected to a first clock signal terminal, a first electrode of the first transistor is connected to an input signal terminal, and a second electrode of the first transistor is connected to a second node.

[0042] like Figure 2 As shown, in some exemplary embodiments, the first output module includes a second transistor T2, the control electrode of the second transistor is connected to the second node, the first electrode of the second transistor is connected to the first power signal terminal, and the second electrode of the second transistor is connected to the output signal terminal.

[0043] like Figure 2 As shown, in some exemplary embodiments, the second output module includes a third transistor T3, the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second power signal terminal, and the second electrode of the third transistor is connected to the output signal terminal.

[0044] like Figure 2 As shown, in some exemplary embodiments, the first control module includes a fourth transistor T4, the control electrode of the fourth transistor is connected to the second node, the first electrode of the fourth transistor is connected to the second power signal terminal, and the second electrode of the fourth transistor is connected to the first node.

[0045] like Figure 2 As shown, in some exemplary embodiments, the second control module includes a fifth transistor T5, a control electrode of the fifth transistor is connected to the third node, a first electrode of the fifth transistor is connected to the first clock signal terminal, and a second electrode of the fifth transistor is connected to the first node.

[0046] like Figure 2 As shown, in some exemplary embodiments, the third control module includes a sixth transistor and a seventh transistor, the control electrode of the sixth transistor is connected to the input signal terminal, the first electrode of the sixth transistor is connected to the second power signal terminal, the second electrode of the sixth transistor is connected to the third node, the control electrode of the seventh transistor is connected to the second clock signal terminal, the first electrode of the seventh transistor is connected to the second power signal terminal, and the second electrode of the seventh transistor is connected to the third node.

[0047] like Figure 2 As shown, in some exemplary embodiments, the fourth control module includes an eighth transistor and a ninth transistor, the control electrode of the eighth transistor is connected to the first clock signal terminal, the first electrode of the eighth transistor is connected to the first power supply signal terminal, the second electrode of the eighth transistor is connected to the fourth node, the control electrode of the ninth transistor is connected to the second clock signal terminal, the first electrode of the ninth transistor is connected to the second power supply signal terminal, and the second electrode of the ninth transistor is connected to the fourth node.

[0048] Figure 3 Another equivalent circuit diagram of a shift register is provided.

[0049] like Figure 3 As shown, in some exemplary embodiments, the first output module further includes a second capacitor C2, one end of the second capacitor is connected to the control electrode of the second transistor, and the other end of the second capacitor is connected to the second electrode of the second transistor. The second capacitor is connected across the control electrode and the second electrode of the second transistor, and can stabilize the potential of the control electrode of the second transistor.

[0050] like Figure 3 As shown, in some exemplary embodiments, the second output module further includes a third capacitor C3, one end of the third capacitor is connected to the control electrode of the third transistor, and the other end of the third capacitor is connected to the first electrode of the third transistor. The third capacitor is connected between the control electrode and the first electrode of the third transistor, and can stabilize the potential of the control electrode of the third transistor.

[0051] Figure 4 Another equivalent circuit diagram of a shift register is provided.

[0052] like Figure 4As shown, in some exemplary embodiments, the first output module further includes a tenth transistor T10, the control electrode of the tenth transistor is connected to the first power signal terminal, the first electrode of the tenth transistor is connected to the second node, and the second electrode of the tenth transistor is connected to the control electrode of the second transistor. The tenth transistor is arranged between the second node and the control electrode of the second transistor to stabilize the potential of the control electrode of the second transistor.

[0053] In some exemplary embodiments, all transistors in the shift register are N-type transistors.

[0054] In some exemplary embodiments, when all transistors in the shift register are N-type transistors, a working cycle of the shift register includes the following multiple time periods: a first time period, a second time period, a third time period, a fourth time period, and a fifth time period and a sixth time period that appear alternately multiple times;

[0055] The first power signal and the second power signal are DC signals, the first power signal is a high-level signal, the second power signal is a low-level signal, the input signal is a pulse signal, and the first clock signal and the second clock signal are periodic pulse signals; the input signal is a high-level signal in the first time period and the second time period, and is a low-level signal in other time periods; the first clock signal is a low-level signal in the first time period, the third time period and the fifth time period, and is a high-level signal in the second time period, the fourth time period and the sixth time period; the second clock signal is a high-level signal in the first time period, the third time period and the fifth time period, and is a low-level signal in the second time period, the fourth time period and the sixth time period.

[0056] In some exemplary embodiments, all transistors in the shift register are oxide thin film transistors. Oxide thin film transistors have low carrier mobility, and the coordination of the four control modules and the energy storage module can make the node potential jump in time, shorten the rising and falling edge time of the output pulse signal, and make the output waveform meet the requirements.

[0057] The working process of the shift register is explained below in conjunction with the signal timing diagram.

[0058] Figure 5 The signal timing diagram of the shift register is provided. The shift register adopts Figures 2 to 4In any structure, all transistors are N-type transistors, the first power signal terminal provides a first power signal, the second power signal terminal provides a second power signal, the first clock signal terminal provides a first clock signal, the second clock signal terminal provides a second clock signal, the input signal terminal provides an input signal, and the output signal terminal provides an output signal. The first power signal and the second power signal are DC signals, the input signal is a pulse signal, the first clock signal and the second clock signal are periodic pulse signals, and the first clock signal and the second clock signal are in opposite phases.

[0059] For an N-type transistor, when the voltage of the transistor gate (control electrode) is higher than the turn-on voltage, the transistor is turned on, and when the voltage of the transistor gate is lower than the turn-on voltage, the transistor is in the cut-off state. A high-level signal is a signal higher than the turn-on voltage of the transistor, and a low-level signal is a signal lower than the turn-on voltage of the transistor. The first power supply signal is a high-level signal, and the second power supply signal is a low-level signal.

[0060] A working cycle of the shift register may include multiple time periods: a first time period (t1), a second time period (t2), a third time period (t3), a fourth time period (t4), and a fifth time period (t5) and a sixth time period (t6) that appear alternately multiple times.

[0061] (I) The first period (t1 period)

[0062] The input signal is a high level signal, the first clock signal is a low level signal, and the second clock signal is a high level signal.

[0063] The first clock signal is a low level signal, the first transistor is turned off, the second node maintains the potential of the previous period (t5), and the potential of the previous period is a low level. The potential of the second node is a low level, and the second transistor is turned off.

[0064] The input signal is a high level signal, the sixth transistor is turned on, and the second power supply signal is provided to the third node. The second clock signal is a high level signal, the seventh transistor is turned on, and the second power supply signal is provided to the third node. The second power supply signal is a low level signal, so the potential of the third node is a low level.

[0065] The first clock signal is a low level signal, and the eighth transistor is turned off. The second clock signal is a high level signal, and the ninth transistor is turned on, and the second power supply signal is provided to the fourth node. The second power supply signal is a low level signal, so the potential of the fourth node is a low level.

[0066] The second node is at a low level, and the fourth transistor is turned off. The third node is at a low level, and the fifth transistor is turned off. The first node N1 maintains the potential of the previous period (t5), and the potential of the previous period is a high level.

[0067] The potential of the first node is high, the third transistor is turned on, and the second power supply signal is provided to the output signal terminal. The second power supply signal is a low level signal, so the output signal output by the output signal terminal is a low level signal. When the third capacitor is connected between the control electrode and the first electrode of the third transistor, the first node charges the third capacitor.

[0068] (II) The second period (t2 period)

[0069] The input signal is a high level signal, the first clock signal is a high level signal, and the second clock signal is a low level signal.

[0070] The first clock signal is a high-level signal, the first transistor is turned on, and the input signal is provided to the second node. The input signal is a high-level signal, the potential of the second node jumps from a low level to a high level, the second transistor changes from cutoff to on, and the first power supply signal is provided to the output signal terminal. The first power supply signal is a high-level signal, so the output signal output by the output signal terminal jumps from a low level to a high level.

[0071] The input signal is a high level signal, the sixth transistor is turned on, and the second power supply signal is provided to the third node. The second clock signal is a low level signal, the seventh transistor is turned off. The second power supply signal is a low level signal, so the potential of the third node continues to maintain a low level.

[0072] The first clock signal is a high level signal, the eighth transistor is turned on, and the first power supply signal is provided to the fourth node. The second clock signal is a low level signal, and the ninth transistor is turned off. The first power supply signal is a high level signal, so the potential of the fourth node is a high level. The potential of the fourth node is a high level, the potential of the third node is a low level, and the fourth node charges the first capacitor.

[0073] The second node is at a high level, the fourth transistor is turned on, and the second power supply signal is provided to the first node. The third node is at a low level, and the fifth transistor is turned off. Since the second power supply signal is a low level signal, the potential of the first node jumps from a high level to a low level, and the third transistor changes from being turned on to being turned off. The potential of the third node remains at a low level, which enables the fifth transistor to reliably remain in the off state, so that the potential jump of the first node is only affected by the second node, and the jump of the potential of the second node causes the third transistor to be turned off and the second transistor to be turned on synchronously, thereby shortening the voltage rise time of the output signal.

[0074] (III) The third period (T3 period)

[0075] The input signal is a low level signal, the first clock signal is a low level signal, and the second clock signal is a high level signal.

[0076] The first clock signal is a low level signal, and the first transistor is turned off. The second node maintains the potential of the previous time period (t2), and the potential of the previous time period is a high level. The potential of the second node is a high level, the second transistor continues to remain turned on, and the output signal output by the output signal terminal continues to maintain a high level. When the second capacitor is connected across the control electrode and the second electrode of the second transistor, the second capacitor can maintain the high level of the second node.

[0077] The input signal is a low level signal, the sixth transistor is turned off. The second clock signal is a high level signal, the seventh transistor is turned on, and the second power supply signal is provided to the third node. The second power supply signal is a low level signal, so the potential of the third node continues to maintain a low level.

[0078] The first clock signal is a low level signal, and the eighth transistor is turned off. The second clock signal is a high level signal, and the ninth transistor is turned on, and the second power supply signal is provided to the fourth node. The second power supply signal is a low level signal, so the potential of the fourth node is a low level.

[0079] The potential of the second node continues to maintain a high level, and the fourth transistor continues to be turned on. The potential of the third node continues to maintain a low level, and the fifth transistor continues to be turned off. The potential of the first node continues to maintain a low level, and the third transistor continues to be turned off.

[0080] (IV) The fourth period (T4 period)

[0081] The input signal is a low level signal, the first clock signal is a high level signal, and the second clock signal is a low level signal.

[0082] The first clock signal is a high level signal, the first transistor is turned on, and the input signal is provided to the second node. The input signal is a low level signal, the potential of the second node jumps from a high level to a low level, and the second transistor changes from on to off.

[0083] The input signal is a low level signal, and the sixth transistor is turned off. The second clock signal is a low level signal, and the seventh transistor is turned off.

[0084] The first clock signal is a high-level signal, the eighth transistor is turned on, and the first power supply signal is provided to the fourth node. The second clock signal is a low-level signal, and the ninth transistor is turned off. The first power supply signal is a high-level signal, so the potential of the fourth node changes from a low level to a high level. The potential of the fourth node jumps from a low level to a high level, and under the action of the first capacitor, the potential of the third node jumps following the potential of the fourth node, and jumps from a low level to a high level.

[0085] The second node is at a low level, and the fourth transistor is turned off. The third node is at a high level, and the fifth transistor is turned on, and the first clock signal is provided to the first node. Since the first clock signal is a high-level signal, the potential of the first node jumps from a low level to a high level, the third transistor changes from being turned off to being turned on, and the second power supply signal is provided to the output signal terminal. The second power supply signal is a low-level signal, so the output signal output by the output signal terminal jumps from a high level to a low level. When the third capacitor is connected across the control electrode and the first electrode of the third transistor, the first node charges the third capacitor.

[0086] After the fourth period, the fifth period and the sixth period appear alternately several times until the current working cycle ends.

[0087] (V) Fifth period (T5 period)

[0088] The input signal is a low level signal, the first clock signal is a low level signal, and the second clock signal is a high level signal.

[0089] The first clock signal is a low level signal, and the first transistor is turned off. The second node maintains the potential of the previous period (t4), and the potential of the previous period is a low level. The potential of the second node is a low level, and the second transistor continues to be turned off.

[0090] The input signal is a low level signal, and the sixth transistor is turned off. The second clock signal is a high level signal, and the seventh transistor is turned on, and the second power supply signal is provided to the third node. The second power supply signal is a low level signal, so the potential of the third node jumps from a high level to a low level.

[0091] The first clock signal is a low level signal, and the eighth transistor is turned off. The second clock signal is a high level signal, and the ninth transistor is turned on, and the second power supply signal is provided to the fourth node. The second power supply signal is a low level signal, so the potential of the fourth node is a low level.

[0092] The potential of the second node continues to remain at a low level, and the fourth transistor continues to remain turned off. The potential of the third node jumps from a high level to a low level, and the fifth transistor changes from being turned on to being turned off. The potential of the first node maintains the potential of the previous period (t4), and the potential of the previous period is a high level. The potential of the first node is a high level, the second transistor continues to remain turned on, and the output signal of the output signal terminal remains at a low level.

[0093] (Six) The sixth period (T6 period)

[0094] The input signal is a low level signal, the first clock signal is a high level signal, and the second clock signal is a low level signal.

[0095] The first clock signal is a high level signal, the first transistor is turned on, and the input signal is provided to the second node. The input signal is a low level signal, the potential of the second node remains low, and the second transistor continues to remain off.

[0096] The input signal is a low level signal, and the sixth transistor is turned off. The second clock signal is a low level signal, and the seventh transistor is turned off.

[0097] The first clock signal is a high-level signal, the eighth transistor is turned on, and the first power supply signal is provided to the fourth node. The second clock signal is a low-level signal, and the ninth transistor is turned off. The first power supply signal is a high-level signal, so the potential of the fourth node jumps from a low level to a high level. The potential of the fourth node jumps from a low level to a high level, and under the action of the first capacitor, the potential of the third node jumps following the potential of the fourth node, and jumps from a low level to a high level.

[0098] The third node is at a high level, the fifth transistor is turned on, and the first clock signal is provided to the first node. Since the first clock signal is a high level signal, the potential of the first node continues to remain at a high level, the third transistor continues to remain turned on, and the output signal of the output signal terminal continues to remain at a low level.

[0099] like Figure 6 As shown, an embodiment of the present disclosure also provides a gate drive circuit, including N cascaded shift registers SR(i); the output signal end of the kth shift register SR(k) is connected to the input signal end of the k+1th shift register SR(k+1); 1≤k≤N-1, N>1; at least one shift register SR(i) among the N shift registers adopts the shift register in the above embodiment; 1≤i≤N.

[0100] The gate driving circuit may be connected to a pixel driving circuit of a display panel to provide various control signals, such as a row scanning signal, a reset signal, etc., to the pixel driving circuit.

[0101] The display panel includes an organic light-emitting diode (OLED) display panel.

[0102] The embodiment of the present disclosure further provides a display device, comprising the above-mentioned gate driving circuit.

[0103] The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail herein, nor should they be used as limitations on the present invention.

[0104] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted for facilitating the understanding of this application and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A shift register, comprising: An input module, a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module and an energy storage module; An input module connected to the input signal terminal, the first clock signal terminal and the second node, and configured to provide an input signal of the input signal terminal to the second node under the control of the first clock signal of the first clock signal terminal; A first output module, connected to the first power signal terminal, the second node and the output signal terminal, configured to provide the first power signal of the first power signal terminal to the output signal terminal under the voltage control of the second node; A second output module, connected to the second power signal terminal, the first node and the output signal terminal, configured to provide the second power signal of the second power signal terminal to the output signal terminal under the voltage control of the first node; A first control module is connected to the second power signal terminal, the second node and the first node, and is configured to provide the second power signal of the second power signal terminal to the first node under the voltage control of the second node; A second control module is connected to the first clock signal terminal, the third node and the first node, and is configured to provide the first clock signal of the first clock signal terminal to the first node under the voltage control of the third node; A third control module is connected to the input signal terminal, the second power signal terminal, the second clock signal terminal and the third node, and is configured to provide the second power signal of the second power signal terminal to the third node under the control of the input signal of the input signal terminal, and to provide the second power signal of the second power signal terminal to the third node under the control of the second clock signal of the second clock signal terminal; a fourth control module connected to the first power signal terminal, the first clock signal terminal, the second power signal terminal, the second clock signal terminal and the fourth node, and configured to provide the first power signal of the first power signal terminal to the fourth node under the control of the first clock signal of the first clock signal terminal, and to provide the second power signal of the second power signal terminal to the fourth node under the control of the second clock signal of the second clock signal terminal; The energy storage module includes a first capacitor, wherein two ends of the first capacitor are respectively connected to a third node and a fourth node.

2. The shift register according to claim 1, wherein: The input module comprises a first transistor, a control electrode of the first transistor is connected to a first clock signal terminal, a first electrode of the first transistor is connected to an input signal terminal, and a second electrode of the first transistor is connected to a second node; The first output module includes a second transistor, a control electrode of the second transistor is connected to the second node, a first electrode of the second transistor is connected to the first power signal terminal, and a second electrode of the second transistor is connected to the output signal terminal; The second output module includes a third transistor, a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the second power signal terminal, and a second electrode of the third transistor is connected to the output signal terminal.

3. The shift register according to claim 1, wherein: The first control module includes a fourth transistor, a control electrode of the fourth transistor is connected to the second node, a first electrode of the fourth transistor is connected to the second power signal terminal, and a second electrode of the fourth transistor is connected to the first node; The second control module includes a fifth transistor, a control electrode of the fifth transistor is connected to the third node, a first electrode of the fifth transistor is connected to the first clock signal terminal, and a second electrode of the fifth transistor is connected to the first node.

4. The shift register according to claim 1, wherein: The third control module includes a sixth transistor and a seventh transistor, the control electrode of the sixth transistor is connected to the input signal terminal, the first electrode of the sixth transistor is connected to the second power signal terminal, the second electrode of the sixth transistor is connected to the third node, the control electrode of the seventh transistor is connected to the second clock signal terminal, the first electrode of the seventh transistor is connected to the second power signal terminal, and the second electrode of the seventh transistor is connected to the third node.

5. The shift register according to claim 1, wherein: The fourth control module includes an eighth transistor and a ninth transistor, the control electrode of the eighth transistor is connected to the first clock signal terminal, the first electrode of the eighth transistor is connected to the first power supply signal terminal, the second electrode of the eighth transistor is connected to the fourth node, the control electrode of the ninth transistor is connected to the second clock signal terminal, the first electrode of the ninth transistor is connected to the second power supply signal terminal, and the second electrode of the ninth transistor is connected to the fourth node.

6. The shift register according to claim 2, wherein: The first output module further includes a second capacitor, one end of the second capacitor is connected to the control electrode of the second transistor, and the other end of the second capacitor is connected to the second electrode of the second transistor; The second output module further includes a third capacitor, one end of the third capacitor is connected to the control electrode of the third transistor, and the other end of the third capacitor is connected to the first electrode of the third transistor.

7. The shift register according to claim 2, wherein: The first output module further includes a tenth transistor, a control electrode of the tenth transistor is connected to the first power signal terminal, a first electrode of the tenth transistor is connected to the second node, and a second electrode of the tenth transistor is connected to the control electrode of the second transistor.

8. The shift register according to any one of claims 2 to 7, characterized in that: All transistors included in the shift register are oxide thin film transistors.

9. The shift register according to any one of claims 2 to 7, characterized in that: When all transistors in the shift register are N-type transistors, a working cycle of the shift register includes the following multiple time periods: a first time period, a second time period, a third time period, a fourth time period, and a fifth time period and a sixth time period that appear alternately multiple times; The first power signal and the second power signal are DC signals, the first power signal is a high level signal, the second power signal is a low level signal, the input signal is a pulse signal, and the first clock signal and the second clock signal are periodic pulse signals; The input signal is a high-level signal in the first and second time periods, and is a low-level signal in other time periods; the first clock signal is a low-level signal in the first, third and fifth time periods, and is a high-level signal in the second, fourth and sixth time periods; the second clock signal is a high-level signal in the first, third and fifth time periods, and is a low-level signal in the second, fourth and sixth time periods.

10. A gate drive circuit comprising: N cascaded shift registers SR(i); the output signal terminal of the kth shift register SR(k) is connected to the input signal terminal of the k+1th shift register SR(k+1); 1≤k≤N-1, N>1; at least one shift register SR(i) among the N shift registers adopts the shift register described in any one of claims 1 to 9; 1≤i≤N.

11. A display device, comprising: The gate drive circuit as claimed in claim 10.

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