Storage system and control method

Abstract

One embodiment of the present application realizes a storage system and a control method capable of reducing consumption of a nonvolatile memory. A controller creates a first namespace including a first logical address range and having a first attribute, in accordance with a situation where a command to create the first namespace specifying the first attribute is received from a host. The controller sets each logical address included in the first logical address range to an unallocated state in which a physical address of the nonvolatile memory is not mapped, during a first period from when a power-off advance notification is received from the host or when an abnormal power-off is detected until the controller becomes a ready state again when power is supplied to the storage system.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-11137 (filed on January 27, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to a storage system having non-volatile memory and a method for controlling the non-volatile memory. Background Technology

[0003] In recent years, storage systems with non-volatile memory have become widely used. Solid-state drives (SSDs) with NAND flash memory are one such example.

[0004] Storage devices like SSDs, capable of high-speed data input / output, are effectively utilized as swap space due to their high performance. Swap space is a storage area used to temporarily back off data swapped out from the host's memory via the operating system's swapping function. In an SSD, the following process is performed: data swapped out from the host's memory is stored non-volatilely. Thus, the swapped-out data can be cyclically retained within the SSD across its power supply cycles.

[0005] However, the swap space is required to retain stored data only while the host is powered off, similar to the volatile memory located in the host. Therefore, keeping data swapped out of the host's memory across the SSD's power cycle within the SSD results in the SSD continuously storing data that is no longer used by the host. This can lead to unnecessary consumption of the non-volatile memory within the SSD.

[0006] Therefore, there is a need for new technologies that can reduce the consumption of non-volatile memory. Summary of the Invention

[0007] One embodiment of the present invention aims to solve the problem of providing a storage system and control method capable of reducing the consumption of non-volatile memory.

[0008] According to one embodiment, a storage system capable of connecting to a host includes non-volatile memory and a controller electrically connected to the non-volatile memory. The controller creates a first namespace including a first logical address range and having the first attribute based on a command to create a first namespace specifying a first attribute received from the host. During a first period, the controller sets each logical address included in the first logical address range to an unallocated state, i.e., an unmapped physical address of the non-volatile memory. This first period is from the time the host receives a power-off warning notification or detects an abnormal power outage of the storage system until power is restored to the storage system and the controller becomes ready to process commands from the host. The power-off warning notification is a notification that foreshadows the disconnection of power supply to the storage system. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a structural example of an information processing system that includes a storage system according to the embodiments.

[0010] Figure 2 This is a diagram illustrating a structural example of a NAND flash memory within a storage system according to an embodiment.

[0011] Figure 3 This is a diagram illustrating an example structure of a logical physical address translation table managed in a storage system according to an implementation method.

[0012] Figure 4 This is a diagram used to illustrate multiple namespaces managed in the storage system involved in the implementation.

[0013] Figure 5 This is a diagram showing the namespace management table managed in the storage system involved in the implementation.

[0014] Figure 6 This is a diagram showing the block management table managed in the storage system involved in the implementation.

[0015] Figure 7 This is a diagram showing the block usage order management table managed in the storage system involved in the implementation.

[0016] Figure 8 This is a diagram used to illustrate the data written to the NAND flash memory included in the storage system according to the embodiment.

[0017] Figure 9A This is the first diagram used to explain the preparation process for restoring the logical-physical address translation table performed in the storage system involved in the implementation.

[0018] Figure 9BThis is the second diagram used to explain the preparation process for restoring the logical-physical address translation table performed in the storage system involved in the implementation.

[0019] Figure 10 This diagram illustrates the actions performed in the storage system described in the implementation, including the creation of namespaces with clear attributes and the restoration preparation process for omitting the logical-physical address translation table associated with the namespaces with clear attributes.

[0020] Figure 11 This is a diagram used to illustrate the cleanup process performed in the storage system according to the implementation method.

[0021] Figure 12 This diagram illustrates the action performed in the storage system described in the implementation, which sets the logical physical address translation table associated with a namespace having a clearing attribute to an initial state or discards it.

[0022] Figure 13 This diagram illustrates the action performed in the storage system described in the implementation, which manages blocks previously associated with namespaces having clearing attributes as free blocks.

[0023] Figure 14 This is a diagram used to illustrate the process of reformatting a namespace with cleanup attributes, which is performed on the host machine.

[0024] Figure 15 This is a flowchart illustrating the steps of a namespace creation process performed in the storage system involved in the implementation.

[0025] Figure 16 This is a flowchart illustrating the steps of the restoration preparation process performed in the storage system involved in the implementation.

[0026] Figure 17 This is a flowchart illustrating the steps of the processing performed in the storage system according to the implementation method from the time the host receives a power disconnection warning until the controller of the storage system becomes ready to resume power supply to the storage system.

[0027] Figure 18 This is a flowchart illustrating the steps of the processing performed in the storage system according to the embodiment from the detection of an abnormal power disconnection to the time when power is supplied to the storage system again and the controller of the storage system becomes ready.

[0028] Figure 19 This is a flowchart illustrating the steps of the shutdown preparation process performed in the storage system involved in the implementation.

[0029] Figure 20 This is a flowchart illustrating the steps of the suspend preparation process performed in the storage system involved in the implementation.

[0030] Figure 21 This is a flowchart illustrating the steps of a cleanup process performed in the storage system involved in the implementation.

[0031] Figure 22 This is a flowchart illustrating the steps of the processing performed in the storage system and host involved in the implementation after power is supplied to the storage system again.

[0032] Label Explanation

[0033] 1 Information processing system, 2 Host, 3 SSD, 4 Controller, 5 NAND flash memory, 6 DRAM, 7 Power supply circuit, 10 Bus, 11 Host interface, 12 CPU, 13 NAND interface, 14 DRAM interface, 15 DMAC, 16 SRAM, 17 ECC encoding / decoding unit, 21 Namespace management command processing unit, 22 I / O command processing unit, 23 Clearing processing unit, 24 Restore processing unit, 31-1 to 31-n L2P tables, 32 Namespace management table, 33 Block management table, 34 Block usage order management table. Detailed Implementation

[0034] The embodiments will now be described with reference to the accompanying drawings.

[0035] Figure 1 This is a block diagram illustrating a structural example of an information processing system 1 that includes the storage system according to the embodiments. The information processing system 1 includes a host (host device) 2 and an SSD 3.

[0036] A storage system is a semiconductor storage device configured to write data to and read data from non-volatile memory. For example, a storage system can be implemented as an SSD3 that includes NAND flash memory 5.

[0037] SSD3 can also be connected to host 2 via cable or network. Alternatively, SSD3 can be built into host 2. NVM Express can be used as the standard logical interface for connecting host 2 and SSD3. TM (NVMe TM ), Serial Attached SCSI (SAS) or Serial ATA (SATA), etc.

[0038] Host 2 is an information processing device configured to control SSD3. Examples of host 2 include personal computers, server computers, portable terminals, and in-vehicle devices.

[0039] Host 2 includes processor 101 and memory 102. Processor 101 is a CPU (Central Processing Unit) configured to control the operation of various components within host 2. Processor 101 executes software (host software) loaded into memory 102 from other storage devices or SSD 3 connected to host 2. Host software includes operating system (OS) 1011. In addition to operating system 1011, host software also includes file systems, device drivers, and applications, etc.

[0040] Memory 102 is the main memory located in host 2. Memory 102 is implemented, for example, by random access memory such as DRAM (Dynamic Random Access Memory). DRAM is a volatile memory in which the stored data is lost when the power supply is interrupted.

[0041] Operating system 1011 manages the overall resources of information processing system 1, including processor 101, memory 102, and SSD 3. In addition, operating system 1011 manages the applications (hereinafter referred to as "programs") running on host 2.

[0042] exist Figure 1 In this example, the operating system 1011 includes a process management unit 1111 and a memory management unit 1112. The process management unit 1111 manages the generation, execution, and termination of each process executed in the host 2. The memory management unit 1112, based on memory allocation requests from the process management unit 1111, executes a process of allocating a portion of the storage area within the memory 102 to a specific process.

[0043] When a program begins execution, the processing management unit 1111 within the operating system 1011 generates processing for that program. Furthermore, the processing management unit 1111 requests memory allocation from the memory management unit 1112 for the generated processing. Upon receiving the memory allocation request, the memory management unit 1112 allocates a portion of the storage area within the memory 102 to the processing. The processing management unit 1111 reads the program from the SSD3 or another storage device within the information processing system 1 and loads the program into the allocated storage area.

[0044] Here, we will explain how the contents of the storage area allocated to a certain process are written to or read from the SSD3 during the swapping-out or swapping-in process.

[0045] Upon receiving a memory allocation request from the processing management unit 1111, the memory management unit 1112 sometimes swaps out data stored in a memory area allocated to other processes to the SSD3 in order to secure the memory area allocated to that process. This swapping-out process is called swapping out. The data swapped out from memory 102 to the SSD3 is written to the non-volatile memory within the SSD3. When the temporary swapping process is executed again on the processor 101, the swapped-out data is read from the SSD3 and restored to the memory area within memory 102. This restoration process is called swapping in.

[0046] Here, swapping out and swapping in between memory 102 and SSD3 only occurs when the host 2 is powered on. After the host 2 is powered off due to the operating system 1011 being shut down, that is, after the power supply from the host 2 to the SSD3 is cut off, the data written to the SSD3 through swapping out becomes data that is no longer used by the host 2.

[0047] Similar to the data that was written to the SSD3 by being swapped out, files written to folders called "Tmp folder" (or " / Tmp directory") also become data that is no longer used by the host 2 after the power supply to the SSD3 is cut off due to the shutdown of the operating system 1011.

[0048] Next, the structure of SSD3 will be described. SSD3 includes a controller 4, non-volatile memory (e.g., NAND flash memory 5), random access memory (e.g., DRAM 6), and power supply circuitry 7.

[0049] The controller 4 controls the data writing operation of writing data to the NAND flash memory 5 based on the command received from the host 2, and the data reading operation of reading object data from the NAND flash memory 5 based on the command received from the host 2.

[0050] Controller 4 can also be implemented by circuitry such as a System-on-a-chip (SoC). The functions of controller 4 can be implemented by dedicated hardware circuitry, a processor executing programs (firmware), or any combination thereof.

[0051] Controller 4 is not limited to this, but is electrically connected to NAND flash memory 5 via NAND interface 13 conforming to Toggle NAND flash interface or Open NAND flash interface (ONFI). Controller 4 operates as a memory controller configured to control NAND flash memory 5.

[0052] The controller 4 can function as a flash translation layer (FTL), which is configured to perform data management and block management of the NAND flash memory 5.

[0053] Data management performed by the FTL includes (1) managing address translation data (mapping information) that represents the correspondence between each logical address and each physical address of the NAND flash memory 5, and (2) handling constraints on the NAND flash memory 5 (such as page-level read / write operations and block-level erase operations). The physical address corresponding to a certain logical address represents the physical storage location within the NAND flash memory 5 where data corresponding to that logical address has been written. The controller 4 uses a logical-to-physical address translation table (L2P table) to manage the mapping between each logical address and each physical address. Logical block addresses (LBAs) can be used as logical addresses.

[0054] In this embodiment, the controller 4 is configured to manage the mapping between each logical address corresponding to a namespace and each physical address of the NAND flash memory 5 by using multiple L2P tables (e.g., L2P tables 31-1 to 31-n) corresponding to multiple namespaces.

[0055] Part or all of the address translation data of each of the L2P tables 31-1 to 31-n is loaded from the NAND flash memory 5 into the DRAM 5 during the initialization process performed by the controller 4 based on the condition that power is supplied to the SSD 3.

[0056] L2P tables 31-1 to 31-n are not individually limited, but can also be implemented as hierarchical L2P tables, which include multiple tables corresponding to multiple hierarchical levels. An example of the structure of a hierarchical L2P table will be provided in [reference needed]. Figure 3 The following will describe it.

[0057] The NAND flash memory 5 includes a memory cell array comprising multiple memory cells arranged in a matrix. The NAND flash memory 5 can be either a two-dimensional or a three-dimensional flash memory.

[0058] like Figure 2 As shown, the NAND flash memory 5's memory cell array includes multiple blocks BLK0 to BLKx-1. Each block BLK0 to BLKx-1 includes multiple pages (here, pages P0 to Py-1). Each page includes multiple memory cells connected to the same word line. Blocks BLK0 to BLKx-1 are the units for data erasure operations. Pages P0 to Py-1 are the units for data write operations and data read operations, respectively.

[0059] Return to the description Figure 1 The NAND flash memory 5 is used to store multiple L2P tables 31-1 to 31-n corresponding to multiple namespaces NS#1 to NS#n, and multiple user data 41-1, ..., 41-n corresponding to multiple namespaces NS#1 to NS#n.

[0060] DRAM6 is a volatile memory. A portion of the DRAM6's storage area is used to store L2P tables 31-1 to 31-n, namespace management table 32, block management table 33, and block usage order management table 34. For details regarding namespace management table 32, block management table 33, and block usage order management table 34, please refer to... Figure 5 , Figure 6 as well as Figure 7 The following will describe it.

[0061] The power supply circuit 7 uses the power supplied from the host 2, that is, the power supply voltage Vcc, to generate a power supply voltage for driving the controller 4, a power supply voltage for driving the NAND flash memory 5, and a power supply voltage for driving the DRAM 6, and supplies the generated power supply voltages to the controller 4, the NAND flash memory 5, and the DRAM 6 respectively.

[0062] Additionally, the power supply circuit 7 communicates with the controller 4. When the power supply voltage Vcc drops below a predetermined value, the power supply circuit 7 notifies the controller 4 that the power supply to the SSD3 has been cut off (hereinafter referred to as a power disconnection detection notification). For example, if the controller 4 receives the power disconnection detection notification from the power supply circuit 7 before receiving a notification from the host 2 that the power supply to the SSD3 has been cut off (hereinafter referred to as a power disconnection warning notification), the controller 4 detects an abnormal power disconnection. An abnormal power disconnection means that the power supply to the SSD3 is suddenly cut off without prior notification that the power supply to the SSD3 will soon be cut off.

[0063] Additionally, the power supply circuit 7 may also have a power loss protection (PLP) function, enabling it to continue supplying power voltage to the controller 4, NAND flash memory 5, and DRAM 6 respectively during a predetermined period from the occurrence of an abnormal power outage. In this case, the power supply circuit 7 may, for example, be connected to a capacitor 71. When the supply of power voltage Vcc from the host 2 to the power supply circuit 7 is interrupted due to an abnormal power outage, the power supply circuit 7 uses the energy stored in the capacitor 71 to supply power voltage to the controller 4, NAND flash memory 5, and DRAM 6 respectively during the predetermined period from the occurrence of the abnormal power outage.

[0064] Next, the detailed configuration of controller 4 will be described. Controller 4 includes a host interface (host I / F) 11, a CPU 12, a NAND interface (NAND I / F) 13, a DRAM interface (DRAM I / F) 14, a direct memory access controller (DMAC) 15, static random access memory (SRAM) 16, and an error correction code (ECC) encoder / decoder 17. These host interface 11, CPU 12, NAND interface 13, DRAM interface 14, DMAC 15, SRAM 16, and ECC encoder / decoder 17 are interconnected via bus 10.

[0065] Host interface 11 is a host interface circuit configured to perform communication with host 2. Host interface circuit 11 receives various requests or notifications from host 2. Examples of various requests or notifications include power-off warning notifications, namespace creation requests (namespace creation commands), namespace deletion requests (namespace deletion commands), write requests (write commands), and read requests (read commands).

[0066] The power outage warning notification is a notification that foreshadows the potential disconnection of power supply to SSD3, as described above. Before the power supply to host 2 becomes disconnected, host 2 sends a power outage warning notification to SSD3, informing SSD3 that the power supply to SSD3 will soon be cut off.

[0067] As a power-off warning notification, for example, the ShutdownNotification specified by the NVMe standard or the STANDBY IMMEDIATE command specified by the SATA standard can be used.

[0068] Upon receiving a power-off warning notification from host 2, controller 4 performs a shutdown preparation process, which includes writing the contents of DRAM 6 (e.g., the contents of an updated L2P table) that have not yet been written to NAND flash memory 5 to NAND flash memory 5. Host 2 does not cut off power supply to SSD 3 until it is notified from controller 4 that the shutdown preparation process of SSD 3 is complete, or until a predetermined period has elapsed since the power-off warning notification was sent to SSD 3.

[0069] The namespace creation command is used to create namespaces for SSD3. The namespace deletion command is used to delete specific namespaces for SSD3.

[0070] The write command is a command that instructs the SSD3 to write data to a specific namespace. The write command specifies the namespace identifier of the namespace where the write data should be written, the starting LBA corresponding to the write data, the size of the write data (size, the number of LBAs), and the data pointer (cache address) representing the location within the memory 102 where the write data is stored.

[0071] The read command is a command used by the SSD3 to read the data it requests. The read command specifies the namespace identifier of the namespace from which the data to be read should be read, the starting LBA corresponding to the data to be read, the size of the data to be read (the number of LBAs), and the data pointer (cache address) representing the location within the memory 102 from which the data to be read should be transferred.

[0072] NAND interface 13 is configured as a NAND controller to control NAND flash memory 5 under the control of CPU 12. When NAND flash memory 5 is composed of multiple NAND flash memory chips (NAND flash memory dies), NAND interface 13 can also be connected to these NAND flash memory chips via multiple channels (Ch).

[0073] DRAM interface 14 is configured as a DRAM controller to control DRAM 6 under the control of CPU 12.

[0074] DMAC15, under the control of CPU12, performs data transfer between the host 2's memory 102 and SRAM16 (or DRAM6).

[0075] SRAM16 is a volatile memory. SRAM16 includes an internal cache 161. The internal cache 161 can also be used as a write cache for temporarily storing write data that should be written to the NAND flash memory 5.

[0076] The ECC encoding / decoding unit 17 encodes the write data when it is appropriate to write data to the NAND flash memory 5, and adds ECC as a redundancy code to the write data. When data is read from the NAND flash memory 5, the ECC encoding / decoding unit 17 uses the ECC appended to the read data to perform error correction on the data.

[0077] CPU 12 is a processor configured to control host interface 11, NAND interface 13, DRAM interface 14, DMAC 15, SRAM 16, and ECC encoding / decoding unit 17. CPU 12 performs various processes by loading a control program (firmware) stored in NAND flash memory 5 or ROM (not shown) into SRAM 16 (or DRAM 6) and then executing the firmware.

[0078] CPU 12 can function as a namespace management command processing unit 21, an I / O command processing unit 22, a clearing processing unit 23, and a recovery processing unit 24. Some or all of these namespace management command processing units 21, I / O command processing units 22, clearing processing units 23, and recovery processing units 24 can also be implemented by dedicated hardware within the controller 4.

[0079] The namespace management command processing unit 21 creates namespaces based on namespace creation commands received from host 2 and manages the created namespaces. The namespace management command processing unit 21 is capable of creating and managing multiple namespaces. These multiple namespaces are independent logical address ranges. The multiple namespaces are used to make a single storage device function as multiple storage devices. The multiple namespaces are used by host 2 for accessing the SSD3.

[0080] In addition, based on the namespace deletion command received from host 2, the namespace management command processing unit 21 deletes the namespace specified by the namespace deletion command.

[0081] In this embodiment, the namespace management command processing unit 21 is configured to create and manage namespaces with a clear attribute. A namespace with a clear attribute is a namespace that allows data associated with the logical address range of that namespace to be invalidated after the power supply to the SSD3 is disconnected. In other words, a namespace with a clear attribute is a namespace that does not require the retention of data written to it across the SSD3's power cycle.

[0082] The process of disconnecting the power supply from host 2 to SSD3 and then reconnecting the power supply from host 2 to SSD3 is equivalent to one power cycle of SSD3.

[0083] When the power supply to SSD3 is temporarily disconnected, even if power is restored to SSD3, data written by host 2 to the namespace with the clear attribute before the power supply to SSD3 was disconnected will no longer be accessible to host 2. Data written to the namespace with the clear attribute is only retained during the period when power is supplied to SSD3, that is, only during the period when host 2's power state is in a working state capable of executing host software (power-on state).

[0084] The namespace management command processing unit 21 supports a new namespace creation command that can specify the clearing attribute. This new namespace creation command includes a parameter specifying whether the namespace to be created should have a clearing attribute or a non-clearing attribute. This parameter is set by the host 2 to either a value representing the clearing attribute or a value representing the non-clearing attribute.

[0085] Upon receiving a namespace creation command specifying a clear attribute from host 2—that is, a namespace creation command including parameters set to represent the clear attribute value—namespace management command processing unit 21 creates a namespace with the clear attribute and sends the namespace identifier of the created namespace to host 2. Furthermore, namespace management command processing unit 21 manages the created namespace identifier in association with attribute information representing the clear attribute by using namespace management table 32.

[0086] Host 2 can use namespaces with clear attributes as write destination namespaces for data that do not need to be retained across the power cycle of SSD3, such as swap space.

[0087] When the namespace creation command without specifying a clear attribute is received from host 2, that is, a namespace creation command that includes a parameter set to represent a non-clear attribute, the namespace management command processing unit 21 creates a namespace with a non-clear attribute. A namespace with a non-clear attribute is a namespace for which data associated with a logical address range needs to be maintained across the power cycles of the SSD3. Furthermore, the namespace management command processing unit 21 manages the namespace identifier of the created namespace by associating it with attribute information representing the non-clear attribute using the namespace management table 32.

[0088] Host 2 can use a namespace with non-purge properties as a write destination namespace for data that needs to be persisted across the power cycle of SSD3.

[0089] The I / O command processing unit 22 processes various I / O commands received from the host 2. I / O commands include write commands, read commands, etc.

[0090] When the controller 4 receives a write command specifying a certain namespace identifier from the host 2, the I / O command processing unit 22 performs a process of writing the data associated with the received write command into the NAND flash memory 5. In this case, the I / O command processing unit 22 allocates a write destination block for a specific namespace identified by the namespace identifier specified by the received write command. Then, the I / O command processing unit 22 writes the data associated with the received write command into the write destination block. Furthermore, if the write destination block for the specific namespace has already been allocated, there is no need to perform a process of reallocating the write destination block. The I / O command processing unit 22 also updates the L2P table associated with the specific namespace so that the physical address representing the physical storage location in the NAND flash memory 5 where the data has been written is mapped to the logical address corresponding to the data. The L2P table associated with the specific namespace is used to manage the mapping between each logical address within the logical address range of the specific namespace and each physical address in the NAND flash memory 5.

[0091] When the controller 4 receives a read command from the host 2 specifying a certain namespace identifier, the I / O command processing unit 22 refers to the L2P table associated with the namespace specified by the namespace identifier and obtains the physical address of the LBA mapped to the read target data specified by the received read command. The I / O command processing unit 22 reads the data stored at the physical storage location in the NAND flash memory 5 represented by the obtained physical address. Furthermore, the I / O command processing unit 22 returns the read data as read target data to the host 2.

[0092] The cleaning processing unit 23 performs cleaning processing on namespaces with cleaning attributes. The cleaning processing is performed from the time the controller 4 receives a power disconnection warning notification from the host 2 or detects an abnormal power disconnection until the controller 4 becomes ready to process commands and resumes power supply to the SSD 3.

[0093] The cleanup process involves setting the logical addresses within the logical address range of the namespace with the cleanup attribute to an unallocated state, meaning they are all unmapped physical addresses. Through this cleanup process, all data associated with the logical address range of the namespace with the cleanup attribute becomes invalid data. Therefore, the namespace with the cleanup attribute becomes in the same state as a newly created namespace that has not yet been written to. Consequently, all blocks associated with the namespace with the cleanup attribute become free blocks containing no valid data.

[0094] Therefore, by using a namespace with clearing properties as a destination for data that does not need to be retained across the power cycle of the SSD3, such as a swap area, it is possible to prevent the physical storage area within the NAND flash memory 5 from being wasted by data that does not need to be retained across the power cycle of the SSD3.

[0095] The cleaning process unit 23 may perform cleaning processes, for example, during the period from when power is supplied to the SSD3 again until the controller 4 becomes ready.

[0096] Alternatively, the clearing unit 23 may perform clearing processing based on the controller 4 receiving a power-off warning notification from the host 2, or based on the controller 4 detecting an abnormal power-off. In the case where the clearing unit 23 performs clearing processing based on the controller 4 receiving a power-off warning notification from the host 2, or based on the controller 4 detecting an abnormal power-off, the clearing unit 23 preferably writes information indicating that the clearing processing is complete as clearing processing status information to the NAND flash memory 5 upon completion of the clearing processing. Thus, after power is supplied to the SSD 3 again, the clearing unit 23 can determine whether the clearing processing for the namespace with clearing attributes has been completed normally.

[0097] In cases where the cleanup process is performed from the time power is restored to the SSD3 until the controller 4 becomes ready, the cleanup process unit 23 does not need to perform the cleanup process when the controller 4 receives a power-off warning notification from the host 2 or when the controller 4 detects an abnormal power-off. Therefore, for example, the time required from receiving the power-off warning notification from the SSD3 until the SSD3 transitions to a state where it can be safely shut down can be shortened. Furthermore, the process of writing status information indicating whether the cleanup process is complete to the NAND flash memory 5 is also unnecessary. Therefore, compared to the case where the cleanup process is performed based on the receipt of a power-off warning notification or the detection of an abnormal power-off, the amount of processing required by the controller 4 can be reduced.

[0098] In order to set each logical address included in a namespace with a clearing attribute (e.g., namespace NS#1) to an unallocated state, the clearing processing unit 23 can set the L2P table 31-1 corresponding to the namespace with the clearing attribute NS#1 to an initial state. The L2P table 31-1 being in an initial state means that a specific value (e.g., an initial value) used to represent the unallocated state is stored in the L2P table 31-1 as address translation data.

[0099] Alternatively, instead of setting the L2P table 31-1 corresponding to the namespace NS#1 with the cleanup attribute to the initial state, the cleanup processing unit 23 may discard the L2P table 31-1 corresponding to the namespace NS#1 with the cleanup attribute, thereby setting the logical addresses included in the namespace NS#1 to the unallocated state. In this case, the cleanup processing unit 23 may also generate a new L2P table in the initial state and allocate the generated table as a new L2P table 31-1 for the namespace NS#1.

[0100] When L2P table 31-1 is implemented as a hierarchical L2P table that includes multiple tables corresponding to multiple hierarchical levels, the clearing processing unit 23 can easily set the logical addresses included in namespace NS#1 to an unallocated state by setting only the table of the highest hierarchical level among the multiple hierarchical levels in the hierarchical L2P table to an initial state or discard it.

[0101] As a standard specification for power control of systems such as computers, the Advanced Configuration and Power Interface (ACPI) method is known. In the ACPI method, the system's power states are defined as system states (S0 to S5), and the device's power states are defined as device power states (D0 to D3). In the following description, without limitation, examples of power states specified in the ACPI method are given for both host 2 and SSD3.

[0102] When the power state of host 2, that is, the system power state, changes from the working state (S0 state) to the paused state (S3 state or S4 state), host 2 sends an indication to SSD3 to change the current power state of SSD3 (that is, the current device power state of SSD3) from the on state (D0 state) to a low power state (e.g., D1 state, D2 state or D3 state) corresponding to the paused state (S3 state or S4 state) of host 2 (hereinafter referred to as pause indication).

[0103] Here, the working state (S0 state) is the state in which the processor 101 executes commands and can perform read and write operations on the memory 102. As a pause state, a sleep state (S3 state) or a hibernation state (S4 state) can be used. In the sleep state (S3 state), almost all components within the host 2, except for the memory 102, are powered off. On the other hand, in the hibernation state (S4 state), with the contents of the memory 102 stored as a hibernation file in a non-clearable namespace within the SSD 3, almost all components within the host 2, including the memory 102, are powered off.

[0104] Based on the status of receiving the pause instruction from host 2, controller 4 changes the current power state of SSD3 from the ON state (D0 state) to the low power state (D1 state, D2 state, or D3 state).

[0105] The ON state (D0 state) is when power is supplied to the SSD3 and the SSD3 can execute commands. The D1, D2, or D3 states are power states that consume less power than the ON state (D0 state). In the D3 state, virtually no command processing is performed. In the D3 state, power to the SSD3 is disconnected. In the D1 and D2 states, to reduce the SSD3's power consumption, for example, while maintaining the state of power supply to the SSD3, power supply to at least a portion of the SSD3's components, such as DRAM6, is disconnected.

[0106] For example, when the power state of host 2 changes from active state (S0 state) to sleep state (S3 state), host 2 can also send a pause instruction to SSD3 to change the current power state of SSD3 from D0 state to D1 state or D2 state. In this case, the current power state of SSD3 changes from D0 state to D1 state or D2 state.

[0107] Additionally, for example, when the power state of host 2 changes from active state (S0 state) to hibernation state (S4 state), host 2 can also send a pause instruction to SSD3 to change the current power state of SSD3, for example, from D0 state to D3 state. In this case, the current power state of SSD3 changes from D0 state to D3 state.

[0108] Additionally, when the power state of host 2 is restored from the suspended state to the working state and the operating system 1011 resumes processing, host 2 sends an instruction to SSD3 to restore the current power state of SSD3 from the low power state (e.g., D1 state, D2 state, or D3 state) to the working state (D0 state) (hereinafter referred to as the resume instruction).

[0109] During the period when SSD3 is in state D3, the supply of power voltage Vcc to SSD3 is stopped. Therefore, when the current power state of SSD3 is restored from state D3 to state D0, host 2 also starts supplying power voltage Vcc to SSD3, thereby resuming the supply of power (power voltage Vcc) to SSD3.

[0110] Based on the restart instruction received from host 2, controller 4 changes the current power state of SSD3 from low power state (D1 state, D2 state, or D3 state) to on state (D0 state).

[0111] When the power state of host 2 resumes from the suspended state to the working state, the operating system 1011 sometimes causes the data that was swapped to SSD3 before returning to the suspended state to memory 102.

[0112] Therefore, if a pause instruction is received from host 2, or a restart instruction is received from host 2, the clearing processing unit 23 does not perform clearing processing. As a result, SSD3 can continue to retain the data written to the namespace with the clearing attribute. Thus, host 2 can normally read the data that was swapped out to SSD3 before it entered the pause state.

[0113] The recovery processing unit 24 performs the process of loading the L2P table from the NAND flash memory 5 to the DRAM 6, the shutdown preparation process, the recovery process for recovering the L2P table, and the preparation process for the recovery process, namely the recovery preparation process.

[0114] After power is supplied from host 2 to SSD 3, recovery processing unit 24 loads the address translation data included in each of the L2P tables 31-1 to 31-n stored in NAND flash memory 5 into DRAM 6. In this case, recovery processing unit 24 does not necessarily need to load the entire address translation data included in each L2P table into DRAM 6; it may load only a portion of the address translation data included in each L2P table into DRAM 6. When data is written to a certain namespace, I / O command processing unit 22 updates the address translation data stored in DRAM 6 corresponding to that namespace, so that the physical address where the data was written is mapped to the logical address corresponding to that data. In this way, the address translation data of each of L2P tables 31-1 to 31-n is updated in DRAM 6.

[0115] Regarding the L2P tables corresponding to the namespaces with non-clear attributes, the recovery processing unit 24 performs shutdown preparation processing upon receiving a power-off warning notification from the host 2 via the controller 4. During this shutdown preparation processing, the recovery processing unit 24 writes updated address translation data from the DRAM 6 that has not yet been reflected in the L2P tables stored in the NAND flash memory 5 to the NAND flash memory 5. Thus, before the power supply to the SSD 3 is disconnected, updated address translation data from the DRAM 6 that has not yet been reflected in the L2P tables stored in the NAND flash memory 5 can be reflected in the L2P tables stored in the NAND flash memory 5. Furthermore, when the power circuit 7 has a PLP function, the recovery processing unit 24 can also perform shutdown preparation processing for the L2P tables corresponding to the namespaces with non-clear attributes when the controller 4 detects an abnormal power-off.

[0116] Regarding the L2P tables corresponding to the namespaces with clearing attributes, the recovery processing unit 24 omits the execution of the shutdown preparation process. That is, when the controller 4 receives a power-off warning notification from the host 2, the recovery processing unit 24 does not write the updated address translation data in the DRAM 6, which has not yet been reflected in the L2P tables stored in the NAND flash memory 5, to the NAND flash memory 5. When the power supply circuit 7 has a PLP function, when the controller 4 detects an abnormal power-off, the recovery processing unit 24 also omits the execution of the shutdown preparation process for the L2P tables corresponding to the namespaces with clearing attributes.

[0117] In this way, by omitting the execution of the close preparation process for the L2P tables corresponding to each namespace with the clear attribute, compared to the configuration of executing the close preparation process for all L2P tables corresponding to all namespaces, the amount of writes to the NAND flash memory 5 can be reduced.

[0118] In the event of an abnormal power outage, the closing preparation process for the L2P tables corresponding to each namespace with the non-clear attribute may not execute properly, resulting in the loss of the latest L2P table content for each namespace with the non-clear attribute. In this case, after power is restored to the SSD3 following the abnormal power outage, the recovery processing unit 24 performs recovery processing to restore the L2P tables corresponding to each namespace with the non-clear attribute. The recovery processing unit 24 does not perform recovery processing to restore the L2P tables corresponding to each namespace with the clear attribute. For details regarding the recovery processing, please refer to [link to relevant documentation]. Figures 9A-9B The following will describe it.

[0119] In addition, during the period when SSD3 is in the on state (D0 state), the recovery processing unit 24 only performs recovery preparation processing for the L2P tables corresponding to the namespaces with non-clear attributes, and does not perform recovery preparation processing for the L2P tables corresponding to the namespaces with clear attributes.

[0120] In the restoration preparation process for L2P tables corresponding to namespaces with non-clearing attributes, the restoration processing unit 24 performs the following processing.

[0121] The recovery processing unit 24 performs the following actions: (1) at each checkpoint, writing updated address translation data from DRAM 6 that has not yet been reflected in the L2P table stored in NAND flash memory 5 to NAND flash memory 5; and (2) at each checkpoint, writing the sequence number assigned to the block currently allocated as the write destination block for that namespace into NAND flash memory 5 as information for determining the block group for recovery processing of the L2P table used for that namespace. For details regarding the recovery preparation process, please refer to [link to relevant documentation]. Figures 9A-9B The following will describe it.

[0122] Regarding the L2P table corresponding to the namespace with the clearing attribute, the restoration processing unit 24 does not perform restoration preparation processing.

[0123] That is, regarding the L2P table corresponding to the namespace with the clearing attribute, the recovery processing unit 24 does not perform the recovery preparation process, which includes: (3) writing updated address translation data in the DRAM 6 that has not yet been reflected in the L2P table stored in the NAND flash memory 5 to the NAND flash memory 5 at each checkpoint; and (4) writing the sequence number assigned to the block currently assigned as the write destination block for the namespace to the NAND flash memory 5 as information for determining the block group for the recovery process of the L2P table used for the namespace at each checkpoint.

[0124] In this way, by omitting the execution of the restoration preparation process for the L2P table corresponding to the namespace with the clear attribute, the load on controller 4 can be reduced compared to the configuration of executing the restoration preparation process for all L2P tables corresponding to all namespaces.

[0125] Next, the structure of the address translation table will be explained. Figure 3 This is a diagram illustrating an example of the structure of the address translation table managed in the SSD3 according to the implementation method.

[0126] L2P tables 31-1 to 31-n can each be implemented as a single-level L2P table without hierarchical structure or a hierarchical L2P table with hierarchical structure. Figure 3 The paper envisions the case where L2P table 31-1, corresponding to namespace NS#1, is implemented as a hierarchical L2P table.

[0127] The L2P table 31-1, implemented as a hierarchical L2P table, includes multiple tables corresponding to multiple hierarchical levels. The number of hierarchical levels can be any number of two or more, but this example illustrates the case where the number of hierarchical levels is three.

[0128] L2P table 31-1 includes lower table T1-1, upper table T1-2, and uppermost table T1-3.

[0129] The lower-level table T1-1 is used to manage the various physical addresses within the NAND flash memory 5 where data received from host 2 has been written. The logical address range of namespace NS#1 is further divided into multiple ranges. Each range includes a specific number of consecutive logical addresses (LBAs). For example, lower-level table T1-1 includes the same number of address translation data as these multiple ranges. In the case where the logical address range of namespace NS#1 is divided into 128 ranges, each including 32 LBAs, lower-level table T1-1 includes 128 address translation data called segments, namely segments #0, #1, ..., #96, ..., #127.

[0130] A segment of the lower-level table T1-1 includes 32 physical addresses corresponding to 32 consecutive LBAs as mapping information. Each segment belonging to the lower-level table T1-1 is also called a lower-level segment. The logical address range covered by a lower-level segment is equivalent to 32 LBAs.

[0131] The upper-level table T1-2 is used to manage the physical addresses within the NAND flash memory 5, where each lower-level segment is written. The upper-level table T1-2 also includes multiple address translation data called segments, such as segments #0, #1, ..., #3.

[0132] A segment of the upper-level table T1-2 represents, for example, 32 locations (physical storage locations) within a NAND flash memory 5 that stores 32 consecutive lower-level segments. Each segment of the upper-level table T1-2 represents the location of these 32 lower-level segments; therefore, the total number of segments included in the upper-level table T1-2 is 1 / 32 of the total number of lower-level segments. The logical address range covered by a segment of the upper-level table T1-2 is equivalent to 32 × 32 LBAs. Each segment of the upper-level table T1-2 is also called an upper-level segment.

[0133] The topmost table T1-3 includes address translation data called a segment. The segment of the topmost table T1-3 represents the location (physical storage location) within the NAND flash memory 5 that stores all the topmost segments #0, #1, ..., #3. That is, the segment of the topmost table T1-3 includes four pointers (pointers 0, 1, 2, and 3) corresponding to the topmost segments #0, #1, ..., #3 respectively. These four pointers represent the location of their respective topmost segments. The logical address range covered by the segment of the topmost table T1-3 is equivalent to 4 × 32 × 32 LBAs. The segment of the topmost table T1-3 is called the topmost segment or the root table.

[0134] Thus, the logical address range covered by a topmost segment is larger than the logical address range covered by a top-level table segment. Furthermore, the logical address range covered by a top-level table segment is larger than the logical address range covered by a bottom-level table segment.

[0135] Therefore, controller 4 can set the 32 entries in the upper segment #0 to specific values ​​indicating an unallocated state simply by setting them individually, thus setting the 32×32 LBAs corresponding to upper segment #0 to an unallocated state. Alternatively, instead of setting specific values ​​for each of the 32 entries in upper segment #0, controller 4 can set the value of pointer 0 in the uppermost segment to a specific value indicating an unallocated state. In this case, the 32×32 LBAs corresponding to upper segment #0 can also be set to an unallocated state.

[0136] In the cleanup process of namespace NS#1, controller 4, for example, sets the four pointers within the topmost segment to specific values ​​representing an unallocated state. This allows all LBAs included in namespace NS#1 to be easily set to an unallocated state. Alternatively, controller 4 can discard the topmost segment itself. In this case, all LBAs included in namespace NS#1 can also be set to an unallocated state. Even after discarding the topmost segment, controller 4 can create a new topmost segment and use it as the topmost table of the L2P table for namespace NS#1 for reallocation.

[0137] Figure 4 This is a diagram used to illustrate the multiple namespaces managed in the SSD3 described in the implementation.

[0138] exist Figure 4 The example illustrates the scenario where namespaces NS#1, NS#2, ..., NS#n are managed by controller 4 of SSD3. Each namespace is identified by a namespace identifier (NSID).

[0139] Each namespace comprises a contiguous set of logical addresses (LBAs). The logical address range corresponding to each namespace begins with LBA0. Each namespace can be set to any size. The size of each namespace corresponds to the number of LBAs it contains.

[0140] exist Figure 4 The following examples illustrate the situation: Namespace NS#1 contains i+1 consecutive LBAs from LBA0 to LBAi, namespace NS#2 contains j+1 consecutive LBAs from LBA0 to LBAj, and namespace NS#n contains k+1 consecutive LBAs from LBA0 to LBAk.

[0141] Namespace management table 32 is used to manage the information associated with these namespaces.

[0142] Figure 5 This is a diagram illustrating the namespace management table 32 managed in the SSD3 described in the implementation. In the namespace management table 32, for each created namespace, the namespace identifier, the clearing identifier, and the namespace size are managed as namespace information.

[0143] The Namespace Identifier (NSID) for each namespace is an identifier used by Controller 4 for accessing each namespace. The clearing identifier is an identifier indicating whether the corresponding namespace has a clearing attribute. The clearing identifier is used as attribute information to indicate either the clearing attribute or the non-clearing attribute. For example, a clearing identifier set to "1" indicates that the corresponding namespace has a clearing attribute. On the other hand, a clearing identifier set to "0" indicates that the corresponding namespace has a non-clearing attribute.

[0144] exist Figure 5 The example illustrates the following: the namespace NS#1, which is assigned the namespace identifier NSID1, and the namespace NS#n, which is assigned the namespace identifier NSIDn, have clear attributes, while the namespace NS#2, which is assigned the namespace identifier NSID2, does not have clear attributes (it has non-clear attributes).

[0145] The size of a namespace is represented by the number of logical addresses (LBAs) included in the logical address range of the corresponding namespace.

[0146] Next, the block management in the SSD3 involved in the implementation method will be explained.

[0147] When the controller 4 receives a write command from the host 2, the I / O command processing unit 22 determines the namespace of the write destination based on the namespace identifier included in the write command. The write destination blocks currently allocated to each namespace are managed by the block management table 33. For example... Figure 6 As shown, in the block management table 33, the active block lists 331-1, 331-2, ..., 331-n corresponding to the namespaces NS#1, NS#2, ..., NS#n are managed respectively.

[0148] In each of the active block lists 331-1, 331-2, ..., 331-n, the block identifiers of the active blocks containing valid data in their respective namespaces are managed. The block identifier of the write destination block currently allocated to the corresponding namespace in each of the active block lists 331-1, 331-2, ..., 331-n is also managed as one of the block identifiers of the active block.

[0149] Valid data refers to data associated with a logical address. For example, data stored at a physical address referenced by an L2P table (i.e., data associated with the logical address as the latest data) is valid data. Valid data is data that may be read by host 2 later. Blocks containing at least one valid data are managed as active blocks.

[0150] Invalid data refers to data that is not associated with any logical address. For example, data stored at a physical address that is not referenced by any L2P table is invalid data. Invalid data is data that can no longer be read by host 2. When updated data associated with a certain logical address is written to NAND flash memory 5, the data previously associated with that logical address becomes invalid data, and the updated data becomes valid data. Furthermore, if a namespace is cleared, all valid data previously associated with logical addresses in that namespace becomes invalid data.

[0151] The block identifiers of blocks that do not contain valid data are managed by the free block list 332 as the block identifiers of free blocks.

[0152] The following describes the writing to namespace NS#2 and the management of blocks allocated to namespace NS#2. The same process applies to other namespaces.

[0153] The active block list 331-2 is a list that manages the block identifiers of each active block associated with namespace NS#2. For example, if the controller 4 receives a write command from the host 2 that includes the namespace identifier (NSID2) of namespace NS#2, the I / O command processing unit 22 writes the write data associated with the write command to the next writable page in the write destination block allocated to namespace NS#2. Furthermore, the I / O command processing unit 22 updates the L2P table 31-2 associated with namespace NS#2 so that the physical address in the NAND flash memory 5 where the write data has been written is associated with the logical address corresponding to the write data.

[0154] When writing subsequent data to a write destination block, if there are no pages available to write to that write destination block, the I / O command processing unit 22 selects any free block from the free block list 332 and reassigns the selected free block as a write destination block for the namespace NS#2.

[0155] When a new block is allocated as a write destination block for namespace NS#2, controller 4 assigns a sequence number to the new block. The sequence number is a number that indicates the order in which the block was allocated as a write destination block for namespace NS#2.

[0156] Figure 7 This is a diagram showing the block usage order management table 34 managed in the SSD3 involved in the implementation.

[0157] The block usage order management table 34 manages the correspondence between the block identifiers of the blocks allocated for the write destination blocks of that namespace and the sequence numbers assigned to these blocks.

[0158] Here, we will focus on the block usage sequence management table 341-2 associated with namespace NS#2 for explanation. First, namespace NS#2 is created. When a write command associated with namespace NS#2 is received for the first time, controller 4 selects any free block (e.g., block BLK1) from free block list 332 and assigns block BLK1 as the write destination block for namespace NS#2. At this time, controller 4 assigns sequence number 1 to block BLK1.

[0159] After writing data to block BLK1 and finding that no pages are available to write to block BLK1, controller 4 selects block BLK3 from free block list 332, for example, and assigns block BLK3 as the write destination block for namespace NS#2. Furthermore, controller 4 assigns sequence number 2 to block BLK3.

[0160] By repeating this action, controller 4 assigns sequence numbers 3 and 4 to block BLK0, which is allocated as the next write destination block for namespace NS#2, and block BLK2, which is further allocated as the next write destination block.

[0161] Therefore, in the block usage order management table 341-2, BLK1, BLK3, BLK0, and BLK2 are managed as the block identifiers of the blocks assigned sequence numbers 1, 2, 3, and 4, respectively.

[0162] Figure 8 This diagram illustrates the data written to the NAND flash memory 5 included in the SSD3 according to the embodiment.

[0163] Here, we will illustrate an example of data written to block BLK1. Figure 8 In the block BLK1, each line represents a page, numbered from top to bottom as page 0, page 1, ..., page y-1.

[0164] In each page, for example, four data items, each with a size of 4 KiB, are stored together with four logical addresses (LBAs) corresponding to these four data items. For example, the four data items written to page 0 correspond to LBA16, LBA17, LBA18, and LBA20, respectively. Controller 4 can read the four data items and the four LBAs corresponding to these four data items from each page in block BLK1, thereby obtaining the four LBAs corresponding to the four physical addresses where these four data items are written. Alternatively, instead of storing the data and LBA pairs in each page, controller 4 can write a list of LBAs corresponding to the data written to block BLK1 in the last page Py-1 of block BLK1.

[0165] In this way, by writing the LBA along with the data in each block, even if the updated address translation data in the DRAM6 that has not yet been reflected in the L2P table in the NAND flash memory 5 is lost due to an abnormal power outage, the L2P table in the NAND flash memory 5 can be restored by parsing the contents of the last few blocks written.

[0166] Next, an example of the restoration preparation process performed by the restoration processing unit 24 will be described. Here, the restoration preparation process for the namespace NS#2, which has a non-clearing attribute, will be described.

[0167] First, the operation of writing the updated address translation data of L2P table 31-2 into NAND flash memory 5 will be explained.

[0168] Figure 9A This is the first diagram used to explain the restoration preparation process of L2P table 31-2 performed in the SSD3 according to the implementation method. Figure 9B This is the second figure used to explain the restoration preparation process of L2P Tables 31-2 performed in the SSD3 according to the implementation method.

[0169] The recovery processing unit 24 periodically writes the updated address translation data of L2P table 31-2 from DRAM 6 to NAND flash memory 5. The timing of this operation is called a checkpoint. The checkpoint period can be at regular intervals or determined by a specific algorithm.

[0170] At the initial checkpoint cp1, the recovery processing unit 24 writes the updated address translation data in DRAM6, which has not yet been reflected in L2P table 31-2 on NAND flash memory 5, to NAND flash memory 5. Thus, the content of the updated address translation data is reflected in L2P table 31-2 on NAND flash memory 5.

[0171] exist Figure 9A The following scenario is envisioned: the address translation data corresponding to LBA10, LBA35, and LBA290 have not yet been reflected in the L2P table 31-2 on the NAND flash memory 5. In this case, the recovery processing unit 24 writes the address translation data corresponding to LBA10, LBA35, and LBA290 as updated address translation data into the NAND flash memory 5, so that the address translation data corresponding to these LBA10, LBA35, and LBA290 are reflected in the L2P table 31-2 in the NAND flash memory 5.

[0172] At this time, the recovery processing unit 24 writes the sequence number assigned to the block currently allocated as the write destination block for namespace NS#2 into the NAND flash memory 5 as checkpoint information. For example... Figure 9B As shown, at checkpoint cp1, block BLK0 is assigned as the write destination block for namespace NS#2. Therefore, the recovery processing unit 24 writes the sequence number 3 assigned to block BLK0 as checkpoint information into the NAND flash memory 5.

[0173] At the next checkpoint cp2, the recovery processing unit 24 writes the updated address translation data in DRAM6, which has not yet been reflected in L2P table 31-2 on NAND flash memory 5, back into NAND flash memory 5. Thus, the content of the updated address translation data is reflected in L2P table 31-2 on NAND flash memory 5.

[0174] exist Figure 9A The following scenario is envisioned: the address translation data corresponding to LBA26, LBA34, and LBA553 have not yet been reflected in the L2P table 31-2 on the NAND flash memory 5. In this case, the recovery processing unit 24 writes the address translation data corresponding to LBA26, LBA34, and LBA553 as updated address translation data into the NAND flash memory 5, so that the address translation data corresponding to these LBA26, LBA34, and LBA553 are reflected in the L2P table 31-2 in the NAND flash memory 5.

[0175] At this time, the recovery processing unit 24 writes the sequence number assigned to the block currently allocated as the write destination block for namespace NS#2 into the NAND flash memory 5 as checkpoint information. For example... Figure 9B As shown, at checkpoint cp2, block BLK20 is assigned as the write destination block for namespace NS#2. Therefore, the recovery processing unit 24 writes the sequence number 8 assigned to block BLK20 as checkpoint information into the NAND flash memory 5.

[0176] like Figure 9A As shown, at the next checkpoint cp3, the recovery processing unit 24 writes the address translation data corresponding to LBA7, LBA88, and LBA357 respectively into the NAND flash memory 5 as updated address translation data.

[0177] Additionally, the recovery processing unit 24 writes the sequence number assigned to the block currently allocated as the write destination block for namespace NS#2 into the NAND flash memory 5 as checkpoint information. For example... Figure 9B As shown, at checkpoint cp3, block BLK31 is assigned as the write destination block for namespace NS#2. Therefore, the recovery processing unit 24 writes the sequence number 23 assigned to block BLK31 as checkpoint information into the NAND flash memory 5.

[0178] After an abnormal power outage, when power is supplied to the SSD3 again from the host 2, the recovery processing unit 24 determines the block group that should be used for the recovery processing of L2P table 31-2 based on the checkpoint information (serial number) obtained at the last checkpoint.

[0179] For example, consider the following scenario: an abnormal power outage occurs immediately after checkpoint cp1. In this case, during the recovery process of L2P table 31-2, the recovery processing unit 24 retrieves the sequence number assigned to the block currently allocated as the write destination block for namespace NS#2, i.e., the block allocated as the write destination block when the abnormal power outage occurred, from the block usage sequence management table 341-2. Furthermore, the block group assigned the following sequence numbers is determined as the block group to be used for the recovery process of L2P table 31-2: this sequence number falls within the range from sequence number 3 obtained at checkpoint cp1 to the sequence number assigned to the block allocated as the write destination block when the abnormal power outage occurred.

[0180] For example, if an abnormal power outage occurs while block BLK2 is assigned as the destination block for writing, the sequence number assigned to block BLK2, which was assigned as the destination block when the abnormal power outage occurred, is 4. Therefore, block BLK0, which was assigned sequence number 3 at checkpoint cp1, and block BLK2, which was assigned sequence number 4, are determined to be the block group that should be used for the restoration process of L2P table 31-2.

[0181] Next, the recovery processing unit 24 uses the LBA groups stored in blocks BLK0 and BLK2 respectively to determine the correspondence between each physical address in blocks BLK0 and BLK2 and the LBA corresponding to the data stored at those physical addresses. Furthermore, the recovery processing unit 24 uses the determined correspondence between each physical address and each LBA to restore the L2P table 31-2 in the NAND flash memory 5 to its latest content.

[0182] Figure 10 This diagram illustrates the actions performed in the SSD3 according to the implementation method, including the creation of a namespace with clearing attributes and the omission of the restoration preparation process for the L2P table associated with the namespace with clearing attributes.

[0183] For example, when it is desired to create a namespace to be used as a swap area, host 2 sends a namespace creation command specifying the clear attribute to SSD 3. When controller 4 receives the namespace creation command from host 2, namespace management command processing unit 21 creates a namespace with the clear attribute. Namespace management command processing unit 21 manages the creation of the namespace identifier associated with the attribute information indicating the clear attribute by using namespace management table 32. Furthermore, controller 4 creates an L2P table corresponding to the created namespace. In addition, according to the namespace created by namespace management command processing unit 21, controller 4 manages the active block list using block management table 33 and manages the block usage order using block usage order management table 34.

[0184] When the controller 4 receives a namespace deletion command from the host 2 requesting the deletion of a namespace, the namespace management command processing unit 21 deletes the namespace with the namespace identifier specified by the namespace deletion command.

[0185] The recovery processing unit 24 skips the recovery preparation process for the L2P table associated with the namespace having the clear attribute. The recovery preparation process includes: writing updated address translation data in the DRAM 6 that has not yet been reflected in the L2P table stored in the NAND flash memory 5 to the NAND flash memory 5 at each checkpoint; and writing the sequence number assigned to the block currently allocated as the write destination block for the namespace to the NAND flash memory 5 as information for determining the block group that should be used for the recovery process of the L2P table at each checkpoint.

[0186] Figure 11 This is a diagram used to illustrate the cleaning process performed in the SSD3 according to the implementation method.

[0187] The cleaning process unit 23 performs the cleaning process from the time the controller 4 receives a power disconnection warning notification from the host 2 or detects an abnormal power disconnection until it resumes power supply to the SSD 3 and the controller 4 becomes ready to process commands from the host 2.

[0188] For example, the cleanup processing unit 23 may also perform cleanup processing based on the condition that power has been supplied to the SSD3 again, so that the logical addresses included in the namespaces with cleanup attributes become unallocated. In the cleanup processing, for example, the cleanup processing unit 23 sets the logical addresses included in the namespaces with cleanup attributes to an unallocated state by setting the L2P table associated with the namespaces with cleanup attributes to an initial state or discarding it.

[0189] Figure 12 This diagram illustrates the action of setting the logical physical address translation table associated with a namespace having a clearing attribute to an initial state or discarding it through a clearing process performed in the SSD3 involved in the implementation.

[0190] Here, we envision the following scenario: L2P table 31-1 associated with namespace NS#1, L2P table 31-2 associated with namespace NS#2, ..., L2P table 31-n associated with namespace NS#n are implemented as hierarchical L2P tables.

[0191] L2P table 31-1 includes a lower-level table T1-1, a higher-level table T1-2, and a top-level table T1-3. L2P table 31-2 includes a lower-level table T2-1, a higher-level table T2-2, and a top-level table T2-3. L2P table 31-n includes a lower-level table Tn-1, a higher-level table Tn-2, and a top-level table Tn-3.

[0192] In addition, Figure 12The diagram shows that the number of lower-level segments and the number of higher-level segments appear to be the same across all L2P tables. However, in reality, the number of lower-level segments and the number of higher-level segments included in a given L2P table are determined by the size of the namespace corresponding to that L2P table.

[0193] The cleanup processing unit 23 selects namespaces NS#1 and NS#n with cleanup attributes from namespaces NS#1 to NS#n and performs cleanup processing on namespaces NS#1 and NS#n.

[0194] First, the cleanup process for namespace NS#1 will be explained. The cleanup processing unit 23 sets each logical address managed in the L2P table 31-1 associated with namespace NS#1 to an unallocated state. For example, the cleanup processing unit 23 sets the uppermost table T1-3 included in L2P table 31-1 to an initial state or discards it. When the uppermost table T1-3 is set to an initial state or discarded, the controller 4 becomes unable to reference the uppermost table T1-2, and further, also becomes unable to reference the lowermost table T1-1.

[0195] Therefore, by setting the topmost table T1-3 to its initial state or discarding it, the logical addresses included in the namespace NS#1 all become unallocated.

[0196] Similarly, the clearing processing unit 23 sets the logical addresses managed in L2P tables 31-n to an unallocated state. For example, the clearing processing unit 23 sets the topmost table Tn-3 included in L2P tables 31-n to an initial state or discards it. As a result, all logical addresses included in the namespace NS#n become unallocated.

[0197] Therefore, all active blocks associated with the namespace NS#1 with the clearing attribute and all active blocks associated with the namespace NS#n with the clearing attribute become blocks that only store invalid data. Thus, the clearing processing unit 23 moves all block identifiers of the active blocks previously associated with the namespaces NS#1 and NS#n with the clearing attribute to the free block list 332.

[0198] Figure 13 This diagram illustrates the action of managing blocks (active blocks) previously associated with namespaces having clearing attributes as free blocks through a clearing process performed in the SSD3 described in the implementation.

[0199] When the clearing processing unit 23 sets each logical address included in namespace NS#1 to an unallocated state, data stored in any active block managed by the active block list 331-1 becomes invalid data. Similarly, when the clearing processing unit 23 sets each logical address included in namespace NS#n to an unallocated state, data stored in any active block managed by the active block list 331-n becomes invalid data.

[0200] Therefore, there are no longer any blocks with valid data written to them in the blocks managed by the active block list 331-1. The clearing processing unit 23 moves the block identifiers of all blocks managed by the active block list 331-1 to the free block list 332.

[0201] Similarly, no longer are there any blocks with valid data written to them in the blocks managed by the active block lists 331-n. The clearing processing unit 23 moves the block identifiers of all blocks managed by the active block lists 331-n to the free block list 332. As a result, the active blocks previously associated with each namespace with the clearing attribute become physical storage areas that can be reused for writing data (or management information such as L2P tables).

[0202] Figure 14 This diagram illustrates the process of reformatting a namespace with a cleanup attribute, which is performed on host 2.

[0203] Several LBAs surrounding LBA0 of a certain namespace contain information related to the namespace's format, such as the type of file system corresponding to that namespace and the mount point. When performing cleanup processing on a namespace with cleanup attributes, this format-related information cannot be read from that namespace. Therefore, in order to enable the namespace with cleanup attributes to be reused for data writing and reading, host 2 performs a reformatting process to rewrite the format-related information in the namespace with cleanup attributes.

[0204] After power is supplied to SSD3 again and controller 4 becomes ready, host 2 can also first obtain information about the various namespaces managed by SSD3 from SSD3, and determine the namespaces with clearing attributes from the namespaces managed by SSD3.

[0205] In this scenario, host 2 sends a request to controller 4 to retrieve the specified namespace information, specifically the NSID of that namespace. This request can be made, for example, using the `identify` command (Identify Namespace data structure) defined by the NVMe standard.

[0206] Upon receiving a request to retrieve namespace information, the namespace management command processing unit 21 sends namespace information related to the namespace with the specified NSID to the host 2. This namespace information includes various details related to the namespace with the specified NSID, such as a global namespace identifier to uniquely identify the namespace, a clear identifier as attribute information of the namespace, and the size of the namespace. For example, the Namespace Globally Unique Identifier (NGUID) can be used as the global namespace identifier. Storage devices conforming to the NVMe standard may include multiple controllers. The NGUID is an identifier that uniquely identifies each namespace managed within an NVMe-compliant storage device.

[0207] When host 2 confirms that the namespace has a clearing attribute, it instructs SSD 3 to perform a formatting action, thereby reformatting the namespace. By performing this namespace reformatting, information related to the namespace's format can be rewritten to several LBAs surrounding LBA0 of the namespace. Thus, host 2 can reuse the namespace with the clearing attribute, for example, as a swap space again.

[0208] After the reformatting of all namespaces with the clear attribute is completed, host 2 issues I / O commands (write commands, read commands) to SSD3 to cooperate with SSD3 in writing data to and reading data from each namespace.

[0209] Figure 15 This is a flowchart illustrating the steps of the namespace creation process performed in the SSD3 according to the implementation method.

[0210] First, controller 4 receives a namespace creation command from host 2 (step S101). The namespace creation command is a namespace management command that requests the creation of a namespace. The namespace creation command specifies the size of the namespace to be created and the attributes (clear attributes or non-clear attributes) that the namespace to be created should have.

[0211] Controller 4 determines whether the namespace creation command received in step S101 specifies the clear attribute (step S102).

[0212] If the received namespace creation command specifies the clear attribute (step S103: Yes), the controller 4 creates a namespace with the clear attribute (step S103). In step S103, the controller 4 manages the namespace identifier of the namespace created in step S103 by associating it with the attribute information representing the clear attribute using the namespace management table 32.

[0213] If the received namespace creation command does not specify a clear attribute (i.e., specifies a non-clear attribute) (step S103: No), the controller 4 creates a namespace with a non-clear attribute (step S104). The controller 4 manages the namespace identifier of the namespace created in step S104 in association with the attribute information representing the non-clear attribute by using the namespace management table 32.

[0214] The controller 4 returns namespace information related to the namespace created in step S103 or step S104 to the host 2 (step S105). Here, the namespace information sent by the controller 4 to the host 2 includes at least the namespace identifier of the created namespace. The namespace information may also include the namespace identifier of the created namespace, the size of the created namespace, and attribute information indicating the attributes (clear attributes or non-clear attributes) of the created namespace.

[0215] Figure 16 This is a flowchart illustrating the steps of the recovery preparation process performed in the SSD3 according to the implementation method.

[0216] The controller 4 will sequentially select one by one the multiple L2P tables corresponding to the multiple namespaces managed by the controller 4 as the L2P tables to be processed for restoration, and perform the following processing according to the selected L2P tables.

[0217] Controller 4 first selects an L2P table that is to be processed for restoration (step S201). Controller 4 then determines whether the namespace associated with the L2P table selected in step S201 has a clear attribute (step S202).

[0218] If the namespace associated with the selected L2P table has a clear attribute (step S202: Yes), controller 4 ends the recovery preparation process. This is because recovery processing is not required for L2P tables associated with namespaces that have a clear attribute.

[0219] If the namespace associated with the selected L2P table does not have a clear attribute (has a non-clear attribute) (step S202: No), controller 4 performs a restoration preparation process for the selected L2P table at each checkpoint. Here, we assume the following scenario: the selected L2P table is L2P table 31-2 associated with namespace NS#2.

[0220] When the checkpoint is reached, the controller 4 first writes the address translation data of the selected L2P table 31-2 stored in DRAM 6, which has not yet been reflected in the updated L2P table 31-2 stored in NAND flash memory 5, to NAND flash memory 5 (step S203).

[0221] Then, the controller 4 writes the sequence number assigned to the block currently allocated as the write destination block for namespace NS#2 into the NAND flash memory 5 as checkpoint information for determining the block group to be used for the restoration of L2P table 31-2 (step S204). In step S204, the controller 4 performs, for example, the following processing: the sequence number, together with the checkpoint number used to determine the current checkpoint, is recorded as checkpoint information in the NAND flash memory 5.

[0222] Figure 17 This is a flowchart illustrating the steps of the process performed in the SSD3 according to the implementation method from the time the host 2 receives a power disconnection warning until the controller 4 of the SSD3 becomes ready to supply power to the SSD3 again.

[0223] Imagine the following scenario: a cleanup process is performed after power is supplied to the SSD3 again.

[0224] Controller 4 receives a power-off warning notification or a pause instruction from host 2 (step S301). Controller 4 determines whether the notification / instruction received in step S301 is a power-off warning notification or a pause instruction, that is, whether the process to be performed is a shutdown preparation process or a pause preparation process (step S302).

[0225] If the notification / instruction received in step S301 is a power-off warning notification (step S302: shutdown), the controller 4 performs a shutdown preparation process (step S303). In the shutdown preparation process, the controller 4 selects the L2P table associated with a namespace having a non-clear attribute and performs the process of writing the updated address translation data into the NAND flash memory 5.

[0226] When the shutdown preparation process is complete, the controller 4 notifies the host 2 that the shutdown preparation process is complete (step S304). When the host 2 confirms that the shutdown preparation process of the SSD3 is complete, it cuts off the power supply to the SSD3.

[0227] After the power supply to SSD3 is disconnected, and power is restored from host 2 to SSD3 (step S305: power on), controller 4 begins a series of initialization steps to prepare its state to be ready to process commands from host 2. In this initialization sequence, controller 4 performs a cleanup process for namespaces with cleanup attributes (step S306). In step S306, controller 4 sets each logical address within the logical address range of the namespace with cleanup attributes to an unallocated state, and further moves the block identifiers of each block associated with the namespace with cleanup attributes to the free block list 332.

[0228] Additionally, during this initialization sequence, controller 4 also performs the action of loading at least a portion of the address translation data of each of the L2P tables 31-1, ..., 31-n from the NAND flash memory 5 to the DRAM 6. For example, if L2P table 31-1 associated with the namespace NS#1 with the clear attribute is discarded, a new L2P table for namespace NS#1 is created, and at least a portion of the address translation data of the created L2P table is loaded into the DRAM 6.

[0229] When the initialization sequence is complete, controller 4 becomes ready to process commands from host 2. Controller 4 notifies host 2 that it has become ready (step S310).

[0230] If the notification / instruction received in step S301 is a pause instruction (step S302: pause), controller 4 performs pause preparation processing (step S307). In the pause preparation processing, controller 4, with respect to the L2P table corresponding to all namespaces, performs a process of writing the updated address translation data stored in DRAM 6 to NAND flash memory 5. Furthermore, controller 4 performs a process to change the current power state of SSD 3 from the ON state (D0 state) to the low power state (D1 state, D2 state, or D3 state) specified by the pause instruction.

[0231] When the pause preparation process is complete, the controller 4 notifies the host 2 that the pause preparation process is complete (step S308). If the power state of the target change specified by the pause instruction is D3, the host 2 cuts off the power supply to the SSD3 when it confirms that the pause preparation process of the SSD3 is complete.

[0232] After the power state of SSD3 transitions to a low power state, upon receiving a restart instruction from host 2 (step S309), controller 4 begins processing to restore the power state of SSD3 from the low power state to the on state (D0 state). Even when SSD3 is in the D3 state, power can still be supplied to SSD3 from host 2, and host 2 can send a restart instruction to SSD3.

[0233] When the power state of SSD3 returns from low power state to on state (D0 state) and controller 4 becomes ready to process commands from host 2, controller 4 notifies host 2 that controller 4 has become ready (step S310).

[0234] Figure 18 This is a flowchart illustrating the steps of the processing performed in the SSD3 according to the embodiment from the detection of an abnormal power disconnection to the point when power is supplied to the SSD3 again and the controller 4 of the SSD3 becomes ready.

[0235] The following scenario is envisioned: a cleanup process is performed after power is restored to SSD3. If power circuit 7 has a PLP function, a reference process is also performed in the event of an abnormal power outage. Figure 17 The shutdown preparation process has been explained. If power supply circuit 7 lacks the PLP function, the shutdown preparation process will not be executed in the event of an abnormal power outage. The following scenario assumes that power supply circuit 7 lacks the PLP function.

[0236] If the controller 4 receives a power disconnection detection notification from the power circuit 7 before receiving a power disconnection warning notification from the host 2, it detects that an abnormal power disconnection has occurred (step S401).

[0237] After the power supply to SSD3 is interrupted due to an abnormal power outage, and power is restored to SSD3 from host 2 (step S402: power on), controller 4 begins the initialization sequence. In this initialization sequence, controller 4 performs a cleanup process for namespaces with cleanup attributes (step S403). In step S403, controller 4 sets the logical addresses included in the namespaces with cleanup attributes to an unallocated state, and further moves the active blocks previously associated with the namespaces with cleanup attributes to the free block list 332.

[0238] In the initialization sequence, controller 4 further performs restoration processing on the L2P tables corresponding to each namespace with the non-clear attribute (step S404). The L2P tables associated with the namespaces with the clear attribute are set to the initial state or discarded; therefore, controller 4 only performs restoration processing on the L2P tables associated with each namespace with the non-clear attribute.

[0239] Additionally, during this initialization sequence, controller 4 also performs the action of loading at least a portion of the address translation data of each of the L2P tables 31-1, ..., 31-n from the NAND flash memory 5 to the DRAM 6. For example, if L2P table 31-1 associated with the namespace NS#1 with the clear attribute is discarded, a new L2P table for namespace NS#1 is created, and at least a portion of the address translation data of the created L2P table is loaded into the DRAM 6.

[0240] When the initialization sequence is complete, controller 4 becomes ready to process commands from host 2. Controller 4 notifies host 2 that it has become ready (step S405).

[0241] Figure 19 This is a flowchart illustrating the steps of the shutdown preparation process performed in the SSD3 according to the implementation method.

[0242] Upon receiving a power outage warning notification from host 2, controller 4 initiates shutdown preparation processing. If power circuit 7 has PLP functionality, controller 4 also initiates shutdown preparation processing upon detecting an abnormal power outage.

[0243] During the shutdown preparation process, the controller 4 first determines whether updated address translation data exists in the DRAM 6, and whether there is any unselected address translation data among the updated address translation data that has not yet undergone the processing of steps S502 to S505 (step S501). If unselected address translation data exists (step S501: Yes), the controller 4 selects the unselected address translation data from the updated address translation data in the DRAM 6 (step S502). If no updated address translation data exists in the DRAM 6, or if the processing of steps S502 to S505 is performed on all updated address translation data and the unselected address translation data no longer exists (step S501: No), Figure 19 The processing is now complete.

[0244] In step S502, the controller 4 selects any address translation data that has not yet been selected from the updated address translation data stored in the L2P tables 31-1, ..., 31-n in the NAND flash memory 5.

[0245] Controller 4 determines whether the address translation data selected in step S502 is associated with a namespace that has a clear attribute (step S503). That is, controller 4 determines whether the namespace associated with the L2P table that includes the selected address translation data has a clear attribute.

[0246] If the address translation data selected in step S502 is associated with a namespace with a clear attribute (step S503: Yes), the controller 4 skips the execution of the process of writing the selected address translation data into the NAND flash memory 5 (step S504).

[0247] If the address translation data selected in step S502 is associated with a namespace that has a non-clear attribute (step S503: No), the controller 4 performs a process of writing the selected address translation data to the NAND flash memory 5 (step S505). Thus, the content of the selected address translation data is reflected in the L2P table within the NAND flash memory 5 corresponding to the selected address translation data.

[0248] After step S504 or step S505, the process returns to step S501. In step S501, the controller 4 again determines whether there is any unselected address translation data in the updated address translation data in DRAM 6.

[0249] If there is unselected address translation data in the updated address translation data in DRAM6 (step S501: Yes), the controller 4 executes the processing of steps S502 to S505 again.

[0250] If there is no longer any unselected address translation data in the updated address translation data in DRAM6 (step S501: No), the controller 4 ends the process.

[0251] Figure 20 This is a flowchart illustrating the steps of the pause preparation process performed in the SSD3 according to the implementation method.

[0252] When a pause instruction is received from host 2, controller 4 begins the pause preparation process.

[0253] During the pause preparation process, the controller 4 first determines whether updated address translation data exists in DRAM 6, and whether there is any unselected address translation data among the updated address translation data that has not yet undergone the processing of steps S602 to S603 (step S601). If unselected address translation data exists (step S601: Yes), the controller 4 selects the unselected address translation data from the updated address translation data in DRAM 6 (step S602). If no updated address translation data exists in DRAM 6, or if the processing of steps S602 to S603 is performed on all updated address translation data and the unselected address translation data no longer exists (step S601: No), Figure 20 The processing is now complete.

[0254] In step S602, the controller 4 selects any address translation data that has not yet been selected from the updated address translation data stored in the L2P tables 31-1, ..., 31-n in the NAND flash memory 5.

[0255] The controller 4 writes the address translation data selected in step S602 into the NAND flash memory 5 (step S603). Thus, the content of the selected address translation data is reflected in the L2P table corresponding to the selected address translation data within the NAND flash memory 5.

[0256] After step S603, the process returns to step S601. In step S601, the controller 4 again determines whether there is any unselected address translation data in the updated address translation data in DRAM 6.

[0257] If there is unselected address translation data in the updated address translation data in DRAM6 (step S601: Yes), that is, if there is still updated address translation data in DRAM6 that has not been reflected in the L2P tables 31-1, ..., 31-n stored in NAND flash memory 5, the controller 4 executes the processing of steps S602 to S603 again.

[0258] If there is no unselected address translation data in the updated address translation data in DRAM6 (step S601: yes or no), that is, if there is no updated address translation data in DRAM6 that has not yet been reflected in the L2P tables 31-1, ..., 31-n stored in NAND flash memory 5, the controller 4 ends the process.

[0259] Figure 21 This is a flowchart illustrating the steps of the cleanup process performed in the SSD3 according to the implementation method.

[0260] The controller 4 determines whether there is a namespace with the clear attribute by referring to the namespace management table 32 (step S701).

[0261] If a namespace with a clearing attribute exists (step S701: Yes), the controller 4, for example, sets each logical address contained in the logical address range included in the namespace with the clearing attribute to an unallocated state by setting the L2P table associated with the namespace with the clearing attribute to an initial state or discarding it (step S702). If the L2P table associated with the namespace with the clearing attribute is implemented by a hierarchical L2P table, in step S702, the controller 4 sets the table at the highest level of the hierarchical L2P table to an initial state or discards it.

[0262] Furthermore, controller 4 moves the block identifiers of all blocks previously associated with the namespace with the clear attribute to the free block list 332, and manages these all blocks as free blocks (step S703).

[0263] If no namespace with the cleanup attribute exists (step S701: No), controller 4 ends the cleanup process.

[0264] Figure 22 This is a flowchart illustrating the steps of the processing performed in the SSD3 and host 2 according to the implementation method after power is supplied to the SSD3 again.

[0265] After the power supply to SSD3 is disconnected, when power is supplied to SSD3 again, the controller 4 within SSD3 begins an initialization process including a clearing process (step S801). In the initialization process, the controller 4 also performs a process of loading at least a portion of the address translation data of each of the L2P tables 31-1 to 31-n in the NAND flash memory 5 onto the DRAM 6.

[0266] When controller 4 becomes ready, it notifies host 2 of this status (S802). Upon receiving notification from controller 4 that it has become ready, host 2 sends a request to controller 4 to retrieve the specified namespace information for a particular namespace's NSID (step S803). Having received the request from host 2, controller 4 sends namespace information related to the namespace with the specified NSID to host 2 (step S804). The namespace information includes a global namespace identifier that uniquely identifies the namespace, a clear identifier that serves as attribute information for the namespace, and the size of the namespace, etc.

[0267] When host 2 confirms that the namespace has a cleanup attribute, it performs a reformatting process (step S805) to write information related to the namespace's format to several LBAs surrounding LBA0 of the namespace. This allows normal access to the namespace that has already undergone cleanup.

[0268] As explained above, according to this embodiment, when the controller 4 receives a namespace creation command specifying a clear attribute from the host 2, it creates a namespace with a clear attribute. When the host 2 receives a write command specifying a namespace identifier for recognizing the namespace with the clear attribute, the controller 4 executes the operation of writing the data associated with the received write command into the NAND flash memory 5. Furthermore, the controller 4 performs the following operation: updating the L2P table corresponding to the namespace with the clear attribute, so that the physical address of the NAND flash memory 5 to which the data has been written is mapped to the logical address corresponding to the data.

[0269] Furthermore, during the period from receiving a power-off warning or detecting an abnormal power outage until power is restored to the SSD3 and the controller 4 becomes ready, the controller 4 sets each logical address within the logical address range of the namespace with the clear attribute to an unallocated state of the physical address of the unmapped NAND flash memory 5. As a result, all data associated with the logical address range of the namespace with the clear attribute becomes invalid data, thus the namespace with the clear attribute becomes the same state as the namespace immediately after creation, before any data has been written to it. Therefore, all blocks associated with the namespace with the clear attribute become free blocks containing no valid data.

[0270] Therefore, by using a namespace with a clear attribute as a destination for data that does not need to be retained across the power cycles of the SSD3, for example, it is possible to prevent the physical storage area within the NAND flash memory 5 from being wasted by data that does not need to be retained across the power cycles of the SSD3. This reduces the power consumption of the NAND flash memory 5.

[0271] Furthermore, when controller 4 receives a power-off warning notification from host 2, it does not perform the process of writing the updated address translation data stored in DRAM 6 to NAND flash memory 5 regarding the L2P table corresponding to the namespace with the clear attribute. By omitting the process of keeping the L2P table corresponding to the namespace with the clear attribute up-to-date, the amount of writing to NAND flash memory 5 can be reduced, thus further reducing unnecessary consumption of NAND flash memory 5.

[0272] Additionally, while SSD3 is in the enabled state (D0 state), controller 4 also omits the execution of the restoration preparation process for the L2P table corresponding to the namespace with the clear attribute.

[0273] Thus, in this embodiment, by omitting various processing steps related to the address translation data of the L2P table associated with the namespace having clearing attributes, the load on the controller 4 can be reduced, and the consumption of the NAND flash memory 5 can be suppressed.

[0274] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage system capable of connecting to a host, comprising: Non-volatile memory; and The controller is electrically connected to the non-volatile memory. The controller is configured as follows: Based on the situation where a command to create a first namespace specifying a first attribute is received from the host, a first namespace including a first logical address range and having the first attribute is created. The first namespace identifier, used to identify the first namespace, is managed in association with attribute information representing the first attribute. During the first period, based on the managed attribute information, each logical address included in the first logical address range is set to an unallocated state where it is not mapped to the physical address of the non-volatile memory. The first period is the period from when the host receives a power-off warning notification or detects an abnormal power disconnection of the storage system until power is supplied to the storage system again and the controller becomes ready to process commands from the host. The power-off warning notification is a notification that foreshadows the disconnection of power supply to the storage system.

2. The storage system according to claim 1, The first attribute indicates that data associated with the first logical address range does not need to be maintained across the power cycles of the storage system. The controller is configured to determine whether the first namespace is associated with the attribute information representing the first attribute.

3. The storage system according to claim 1, The controller is configured to set each logical address included in the first logical address range to the unallocated state during the first period, from the time power is supplied to the storage system again until the controller becomes the ready state.

4. The storage system according to claim 1, The controller is configured to set each logical address included in the first logical address range to the unallocated state during the first period, from the time the host receives the power disconnection warning notification until the power supply to the storage system is cut off.

5. The storage system according to claim 1, The controller is further configured as follows: The first logical physical address translation table is managed, which is used to manage the mapping between each logical address included in the first logical address range and each physical address of the non-volatile memory. Based on the situation where a first write command is received from the host, specifying a first namespace identifier for identifying the first namespace,... The first data associated with the first write command is written to the non-volatile memory. The first logical physical address translation table is updated so that the first physical address is mapped to the first logical address corresponding to the first data, wherein the first physical address represents the physical storage location in the non-volatile memory where the first data is written.

6. The storage system according to claim 5, The controller is configured to: set the first logical physical address translation table to an initial state or discard it, and set each logical address included in the first logical address range to the unallocated state.

7. The storage system according to claim 5, The first logical physical address translation table includes multiple tables corresponding to multiple hierarchical levels. Each of the multiple tables includes more than one address translation data. The address translation data contained in each table at each hierarchical level covers the logical address range corresponding to that hierarchical level, so that the address translation tables corresponding to higher hierarchical levels cover a larger logical address range compared to the address translation data corresponding to lower hierarchical levels. The controller is configured to: set the table of the highest level among the multiple hierarchical levels to an initial state or discard it, and set each logical address included in the first logical address range to the unallocated state.

8. The storage system according to claim 5, It also has volatile memory. The controller is further configured as follows: The address translation data contained in the first logical physical address translation table is loaded from the non-volatile memory into the volatile memory. Based on the execution of the first write command, the address translation data stored in the volatile memory is updated. Upon receiving the power-off warning notification from the host, the updated address translation data in the volatile memory that has not yet been reflected in the first logical physical address translation table stored in the non-volatile memory is not written to the non-volatile memory. During the first period, each of the logical addresses included in the first logical address range is set to the unallocated state.

9. The storage system according to claim 8, The controller is further configured to: upon receiving an indication from the host to change the power state of the storage system from an on state to a low power state corresponding to the host's pause state, write updated address translation data in the volatile memory that has not yet been reflected in the first logical physical address translation table stored in the non-volatile memory into the non-volatile memory.

10. The storage system according to claim 8, The controller is further configured as follows: Based on the situation where a command to create a second namespace is received from the host without specifying the first attribute, a second namespace is created that includes a second logical address range. This second namespace has a second attribute that requires data associated with the second logical address range to be persisted across the power cycles of the storage system. The second logical physical address translation table is managed, which is used to manage the mapping between each logical address included in the second logical address range and each physical address of the non-volatile memory. The second address translation data contained in the second logical physical address translation table is further loaded from the non-volatile memory into the volatile memory. Based on the execution of the second write command specified for the second namespace identifier used to identify the second namespace, the second address translation data stored in the volatile memory is updated. Based on the status of receiving the power-off warning notification from the host, the updated second address translation data in the volatile memory, which has not yet been reflected in the second logical-physical address translation table stored in the non-volatile memory, is written into the non-volatile memory.

11. The storage system according to claim 8, The controller is further configured as follows: Based on the situation where a command to create a second namespace is received from the host without specifying the first attribute, a second namespace is created that includes a second logical address range. This second namespace has a second attribute that requires data associated with the second logical address range to be persisted across the power cycles of the storage system. The second logical physical address translation table is managed, which is used to manage the mapping between each logical address included in the second logical address range and each physical address of the non-volatile memory. The second address translation data contained in the second logical physical address translation table is further loaded from the non-volatile memory into the volatile memory. Based on the execution of the second write command specified for the second namespace identifier used to identify the second namespace, the second address translation data stored in the volatile memory is updated. Regarding the second logical physical address translation table, a restoration preparation process including actions (1) and (2) is performed. Action (1) is, at each checkpoint, writing the updated second address translation data in the volatile memory, which has not yet been reflected in the second logical physical address translation table stored in the non-volatile memory, to the non-volatile memory. Action (2) is, at each checkpoint, writing the sequence number assigned to the first block currently allocated as the write destination block for the second namespace, as information for determining the block group to be used for the restoration process of the second logical physical address translation table stored in the non-volatile memory, to the non-volatile memory. Regarding the first logical physical address translation table, the execution of the restoration preparation process including actions (3) and (4) is omitted. Action (3) is, at each checkpoint, writing the updated address translation data in the volatile memory that has not yet been reflected in the first logical physical address translation table stored in the non-volatile memory to the non-volatile memory. Action (4) is, at each checkpoint, writing the sequence number assigned to the second block currently allocated as the write destination block for the first namespace into the non-volatile memory as information for determining the block group to be used for the restoration process of the first logical physical address translation table stored in the non-volatile memory. The sequence number assigned to the first block indicates the order in which the first block is allocated as a write destination block for the second namespace, and the sequence number assigned to the second block indicates the order in which the second block is allocated as a write destination block for the first namespace.

12. A control method for controlling a storage system including non-volatile memory, comprising: Based on the situation that a command to create a first namespace specifying a first attribute is received from the host, a first namespace including a first logical address range is created, wherein the first namespace does not need to maintain the data associated with the first logical address range across the power cycle of the storage system; The first namespace identifier, used to identify the first namespace, is managed in association with attribute information representing the first attribute. During the first period, based on the managed attribute information, each logical address included in the first logical address range is set to an unallocated state where it is not mapped to the physical address of the non-volatile memory. The first period is the period from when the host receives a power-off warning notification or detects an abnormal power disconnection of the storage system until power is restored to the storage system and the controller within the storage system becomes ready to process commands from the host. The power-off warning notification is a notification that foreshadows the disconnection of power supply to the storage system.

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