A hybrid NVME SSD storage system based on MRAM cache

Abstract

The present invention discloses a hybrid NVME SSD storage system based on MRAM cache, which includes an SSD controller, a volatile storage layer, and a non-volatile storage layer. The SSD controller includes a PCIe interface, an NVME command parser, an FTL mapping manager, a NAND controller, an MRAM controller, and a DRAM controller. The volatile storage layer includes an external DRAM, and the non-volatile storage layer includes an external NAND and an external MRAM. The PCIe interface, the NVME command parser, and the FTL mapping manager are connected in sequence. The NAND controller, the MRAM controller, and the DRAM controller are all connected to the FTL mapping manager. The external DRAM is connected to the DRAM controller, the external NAND is connected to the NAND controller, and the external MRAM is connected to the MRAM controller. The present invention can improve the random performance and reliability of the NVME SSD controller, ensure data security, solve the power-off protection problem, and reduce the power-off recovery time.

Description

Technical Field

[0001] The present invention relates to the field of mobile storage, and in particular to a hybrid NVME SSD storage system based on MRAM cache. Background Art

[0002] NVME is a host controller interface specification for non-volatile memory. It is currently widely used in the application layer protocol implemented by the PCIExpress bus to connect to non-volatile storage media. Compared with the maximum 32 command queues that traditional SATA SSD hard drives can provide, NVME SSD provides thousands of parallel queues to control IO data flow, which can greatly reduce latency and significantly improve the IOPS capability of SSD.

[0003] The current NVME SSD uses NAND FLASH as non-volatile memory, but when NAND FLASH is used, it is necessary to combine its usage restrictions to complete the development of SSD software code. At the same time, because the error rate of 3D TLC NAND is too high, BCH cannot solve it, so LDPC must be used. In addition, if an abnormal power failure occurs when the SSD reads, writes, deletes, etc. is working normally, it may cause the FTL mapping table to be lost because it cannot be updated in time, resulting in the failure of the SSD to be recognized by the system. Summary of the invention

[0004] In view of the defects of the prior art, the present invention provides a hybrid NVME SSD storage system based on MRAM cache, which improves the random performance and reliability of the NVME SSD controller, ensures data security, solves the power-off protection problem, and reduces the power-off recovery time.

[0005] To solve the above technical problems, the technical solution adopted by the present invention is as follows: A hybrid NVME SSD storage system based on MRAM cache, comprising an SSD controller, a volatile storage layer, and a non-volatile storage layer. The SSD controller includes a PCIe interface, an NVME command parser, an FTL mapping manager, a NAND controller, an MRAM controller, and a DRAM controller. The volatile storage layer includes an external DRAM, and the non-volatile storage layer includes an external NAND and an external MRAM. The PCIe interface, the NVME command parser, and the FTL mapping manager are connected in sequence. The NAND controller, the MRAM controller, and the DRAM controller are all connected to the FTL mapping manager. The external DRAM is connected to the DRAM controller, the external NAND is connected to the NAND controller, and the external MRAM is connected to the MRAM controller. The PCIE interface is used for data transmission with the upper application layer. The NVME controller is used to process the NVME protocol and complete the creation and use of the storage buffer CMB and the permanent memory area PMR inside the SSD controller in the external MRAM in the non-volatile storage layer. The FTL mapping manager is responsible for maintaining the mapping relationship between the logical block address LBA and the physical block address PBA of the storage medium in the volatile storage layer and the non-volatile storage layer. The external DRAM is used to store read buffer data and the FTL mapping table. The external NAND is used to store user data in ordinary applications and the FTL mapping table. The external MRAM is used to store CMB data, PMR data, write buffer data, the change amount Delta of the FTL mapping table, and log information. When using the volatile storage layer of the external DRAM, the FTL mapping manager places the mapping table and the read data cache in the external DRAM through the DRAM controller. When using the MRAM storage area in the non-volatile storage layer, the FTL mapping manager places the write data cache, Delta data, and Log data in the external MRAM through the MRAM controller. When using the NAND FLASH storage area in the non-volatile storage layer, the FTL mapping manager places the user data in the external NAND through the NAND controller.

[0006] Further, the data flow paths between components of the system are as follows: for the write direction of the user data flow, it is from the FTL mapping manager to the MRAM controller or from the FTL mapping manager to the NAND controller; for the read direction of the user data flow, it is from the NAND controller to the DRAM controller, and then from the DRAM controller to the external DRAM or from the DRAM controller to the FTL mapping manager; for the write direction of the mapping table data flow, it is from the NAND controller to the DRAM controller, and for the read direction of the mapping table data flow, it is from the DRAM controller to the NAND controller; for the write direction of the Delta data flow, it is from the DRAM controller to the MRAM controller, and for the read direction of the Delta data flow, it is from the MRAM controller to the DRAM controller; for the write direction of the Log data flow, it is from the FTL mapping manager to the MRAM controller, and for the read direction of the Log data flow, it is from the MRAM controller to the FTL mapping manager.

[0007] Further, a storage buffer CMB is provided in the memory address of the SSD controller. The CMB configuration supported by the SSD controller is submitted to the host side through the NVME Identify command. The host side configures the base address and offset address of the storage buffer CMB in the NVME register through the PCIE interface using CMBLOC, and configures the size of the storage buffer CMB using CMBSZ; for the send queue implemented based on the CMB, the host directly writes the commands in the send queue into the internal storage buffer CMB of the SSD controller.

[0008] Further, the PRP list or SGL list needs to be read separately on the PCIe interface, and the read operations of the controller are reduced by writing the PRP or SGL into the internal storage buffer CMB of the SSD controller.

[0009] Further, a permanent memory area PMR is provided in the external MRAM. The permanent memory area PMR is managed through the NVME protocol, and the MRAM medium is used to achieve read and write in units of 1 / 2 / 4 / 8 bytes. At the same time, the permanent memory area PMR provides a predictable low-latency mode to the NVME host side.

[0010] Further, the NAND controller includes a NAND ECC unit and a NAND interface. The NAND interface is responsible for data interaction with the external NAND in the underlying storage medium layer. The NAND ECC unit uses the low-density forward error correction code LDPC error correction algorithm to protect data blocks.

[0011] Further, the DRAM controller includes a DRAM ECC unit and a DRAM interface. The DRAM interface is responsible for completing data interaction with the external DRAM in the underlying storage medium layer. The DRAM ECC unit uses the Hamming code algorithm for protection by byte, supporting correcting one bit and detecting two bits.

[0012] Further, the MRAM controller includes an MRAM ECC unit and an MRAM interface. The MRAM interface is responsible for completing data interaction with the external MRAM in the underlying storage medium layer. The MRAM ECC unit uses a simplified version of the BCH algorithm for protection by single byte or double byte, supporting correcting 2 bits and detecting 3 bits.

[0013] Further, the MRAM ECC unit uses the Reed-Solomon (RS) code algorithm for protection by 4 bytes or 8 bytes, supporting correcting 3 bits and detecting 4 bits.

[0014] Advantages of the present invention:

[0015] 1. The data is more secure. The cached data and key management data are still stored in the MRAM and can be used continuously after power failure and power-on again. Data will not be lost during shutdown or restart, and can be immediately reloaded after system recovery, shortening the server restart time from the minute level to the second level.

[0016] 2. It provides a wider range of application scenarios and improves the system stability. With the increasing demand for the capacity of NAND FLASH, in the traditional solution, in order to cache more mapping tables or write data in the DRAM, enough capacitors need to be added to ensure that all the data in the cache is written into the NAND FLASH before the system power failure. Based on the MRAM medium, the present invention saves the last updated mapping table in the MRAM. When the SSD is powered on again, it searches for the new data written after the last mapping table is saved, reconstructs the mapping table, and quickly enables the SSD to enter the normal state.

[0017] 3. As a write buffer, it can achieve more efficient I / O management. Replacing the cache from DRAM with MRAM can improve the I / O performance of the SSD, enabling SSD manufacturers to better manage the I / O stream, reducing the management pressure on the NAND controller during read and write concurrency, thereby achieving better latency determinacy and improving QoS.

[0018] 4. Solve problems including slow startup of computers or servers, data loss, slow data loading, short battery life, etc.

[0019] 5. In the MRAM controller, according to the reliability level requirements of the actual user data and the memory access requirements of each component in the SSD controller, it meets the ECC requirements of simultaneous reading and writing of 1 / 2 / 4 / 8 bytes, ensuring the overall reliability of the system. Brief Description of the Drawings

[0020] Figure 1 This is the principle block diagram of the present invention. Detailed Embodiments

[0021] The present invention will be further described below in conjunction with the drawings and specific embodiments.

[0022] Embodiment 1

[0023] This embodiment discloses a hybrid NVME SSD storage system based on MRAM cache, which specifically improves the random performance and reliability of the NVME SSD controller, ensures data security, solves the power-off protection problem, and reduces the power-off recovery time.

[0024] As Figure 1 shown, this system includes an SSD controller, a volatile storage layer, and a non-volatile storage layer. The SSD controller includes a PCIe interface, an NVME command parser, an FTL mapping manager, a NAND controller, an MRAM controller, and a DRAM controller. The volatile storage layer includes an external DRAM, and the non-volatile storage layer includes an external NAND and an external MRAM. The PCIe interface, the NVME command parser, and the FTL mapping manager are connected in sequence. The NAND controller, the MRAM controller, and the DRAM controller are all connected to the FTL mapping manager. The external DRAM is connected to the DRAM controller, the external NAND is connected to the NAND controller, and the external MRAM is connected to the MRAM controller.

[0025] The PCIE interface is used for data transmission with the upper application layer.

[0026] The NVME controller is used to process the NVME protocol, complete the parsing of NVME protocol recognition, read, write, control and other commands, and complete the creation and use of the storage buffer CMB inside the SSD controller and the permanent memory area PMR in the external MRAM in the non-volatile storage layer.

[0027] The FTL mapping manager is responsible for maintaining the mapping relationship between the logical block address LBA and the physical block address PBA of the storage medium in the volatile storage layer and the non-volatile storage layer.

[0028] The external DRAM is used to store read buffer data and the FTL mapping table. The external NAND is used to store user data in ordinary applications and the FTL mapping table. The external MRAM is used to store CMB data, PMR data, write buffer data, the change amount Delta of the FTL mapping table, and log information. When using the volatile storage layer of the external DRAM, the FTL mapping manager places the mapping table and read data cache in the external DRAM through the DRAM controller. When using the MRAM storage area in the non-volatile storage layer, the FTL mapping manager places the write data cache, Delta data, and Log data in the external MRAM through the MRAM controller. When using the NAND FLASH storage area in the non-volatile storage layer, the FTL mapping manager places the user data in the external NAND through the NAND controller.

[0029] In this embodiment, the NAND controller includes a NAND ECC unit and a NAND interface. The NAND interface is responsible for completing data interaction with the external NAND in the underlying storage medium layer. The NAND ECC unit uses the low-density forward error correction code LDPC error correction algorithm to protect data blocks.

[0030] The DRAM controller includes a DRAM ECC unit and a DRAM interface. The DRAM interface is responsible for completing data interaction with the external DRAM in the underlying storage medium layer. The DRAM ECC unit uses the Hamming code algorithm to perform byte-level protection and supports correcting one bit and detecting two bits.

[0031] The MRAM controller includes an MRAM ECC unit and an MRAM interface. The MRAM interface is responsible for completing data interaction with the external MRAM in the underlying storage medium layer. The MRAM ECC unit uses a simplified version of the BCH algorithm to perform single-byte or double-byte protection and supports correcting 2 bits and detecting 3 bits. To further improve reliability, the MRAM ECC unit also uses the Reed-Solomon code RS algorithm to perform 4-byte or 8-byte protection and supports correcting 3 bits and detecting 4 bits.

[0032] In this embodiment, the data flow path between components of the system is as follows: for the write direction of the user data flow, it is from the FTL mapping manager to the MRAM controller or from the FTL mapping manager to the NAND controller; for the read direction of the user data flow, it is from the NAND controller to the DRAM controller, and then from the DRAM controller to the external DRAM or from the DRAM controller to the FTL mapping manager; for the write direction of the mapping table data flow, it is from the NAND controller to the DRAM controller, and for the read direction of the mapping table data flow, it is from the DRAM controller to the NAND controller; for the write direction of the Delta data flow, it is from the FTL mapping manager to the MRAM controller, and for the read direction of the Delta data flow, it is from the MRAM controller to the DRAM controller; for the write direction of the Log data flow, it is from the FTL mapping manager to the MRAM controller, and for the read direction of the Log data flow, it is from the MRAM controller to the FTL mapping manager.

[0033] In this embodiment, a storage buffer CMB is provided in the memory address of the SSD controller. The CMB configuration supported by the SSD controller is submitted to the host side through the NVME Identify command. The host side configures the base address and offset address of the storage buffer CMB in the NVME register through the PCIE interface by CMBLOC, and configures the size of the storage buffer CMB by CMBSZ; for the send queue implemented based on the CMB, the host directly writes the commands in the send queue into the internal storage buffer CMB of the SSD controller, which reduces the action of a controller reading commands from the host and can reduce the latency of command execution.

[0034] Similarly, the PRP list or SGL list needs to be read separately on the PCIe interface, and this can also reduce the read action of the controller by writing the PRP or SGL into the controller memory buffer. Without adopting this mode, the host side will write the PRP or SGL list into the DRAM of the upper computer. After enabling the CMB mode, the upper computer can write the PRP or SGL list into the CMB in the SSD controller to achieve the purpose of reducing latency.

[0035] The external MRAM is provided with a permanent memory area PMR. The permanent memory area PMR is managed through the NVME protocol and uses the MRAM medium to achieve read and write operations in units of 1 / 2 / 4 / 8 bytes. For the read and write access of MRAM, the built-in MCU or CPU can be used for byte-by-byte access, without the need to read and write according to a certain page size like the NAND FLASH permanent storage medium, which improves the flexibility. To achieve low latency, the read and write latencies of the MRAM medium are fixed, so they are predictable; at the same time, the read and write speeds of this medium are similar to those of DRAM, and it is a medium with low-latency access. Therefore, it can provide a predictable low-latency mode, and the data will not be lost after power-off. It is used to store user data that needs to be modified frequently, improve the durability of the system, reduce the programming and erasing times of NAND FLASH, and is specifically used for environments that need to frequently access complex data sets. At the same time, it provides a predictable low-latency mode to the NVME host side. Since the data in this area does not need to consider factors such as garbage collection and wear leveling, the impact of flash garbage collection and other maintenance operations on the random read latency is greatly reduced.

[0036] The above description is only the basic principle and preferred embodiments of the present invention. The improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

1. A hybrid NVME SSD storage system based on MRAM cache, characterized in that: it includes an SSD controller, a volatile storage layer, and a non-volatile storage layer. The SSD controller includes a PCIe interface, an NVME command parser, an FTL mapping manager, a NAND controller, an MRAM controller, and a DRAM controller. The volatile storage layer includes an external DRAM, and the non-volatile storage layer includes an external NAND and an external MRAM. The PCIe interface, the NVME command parser, and the FTL mapping manager are connected in sequence. The NAND controller, the MRAM controller, and the DRAM controller are all connected to the FTL mapping manager. The external DRAM is connected to the DRAM controller, the external NAND is connected to the NAND controller, and the external MRAM is connected to the MRAM controller; The PCIe interface is used for data transmission with the upper application layer. The NVME command parser is used to process the NVME protocol and complete the creation and use of the storage buffer CMB inside the SSD controller and the permanent memory area PMR in the external MRAM in the non-volatile storage layer. The FTL mapping manager is responsible for maintaining the mapping relationship between the logical block address LBA and the physical block address PBA of the storage medium in the volatile storage layer and the non-volatile storage layer; The external DRAM is used to store read data cache and FTL mapping table. The external NAND is used to store user data in ordinary applications and FTL mapping table. The external MRAM is used to store CMB data, PMR data, write data cache, FTL mapping table change amount Delta, and Log data. When using the volatile storage layer of the external DRAM, the FTL mapping manager places the FTL mapping table and read data cache in the external DRAM through the DRAM controller. When using the MRAM storage area in the non-volatile storage layer, the FTL mapping manager places the write data cache, Delta data, and Log data in the external MRAM through the MRAM controller. When using the NAND FLASH storage area in the non-volatile storage layer, the FTL mapping manager places the user data in the external NAND through the NAND controller. There is a permanent memory area PMR in the external MRAM. The permanent memory area PMR is managed through the NVME protocol and uses the MRAM medium to achieve read and write by 1 / 2 / 4 / 8 bytes.

2. The hybrid NVME SSD storage system based on MRAM cache according to claim 1, characterized in that: Based on the component - to - component data flow path of this system: The write direction of the user data flow is from the FTL mapping manager to the MRAM controller or from the FTL mapping manager to the NAND controller; The read direction of the user data flow is from the NAND controller to the DRAM controller, and then from the DRAM controller to the external DRAM or from the DRAM controller to the FTL mapping manager; The write direction of the mapping table data stream is from the NAND controller to the DRAM controller, and the read direction of the mapping table data stream is from the DRAM controller to the NAND controller; the write direction of the Delta data stream is from the DRAM controller to the MRAM controller, and the read direction of the Delta data stream is from the MRAM controller to the DRAM controller; the write direction of the Log data stream is from the FTL mapping manager to the MRAM controller, and the read direction of the Log data stream is from the MRAM controller to the FTL mapping manager.

3. The hybrid NVME SSD storage system based on MRAM cache according to claim 1, characterized in that: A storage buffer CMB is provided in the memory address of the SSD controller. The CMB configuration supported by the SSD controller is submitted to the host side through the NVME Identify command. The host side configures the base address and offset address of the storage buffer CMB in the NVME register through the CMBLOC of the PCIE interface, and configures the size of the storage buffer CMB through the CMBSZ; for the transmit queue implemented based on the CMB, the host directly writes the commands in the transmit queue into the internal storage buffer CMB of the SSD controller.

4. The hybrid NVME SSD storage system based on MRAM cache according to claim 3, characterized in that: The PRPlist or SGL list needs to perform a separate read operation on the PCIe interface, and the read operation of the controller is reduced by writing the PRP or SGL into the internal storage buffer CMB of the SSD controller.

5. The hybrid NVME SSD storage system based on MRAM cache according to claim 1, characterized in that: The persistent memory area PMR provides a predictable low-latency mode to the NVME host side.

6. The hybrid NVME SSD storage system based on MRAM cache according to claim 1, characterized in that: The NAND controller includes a NAND ECC unit and a NAND interface. The NAND interface is responsible for data interaction with the external NAND in the underlying storage medium layer. The NAND ECC unit uses a low-density forward error correction code LDPC error correction algorithm to protect data blocks.

7. The hybrid NVME SSD storage system based on MRAM cache according to claim 1, characterized in that: The DRAM controller includes a DRAM ECC unit and a DRAM interface. The DRAM interface is responsible for data interaction with the external DRAM in the underlying storage medium layer. The DRAM ECC unit uses the Hamming code algorithm for byte-by-byte protection and supports correcting one bit and detecting two bits.

8. The hybrid NVME SSD storage system based on MRAM cache according to claim 1, characterized in that: The MRAM controller includes an MRAM ECC unit and an MRAM interface. The MRAM interface is responsible for data interaction with the external MRAM in the underlying storage medium layer. The MRAM ECC unit uses a simplified version of the BCH algorithm for protection by single byte or double byte, supporting correction of 2 bits and detection of 3 bits; or the MRAM ECC unit uses the Reed-Solomon (RS) code algorithm for protection by 4 bytes or 8 bytes, supporting correction of 3 bits and detection of 4 bits.

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