memory devices

Abstract

This document provides a memory device comprising: a memory block having memory cells connected to word lines and bit lines; a page buffer connected to the memory block via bit lines, configured during programming operations to convert raw data received from an external device into variable data grouped according to the amount of specific data, and configured to apply a programming enable voltage or programming disable voltage to the bit lines according to the variable data; and a data mode manager configured to control the page buffer to convert raw data into variable data during programming operations.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to memory devices, and more specifically, to memory devices capable of performing programming operations. Background Technology

[0002] Memory devices may include volatile memory devices that lose the data stored therein when power is interrupted and non-volatile memory devices that retain the data stored therein even when power is interrupted.

[0003] Volatile memory devices may include dynamic random access memory (DRAM) and static random access memory (SRAM). Non-volatile memory devices may include read-only memory (ROM), programmable read-only memory (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), NAND flash, etc.

[0004] A memory device may include a memory cell array, peripheral circuitry, and control logic circuitry.

[0005] A memory cell array may include multiple memory blocks, and each of the multiple memory blocks may include multiple memory cells capable of storing data. Peripheral circuitry may be configured to perform programming, reading, or erasing operations based on control logic circuitry. The control logic circuitry may be configured to control the peripheral circuitry in response to input commands according to programming, reading, or erasing algorithms. Summary of the Invention

[0006] Embodiments of this disclosure may provide a memory device comprising: a memory block including memory cells connected to word lines and bit lines; a page buffer connected to the memory block via bit lines, configured during programming operations to convert raw data received from an external device into variable data grouped according to the amount of specific data, and configured to apply a programming enable voltage or programming disable voltage to the bit lines according to the variable data; and a data mode manager configured to control the page buffer to convert raw data into variable data during programming operations.

[0007] Embodiments of this disclosure may provide a memory device comprising: a page buffer having a plurality of latches configured to store first logical page data, second logical page data, and third logical page data respectively in a portion of the latches; and a data mode manager configured to control the page buffer to convert raw data into variable data by moving the first logical page data to the third logical page data between the latches, wherein, when the raw data is converted into variable data, the data mode manager is configured to control the page buffer to generate variable data having a data combination divided into multiple groups according to the number of specific data included in the first logical page data to the third logical page data.

[0008] Embodiments of this disclosure may provide a memory device comprising: a memory cell programmed into various states according to a combination of N bits of data; peripheral circuitry configured to receive raw data to perform programming operations on the memory cell and convert the raw data into variable data divided into a first group to a (N+1)th group according to the amount of specific data; and control logic circuitry configured to control the peripheral circuitry to convert the raw data into variable data and to control the peripheral circuitry to program the memory cell using the variable data. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a memory system according to the present disclosure.

[0010] Figure 2 This is a diagram illustrating a memory device according to the present disclosure.

[0011] Figure 3 This is a diagram illustrating a storage block according to this disclosure.

[0012] Figure 4 This is a diagram illustrating a page buffer group according to the present disclosure.

[0013] Figure 5 This is a diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0014] Figure 6 This is a diagram illustrating programming operations according to this disclosure.

[0015] Figures 7A to 7C This is a diagram illustrating the operation of the page buffer according to this disclosure.

[0016] Figure 8 This is a diagram illustrating a data conversion method according to a first embodiment of the present disclosure.

[0017] Figure 9A and Figure 9BThe diagram illustrates various embodiments of the conversion data according to the first embodiment of this disclosure.

[0018] Figure 10 This is a diagram illustrating a data conversion method according to a second embodiment of the present disclosure.

[0019] Figure 11A and Figure 11B The diagram illustrates various embodiments of the conversion data according to the second embodiment of this disclosure.

[0020] Figure 12 This is a diagram illustrating a memory card system using the memory device of the present disclosure.

[0021] Figure 13 This is a diagram illustrating a solid-state drive (SSD) system that utilizes the memory device of this disclosure. Detailed Implementation

[0022] Various embodiments of this disclosure relate to memory devices capable of converting raw data input into a memory device into variable data partitioned according to given rules during programming operations.

[0023] Figure 1 This is a diagram illustrating a memory system according to the present disclosure.

[0024] Reference Figure 1 The memory system 1000 may include a storage device 1100 and a memory controller 1200. The storage device 1100 may include a plurality of memory devices MD, and the memory devices MD may be connected to the memory controller 1200 via channels.

[0025] The memory controller 1200 can communicate between the host 1500 and the memory device MD. The memory controller 1200 can generate a command CMD in response to a request RQ from the host 1500 to control the memory device MD, and can perform background operations to improve the performance of the memory system 1000 even without a request RQ from the host 1500. For example, if the host 1500 sends a request RQ and data DATA to the memory system 1000 for programming operations, the memory controller 1200 can convert the received request RQ into a command CMD and send the command CMD and data DATA to the storage device 1100. The selected memory device MD among those included in the storage device 1100 can receive the command CMD and data DATA output from the memory controller 1200, and can program the data DATA in response to the command CMD.

[0026] The memory device MD can convert raw data DATA received from the memory controller 1200 and then program the converted data. The memory device MD configured to convert and program the converted data will be described with reference to the following figures.

[0027] The host 1500 can generate request RQs for various operations and output the generated request RQs to the memory system 1000. For example, the request RQs may include programming requests for controlling programming operations, read requests for controlling read operations, and erase requests for controlling erase operations.

[0028] The host 1500 can communicate with the memory system 1000 through various interfaces such as the following: PCIe interface, Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, Parallel ATA (PATA) interface, Serial Attached SCSI (SAS) interface, NVMe interface, Universal Serial Bus (USB) interface, Multimedia Card (MMC) interface, Enhanced Small Disk Interface (ESDI) or Integrated Drive Electronics (IDE) interface.

[0029] Figure 2 This is a diagram illustrating a memory device according to the present disclosure.

[0030] Reference Figure 2 The memory device MD may include a memory cell array 110 that stores data therein, peripheral circuitry 200 that performs programming, reading or erasing operations, and control logic circuitry 300 that controls the peripheral circuitry 200.

[0031] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKi. Each of the memory blocks BLK1 to BLKi (i is a positive integer) may include a plurality of memory cells, and the memory cells may be implemented as a two-dimensional structure arranged parallel to the substrate or a three-dimensional structure stacked perpendicular to the substrate.

[0032] The peripheral circuitry 200 may include a voltage generator 120, a line decoder 130, a page buffer group 140, and an input / output circuitry 150.

[0033] Voltage generator 120 can generate operating voltages required for various operations in response to voltage code VCD, and can output the operating voltages through global line GL. For example, voltage generator 120 can generate programming voltage, verification voltage, read voltage, pass voltage, erase voltage, etc. in response to voltage code VCD, and can output the generated operating voltages through global line GL.

[0034] The row decoder 130 can select a memory block from memory blocks BLK1 to BLKi included in the memory cell array 110 according to the row address RADD, and can send an operating voltage through a local line LL connected to the selected memory block. For example, the row decoder 130 can receive the operating voltage through the global line GL and can send the operating voltage to the selected memory block through the selected local line LL in response to the row address RADD.

[0035] Page buffer group 140 can be connected to memory cell array 110 via bit line BL. For example, page buffer group 140 may include multiple page buffers, each connected to bit line BL. Multiple page buffers can operate simultaneously in response to page buffer control signal PBCTS and can temporarily store data during programming or reading operations. After page buffer group 140 stores raw data received from input / output circuitry 150 during programming operations, page buffer group 140 can generate variable data by transforming the raw data according to a given rule in response to page buffer control signal PBCTS. If variable data is generated, the variable data, instead of the raw data, can be stored in page buffer group 140. Memory device MD can perform programming operations using the variable data.

[0036] Input / output circuit 150 can be connected to memory controller 1200 via input / output lines (see...). Figure 1 Input / output circuit 150 can input and output commands CMD, addresses ADD, and data DATA via input / output lines. For example, input / output circuit 150 can send commands CMD and addresses ADD received via input / output lines to control logic circuit 300, and can send data DATA received from memory controller 1200 via input / output lines to page buffer group 140 during programming operations. The data DATA sent by input / output circuit 150 can be raw data.

[0037] The control logic circuit 300 can output voltage code VCD, row address RADD, and page buffer control signal PBCTS in response to command CMD and address ADD. For example, the control logic circuit 300 may include software configured to execute an algorithm in response to command CMD and hardware configured to output various signals according to address ADD and the algorithm. Furthermore, the control logic circuit 300 may include a data pattern manager 310, which is configured to convert raw data input to page buffer group 140 into variable data during programming operations.

[0038] The data pattern manager 310 can be configured to convert raw data into variable data according to a given rule. For example, the data pattern manager 310 can divide the target programming state of the memory cell into multiple groups based on the amount of specific data, and can convert the raw data into variable data such that the amount of specific data included in the variable data is the same within each group. In other words, the amount of specific data can be set in the raw data in various ways, regardless of the target programming state, but according to this embodiment, the amount of specific data in the variable data can be set to constant based on the group of the target programming state. The specific data can be selected from 0 or 1. In this embodiment, the case where 1 is set as the specific data will be described.

[0039] Figure 3 This is a diagram illustrating a storage block according to this disclosure, and is illustrated by way of example. Figure 2 The i-th storage block BLKi is shown among the multiple storage blocks BLK1 to BLKi.

[0040] Reference Figure 3 The i-th storage block BLKi can include multiple strings ST1 to STj, where j is a positive integer. The first string ST1 to the j-th string STj can be connected between the first bit line BL1 to the j-th bit line BLj and the source line SL. For example, the first string ST1 can be connected between the first bit line BL1 and the source line SL, the second string ST2 can be connected between the second bit line BL2 and the source line SL, and the j-th string STj can be connected between the j-th bit line BLj and the source line SL.

[0041] Each of the first string ST1 to the j-th string STj may include a source-select transistor SST, multiple memory cells C1 to Cn, and a drain-select transistor DST. Although not shown in the figure, dummy cells may also be included between the memory cells C1 to Cn and the source-select transistor SST or the drain-select transistor DST. The j-th string STj can be used as an example to describe the construction of the string in detail.

[0042] The gates of the source selection transistors SST, included in different strings ST1 to STj, can be connected to the source selection line SSL. The gates of the first memory cell C1 to the nth memory cell Cn can be connected to the first word line WL1 to the nth word line WLn. The gates of the drain selection transistors DST can be connected to the drain selection line DSL. For example, the source selection transistor SST included in the j-th string STj can electrically connect or disconnect the source line SL and the first memory cell C1 based on the voltage applied to the source selection line SSL. Variable data can be stored in the first memory cells C1 to the nth memory cell Cn. The drain selection transistor DST can electrically connect or disconnect the j-th bit line BLj and the nth memory cell Cn based on the voltage applied to the drain selection line DSL. A group of memory cells connected to the same word line is called a page PG, and programming and reading operations can be performed based on the page PG.

[0043] Memory cells C1 to Cn can store data with at least one bit, depending on the programming method. For example, storing one bit of data in one memory cell is called the single-level cell method, storing two bits of data in one memory cell is called the multi-level cell method, storing three bits of data in one memory cell is called the three-level cell method, and storing four bits of data in one memory cell is called the four-level cell method. Furthermore, five or more bits of data can be stored in a single memory cell.

[0044] Read operations can be performed in the same way as programming operations. For example, if memory cells included in a selected memory block are programmed using the three-level cell method, then read operations can also be performed using the three-level cell method.

[0045] Figure 4 This is a diagram illustrating a page buffer group according to the present disclosure.

[0046] Reference Figure 4 Page buffer group 140 may include first page buffers PB1 to j-th page buffers PBj respectively connected to the first bit line BL1 to the j-th bit line BLj. First page buffers PB1 to j-th page buffers PBj can operate simultaneously in response to the page buffer control signal PBCTS. During programming operations, first page buffers PB1 to j-th page buffers PBj can be configured to temporarily store data from input / output circuitry 150 (see input / output circuitry 150) in response to the page buffer control signal PBCTS. Figure 2The system outputs the raw data and converts it into variable data. The first page buffer PB1 to the j-th page buffer PBj can apply a programming enable voltage or a programming disable voltage to the first bit line BL1 to the j-th bit line BLj based on the variable data. When voltage is supplied to the first bit line BL1 to the j-th bit line BLj and a programming voltage is applied to the selected page included in the i-th memory block BLKi, the memory cells included in the selected page can be programmed.

[0047] Since the first page buffer PB1 to the j-th page buffer PBj are configured identically, the construction of the page buffers will be described in detail below using the first page buffer PB1 as an example.

[0048] Figure 5 This is a diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0049] Reference Figure 5 The first page buffer PB1 may include first switches S1 to eighteenth switches S18, sensing latches LAS, and first latches LA1 to fourth latches LA4. Because in Figure 5 The circuitry required for this embodiment is shown in the first page buffer PB1, and therefore may be further included with circuitry (not shown) performing various functions. Figure 5 The circuit shown. Page buffer control signal PBCTS (see...) Figure 2 This includes signals controlling the first switch S1 through the eighteenth switch S18. In other words, the first switch S1 through the eighteenth switch S18 can each respond to the page buffer control signal PBCTS (see...). Figure 2 And operation.

[0050] The following will describe it in detail. Figure 5 Each of the switches and latches shown.

[0051] The first switch S1 can be implemented as an NMOS transistor that can electrically connect the first bit line BL1 and the second switch S2 in response to the bit line select signal BLSEL. The second switch S2 can be connected between the first switch S1 and the ground terminal GND and can be implemented as an NMOS transistor that can discharge the node between the first switch S1 and the second switch S2 in response to the bit line discharge signal BLDIS. For example, the first switch S1 can be turned on when a voltage is applied to the first bit line BL1 in the first page buffer PB1, when the voltage or current of the first bit line BL1 is sensed, or when the first bit line BL1 is discharged. The second switch S2 can be turned on when the first bit line BL1 is discharged.

[0052] The third switch S3 can be connected between the node connecting the first switch S1 and the second switch S2 and the current sensing node CSO, and can be implemented as an NMOS transistor that turns on in response to the page buffer sensing signal PBSENSE. The third switch S3 can be turned on when voltage is applied to the first line BL1 in the first page buffer PB1, or when the voltage or current of the first line BL1 is sensed. The fourth switch S4 can be connected between the power supply voltage terminal VCORE and the current sensing node CSO, and can be implemented as an NMOS transistor that turns on in response to the current sensing node control signal SA_CSOC. The third switch S3 and the fourth switch S4 can be turned on when voltage is applied to the first line BL1 in the first page buffer PB1, or when the current in the first line BL1 remains constant.

[0053] The fifth switch S5 can be connected between the current sensing node CSO and the sensing node SO and can be implemented as an NMOS transistor that can be turned on in response to the sensing node transmission signal TRANSO. The fifth switch S5 can be turned on when the voltage of the sensing node SO is transmitted to the current sensing node CSO, when the current sensing node CSO is pre-charged, and when the voltage or current of the current sensing node CSO is transmitted to the sensing node SO. The sixth switch S6 can be connected between the seventh switch S7 and the sensing node SO and can be implemented as a PMOS transistor that can be turned on in response to the inverted pre-charge signal SA_PRE_N. The seventh switch S7 can be connected between the power supply voltage terminal VCORE and the sixth switch S6 and can be implemented as a PMOS transistor that can be turned on or off according to the data stored in the data sensing node QS. The eighth switch S8 can be implemented as a PMOS transistor that can transmit the power supply voltage provided to the power supply voltage terminal VCORE to the node between the sixth switch S6 and the seventh switch S7 in response to the inverted pre-charge signal SA_PRE_N.

[0054] Multiple latches LAS, LA1, LA2, LA3, and LA4 can be connected to the sensing node SO via multiple switches S9 to S18. For example, the sensing latch LAS can be connected to the sensing node SO via the ninth switch S9 and the tenth switch S10; the first latch LA1 can be connected to the sensing node SO via the eleventh switch S11 and the twelfth switch S12; the second latch LA2 can be connected to the sensing node SO via the thirteenth switch S13 and the fourteenth switch S14; the third latch LA3 can be connected to the sensing node SO via the fifteenth switch S15 and the sixteenth switch S16; and the fourth latch LA4 can be connected to the sensing node SO via the seventeenth switch S17 and the eighteenth switch S18. Additionally, more latches can be connected to the sensing node SO. A detailed description follows. Figure 5The diagram shows multiple latches LAS, LA1, LA2, LA3 and LA4, and multiple switches S9 to S18.

[0055] Ninth switch S9 and tenth switch S10 can be connected between sensing node SO and ground terminal GND, and sensing latch LAS can be connected to the gate of tenth switch S10. Ninth switch S9 can be implemented as an NMOS transistor that connects sensing node SO and tenth switch S10 in response to sensing transmission signal TRANS. Tenth switch S10 can be implemented as an NMOS transistor that connects or disconnects ninth switch S9 and ground terminal GND according to data stored in sensing node QS by sensing latch LAS.

[0056] The sense latch LAS may include an inverter connected between a data sensing node QS and an inverting data sensing node QS_N, which store different data. Conventionally, a transistor configured to connect or disconnect the sense node SO and the inverting data sensing node QS_N is included in region 51 between the sense node SO and the inverting data sensing node QS_N. However, according to this embodiment, the transistor formed in the corresponding region 51 can be removed to reduce the size of the memory device.

[0057] Eleventh switch S11 and twelfth switch S12 can be connected between sensing node SO and ground terminal GND, and first latch LA1 can be connected to the gate of twelfth switch S12. Eleventh switch S11 can be implemented as an NMOS transistor connecting sensing node SO and twelfth switch S12 in response to first transmission signal TRAN1. Twelfth switch S12 can be implemented as an NMOS transistor connecting or disconnecting eleventh switch S11 and ground terminal GND according to data stored in first node Q1 of first latch LA1.

[0058] The first latch LA1 may include an inverter connected between a first node Q1 and a first inverting node Q1_N storing different data. Conventionally, a transistor configured to connect or disconnect the sensing node SO and the first inverting node Q1_N is included in the region 52 between the sensing node SO and the first inverting node Q1_N. However, according to this embodiment, the transistor formed in the corresponding region 52 can be removed to reduce the size of the memory device.

[0059] The thirteenth switch S13 and the fourteenth switch S14 can be connected between the sensing node SO and the ground terminal GND, and the second latch LA2 can be connected to the gate of the fourteenth switch S14. The thirteenth switch S13 can be implemented to connect the sensing node SO and the NMOS transistor of the fourteenth switch S14 in response to the second transmission signal TRAN2. The fourteenth switch S14 can be implemented to connect or disconnect the thirteenth switch S13 and the NMOS transistor of the ground terminal GND according to the data stored in the second node Q2 of the second latch LA2.

[0060] The second latch LA2 may include an inverter connected between a second node Q2 and a second inverting node Q2_N storing different data. Conventionally, a transistor configured to connect or disconnect the sensing node SO and the second inverting node Q2_N is included in region 53 between the sensing node SO and the second inverting node Q2_N. However, according to this embodiment, the transistor formed in the corresponding region 53 can be removed to reduce the size of the memory device.

[0061] The fifteenth switch S15 and the sixteenth switch S16 can be connected between the sensing node SO and the ground terminal GND, and the third latch LA3 can be connected to the gate of the sixteenth switch S16. The fifteenth switch S15 can be implemented to connect the sensing node SO and the NMOS transistor of the sixteenth switch S16 in response to the third transmission signal TRAN3. The sixteenth switch S16 can be implemented to connect or disconnect the fifteenth switch S15 and the NMOS transistor of the ground terminal GND according to the data stored in the third node Q3 of the third latch LA3.

[0062] The third latch LA3 may include an inverter connected between a third node Q3 and a third inverting node Q3_N storing different data. Conventionally, a transistor configured to connect or disconnect the sensing node SO and the third inverting node Q3_N is included in region 54 between the sensing node SO and the third inverting node Q3_N. However, according to this embodiment, the transistor formed in the corresponding region 54 can be removed to reduce the size of the memory device.

[0063] Seventeenth switch S17 and eighteenth switch S18 can be connected between sensing node SO and ground terminal GND, and fourth latch LA4 can be connected to the gate of eighteenth switch S18. Seventeenth switch S17 can be implemented as an NMOS transistor connecting sensing node SO and eighteenth switch S18 in response to fourth transmission signal TRAN4. Eighteenth switch S18 can be implemented as an NMOS transistor connecting or disconnecting seventeenth switch S17 and ground terminal GND according to data stored in fourth node Q4 of fourth latch LA4.

[0064] The fourth latch LA4 may include an inverter connected between a fourth node Q4 and a fourth inverting node Q4_N storing different data. Conventionally, a transistor configured to connect or disconnect the sensing node SO and the fourth inverting node Q4_N is included in region 55 between the sensing node SO and the fourth inverting node Q4_N. However, according to this embodiment, the transistor formed in the corresponding region 55 can be removed to reduce the size of the memory device.

[0065] During programming operations, the first page buffer PB1 can temporarily store raw data received from external devices in first latches LA1 to third latches LA3, and can convert the raw data stored in first latches LA1 to third latches LA3 into variable data. For this purpose, the first page buffer PB1 includes at least one more latch than the number of logical page data. For example, in a three-level cell approach, logical page data may include least significant bit (LSB) data, middle significant bit (CSB) data, and most significant bit (MSB) data. Since three pieces of logical page data are used in the three-level cell approach, the first page buffer PB1 can be configured to include four or more latches.

[0066] Figure 5 The remaining page buffers, not shown, can also be configured and operated in the same manner as the first page buffer PB1. Since the original data stored in the latches of the page buffers are different from each other even if the page buffers operate in the same manner, the variable data transformed in the page buffers can also be different from each other.

[0067] Figure 6 This is a diagram illustrating programming operations according to this disclosure.

[0068] Reference Figure 6 When a programming operation is performed on the i-th memory block BLKi, the first page buffers PB1 to the j-th page buffers PBj included in the page buffer group 140 can receive raw data DATA_OR in response to the page buffer control signal PBCTS and can convert the raw data DATA_OR into variable data DATA_VR according to a given rule. The first page buffers PB1 to the j-th page buffers PBj can program the selected page of the i-th memory block BLKi using the variable data DATA_VR. The steps of the programming operation according to this embodiment will be described below.

[0069] Figures 7A to 7C This is a diagram illustrating the operation of a page buffer according to this disclosure, and the operation described in the first page buffer PB1 is taken as an example.

[0070] Reference Figure 7AIf programming operations begin, in response to the page buffer control signal PBCTS, the raw data DATA_OR, including the least significant bit (LSB), middle significant bit (CSB), and most significant bit (MSB) data, can be input into the first page buffer PB1. Here, the raw data can be data received from an external device. The external device can be the memory controller 1200 (see [link to memory controller]). Figure 1 ).

[0071] Reference Figure 7B The first page buffer PB1 can convert the raw data DATA_OR into variable data DATA_VR in response to the page buffer control signal PBCTS. The variable data DATA_VR can be stored in the first latch LA1 to the third latch LA3 that store the raw data DATA_OR, but it can be stored in a different latch than the latch that stores the raw data DATA_OR. Figure 7B An implementation of overwriting variable data DATA_VR in first latches LA1 to third latches LA3 storing the original data DATA_OR is illustrated. In this implementation, the variable data can have a pattern in which it is divided into multiple groups based on the number of specific data. For example, when data 1 in data 0 and 1 is set as specific data, the variable data can have a pattern in which the erase state and the seven programming states are distinguished from each other based on the number of data 1 in the variable data.

[0072] Reference Figure 7C The first page buffer PB1 can generate a bit line voltage Vbl based on the variable data DATA_VR stored in the first latch LA1 to the third latch LA3 in response to the page buffer control signal PBCTS, and can apply the bit line voltage Vbl to the first bit line BL1. The bit line voltage Vbl can have a programmable disable voltage level or a programmable enable voltage level. For example, the programmable disable voltage level can be a positive voltage level, while the programmable enable voltage level can be 0V.

[0073] Figure 8 A diagram illustrating a data conversion method according to a first embodiment of the present disclosure is shown, wherein a three-level unit method is illustrated as the first embodiment.

[0074] Reference Figure 8In the three-level cell method, the state of a memory cell can be divided into an erase state ER and first programming states P1 to seventh programming states P7. In the erase state ER, the threshold voltage of the memory cell can be the lowest. From the first programming state P1 to the seventh programming state P7, the memory cell can have progressively increasing threshold voltages. The state of the memory cell can be determined based on a combination of the least significant bit (LSB) data, the center significant bit (CSB) data, and the most significant bit (MSB) data. For example, in the original data DATA_OR, the erase state ER can be set to 1 for the least significant bit (LSB), 1 for the center significant bit (CSB), and 1 for the most significant bit (MSB). If the original data DATA_OR set in each of the first programming states P1 to the seventh programming state P7 is arranged in the order of LSB, CSB, and MSB, it can be 110, 100, 000, 010, 011, 001, and 101. Figure 8 The raw data DATA_OR shown can have any setting mode to aid in understanding this implementation, and can be set to any of the following: Figure 8 Various modes other than the one shown.

[0075] However, since the raw data DATA_OR corresponding to each of the erase state ER and the first programming states P1 to the seventh programming states P7 is not set in the predetermined mode, a large number of latches may be required for each of the page buffers to perform programming operations using the raw data DATA_OR.

[0076] Therefore, according to this embodiment, in order to minimize the number of latches included in the page buffer, the original data DATA_OR can be converted into variable data DATA_VR using a given rule. The operation of converting the original data DATA_OR into variable data DATA_VR can be performed by, for example... Figure 2 The data pattern manager 310 shown is executing. Although Figure 2 An example is shown where the data mode manager 310 is included in the control logic circuit 300 (see...). Figure 2 However, the data mode manager can be set independently in the control logic circuit 300 (see...). Figure 2 )external.

[0077] According to the given rules of this embodiment, the combination of LSB data, CSB data, and MSB data can be divided into multiple groups according to the specific amount of data, and the state of the memory cell can correspond to the different data combinations contained in each group. For example, the erase state ER can be set to a combination of LSB data, CSB data, and MSB data with a data quantity (#N) of three (3), the first programming state P1 to the third programming state P3 can be set to a combination of LSB data, CSB data, and MSB data with a data quantity (#N) of two (2), the fourth programming state P4 to the sixth programming state P6 can be set to a combination of LSB data, CSB data, and MSB data with a data quantity (#N) of one, and the seventh programming state P7 can be set to a combination of LSB data, CSB data, and MSB data with a data quantity (#N) of zero (0).

[0078] In other words, in the original data DATA_OR, the number of data 1s (#N) included in the combinations of LSB, CSB, and MSB data from the first programming state P1 to the third programming state P3 is 2, 1, and 0, respectively, and the number of data 1s (#N) included in the combinations of LSB, CSB, and MSB data from the fourth programming state P4 to the sixth programming state P6 is 1, 2, and 1, respectively. Therefore, the original data DATA_OR may not be able to adhere to the given rule.

[0079] However, the variable data DATA_VR converted according to this embodiment can be set according to a given rule, in which the data combinations corresponding to the erase state ER to the seventh programming state P7 are divided according to the number of data 1. The variable data DATA_VR according to the first embodiment will be described in detail below.

[0080] Figure 9A and Figure 9B The diagram illustrates various embodiments of converted data according to the first embodiment of this disclosure.

[0081] Reference Figure 9A The erase state ER with the lowest threshold voltage can be set to a combination of LSB data, CSB data and MSB data with a data 1 quantity (#N) of three (3). The first programming state P1 to the third programming state P3 can be set to a combination of LSB data, CSB data and MSB data with a data 1 quantity (#N) of two (2). The fourth programming state P4 to the sixth programming state P6 can be set to a combination of LSB data, CSB data and MSB data with a data 1 quantity (#N) of one (1). The seventh programming state P7 with the highest threshold voltage can be set to a combination of LSB data, CSB data and MSB data with a data 1 quantity (#N) of zero (0).

[0082] For example, the variable data DATA_VR corresponding to the erase state ER can be set to 111 in the order of LSB, CSB, MSB. The variable data DATA_VR corresponding to the first programming states P1 to the third programming states P3 can be set to 110, 101, and 011 in the order of LSB, CSB, and MSB. The variable data DATA_VR corresponding to the fourth programming states P4 to the sixth programming states P6 can be set to 010, 100, and 001 in the order of LSB, CSB, and MSB. The variable data DATA_VR corresponding to the seventh programming state P7 can be set to 000 in the order of LSB, CSB, and MSB.

[0083] Assuming the data combination with the most instances of data 1 is called the first group, and the data combination with the fewest instances of data 1 is called the second group, then in groups of data combinations other than the first and second groups, the matching of the memory cell state with the variable data DATA_VR can be changed in various ways. In other words, the matching of the memory cell state with the variable data DATA_VR included in groups having the same number of instances of data 1 can be changed in various ways. Among these data combinations, reference will be made to... Figure 9B Description and Figure 9A The data combinations shown are different data combinations.

[0084] Reference Figure 9B , as in reference Figure 9A As in the described implementation, the number of data 1 is set to three (3) in the erase state ER, the number of data 1 is set to two (2) in the first programming state P1 to the third programming state P3, the number of data 1 is set to one (1) in the fourth programming state P4 to the sixth programming state P6, and data 1 is not included in the seventh programming state P7.

[0085] In groups with the same number of data 1s, and excluding the groups with the most and fewest data 1s, the matching of memory cell states P1 to P3 and P4 to P6 with variable data DATA_VR can be changed in various combinations. For example, the variable data DATA_VR corresponding to the erase state ER can be set to 111 in the order of LSB, CSB, and MSB. The variable data DATA_VR corresponding to the first programming states P1 to the third programming states P3 can be set to 011, 101, and 110 in the order of LSB, CSB, and MSB. The variable data DATA_VR corresponding to the fourth programming states P4 to the sixth programming states P6 can be set to 010, 001, and 100 in the order of LSB, CSB, and MSB. The variable data DATA_VR corresponding to the seventh programming state P7 can be set to 000 in the order of LSB, CSB, and MSB.

[0086] In the three-level cell method, since three logical page data LSB, CSB and MSB are used, the combination of variable data DATA_VR that can be generated according to this embodiment can be changed in various ways as shown in Tables 1 to 36.

[0087] Table 1

[0088] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 1 0 0 1 0 0 CSB 1 1 0 1 1 0 0 0 MSB 1 0 1 1 0 0 1 0

[0089] Table 2

[0090] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 1 0 1 0 0 0 CSB 1 1 0 1 0 1 0 0 MSB 1 0 1 1 0 0 1 0

[0091] Table 3

[0092] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 1 0 1 0 0 0 CSB 1 1 0 1 0 0 1 0 MSB 1 0 1 1 0 1 0 0

[0093] Table 4

[0094]

[0095]

[0096] Table 5

[0097] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 1 0 0 0 1 0 CSB 1 1 0 1 1 0 0 0 MSB 1 0 1 1 0 1 0 0

[0098] Table 6

[0099] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 1 0 0 0 1 0 CSB 1 1 0 1 0 1 0 0 MSB 1 0 1 1 1 0 0 0

[0100] Table 7

[0101] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 0 1 0 0 CSB 1 1 0 1 1 0 0 0 MSB 1 1 1 0 0 0 1 0

[0102] Table 8

[0103] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 1 0 0 0 CSB 1 1 0 1 0 1 0 0 MSB 1 1 1 0 0 0 1 0

[0104] Table 9

[0105] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 1 0 0 0 CSB 1 1 0 1 0 0 1 0 MSB 1 1 1 0 0 1 0 0

[0106] Table 10

[0107] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 0 1 0 0 CSB 1 1 0 1 0 0 1 0 MSB 1 1 1 0 1 0 0 0

[0108] Table 11

[0109] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 0 0 1 0 CSB 1 1 0 1 1 0 0 0 MSB 1 1 1 0 0 1 0 0

[0110] Table 12

[0111] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 0 0 1 0 CSB 1 1 0 1 0 1 0 0 MSB 1 1 1 0 1 0 0 0

[0112] Table 13

[0113] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 1 0 0 1 0 0 CSB 1 0 1 1 1 0 0 0 MSB 1 1 0 1 0 0 1 0

[0114] Table 14

[0115] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 1 0 1 0 0 0 CSB 1 0 1 1 0 1 0 0 MSB 1 1 0 1 0 0 1 0

[0116] Table 15

[0117]

[0118]

[0119] Table 16

[0120] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 1 0 0 1 0 0 CSB 1 0 1 1 0 0 1 0 MSB 1 1 0 1 1 0 0 0

[0121] Table 17

[0122] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 1 0 0 0 1 0 CSB 1 0 1 1 1 0 0 0 MSB 1 1 0 1 0 1 0 0

[0123] Table 18

[0124] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 1 0 0 0 1 0 CSB 1 0 1 1 0 1 0 0 MSB 1 1 0 1 1 0 0 0

[0125] Table 19

[0126] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 0 1 0 0 CSB 1 0 1 1 1 0 0 0 MSB 1 1 1 0 0 0 1 0

[0127] Table 20

[0128] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 1 0 0 0 CSB 1 0 1 1 0 1 0 0 MSB 1 1 1 0 0 0 1 0

[0129] Table 21

[0130] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 1 0 0 0 CSB 1 0 1 1 0 0 1 0 MSB 1 1 1 0 0 1 0 0

[0131] Table 22

[0132] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 0 1 0 0 CSB 1 0 1 1 0 0 1 0 MSB 1 1 1 0 1 0 0 0

[0133] Table 23

[0134] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 0 0 1 0 CSB 1 0 1 1 1 0 0 0 MSB 1 1 1 0 0 1 0 0

[0135] Table 24

[0136] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 0 0 1 0 CSB 1 0 1 1 0 1 0 0 MSB 1 1 1 0 1 0 0 0

[0137] Table 25

[0138] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 0 1 0 0 CSB 1 1 1 0 1 0 0 0 MSB 1 1 0 1 0 0 1 0

[0139] Table 26

[0140]

[0141]

[0142] Table 27

[0143] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 1 0 0 0 CSB 1 1 1 0 0 0 1 0 MSB 1 1 0 1 0 1 0 0

[0144] Table 28

[0145] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 0 1 0 0 CSB 1 1 1 0 0 0 1 0 MSB 1 1 0 1 1 0 0 0

[0146] Table 29

[0147] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 0 0 1 0 CSB 1 1 1 0 1 0 0 0 MSB 1 1 0 1 0 1 0 0

[0148] Table 30

[0149] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 0 1 1 0 0 1 0 CSB 1 1 1 0 0 1 0 0 MSB 1 1 0 1 1 0 0 0

[0150] Table 31

[0151] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 0 1 0 0 CSB 1 1 1 0 1 0 0 0 MSB 1 0 1 1 0 0 1 0

[0152] Table 32

[0153] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 1 0 0 0 CSB 1 1 1 0 0 1 0 0 MSB 1 0 1 1 0 0 1 0

[0154] Table 33

[0155] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 1 0 0 0 CSB 1 1 1 0 0 0 1 0 MSB 1 0 1 1 0 1 0 0

[0156] Table 34

[0157] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 0 1 0 0 CSB 1 1 1 0 0 0 1 0 MSB 1 0 1 1 1 0 0 0

[0158] Table 35

[0159] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 0 0 1 0 CSB 1 1 1 0 1 0 0 0 MSB 1 0 1 1 0 1 0 0

[0160] Table 36

[0161] ER P1 P2 P3 P4 P5 P6 P7 LSB 1 1 0 1 0 0 1 0 CSB 1 1 1 0 0 1 0 0 MSB 1 0 1 1 1 0 0 0

[0162] Referring to Tables 1 to 36, it can be seen that the variable data DATA_VR matched with the erase state ER, which has the lowest threshold voltage, is all fixed at 111, and the variable data DATA_VR matched with the seventh programming state P7, which has the highest threshold voltage, is all fixed at 000. Furthermore, it can be seen that the number of data 1s in the variable data DATA_VR matched with the first programming states P1 to the third programming states P3 is 2, and the number of data 1s in the variable data DATA_VR matched with the fourth programming states P4 to the sixth programming states P6 is 1.

[0163] Figure 10 The diagram illustrates a data conversion method according to a second embodiment of the present disclosure, wherein a four-level unit method is shown as the second embodiment.

[0164] Reference Figure 10 In the four-level cell method, the state of a memory cell can be divided into an erase state ER and first programming states P1 to fifteenth programming states P15. In the erase state ER, the threshold voltage of the memory cell can be the lowest. From the first programming state P1 to the fifteenth programming state P15, the memory cell can have progressively increasing threshold voltages. The state of the memory cell can be determined based on a combination of the least significant bit (LSB) data, the first center significant bit (LCSB) data, the second center significant bit (MCSB) data, and the most significant bit (MSB) data. For example, in the original data DATA_OR, the erase state ER can be set to 1 for the least significant bit (LSB), 1 for the center significant bit (CSB), and 1 for the most significant bit (MSB). If the original data DATA_OR set in each of the first programming states P1 to the fifteenth programming state P15 is arranged in the order of LSB, LCSB, MCSB and MSB, they can be 1100, 1110, 1100, 1000, 0000, 0100, 0101, 0111, 0110, 0010, 1010, 1011, 0011, 0001, 1001, 1101. Figure 10 The raw data DATA_OR shown can have any setting mode to aid in understanding this implementation, and can be set to any of the following: Figure 10 Various modes other than the one shown.

[0165] However, since the raw data DATA_OR corresponding to each of the erase state ER and the first programming states P1 to the fifteenth programming states P15 is not set in a predetermined pattern, a large number of latches may be required for each of the page buffers to perform programming operations by using the raw data DATA_OR.

[0166] Therefore, according to this embodiment, in order to minimize the number of latches included in the page buffer, the original data DATA_OR can be converted into variable data DATA_VR using a given rule. The operation of converting the original data DATA_OR into variable data DATA_VR can be performed by, for example... Figure 2 The data pattern manager 310 shown is executing. Although Figure 2 An example is shown where the data mode manager 310 is included in the control logic circuit 300 (see...). Figure 2 However, the data mode manager can be set independently in the control logic circuit 300 (see...). Figure 2 The outside of ).

[0167] According to the given rules of this embodiment, the combination of LSB data, LCSB data, MCSB data and MSB data can be divided into multiple groups according to the specific amount of data, and the state of the memory cell can correspond to the different data combinations included in each group. For example, the erase state ER can be set to a combination of LSB, LCSB, MCSB and MSB with a data 1 quantity (#N) of four (4), the first programming state P1 to the fourth programming state P4 can be set to a combination of LSB, LCSB, MCSB and MSB with a data 1 quantity (#N) of three (3), the fifth programming state P5 to the tenth programming state P10 can be set to a combination of LSB, LCSB, MCSB and MSB with a data 1 quantity (#N) of two (2), the eleventh programming state P11 to the fourteenth programming state P14 can be set to a combination of LSB, LCSB, MCSB and MSB with a data 1 quantity (#N) of one (1), and the fifteenth programming state P15 can be set to a combination of LSB, LCSB, MCSB and MSB with a data 1 quantity (#N) of zero (0).

[0168] In other words, in the original data DATA_OR, the number of data 1s (#N) in the data combinations of LSB, LCSB, MCSB, and MSB in the first programming state P1 to the fourth programming state P4 are 3, 2, 1, and 0, respectively; the number of data 1s (#N) in the data combinations of LSB, LCSB, MCSB, and MSB in the fifth programming state P5 to the tenth programming state P10 are 1, 2, 3, 2, and 1, respectively; the number of data 1s (#N) in the data combinations of LSB, LCSB, MCSB, and MSB in the eleventh programming state P11 to the fourteenth programming state P14 are 3, 2, 1, and 2, respectively; and the number of data 1s (#N) in the data combinations of LSB, LCSB, MCSB, and MSB in the fifteenth programming state P15 is 3. Therefore, there is no given rule.

[0169] However, the variable data DATA_VR converted according to this embodiment can be set according to a given rule, in which the data combinations corresponding to the erase state ER to the fifteenth programming state P15 are divided according to the number of data 1. The variable data DATA_VR according to the second embodiment will be described in detail below.

[0170] Figure 11A and Figure 11B The diagram illustrates various embodiments of the conversion data according to the second embodiment of this disclosure.

[0171] Reference Figure 11A The erase state ER with the lowest threshold voltage can be set to a combination of LSB, LCSB, MCSB and MSB with a data number (#N) of four (4). The first programming state P1 to the fourth programming state P4 can be set to a combination of LSB, LCSB, MCSB and MSB with a data number (#N) of three (3). The fifth programming state P5 to the tenth programming state P10 can be set to a combination of LSB, LCSB, MCSB and MSB with a data number (#N) of two (2). The eleventh programming state P11 to the fourteenth programming state P14 can be set to a combination of LSB, LCSB, MCSB and MSB with a data number (#N) of one (1). The fifteenth programming state P15 with the highest threshold voltage can be set to a combination of LSB, LCSB, MCSB and MSB with a data number (#N) of zero (0).

[0172] For example, the variable data DATA_VR corresponding to the erase state ER can be set to 1111 in the order of LSB, LCSB, MCSB, and MSB. The variable data DATA_VR corresponding to the first programming state P1 to the fourth programming state P4 can be set to 1110, 1101, 1011, and 0111 in the order of LSB, LCSB, MCSB, and MSB. The variable data DATA_VR corresponding to the fifth programming state P5 to the tenth programming state P10 can be set to 1100, 1010, 1001, 0110, 0101, and 0011 in the order of LSB, LCSB, MCSB, and MSB. The variable data DATA_VR corresponding to the eleventh programming state P11 to the fourteenth programming state P14 can be set to 1000, 0100, 0010, and 0001 in the order of LSB, LCSB, MCSB, and MSB. The variable data DATA_VR corresponding to programming state P15 can be set to 0000 in the order of LSB, LCSB, MCSB and MSB.

[0173] Assuming the data combination with the most instances of data 1 is called the first group, and the data combination with the fewest instances of data 1 is called the second group, then in the data combinations of groups other than the first and second groups, the matching of the memory cell state with the variable data DATA_VR can be changed in various ways. In other words, the matching of the memory cell state with the variable data DATA_VR included in groups having the same number of instances of data 1 can be changed in various ways. Among these data combinations, reference will be made to... Figure 11B Description and Figure 11A The data combinations shown are different data combinations.

[0174] Reference Figure 11B For reference Figure 11A The implementation described is the same. The number of data 1s is set to four (4) in the erase state ER, the number of data 1s is set to three (3) in the first programming state P1 to the fourth programming state P4, the number of data 1s is set to two (2) in the fifth programming state P5 to the tenth programming state P10, the number of data 1s is set to one (1) in the eleventh programming state P11 to the fourteenth programming state P14, and data 1s are not included in the fifteenth programming state P15 (#N=0).

[0175] In groups with the same number of data 1s, except for the groups with the most and fewest data 1s, the matching of the programming states P1 to P4, P5 to P10, and P11 to P14 of the memory cells with the variable data DATA_VR can be changed in various combinations. For example, the variable data DATA_VR with the erase state ER can be set to 1111 in the order of LSB, LCSB, MCSB, and MSB. The variable data DATA_VR corresponding to the first programming states P1 to the fourth programming states P4 can be set to 0111, 1011, 0111, and 1110 in the order of LSB, LCSB, MCSB, and MSB. The variable data DATA_VR corresponding to the fifth programming states P5 to the tenth programming states P10 can be set to 0011, 0101, 1001, 0110, 1010, and 1100 in the order of LSB, LCSB, MCSB, and MSB. The variable data DATA_VR corresponding to the eleventh programming states P11 to the fourteenth programming states P14 can be set to 0001, 0010, 0100, and 1000 in the order of LSB, LCSB, MCSB, and MSB. The variable data DATA_VR corresponding to the fifteenth programming state P15 can be set to 0000 in the order of LSB, LCSB, MCSB, and MSB.

[0176] In this embodiment, methods for converting raw data DATA_OR to variable data DATA_VR in three-level and four-level cell methods have been disclosed, but this disclosure is not limited thereto. Higher-level cell methods can utilize the same rules and can be set according to the specific amount of data. Within the same group, the combination of programming state and variable data DATA_VR can also be changed in various ways.

[0177] Figure 12 This is a diagram illustrating a memory card system using the memory device of the present disclosure.

[0178] Reference Figure 12 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0179] Memory controller 2100 can be connected to memory device 2200. Memory controller 2100 can be configured to access memory device 2200. For example, memory controller 2100 can be configured to control programming operations, read operations, or erase operations, or to control background operations of memory device 2200. Memory controller 2100 can provide an interface between memory device 2200 and a host. Memory controller 2100 can drive the firmware that controls memory device 2200. Memory device 2200 can be connected to a reference... Figure 2 The memory device MD described is implemented in the same manner.

[0180] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) based on a specific communication protocol. In embodiments, the memory controller 2100 can communicate with external devices via at least one of various communication protocols such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe) protocols. In embodiments, connector 2300 can be defined using at least one of the aforementioned communication protocols.

[0181] In implementations, memory device 2200 can be implemented as any of a variety of non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0182] In this implementation, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card, such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash Card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, Micro MMC, eMMC), an SD card (SD, Mini SD, Micro SD or SDHC), or Universal Flash Storage (UFS).

[0183] Figure 13 This is a diagram illustrating a solid-state drive (SSD) system that utilizes the memory device of this disclosure.

[0184] Reference Figure 13The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 through a signal connector 3001 and can receive power supply voltage through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memory units 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0185] According to embodiments of this disclosure, flash memory 3221 to 322n can be compared with reference to... Figure 2 The described memory device MD has the same configuration.

[0186] SSD controller 3210 can control multiple flash memory devices 3221 to 322n in response to signals received from host 3100. In an implementation, the signal can be based on the interface between host 3100 and SSD 3200. For example, the signal can be defined according to at least one of various interfaces such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe) interface.

[0187] Auxiliary power supply 3230 can be connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can be supplied with power from host 3100 and can be charged by that power. When power supply from host 3100 is unstable, auxiliary power supply 3230 can power SSD 3200. In implementations, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be located within the motherboard and can supply auxiliary power to SSD 3200.

[0188] Buffer memory 3240 can be used as a buffer memory for SSD 3200. For example, buffer memory 3240 can temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or it can temporarily store metadata (e.g., mapping tables) of flash memories 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0189] According to this disclosure, the size of the memory device can be reduced and the reduction in programming speed due to the size reduction can be prevented.

[0190] Cross-reference to related applications

[0191] This application claims priority to Korean Patent Application No. 10-2021-0007384, filed on January 19, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device comprising: A memory block having memory cells, with word lines and bit lines connected to the memory cells; A page buffer, which is connected to the memory block via the bit line, converts raw data received from an external device into variable data with multiple data combinations, which are divided into multiple groups according to the amount of specific data, and applies a programming enable voltage or programming disable voltage to the bit line according to the variable data. as well as A data pattern manager controls the page buffer to convert the raw data into the variable data during the programming operation so that the amount of the specific data included in each of the plurality of data combinations is the same.

2. The memory device according to claim 1, wherein, Each of the page buffers includes multiple latches that store the raw data or the variable data.

3. The memory device according to claim 2, wherein, The data mode manager outputs a page buffer control signal, which controls the page buffer to convert the raw data stored in the latch into the variable data.

4. The memory device according to claim 1, in, Each of the original data and the variable data includes 3 or more bits of data 0 or data 1, and The specific data is set to data 1.

5. The memory device according to claim 1, wherein, In the variable data, The first data combination with the largest number of specific data matches the erase state with the lowest threshold voltage of the memory cell, and The second data combination with the fewest specific data values ​​matches the programming state with the highest threshold voltage.

6. The memory device according to claim 5, wherein, The remaining programming states between the erase state and the programming state with the highest threshold voltage are each matched with a third data combination divided according to the order of threshold voltage changes.

7. The memory device according to claim 6, wherein, The data pattern manager changes the matching of the programming state with the third data combination within a group having the same amount of specific data.

8. A memory device comprising: A page buffer having multiple latches, wherein the page buffer stores first logical page data, second logical page data and third logical page data in a portion of the multiple latches respectively; as well as A data mode manager controls the page buffer to convert the original data into variable data by moving the first logical page data of the original data to the third logical page data between the latches. When the original data is converted into the variable data, the data pattern manager controls the page buffer to generate the variable data, which has multiple data combinations and is divided into multiple groups based on the number of specific data included in the first logical page data to the third logical page data. The number of specific data included in each of the multiple data combinations is the same.

9. The memory device according to claim 8, wherein, The specific data is either data 0 or data 1.

10. The memory device according to claim 8, wherein, The variable data is divided into: In the first group, all the data from the first logical page to the third logical page are the specific data. The second group, in which the specific data refers to two of the data from the first logical page to the third logical page, is comprised of such data. The third group, in which the specific data is one of the first logical page data to the third logical page data, and The fourth group, in which the first logical page data to the third logical page data does not include the specific data.

11. The memory device according to claim 10, wherein, Based on the variable data having the first to the fourth groups, the memory cell is either kept in an erased state or programmed to be in any of the first to the seventh programming states.

12. The memory device according to claim 11, in, The variable data in the first group matches the erasure state. The variable data in the second group matches the first programming state to the third programming state. Wherein, the variable data of the third group matches the fourth to sixth programming states, and The variable data in the fourth group matches the seventh programming state.

13. The memory device according to claim 12, wherein, The variable data that matches each of the first to the third programming states includes different combinations of data from the first to the third logical page data, each containing two specific data items.

14. The memory device according to claim 12, wherein, The variable data that matches each of the fourth to sixth programming states includes different combinations of data from the first logical page data to the third logical page data, each containing a specific piece of data.

15. A memory device comprising: A memory unit that is programmed into various states based on a combination of N bits of data; The peripheral circuit receives raw data to perform programming operations on the memory cell and converts the raw data into variable data with multiple data combinations, which are divided into a first group to the N+1th group according to the amount of specific data. as well as A control logic circuit controls the peripheral circuit to convert the original data into the variable data such that the number of specific data in each of the multiple data combinations included in the first group to the N+1th group is the same, and controls the peripheral circuit to program the memory cell using the variable data.

16. The memory device according to claim 15, wherein, The control logic circuit: Set the first group of the variable data containing N specific data items to the erase state, and Set the (N+1)th group of the variable data that does not contain the specific data to the programming state with the highest threshold voltage.

17. The memory device according to claim 16, wherein, The control logic circuit sets the second group to the Nth group, which are included between the first group and the N+1 group, as a programming state that is included between the erase state and the programming state with the highest threshold voltage.

18. The memory device according to claim 17, wherein, The control logic circuit sets the data combinations included in a group of specific data with the same amount of data into different programming states.

19. The memory device according to claim 15, in, The peripheral circuitry includes a page buffer connected to the memory cell via bit lines. The page buffer temporarily stores the original data based on the control logic circuitry and converts the original data into the variable data.

20. The memory device according to claim 19, wherein, Each of the page buffers includes multiple latches that store the raw data or the variable data.

Images