Method for forming a semiconductor structure
By processing the side wall layers and sacrificial layers alternately arranged in the semiconductor structure, the target pattern reduction problem under the limitations of the lithography machine equipment is solved, the pitch and line width of the target pattern are reduced, and the performance of metal interconnection lines is improved.
Patent Information
- Application Number
- CN202110070502.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-01-19
- Publication Date
- 2025-08-01
- Estimated Expiration
- 2041-01-19
AI Technical Summary
The prior art is difficult to further reduce the pitch and line width between target patterns in semiconductor structures under the limitations of lithography equipment, resulting in the metal line width being too large and unable to meet the increasingly smaller process requirements.
During the formation of the semiconductor structure, a sacrificial layer is formed on the side wall of the first opening with alternately arranged first sub-side wall layer and second sub-side wall layer, and a portion of the pattern definition layer and the sacrificial layer are removed in the second direction to form a second opening, and then a second side wall layer is formed on the side wall of the second opening, and the target layer is etched with the remaining side wall layer as a mask to form a target pattern.
With the process window of the lithography process enlargement, the requirement of continuously reducing the line width of the target pattern is met, the pitch between the target pattern is further reduced, the graphics accuracy and quality are improved, and the electrical connection performance of metal interconnects is enhanced.
Smart Images
Figure CN114823298B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background Art
[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology has continuously advanced towards smaller process nodes driven by Moore's Law, enabling integrated circuits to develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.
[0003] During the development of integrated circuits, generally, as the functional density (i.e., the number of interconnect structures per chip) gradually increases, the geometric size (i.e., the minimum element size that can be produced using process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.
[0004] Currently, in the case of continuously shrinking technology nodes, how to break through the current constraints of lithography equipment and meet the process requirements of smaller and smaller metal line widths has become a challenge. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further reducing the pitch between target patterns.
[0006] To solve the above problem, embodiments of the present invention provide a method for forming a semiconductor structure, including: providing a substrate, the substrate including a target layer for forming a target pattern, a pattern definition layer formed on the target layer, and a plurality of first openings penetrating the pattern definition layer formed in the pattern definition layer, the plurality of first openings extending in a first direction and arranged in a second direction, the second direction and the first direction being perpendicular to each other; forming a first sidewall layer on the sidewalls of the first openings, and along the second direction, the first sidewall layer including alternately arranged first sub-sidewall layers and second sub-sidewall layers; forming a sacrificial layer in the remaining space of the first openings; along the second direction, removing the first sub-sidewall layer, and a part of the width of the pattern definition layer and the sacrificial layer on the sidewalls of the first sub-sidewall layer, or removing the second sub-sidewall layer, and a part of the width of the pattern definition layer and the sacrificial layer on the sidewalls of the second sub-sidewall layer, to form a second opening surrounded by the remaining pattern definition layer, sacrificial layer, and target layer; forming a second sidewall layer on the sidewalls of the second opening; after forming the second sidewall layer, removing the remaining sacrificial layer and pattern definition layer; after removing the remaining sacrificial layer and pattern definition layer, etching the target layer using the remaining first sidewall layer and second sidewall layer as a mask to form a target pattern.
[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0008] The embodiment of the present invention provides a method for forming a semiconductor structure. A first sidewall layer is formed on the sidewall of a first opening. Along a second direction, the first sidewall layer includes alternately arranged first sub-sidewall layers and second sub-sidewall layers. A sacrificial layer is formed in the remaining space of the first opening. Along the second direction, the first sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the first sub-sidewall layer are removed, or the second sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the second sub-sidewall layer are removed, to form a second opening surrounded by the remaining pattern definition layer, sacrificial layer, and target layer. In the embodiment of the present invention, during the process of forming the second opening, by removing the first sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the first sub-sidewall layer, or by removing the second sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the second sub-sidewall layer, the dimensions of the remaining pattern definition layer and sacrificial layer along the second direction are reduced. And by forming a second sidewall layer on the sidewall of the second opening, the second sidewall layer is formed between adjacent first sub-sidewall layers or between adjacent second sub-sidewall layers, that is, the space between adjacent first sub-sidewall layers or between adjacent second sub-sidewall layers is segmented in the second direction by the second sidewall layer. Correspondingly, after etching the target layer using the remaining first sidewall layer and second sidewall layer as a mask, the dimensions of the formed target pattern along the second direction are reduced, that is, the requirement of continuously reducing the pitch of the target pattern is met. Moreover, since a portion of the sacrificial layer will be removed, the initial dimension of the sacrificial layer along the second direction is larger, correspondingly increasing the window of the photolithography process when forming the first opening. In addition, by removing the first sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the first sub-sidewall layer, or by removing the second sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the second sub-sidewall layer, to form the second opening, the window of the photolithography process when forming the second opening is correspondingly increased. Furthermore, it is possible to meet the requirement of continuously reducing the line width of the target pattern while increasing the process window of the photolithography process, thereby facilitating further reduction of the pitch between the target patterns. Description of the Drawings
[0009] Figures 1 to 10 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed Embodiments
[0010] At present, due to the constraints of lithography equipment, the line width of the metal wires formed in semiconductor devices is too large to meet the process requirements of the increasingly smaller line width of the metal wires, making it difficult to further reduce the pitch between the target patterns.
[0011] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a target layer for forming a target pattern, a pattern definition layer is formed on the target layer, and a plurality of first openings penetrating the pattern definition layer are formed in the pattern definition layer, the plurality of first openings extend along a first direction and are arranged along a second direction, the second direction and the first direction are perpendicular to each other; forming a first sidewall layer on the sidewalls of the first openings, along the second direction, the first sidewall layer includes alternately arranged first sub-sidewall layers and second sub-sidewall layers; forming a sacrificial layer in the remaining space of the first openings; along the second direction, removing the first sub-sidewall layer, and part of the width of the pattern definition layer and the sacrificial layer located on the sidewalls of the first sub-sidewall layer, or removing the second sub-sidewall layer, and part of the width of the pattern definition layer and the sacrificial layer located on the sidewalls of the second sub-sidewall layer, to form a second opening surrounded by the remaining pattern definition layer, sacrificial layer and target layer; forming a second sidewall layer on the sidewalls of the second opening; after forming the second sidewall layer, removing the remaining sacrificial layer and pattern definition layer; after removing the remaining sacrificial layer and pattern definition layer, etching the target layer using the remaining first sidewall layer and the second sidewall layer as masks to form a target pattern.
[0012] In the forming method provided by the embodiment of the present invention, a first sidewall layer is formed on the sidewall of the first opening. Along the second direction, the first sidewall layer includes alternately arranged first sub-sidewall layers and second sub-sidewall layers. A sacrificial layer is formed in the remaining space of the first opening. Along the second direction, the first sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the first sub-sidewall layer are removed, or the second sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the second sub-sidewall layer are removed, to form a second opening surrounded by the remaining pattern definition layer, sacrificial layer, and target layer. In the embodiment of the present invention, during the process of forming the second opening, by removing the first sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the first sub-sidewall layer, or by removing the second sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the second sub-sidewall layer, the dimensions of the remaining pattern definition layer and sacrificial layer in the second direction are reduced. And by forming a second sidewall layer on the sidewall of the second opening, a second sidewall layer is formed between adjacent first sub-sidewall layers or between adjacent second sub-sidewall layers, that is, the space between adjacent first sub-sidewall layers or between adjacent second sub-sidewall layers is divided in the second direction by the second sidewall layer. Correspondingly, after etching the target layer using the remaining first sidewall layer and second sidewall layer as a mask, the dimensions of the formed target pattern in the second direction are reduced, that is, the requirement of continuously reducing the pitch of the target pattern is met. Moreover, since a part of the sacrificial layer will be removed, the initial dimension of the sacrificial layer in the second direction is larger, correspondingly increasing the window of the photolithography process when forming the first opening. In addition, by removing the first sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the first sub-sidewall layer, or by removing the second sub-sidewall layer, and a portion of the width of the pattern definition layer and the sacrificial layer located on the sidewall of the second sub-sidewall layer, to form the second opening, the window of the photolithography process when forming the second opening is correspondingly increased. Furthermore, it is possible to meet the requirement of continuously reducing the line width of the target pattern while increasing the process window of the photolithography process, thereby facilitating further reduction of the pitch between the target patterns.
[0013] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.
[0014] Figures 1 to 10 It is a schematic structural diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present invention.
[0015] Reference Figures 1 to 2, a substrate is provided. The substrate includes a target layer 100 for forming a target pattern. A pattern definition layer 101 is formed on the target layer 100, and a plurality of first openings 105 penetrating through the pattern definition layer 101 are formed in the pattern definition layer 101. The plurality of first openings 105 extend in a first direction (such as the Y direction shown in Figure 2 and are arranged in a second direction (such as the X direction shown in Figure 2 ), and the second direction and the first direction are perpendicular to each other.
[0016] The substrate is used to provide a process platform for subsequent process steps.
[0017] In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate, and functional structures such as resistor structures and conductive structures may also be formed in the substrate.
[0018] The target layer 100 is used as a material layer that needs to be patterned subsequently to form a target pattern.
[0019] Among them, the target pattern may be a gate structure, an interconnect trench in a back end of line (BEOL) process, a fin in a fin field effect transistor (FinFET), a channel stack in a gate-all-around (GAA) transistor or a fork sheet transistor, a hard mask (HM) layer, etc.
[0020] In this embodiment, the target layer 100 is a dielectric layer. The target layer 100 is patterned subsequently to form a plurality of interconnect trenches, and then metal interconnect lines are formed in the interconnect trenches. The target layer 100 is used to achieve electrical isolation between metal interconnect lines in the BEOL process.
[0021] For this reason, the material of the target layer 100 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc.
[0022] In this embodiment, the material of the target layer 100 is an ultra-low-k dielectric material, so as to reduce the parasitic capacitance between BEOL interconnect lines, and thus reduce the BEOL RC delay. Specifically, the material of the target layer 100 may be SiOCH.
[0023] It should be noted that in this embodiment, other film layers or structures located below the target layer 100 in the substrate are not shown.
[0024] In this embodiment, the substrate further includes a hard mask material layer (not shown in the figure) located on the target layer 100, and an etch stop layer (not shown in the figure) located on the hard mask material layer.
[0025] The hard mask material layer is used to form a hard mask layer (not shown in the figure) after subsequent patterning processes.
[0026] Specifically, the pattern is first transferred into the hard mask material layer to form the hard mask layer, and then the target layer 100 is etched using the hard mask layer as a mask, which is beneficial to improving the process stability and process effect of patterning.
[0027] In this embodiment, the material of the hard mask material layer is silicon nitride. In other embodiments, the material of the hard mask material layer can also be silicon oxide, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, or tungsten nitride, etc.
[0028] The subsequent manufacturing process includes performing multiple pattern definition processes. The etch stop layer is used to define the etch stop position in the etching process of the subsequent pattern definition process, which is beneficial to reducing the loss of the target layer 100 and improving the depth uniformity of the etching process, thereby improving the effect of the subsequent patterning process.
[0029] In this embodiment, the material of the etch stop layer is silicon oxide. In other embodiments, the material of the etch stop layer can also be silicon nitride, aluminum oxide, titanium nitride, tungsten nitride, or aluminum nitride, etc.
[0030] In this embodiment, the pattern definition layer 101 is formed on the etch stop layer.
[0031] The pattern definition layer 101 provides a process basis for the subsequent manufacturing processes.
[0032] In this embodiment, the material of the pattern definition layer is amorphous silicon.
[0033] It should be noted that the lattice structure of amorphous silicon has unstable characteristics, and the etching rate uniformity when etching amorphous silicon is relatively high, which is beneficial to forming the first opening 105 that penetrates the pattern definition layer 101 in the pattern definition layer 101.
[0034] In this embodiment, the step of forming the pattern definition layer 101 includes: forming a pattern definition material layer 300 on the top of the target layer 100; patterning the pattern definition material layer 300 to form a plurality of first openings 105 in the pattern definition material layer 300, and the remaining patterned definition material layer 300 after patterning is used as the pattern definition layer 101.
[0035] Wherein, the first direction (such asFigure 2 The direction indicated by the Y direction in the figure (shown in the figure) refers to the extending direction of the first opening 105 in the top view.
[0036] In this embodiment, the direction parallel to the surface of the substrate and perpendicular to the first direction is the second direction (such as Figure 2 the X direction shown in the figure).
[0037] In this embodiment, the first opening 105 exposes the top surface of the target layer 100, and the first opening 105 provides a spatial position for subsequently forming the first sidewall layer and the first sacrificial layer.
[0038] In this embodiment, the step of forming the first opening 105 includes: forming a first mask layer 102 having a first mask opening 103 on the top of the pattern definition material layer 300, the first mask opening 103 extending along the first direction and exposing a partial width of the top of the pattern definition material layer 300 in the second direction; using the first mask layer 102 as a mask to remove the exposed pattern definition material layer 300 along the first mask opening 103 to form the first opening 105.
[0039] In this embodiment, an anisotropic dry etching process is used to remove the pattern definition layer 101 that exposes a partial width in the second direction.
[0040] The anisotropic dry etching process has the characteristics of anisotropic etching. Therefore, its longitudinal etching rate is much greater than the lateral etching rate, and it can obtain quite accurate pattern transfer and improve the topography quality of the sidewall of the first opening 105.
[0041] The first mask layer 102 includes a first organic material layer 1021, a first anti-reflection coating 1022 located on the first organic material layer 1021, and a first photoresist layer 1023 located on the first anti-reflection coating 1022.
[0042] The material of the first organic material layer 1021 includes an organic material. In this embodiment, the material of the organic material layer 1021 is spin-on carbon (SOC). In other embodiments, the material of the organic material layer can also be other organic materials, such as: one or more of ODL (organic dielectric layer), DUO (DeepUV Light Absorbing Oxide), and APF (Advanced Patterning Film) materials.
[0043] The material of the first anti-reflection coating 1022 includes BARC (bottom anti-reflective coating) material. As an example, the BARC material is Si-ARC (silicon-containing anti-reflective coating) material.
[0044] In this embodiment, during the formation of the first mask layer 102, using the first photoresist layer 1023 as a mask, the first anti-reflection coating 1022 and the first organic material layer 1021 are etched in sequence.
[0045] It should be noted that in other embodiments, during the etching of the first anti-reflection coating and the first organic material layer, the first photoresist layer will be consumed, and the first mask layer may correspondingly include only the first organic material layer and the first anti-reflection coating located on the first organic material layer.
[0046] In this embodiment, after the formation of the first opening 105, it further includes: removing the remaining first mask layer 102.
[0047] Reference Figure 3 , a first sidewall layer 106 is formed on the sidewall of the first opening 105. Along the second direction (such as the X direction shown in Figure 3 ), the first sidewall layer 106 includes alternately arranged first sub-sidewall layers 1061 and second sub-sidewall layers 1062.
[0048] Either the first sub-sidewall layer 1061 or the second sub-sidewall layer 1062 in the first sidewall layer 106 is used as an etching mask for etching the subsequent target layer 100.
[0049] It should be noted that by forming the first sidewall layer 106 on the sidewall of the first opening 105, the size of the first opening 105 along the second direction is reduced, so that the requirement of continuously reducing the line width of the target pattern can be met while increasing the process window of the lithography process.
[0050] In this embodiment, along the second direction (such as the X direction shown in Figure 3 ), the size of the first sidewall layer 106 is equal to the size of the subsequent second sidewall layer, so that the intervals between subsequent adjacent target patterns are equal.
[0051] It should be noted that the size of the first sidewall layer 106 should not be too large or too small. If the size of the first sidewall layer 106 is too large, it is likely to overly occupy the spatial position of the first opening 105, which may then easily lead to an overly small size of the subsequent formed target pattern, resulting in the inability to meet the linewidth requirements of the target pattern, or the interval between target patterns cannot reach the minimum design interval, thus affecting the performance of the metal interconnect; if the size of the first sidewall layer 106 is too small, it is likely to cause an overly large remaining space in the first opening 105, which may then lead to an overly large size of the target pattern formed by etching the target layer 100 using the first sidewall layer 106 as a mask subsequently, resulting in the inability to meet the requirement of continuously reducing the linewidth of the target pattern, thus affecting the performance of the metal interconnect, or, in order to make the linewidth of the target pattern meet the process requirements, the size of the first opening 105 needs to be reduced accordingly, which may easily reduce the process window for forming the first opening 105. Therefore, in this embodiment, along the second direction, the size of the first sidewall layer 106 is 10 nanometers to 20 nanometers. For example, along the second direction, the size of the first sidewall layer 106 is 13 nanometers, 15 nanometers, or 17 nanometers.
[0052] It should be noted that in this embodiment, the size of the first sidewall layer 106 along the second direction is relatively small, so that a relatively small interval is achieved between subsequent adjacent target patterns.
[0053] In this embodiment, the process for forming the first sidewall layer 106 includes an atomic layer deposition process.
[0054] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the first sidewall layer 106 and enabling the first sidewall layer 106 to cover the sidewalls of the pattern definition layer 101. In other embodiments, a chemical vapor deposition process (CVD) may also be used to form the first sidewall layer.
[0055] The material of the first sidewall layer 106 is selected such that the first sidewall layer 106 can be retained during the subsequent removal of the sacrificial layer and the pattern definition layer, and the target layer 100 can be etched using the first sidewall layer 106 as a mask subsequently.
[0056] Therefore, in this embodiment, the material of the first sidewall layer 106 may include titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the first sidewall layer 106 is titanium oxide. The etching selectivity of the titanium oxide material with respect to amorphous silicon or spin-on glass is relatively large.
[0057] In this embodiment, the steps of forming the first sidewall layer 106 include: forming a first sidewall material layer (not shown in the figure) on the top and sidewalls of the pattern definition layer 101 and the bottom of the first opening 105, removing the first sidewall material layer on the top of the pattern definition layer 101 and the bottom of the first opening 105, and using the remaining first sidewall material layer as the first sidewall layer 106.
[0058] Reference Figure 4 , a sacrificial layer 107 is formed in the remaining space of the first opening 105.
[0059] The sacrificial layer 107 provides a process basis for the subsequent formation of the second sidewall layer.
[0060] It should be noted that the etching selectivity ratios between the sacrificial layer 107 and the materials of the first sidewall layer 103 and the second sidewall layer formed subsequently are relatively large, which is conducive to reducing the damage to the first sidewall layer 103 and the second sidewall layer when removing the remaining sacrificial layer 107 subsequently.
[0061] In this embodiment, the material of the sacrificial layer 107 includes one or more of spin-on glass, ion-enhanced silicon oxide, and tetraethyl orthosilicate, which makes the etching selectivity ratio between the target layer 100 and the sacrificial layer 107 relatively high, facilitating the subsequent removal of the remaining sacrificial layer 107. As an example, the material of the sacrificial layer 107 is spin-on glass.
[0062] Reference Figures 5 to 6 , along the second direction (such as Figure 6 the X direction shown in
[0063] ), the second sub-sidewall layer 1062, and a part of the width of the pattern definition layer 101 and the sacrificial layer 107 located on the sidewalls of the second sub-sidewall layer 1062 are removed to form a second opening 190 surrounded by the remaining pattern definition layer 101, sacrificial layer 107, and target layer 100.
[0064] It should be noted that in this embodiment, by removing the second sub-sidewall layer 1062, and a part of the width of the pattern definition layer 101 and the sacrificial layer 107 located on the sidewalls of the second sub-sidewall layer 1062 during the formation of the second opening 190, the remaining pattern definition layer 101 and sacrificial layer 107 are along the second direction (such as [[ID=Reduce the size in the X direction (as shown in the figure), and form a second sidewall layer on the sidewall of the second opening 190 subsequently, and form a second sidewall layer between adjacent first sub-sidewall layers 1061, that is, divide the space between adjacent first sub-sidewall layers 1061 in the second direction through the second sidewall layer. Correspondingly, after etching the target layer 100 using the remaining first sidewall layer 106 and the second sidewall layer as a mask subsequently, the size of the formed target pattern in the second direction is reduced, that is, the requirement of continuously reducing the pitch of the target pattern is satisfied. Moreover, since part of the sacrificial layer 107 will be removed, the initial size of the sacrificial layer 107 in the second direction is larger, correspondingly increasing the window of the photolithography process when forming the first opening 105. In addition, by removing the second sub-sidewall layer 1062, and part of the width of the pattern definition layer 101 and the sacrificial layer 107 located on the sidewall of the second sub-sidewall layer 1062 to form the second opening 190, the window of the photolithography process when forming the second opening 190 is correspondingly increased. Furthermore, it is possible to satisfy the requirement of continuously reducing the line width of the target pattern under the condition of increasing the process window of the photolithography process, thereby facilitating further reduction of the pitch between the target patterns.
[0065] In this embodiment, in the step of forming the second opening 190, along the second direction, use a dry etching process to remove the second sub-sidewall layer 1062, and part of the width of the pattern definition layer 101 and the sacrificial layer 107 located on the sidewall of the second sub-sidewall layer 1062.
[0066] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching. Therefore, its longitudinal etching rate is much greater than the lateral etching rate, and it can obtain quite accurate pattern transfer and improve the sidewall topography quality of the second opening 190.
[0067] In this embodiment, in the step of forming the second opening 190, along the second direction, the width of the removed sacrificial layer 107 accounts for one-half to two-thirds of the total width of the sacrificial layer 107.
[0068] It should be noted that, along the second direction, the proportion of the width of the sacrificial layer 107 removed should neither be too large nor too small. Subsequently, a second sidewall layer is formed on the sidewall of the second opening 190, and then the target layer is etched using the second sidewall layer as a mask to form a target pattern. That is to say, two target patterns are formed between adjacent first sub-sidewall layers 1061 subsequently. When the dimension of the sacrificial layer 107 along the second direction meets the process requirements, whether the proportion is too large or too small, it is likely to cause the line width of the formed target pattern to fail to reach the target value, thereby affecting the performance of the metal interconnect. Therefore, in this embodiment, in the step of forming the second opening 190, along the second direction, the width of the sacrificial layer 107 removed accounts for one-half to two-thirds of the total width of the sacrificial layer 107.
[0069] In this embodiment, in the step of forming the second opening 190, along the second direction, the width of the pattern definition layer 101 removed accounts for one-half to two-thirds of the total width of the pattern definition layer 101.
[0070] It should be noted that, along the second direction, the proportion of the width of the pattern definition layer 101 removed should neither be too large nor too small. Subsequently, a second sidewall layer is formed on the sidewall of the second opening 190, and then the target layer is etched using the second sidewall layer as a mask to form a target pattern. That is to say, two target patterns are formed between adjacent first sub-sidewall layers 1061 subsequently. When the dimension of the pattern definition layer 101 along the second direction meets the process requirements, whether the proportion is too large or too small, it is likely to cause the line width of the formed target pattern to fail to reach the target value, thereby affecting the performance of the metal interconnect. Therefore, in this embodiment, in the step of forming the second opening 190, along the second direction, the width of the pattern definition layer 101 removed accounts for one-half to two-thirds of the total width of the pattern definition layer 101.
[0071] In this embodiment, in the step of forming the second opening 190, along the second direction, the widths of the remaining sacrificial layer 107 and the remaining pattern definition layer 101 are equal.
[0072] When the widths of the remaining sacrificial layer 107 and the remaining pattern definition layer 101 are equal along the second direction, it is easy to make the line width dimensions of the target pattern equal along the second direction.
[0073] In this embodiment, before forming the second opening 190, it further includes: forming a mask layer 108 with a mask opening 109 on the tops of the pattern definition layer 101, the first sub-sidewall layer 1061, and the sacrificial layer 107. The mask opening 109 extends along the first direction and exposes the second sub-sidewall layer 1062 in the second direction, as well as the pattern definition layer 101 and the sacrificial layer 107 at a partial width of the sidewall of the first sub-sidewall layer 1061.
[0074] The mask layer 108 serves as an etching mask for forming the second opening 190.
[0075] In this embodiment, in the step of forming the second opening 190, using the mask layer 108 as a mask, the pattern definition layer 101, the sacrificial layer 107, and the second sub-sidewall layer 1062 exposed by the mask opening 109 are removed.
[0076] In this embodiment, since the first mask layer 102 is used in the process of forming the first opening 105 described above, the mask layer 108 is defined as the second mask layer 108. The second mask layer 108 includes a second organic material layer 1081, a second anti-reflection coating 1082 located on the second organic material layer 1081, and a second photoresist layer 1083 located on the second anti-reflection coating 1082.
[0077] For the specific description of the mask layer 108, reference can be made to the corresponding description of the first mask layer 102 above, and details are not elaborated here.
[0078] It should be noted that in other embodiments, along the second direction, the first sub-sidewall layer, and the pattern definition layer and the sacrificial layer at a partial width of the sidewall of the first sub-sidewall layer can also be removed to form a second opening surrounded by the remaining pattern definition layer, sacrificial layer, and target layer. Thereby, it can meet the requirement of continuously reducing the line width of the target pattern while increasing the process window of the lithography process, which is beneficial to further reducing the pitch between the target patterns.
[0079] Correspondingly, before forming the second opening, it further includes: forming a mask layer with a mask opening on the tops of the pattern definition layer, the second sub-sidewall layer, and the sacrificial layer. The mask opening extends along the first direction and exposes the first sub-sidewall layer in the second direction, as well as the pattern definition layer and the sacrificial layer at a partial width of the sidewall of the first sub-sidewall layer.
[0080] In the step of forming the second opening, along the second direction, a dry etching process is used to remove the first sub-sidewall layer, and the pattern definition layer and the sacrificial layer at a partial width of the sidewall of the first sub-sidewall layer.
[0081] Reference , a second sidewall layer 110 is formed on the sidewall of the second opening 190.
[0082] It should be noted that by forming the second sidewall layer 110 on the sidewall exposed by the second opening 190, the size of the second opening 190 in the second direction is reduced, so that the requirement of continuously reducing the line width of the target pattern can be met while increasing the process window of the lithography process. At the same time, during the subsequent process of forming the target pattern in the target layer 100, the second sidewall layer 110 will also be used as an etching mask, that is, the second sidewall layer 110 and the first sidewall layer 106 will jointly serve as the mask for subsequent etching of the target layer 100.
[0083] In this embodiment, along the second direction (such as shown by the X direction in
[0084] ), the size of the second sidewall layer 110 is 10 nanometers to 20 nanometers.
[0085] In this embodiment, the process of forming the second sidewall layer 110 includes an atomic layer deposition process.
[0086] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the second sidewall layer 110 and enabling the second sidewall layer 110 to cover the sidewall of the sacrificial layer 107. In other embodiments, a chemical vapor deposition process (Chemical Vapor Deposition, CVD) can also be used to form the first sidewall layer.
[0087] In this embodiment, the material of the second sidewall layer 110 may include titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the second sidewall layer 110 is titanium oxide. The etching selectivity of the titanium oxide material with respect to amorphous silicon or spin-on glass is relatively large, so that the second sidewall layer 110 can be retained during the subsequent process of removing the sacrificial layer 107 and the pattern definition layer 101 to form a target pattern, and the target layer 100 can be etched using the second sidewall layer 110 as a mask subsequently.
[0088] In this embodiment, the step of forming the second sidewall layer 110 includes: forming a second sidewall material layer (not shown in the figure) on the tops of the pattern definition layer 101, the sacrificial layer 107, and the first sub-sidewall layer 1061, and on the bottom and sidewalls of the second opening 190, and removing the second sidewall material layer on the tops of the pattern definition layer 101, the sacrificial layer 107, and the first sub-sidewall layer 1061 and on the bottom of the second opening 190, and the remaining second sidewall material layer serves as the second sidewall layer 110.
[0089] In this embodiment, in the step of forming the second sidewall layer 110, along the second direction, the interval between adjacent second sidewall layers 110 is equal to the width of the remaining sacrificial layer 107 or the remaining pattern definition layer 101, which is conducive to making the line width dimensions of the subsequently formed target pattern equal along the second direction.
[0090] Reference , after forming the second sidewall layer 110, the remaining sacrificial layer 107 and pattern definition layer 101 are removed.
[0091] It should be noted that the remaining sacrificial layer 107 and pattern definition layer 101 are removed to expose the area to be etched.
[0092] In this embodiment, a wet etching process is used to remove the remaining sacrificial layer 107 and pattern definition layer 101.
[0093] The wet etching process has the characteristic of isotropic etching, which is conducive to completely removing the remaining sacrificial layer 107 and pattern definition layer 101 between the remaining first sidewall layer 106 and the second sidewall layer 110. Moreover, during the process of removing amorphous silicon and organic materials by the wet etching process, it has the characteristics of high efficiency and low cost, and can reduce the damage to the underlying film layer.
[0094] In this embodiment, in the step of removing the remaining sacrificial layer 107 and pattern definition layer 101, the etching selectivity ratio of the pattern definition layer 101 to the first sidewall layer 106 is greater than 5:1.
[0095] The etching selectivity between the pattern definition layer 101 and the first sidewall layer 106 should not be too small. If the etching selectivity between the pattern definition layer 101 and the first sidewall layer 106 is too small, it is likely to cause damage to the first sidewall layer 106, thereby affecting the subsequent process of forming the target pattern in the target layer 100, and further affecting the performance of the semiconductor structure. Therefore, in this embodiment, in the step of removing the remaining sacrificial layer 107 and the pattern definition layer 101, the etching selectivity between the pattern definition layer 101 and the first sidewall layer 106 is greater than 5:1.
[0096] In this embodiment, in the step of removing the remaining sacrificial layer 107 and the pattern definition layer 101, the etching selectivity between the pattern definition layer and the second sidewall layer is greater than 5:1.
[0097] It should be noted that the etching selectivity between the pattern definition layer 101 and the second sidewall layer 110 should not be too small. If the etching selectivity between the pattern definition layer 101 and the second sidewall layer 110 is too small, it is likely to cause damage to the second sidewall layer 110, thereby affecting the subsequent process of forming the target pattern in the target layer 100, and further affecting the performance of the semiconductor structure. Therefore, in this embodiment, in the step of removing the remaining sacrificial layer 107 and the pattern definition layer 101, the etching selectivity between the pattern definition layer 101 and the second sidewall layer 110 is greater than 5:1.
[0098] In this embodiment, in the step of removing the remaining sacrificial layer 107 and the pattern definition layer 101, the etching selectivity between the sacrificial layer 107 and the first sidewall layer 106 is greater than 5:1.
[0099] It should be noted that the etching selectivity between the sacrificial layer 107 and the first sidewall layer 106 should not be too small. If the etching selectivity between the sacrificial layer 107 and the first sidewall layer 106 is too small, it is likely to cause damage to the first sidewall layer 106, thereby affecting the subsequent process of forming the target pattern in the target layer 100, and further affecting the performance of the semiconductor structure. Therefore, in this embodiment, in the step of removing the remaining sacrificial layer 107 and the pattern definition layer 101, the etching selectivity between the sacrificial layer and the first sidewall layer is greater than 5:1.
[0100] In this embodiment, in the step of removing the remaining sacrificial layer 107 and the pattern definition layer 101, the etching selectivity between the sacrificial layer 107 and the second sidewall layer 110 is greater than 5:1.
[0101] It should be noted that the etching selectivity between the sacrificial layer 107 and the second sidewall layer 110 should not be too small. If the etching selectivity between the sacrificial layer 107 and the second sidewall layer 110 is too small, it is easy to damage the second sidewall layer 110, thereby affecting the subsequent manufacturing process of forming the target pattern in the target layer 100, and further affecting the performance of the semiconductor structure. Therefore, in this embodiment, in the step of removing the remaining sacrificial layer 107 and the pattern definition layer 101, the etching selectivity between the sacrificial layer 107 and the second sidewall layer 110 is greater than 5:1.
[0102] In this embodiment, the remaining sacrificial layer 107 and the pattern definition layer 101 are removed by the same etching step.
[0103] It should be noted that removing the remaining sacrificial layer 107 and the pattern definition layer 101 in the same etching step can simplify the process steps, correspondingly improve the manufacturing efficiency, and reduce the process cost at the same time.
[0104] Reference , after removing the remaining sacrificial layer 107 and the pattern definition layer 101, the target layer 100 is etched using the remaining first sidewall layer 106 and the second sidewall layer 110 as masks to form a target pattern 120.
[0105] As can be seen from the foregoing description, this embodiment can meet the requirement of continuously reducing the line width of the target pattern 120 while increasing the process window of the lithography process, and is conducive to further reducing the pitch between the target patterns 120, which correspondingly improves the pattern accuracy and pattern quality of the target pattern 120.
[0106] It should be noted that the target layer 100 is a dielectric layer. Therefore, after etching the target layer 100 using the remaining first sidewall layer 106 and the second sidewall layer 110 as masks, the target pattern 120 is an interconnect groove.
[0107] In this embodiment, a hard mask material layer (not shown in the figure) and an etch stop layer (not shown in the figure) are further formed on the target layer 100, and the bottoms of the first opening 105 and the second opening 190 expose the etch stop layer.
[0108] Therefore, using the remaining first sidewall layer 106 and the second sidewall layer 110 as masks, the etch stop layer and the hard mask material layer at the bottoms of the first opening 105 and the second opening 190 are etched in sequence. After the remaining hard mask material layer serves as a hard mask layer (not shown in the figure), the target layer 100 is etched using the hard mask layer as a mask.
[0109] By first transferring the patterns of the first opening 105 and the second opening 190 into the hard mask material layer to form the hard mask layer, it is beneficial to improve the process stability and process effect of etching the target layer 100 and improve the pattern transfer accuracy.
[0110] Reference After forming the interconnect trench, a metal interconnect 130 is formed in the interconnect trench.
[0111] The metal interconnect 130 is used to achieve the electrical connection between the semiconductor structure and an external circuit or other interconnect structures.
[0112] As can be seen from the foregoing description, this embodiment can meet the requirement of continuously reducing the line width of the interconnect trench while increasing the process window of the lithography process, and the pitch between adjacent interconnect trenches is easy to meet the design minimum pitch. Correspondingly, it is beneficial to make the pitch between the metal interconnects 130 meet the design minimum pitch, which is beneficial to further reducing the pitch between the metal interconnects 130, and is also beneficial to improving the pattern accuracy of the metal interconnects 130, and further beneficial to improving the electrical connection performance of the metal interconnects 130.
[0113] In this embodiment, the material of the metal interconnect 130 is copper. In other embodiments, the material of the metal interconnect can also be a conductive material such as aluminum.
[0114] In this embodiment, an electroplating copper method is used to form the metal interconnect 130 in the interconnect trench.
[0115] Correspondingly, the process of forming the metal interconnect 130 includes a step of filling a conductive material and a step of planarizing the conductive material to remove the conductive material higher than the top of the dielectric layer.
[0116] In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.
[0117] The chemical mechanical polishing process makes the metal interconnect 130 formed in the interconnect trench have a flat surface, improving the electrical connection effect of the metal interconnect 130.
[0118] In this embodiment, during the process of forming the metal interconnect 130, the remaining first sub-sidewall layer 1061, the second sidewall layer 110, the etch stop layer, and the hard mask layer are also removed, thereby exposing the top surface of the target layer 100 to prepare for subsequent processes.
[0119] The specific description of the metal interconnect 130 will not be elaborated here.
[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a target layer for forming a target pattern, a pattern definition layer being formed on the target layer, and a plurality of first openings penetrating the pattern definition layer being formed in the pattern definition layer, the plurality of first openings extending in a first direction and arranged in a second direction, the second direction and the first direction being perpendicular to each other; Forming a first sidewall layer on the sidewalls of the first openings, and along the second direction, the first sidewall layer including alternately arranged first sub-sidewall layers and second sub-sidewall layers; Forming a sacrificial layer in the remaining space of the first openings; Along the second direction, removing the first sub-sidewall layer, and a part of the width of the pattern definition layer and the sacrificial layer located on the sidewalls of the first sub-sidewall layer, or removing the second sub-sidewall layer, and a part of the width of the pattern definition layer and the sacrificial layer located on the sidewalls of the second sub-sidewall layer, to form a second opening surrounded by the remaining pattern definition layer, sacrificial layer and target layer; Forming a second sidewall layer on the sidewalls of the second opening; After forming the second sidewall layer, removing the remaining sacrificial layer and pattern definition layer; After removing the remaining sacrificial layer and pattern definition layer, etching the target layer using the remaining first sidewall layer and second sidewall layer as a mask to form a target pattern.
2. The method for forming a semiconductor structure according to claim 1, wherein Before forming the second opening, it further includes: forming a mask layer with a mask opening on the tops of the pattern definition layer, first sub-sidewall layer and sacrificial layer, the mask opening extending in the first direction and exposing the second sub-sidewall layer, and a part of the width of the pattern definition layer and the sacrificial layer located on the sidewalls of the second sub-sidewall layer in the second direction; Or, Forming a mask layer with a mask opening on the tops of the pattern definition layer, second sub-sidewall layer and sacrificial layer, the mask opening extending in the first direction and exposing the first sub-sidewall layer, and a part of the width of the pattern definition layer and the sacrificial layer located on the sidewalls of the first sub-sidewall layer in the second direction; In the step of forming the second opening, using the mask layer as a mask, removing the pattern definition layer and the sacrificial layer exposed by the mask opening.
3. The method for forming a semiconductor structure according to claim 1, wherein, The step of forming the pattern definition layer includes: forming a pattern definition material layer on the top of the target layer; patterning the pattern definition material layer to form a plurality of first openings in the pattern definition material layer, and the remaining patterned pattern definition material layer being used as the pattern definition layer.
4. The method for forming a semiconductor structure according to claim 1, wherein In the step of forming the second opening, along the second direction, using a dry etching process to remove the first sub-sidewall layer, and a part of the width of the pattern definition layer and the sacrificial layer located on the sidewalls of the first sub-sidewall layer; Or, using a dry etching process to remove the second sub-sidewall layer, and a part of the width of the pattern definition layer and the sacrificial layer located on the sidewalls of the second sub-sidewall layer.
5. The method for forming a semiconductor structure according to claim 1, wherein In the step of forming the second opening, along the second direction, the width of the removed sacrificial layer accounts for one half to two thirds of the total width of the sacrificial layer; The width of the removed pattern definition layer accounts for one half to two thirds of the total width of the pattern definition layer.
6. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the first sidewall layer, along the second direction, the size of the first sidewall layer is from 10 nanometers to 20 nanometers.
7. The method for forming a semiconductor structure according to claim 1, wherein, The process of forming the first sidewall layer includes an atomic layer deposition process.
8. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the second sidewall layer, along the second direction, the size of the second sidewall layer is from 10 nanometers to 20 nanometers.
9. The method for forming a semiconductor structure according to claim 1, wherein Along the second direction, the size of the first sidewall layer is equal to the size of the second sidewall layer.
10. The method for forming a semiconductor structure according to claim 1 or 9, characterized in that, In the step of forming the second opening, along the second direction, the widths of the remaining sacrificial layer and the remaining pattern definition layer are equal; In the step of forming the second sidewall layer, along the second direction, the spacing between adjacent second sidewall layers is equal to the width of the remaining sacrificial layer or the remaining pattern definition layer.
11. The method for forming a semiconductor structure according to claim 1, wherein, The process of forming the second sidewall layer includes an atomic layer deposition process.
12. The method for forming a semiconductor structure according to claim 1, wherein, A wet etching process is used to remove the remaining sacrificial layer and pattern definition layer.
13. The method for forming a semiconductor structure according to claim 1, wherein, In the step of removing the remaining sacrificial layer and pattern definition layer, the etching selectivity between the pattern definition layer and the first sidewall layer is greater than 5:1; The etching selectivity between the pattern definition layer and the second sidewall layer is greater than 5:1; The etching selectivity between the sacrificial layer and the first sidewall layer is greater than 5:1; The etching selectivity between the sacrificial layer and the second sidewall layer is greater than 5:
1.
14. The method for forming a semiconductor structure according to claim 1, wherein The material of the pattern definition layer includes amorphous silicon.
15. The method for forming a semiconductor structure according to claim 1, wherein The material of the sacrificial layer includes one or more of spin-on glass, ion-enhanced silicon oxide, and tetraethyl orthosilicate.
16. The method for forming a semiconductor structure as claimed in claim 1, wherein, The material of the first sidewall layer includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, and aluminum oxide; The material of the second sidewall layer includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, and aluminum oxide.
17. The method for forming a semiconductor structure according to claim 1, wherein, The target layer is a dielectric layer, and the target pattern is an interconnect trench; The forming method further includes: after forming the interconnect trench, forming a metal interconnect in the interconnect trench.
Citation Information
Patent Citations
Fin etching method
CN105470137A
Semiconductor structure and forming method thereof
CN110690117A