Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate including a target layer for forming a target pattern, forming a pattern definition layer on the target layer, and forming a first sacrificial layer in the pattern definition layer; removing the first sacrificial layer at the junction of the pattern definition layer and the first sacrificial layer to form a first opening; forming a first sidewall layer on the sidewall of the first opening, the first sidewall layer including a first sub-sidewall layer and a second sub-sidewall layer; filling a second sacrificial layer in the first opening, the second sacrificial layer and the first sacrificial layer constituting a sacrificial structure; removing the sacrificial structure in contact with the sidewall of the first sub-sidewall layer or the sidewall of the second sub-sidewall layer to form a second opening surrounded by the sacrificial structure, the second sub-sidewall layer, and the target layer; forming a second sidewall layer on the sidewall of the second opening; and transferring the patterns of the first sidewall layer and the second sidewall layer to the target layer to form a target pattern. The present invention not only increases the process window but also reduces the pitch between target patterns.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology has continuously advanced towards smaller process nodes driven by Moore's law, enabling integrated circuits to develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.

[0003] During the development of integrated circuits, generally, as the function density (i.e., the number of internal wiring structures per chip) gradually increases, the geometric size (i.e., the minimum element size that can be produced using process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, in the case of continuously shrinking technology nodes, how to break through the current constraints of lithography equipment and meet the process requirements of smaller and smaller metal line widths has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further reducing the pitch between target patterns.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including a target layer for forming a target pattern, a pattern definition layer being formed on the target layer, a first sacrificial layer extending along a first direction and penetrating through the pattern definition layer being formed in the pattern definition layer, an etching selectivity ratio existing between the first sacrificial layer and the pattern definition layer; removing a part of the width of the first sacrificial layer at the junction of the pattern definition layer and the first sacrificial layer along a second direction perpendicular to the first direction to form a first opening surrounded by the pattern definition layer, the target layer, and the remaining first sacrificial layer; forming a first sidewall layer on the sidewall of the first opening, the first sidewall layer including first sub-sidewall layers and second sub-sidewall layers alternately arranged along the second direction; after forming the first sidewall layer, filling a second sacrificial layer in the remaining space of the first opening, the second sacrificial layer and the first sacrificial layer constituting a sacrificial structure; removing a part of the width of the sacrificial structure in contact with the sidewall of the first sub-sidewall layer or the sidewall of the second sub-sidewall layer to form a second opening surrounded by the remaining sacrificial structure, the first sub-sidewall layer, and the target layer, or forming a second opening surrounded by the remaining sacrificial structure, the second sub-sidewall layer, and the target layer; forming a second sidewall layer on the sidewall of the sacrificial structure exposed in the second opening; after forming the second sidewall layer, removing the sacrificial structure; after removing the sacrificial structure, transferring the patterns of the first sidewall layer and the second sidewall layer to the target layer to form a target pattern.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] An embodiment of the present invention provides a method for forming a semiconductor structure. A first sidewall layer is formed on the sidewalls of a first opening. The first sidewall layer includes first sub-sidewall layers and second sub-sidewall layers alternately arranged in a second direction. After forming the first sidewall layer, a second sacrificial layer is filled in the remaining space of the first opening. The second sacrificial layer and the first sacrificial layer form a sacrificial structure. A part of the width of the sacrificial structure that is in contact with the sidewalls of the first sub-sidewall layers or the second sub-sidewall layers is removed, so as to form a second opening surrounded by the remaining sacrificial structure, the first sub-sidewall layers and a target layer, or a second opening surrounded by the remaining sacrificial structure, the second sub-sidewall layers and the target layer. A second sidewall layer is formed on the sidewalls of the sacrificial structure exposed in the second opening. Subsequently, after removing the sacrificial structure, the patterns of the first sidewall layer and the second sidewall layer are transferred to the target layer to form a target pattern. In the embodiment of the present invention, by first forming a first opening with a relatively large line width in the second direction, then removing a part of the width of the sacrificial structure that is in contact with the sidewalls of the first sub-sidewall layers or the second sub-sidewall layers to form a second opening, and forming a second sidewall layer on the sidewalls of the sacrificial structure exposed in the second opening, the space of the first opening is divided in the second direction. This increases the process window of the lithography process used to form the first opening and the second opening, and makes the size of the formed target pattern in the second direction smaller. Therefore, this embodiment can meet the requirement that the line width of the target pattern is continuously reduced while increasing the process window of the lithography process, which is conducive to further reducing the pitch between the target patterns. Description of the Drawings

[0009] Figures 1 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed Embodiment

[0010] Currently, due to the restriction of lithography equipment, the line width of the metal wires formed in semiconductor devices is too large to meet the process requirements of continuously decreasing line width of the metal wires, making it difficult to further reduce the pitch between the target patterns.

[0011] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including a target layer for forming a target pattern, a pattern definition layer is formed on the target layer, a first sacrificial layer extending along a first direction and penetrating through the pattern definition layer is formed in the pattern definition layer, and an etching selectivity exists between the first sacrificial layer and the pattern definition layer; along a second direction perpendicular to the first direction, a part of the width of the first sacrificial layer at the junction of the pattern definition layer and the first sacrificial layer is removed to form a first opening surrounded by the pattern definition layer, the target layer, and the remaining first sacrificial layer; forming a first sidewall layer on the sidewall of the first opening, the first sidewall layer including first sub-sidewall layers and second sub-sidewall layers alternately arranged along the second direction; after forming the first sidewall layer, filling a second sacrificial layer in the remaining space of the first opening, the second sacrificial layer and the first sacrificial layer constituting a sacrificial structure; removing a part of the width of the sacrificial structure in contact with the sidewall of the first sub-sidewall layer or the sidewall of the second sub-sidewall layer to form a second opening surrounded by the remaining sacrificial structure, the first sub-sidewall layer, and the target layer, or forming a second opening surrounded by the remaining sacrificial structure, the second sub-sidewall layer, and the target layer; forming a second sidewall layer on the sidewall of the sacrificial structure exposed in the second opening; after forming the second sidewall layer, removing the sacrificial structure; after removing the sacrificial structure, transferring the patterns of the first sidewall layer and the second sidewall layer to the target layer to form a target pattern.

[0012] In the formation method provided by an embodiment of the present invention, a first sidewall layer is formed on the sidewall of a first opening, and the first sidewall layer includes a first sub-sidewall layer and a second sub-sidewall layer alternately arranged along a second direction. After the first sidewall layer is formed, a second sacrificial layer is filled in the remaining space of the first opening, and the second sacrificial layer and the first sacrificial layer constitute a sacrificial structure. The sacrificial structure of a portion of the width in contact with the sidewall of the first sub-sidewall layer or the sidewall of the second sub-sidewall layer is removed to form a second opening surrounded by the remaining sacrificial structure, the first sub-sidewall layer and the target layer, or a second opening surrounded by the remaining sacrificial structure, the second sub-sidewall layer and the target layer is formed, and a second sidewall layer is formed on the sidewall of the sacrificial structure exposed in the second opening. Subsequently, the sacrificial structure is removed, and the patterns of the first sidewall layer and the second sidewall layer are transferred to the target layer to form a target pattern. In an embodiment of the present invention, a first opening having a larger line width in the second direction is first formed, and then a portion of the width of the sacrificial structure in contact with the sidewall of the first sub-sidewall layer or the sidewall of the second sub-sidewall layer is removed to form a second opening, and a second sidewall layer is formed by the sidewall of the sacrificial structure exposed in the second opening, thereby dividing the space of the first opening in the second direction. This increases the process window of the photolithography process used when forming the first opening and the second opening, and reduces the size of the target pattern formed along the second direction. Therefore, this embodiment can meet the requirement of continuously reducing the line width (width) of the target pattern while increasing the process window of the photolithography process, thereby facilitating further reducing the pitch (pitch) between the target patterns.

[0013] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0014] Figures 1 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for manufacturing a semiconductor structure of the present invention.

[0015] refer to Figures 1 to 2 , providing a substrate, including a target layer 100 for forming a target pattern, a pattern definition layer 103 formed on the target layer 100, and a pattern definition layer 103 formed in the pattern definition layer 103 along a first direction (such as Figure 2 The first sacrificial layer 101 extends (as shown in the Y direction) and penetrates the pattern definition layer 103, and an etching selectivity ratio is established between the first sacrificial layer 101 and the pattern definition layer 103.

[0016] The substrate is used to provide a process platform for subsequent process steps.

[0017] In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate, and functional structures such as resistor structures and conductive structures may also be formed in the substrate.

[0018] The target layer 100 is used as a material layer that needs to be patterned subsequently to form a target pattern.

[0019] Among them, the target pattern can be a gate structure, an interconnect trench in a Back end of line (BEOL) process, a fin in a FinFET, a channel stack in a Gate-All-Around (GAA) transistor or a Forksheet transistor, a Hard Mask (HM) layer, and other patterns.

[0020] In this embodiment, the target layer 100 is a dielectric layer. Subsequently, the target layer 100 is patterned to form a plurality of interconnect trenches in the target layer 100, and then metal interconnect lines are formed in the interconnect trenches. The target layer 100 is used to achieve electrical isolation between the metal interconnect lines in the BEOL process.

[0021] For this reason, the material of the target layer 100 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0022] In this embodiment, the material of the target layer 100 is an ultra-low-k dielectric material, so as to reduce the parasitic capacitance between the BEOL interconnect lines, and further reduce the BEOL RC delay. Specifically, the material of the target layer 100 can be SiOCH.

[0023] In this embodiment, the substrate further includes a hard mask material layer (not shown in the figure) located on the target layer 100, and an etch stop layer (not shown in the figure) located on the hard mask material layer.

[0024] The hard mask material layer is used to form a hard mask layer (not shown in the figure) after subsequent patterning processes.

[0025] Specifically, the pattern is first transferred into the hard mask material layer to form a hard mask layer, and then the target layer 100 is etched using the hard mask layer as a mask, which is beneficial to improving the process stability and process effect of patterning.

[0026] In this embodiment, the material of the hard mask material layer is silicon nitride. In other embodiments, the material of the hard mask material layer can also be silicon oxide, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, tungsten nitride, or other materials.

[0027] The subsequent processes include performing multiple graphic definition processes. The etch stop layer is used to define the etch stop position in the etching process of the subsequent graphic definition processes, thereby facilitating the reduction of the loss of the target layer 100 and improving the depth consistency of the etching process, and further improving the effect of the subsequent patterning process.

[0028] In this embodiment, the material of the etch stop layer is silicon oxide. In other embodiments, the material of the etch stop layer can also be silicon nitride, aluminum oxide, titanium nitride, tungsten nitride, aluminum nitride, etc.

[0029] It should be noted that in this embodiment, other film layer structures below the target layer 100 are not shown.

[0030] In this embodiment, the graphic definition layer 103 and the first sacrificial layer 101 are formed on the etch stop layer.

[0031] In this embodiment, the first sacrificial layer 101 extending along a first direction and penetrating the graphic definition layer 103 is formed in the graphic definition layer 103. Wherein, the first direction refers to the extending direction of the first sacrificial layer 101 in the top view.

[0032] In this embodiment, the direction parallel to the substrate surface and perpendicular to the first direction is the second direction (as Figure 2 shown by the X direction in

[0033] In this embodiment, there is an etch selectivity between the first sacrificial layer 101 and the graphic definition layer 103.

[0034] It should be noted that the first sacrificial layer 101 will be removed subsequently. Subsequently, in the process of transferring the patterns of the first sidewall layer and the second sidewall layer to the target layer 100, the target layer 100 will be etched using the graphic definition layer 103 as a mask. Therefore, by having an etch selectivity between the first sacrificial layer 101 and the graphic definition layer 103, while removing the first sacrificial layer 101, the graphic definition layer 103 is retained and the probability of being damaged is relatively low.

[0035] Wherein, having an etch selectivity between the first sacrificial layer 101 and the graphic definition layer 103 means that: under the same etching process conditions, the etching rates of the first sacrificial layer 101 and the graphic definition layer 103 are different.

[0036] In this embodiment, the steps of forming the first sacrificial layer 101 and the pattern definition layer 103 include: forming a pattern material layer 300 on the top of the target layer 100; doping a part of the pattern material layer 300, and the doped pattern material layer 300 serves as the pattern definition layer 103, and the remaining undoped pattern material layer 300 serves as the first sacrificial layer 101.

[0037] The pattern material layer 300 provides a process basis for forming the pattern definition layer 103 and the first sacrificial layer 101.

[0038] In this embodiment, the material of the first sacrificial layer 101 includes amorphous silicon.

[0039] It should be noted that the lattice structure of amorphous silicon has unstable characteristics, and the etching rate uniformity when etching amorphous silicon is relatively high, which is beneficial to the subsequent removal of the first sacrificial layer 101.

[0040] In this embodiment, an ion implantation process is used to dope a part of the pattern material layer 300.

[0041] It should be noted that the ion implantation process has the characteristics of uniformly implanting ions over a large area, more accurately controlling the ion doping depth, and high repeatability.

[0042] Specifically, after doping the pattern material layer 300, the doped pattern material layer 300 serves as the pattern definition layer 103, and the undoped pattern material layer 300 serves as the first sacrificial layer 101. There is an etching selectivity between the pattern definition layer 103 and the first sacrificial layer 101, which provides a process basis for forming a first opening for the subsequent removal of the first sacrificial layer 101.

[0043] In this embodiment, the doping depth of the doping process is the entire thickness of the pattern material layer 300.

[0044] In this embodiment, in the step of doping the pattern material layer 300, the doping ions include boron ions, phosphorus ions or argon ions.

[0045] Reference Figure 1 , before doping the pattern material layer 300, the method for forming the semiconductor structure further includes: forming a first mask layer 102 on the top of the pattern material layer 300, and the first mask layer 102 covers a part of the top of the pattern material layer 300.

[0046] The first mask layer 102 is used to block the areas in the pattern material layer 300 that are not desired to be doped.

[0047] In this embodiment, the first mask layer 102 includes a first organic material layer 1021, a first anti-reflection coating 1022 located on the first organic material layer 1021, and a first photoresist layer 1023 located on the first anti-reflection coating 1022.

[0048] The material of the first organic material layer 1021 includes an organic material. In this embodiment, the material of the organic material layer 1021 is spin-on carbon (SOC). In other embodiments, the material of the organic material layer may also be other organic materials, such as one or more of ODL (organic dielectric layer) material, DUO (DeepUV Light Absorbing Oxide) material, and APF (Advanced Patterning Film) material.

[0049] The material of the first anti-reflection coating 1022 includes BARC (bottom anti-reflective coating) material. As an example, the BARC material is Si-ARC (silicon-containing anti-reflection coating) material.

[0050] In this embodiment, during the formation of the first mask layer 102, using the first photoresist layer 1023 as a mask, the first anti-reflection coating 1022 and the organic material layer 1021 are etched in sequence.

[0051] In this embodiment, after doping the pattern material layer 300, it further includes: removing the remaining first mask layer 102.

[0052] It should be noted that in other embodiments, during the doping process of the pattern material layer in some regions, it may also be: the pattern material layer doped with ions serves as the first sacrificial layer, and the remaining pattern material layer not doped with ions serves as the pattern definition layer.

[0053] Refer to Figures 3 to 4 , along the second direction (as shown by the X direction in Figure 4 ), a part of the width of the first sacrificial layer 101 at the junction of the pattern definition layer 103 and the first sacrificial layer 101 is removed to form a first opening 106 surrounded by the pattern definition layer 103, the target layer 100, and the remaining first sacrificial layer 101. The second direction is perpendicular to the first direction.

[0054] In this embodiment, the top surface of the target layer 100 is exposed by the first opening 106.

[0055] In this embodiment, the first opening 106 provides a spatial position for subsequently forming the first sidewall layer and the second sacrificial layer.

[0056] In this embodiment, the step of forming the first opening 106 includes: forming a second mask layer 105 having a first mask opening 200 on the tops of the pattern definition layer 103 and the first sacrificial layer 101, the first mask opening 200 extending along the first direction and exposing the top of the first sacrificial layer 101 with a partial width in the second direction; using the second mask layer 105 as a mask to remove the exposed first sacrificial layer 101 along the first mask opening 200 to form the first opening 106.

[0057] In this embodiment, a dry etching process is used to remove a part of the first sacrificial layer 101 at the junction of the pattern definition layer 103 and the first sacrificial layer 101.

[0058] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching. Therefore, its longitudinal etching rate is much greater than the lateral etching rate, and it can obtain quite accurate pattern transfer, improving the sidewall morphology quality of the first opening 106.

[0059] In this embodiment, the sidewall of the first mask opening 200 close to the pattern definition layer 103 is flush with the sidewall of the first sacrificial layer 101.

[0060] It should be noted that since there is an etching selectivity between the first sacrificial layer 101 and the pattern definition layer 103, during the process of forming the first mask opening 200, the process window of the lithography process is increased. For example, in other embodiments, the first mask opening may also expose a part of the pattern definition layer with a partial width at the junction of the pattern definition layer and the first sacrificial layer.

[0061] In this embodiment, the second mask layer 105 includes a second organic material layer 1051, a second anti-reflection coating 1052 located on the second organic material layer 1051, and a second photoresist layer 1053 located on the second anti-reflection coating 1052.

[0062] For the specific description of the second mask layer 105, reference may be made to the corresponding description of the first mask layer 102 above, and details will not be elaborated here.

[0063] In this embodiment, after forming the first opening 106, it further includes: removing the remaining second mask layer 105.

[0064] Reference Figure 5, a first sidewall layer 107 is formed on the sidewall of the first opening 106. The first sidewall layer 107 includes a first sub-sidewall layer 1071 and a second sub-sidewall layer 1072 which are alternately arranged along the second direction (such as the X direction shown in Figure 5 ).

[0065] The first sidewall layer 107 is used as an etching mask for etching the subsequent target layer 100.

[0066] It should be noted that by forming the first sidewall layer 107 on the sidewall of the first opening 106, the size of the first opening 106 along the second direction is reduced, so that the requirement of continuously reducing the line width of the target pattern can be met while increasing the process window of the lithography process.

[0067] It should be noted that along the second direction, the size of the first sidewall layer 107 should not be too large or too small. If the size of the first sidewall layer 107 is too large, it is easy to occupy too much space position of the first opening 106, which may easily lead to too small size of the subsequent formed target pattern, resulting in the inability to meet the requirement of the line width of the target pattern, or the interval between the target patterns cannot reach the minimum design interval, thus affecting the performance of the metal interconnection line; if the size of the first sidewall layer 107 is too small, it is easy to cause too large remaining space of the first opening 106, which may easily lead to too large size of the target pattern formed by etching the target layer 100 with the first sidewall layer 107 as the mask, resulting in the inability to meet the requirement of continuously reducing the line width of the target pattern, thus affecting the performance of the metal interconnection line, or in order to make the line width of the target pattern meet the process requirements, the size of the first opening 106 needs to be reduced accordingly, which may easily reduce the process window for forming the first opening 106. Therefore, in this embodiment, along the second direction, the size of the first sidewall layer 107 is 10 nanometers to 20 nanometers. For example, along the second direction, the size of the first sidewall layer 107 is 13 nanometers, 15 nanometers or 17 nanometers.

[0068] It should be noted that in this embodiment, the size of the first sidewall layer 107 along the second direction is small, so that a small interval can be achieved between subsequent adjacent target patterns.

[0069] In this embodiment, the process for forming the first sidewall layer 107 includes an atomic layer deposition process.

[0070] The atomic layer deposition process includes multiple atomic layer deposition cycles, which is beneficial for improving the thickness uniformity of the first spacer layer 107 and allowing the first spacer layer 107 to cover the sidewalls of the pattern definition layer 103. In other embodiments, the first spacer layer can also be formed using a chemical vapor deposition (CVD) process.

[0071] The material of the first spacer layer 107 is selected such that the first spacer layer 107 can be retained during the subsequent removal of the first sacrificial layer 101 , the second sacrificial layer and the filling layer, and the target layer 100 can be subsequently etched using the first spacer layer 107 as a mask.

[0072] Therefore, in this embodiment, the material of the first spacer 107 may include titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the first spacer 107 is titanium oxide. Titanium oxide has a wider range of etching options than amorphous silicon or spin-on-glass.

[0073] In this embodiment, the step of forming the first sidewall layer 107 includes: forming a first sidewall material layer (not shown) on the top and sidewalls of the graphic definition layer 103, the top and sidewalls of the first sacrificial layer 101, and the bottom of the first opening 106, removing the first sidewall material layer on the top of the graphic definition layer 103, the top of the first sacrificial layer 101 and the bottom of the first opening 106, and the remaining first sidewall material layer serves as the first sidewall layer 107.

[0074] refer to Figure 6 After forming the first spacer layer 107 , a second sacrificial layer 108 is filled in the remaining space of the first opening 106 . The second sacrificial layer 108 and the first sacrificial layer 101 constitute a sacrificial structure 800 .

[0075] Subsequently, the sacrificial structure with a partial width in contact with the side wall of the first sub-spacer layer or the side wall of the second sub-spacer layer is removed to form a second opening surrounded by the remaining sacrificial structure, the first sub-spacer layer and the target layer, or a second opening surrounded by the remaining sacrificial structure, the second sub-spacer layer and the target layer. The second sacrificial layer 108 is used to provide a process platform for the formation of the second opening.

[0076] Subsequently, the sidewall of the sacrificial structure 800 exposed by the second opening forms a second spacer layer, and the patterns of the first spacer layer 107 and the second spacer layer are transferred to the target layer 100 to form a target pattern.

[0077] In this embodiment, in the step of filling the remaining space of the first opening 106 with the second sacrificial layer 108, the second sacrificial layer 108 also covers the tops of the pattern definition layer 103, the first sacrificial layer 101, and the first sidewall layer 107.

[0078] It should be noted that the second sacrificial layer 108 covering the tops of the pattern definition layer 103, the first sacrificial layer 101, and the first sidewall layer 107 provides a process basis for forming a filling layer in the second opening later, and thus provides a process basis for forming a second sidewall layer on the sidewalls of the second sacrificial layer 108 exposed in the filling layer.

[0079] Correspondingly, in this embodiment, the second sacrificial layer 108 provides a process platform for forming the second sidewall layer and the filling layer later.

[0080] In this embodiment, the step of forming the second sacrificial layer 108 includes: forming a second sacrificial material layer (not shown in the figure) on the tops of the pattern definition layer 103, the first sacrificial layer 101, and the first sidewall layer 107, and in the first opening 106; planarizing the second sacrificial material layer, and making the remaining second sacrificial material layer cover the tops of the pattern definition layer 103, the first sacrificial layer 101, and the first sidewall layer 107, and the remaining second sacrificial material layer serves as the second sacrificial layer 108.

[0081] By planarizing the second sacrificial material layer, the flatness of the top surface of the second sacrificial layer 108 is improved, providing a good process basis for subsequent patterning of the second sacrificial layer 108. For example, improving the quality of lithography.

[0082] In other embodiments, the planarization process may not be performed, that is, the second sacrificial material layer formed by deposition is directly used as the second sacrificial layer.

[0083] In this embodiment, the material of the second sacrificial layer 108 includes amorphous silicon, thereby improving the etching selectivity between the first sidewall layer 107 and the second sacrificial layer 108.

[0084] It should be noted that the lattice structure of amorphous silicon has unstable characteristics, which is easy to remove the second sacrificial layer 108 through a dry etching process later, and is beneficial to improving the uniformity of the etching rate.

[0085] Refer to Figures 7 to 8 , removing a part of the width of the sacrificial structure 800 in contact with the sidewalls of the second sub-sidewall layer 1072, and forming a second opening 110 surrounded by the remaining sacrificial structure 800, the second sub-sidewall layer 1072, and the target layer 100.

[0086] It should be noted that in this embodiment, a first opening 106 with a relatively large line width in the second direction is first formed, and then a part of the width of the sacrificial structure 800 in contact with the side wall of the first sub-sidewall layer 1071 or the side wall of the second sub-sidewall layer 1072 is removed to form a second opening 110. A second sidewall layer is formed on the side wall of the sacrificial structure 800 exposed in the second opening 110, and the space of the first opening 106 is segmented in the second direction (such as Figure 8 the X direction shown in the figure), which increases the process window of the lithography process used to form the first opening 106 and the second opening 110, and reduces the size of the target pattern formed in the second direction. Therefore, this embodiment can meet the requirement of continuously reducing the line width of the target pattern while increasing the process window of the lithography process, which is beneficial to further reducing the pitch between the target patterns.

[0087] In this embodiment, along the second direction, the size of the second opening 110 accounts for one-half to two-thirds of the size of the first opening 106.

[0088] It should be noted that the ratio of the size of the second opening 110 to the size of the first opening 106 should not be too large or too small. After forming the second sidewall layer on the side wall of the sacrificial structure exposed in the second opening, the patterns of the first sidewall layer 107 and the second sidewall layer are transferred to the target layer 100 to form the target pattern. That is to say, two target patterns are formed between the adjacent first sub-sidewall layer 1071 and the second sub-sidewall layer 1072. When the size of the first opening 106 in the second direction meets the process requirements, if the ratio is too large or too small, it is easy to cause the line width of the formed target pattern to fail to reach the target value, thus affecting the performance of the metal interconnection. Therefore, in this embodiment, along the second direction, the size of the second opening 110 accounts for one-half to two-thirds of the size of the first opening 106.

[0089] In this embodiment, the step of forming the second opening 110 includes: as Figure 7 shown, a third mask layer 109 with a second mask opening 500 is formed on the top surface of the second sacrificial layer 108. The second mask opening 500 is located on the top of the second sub-sidewall layer 1072 and extends to the top of a part of the pattern definition layer 103 and a part of the first sacrificial layer 101 on both sides of the second sub-sidewall layer 1072 along the second direction; as Figure 8As shown, using the third mask layer 109 as a mask, the exposed second sacrificial layer 108 and first sacrificial layer 101 are etched along the second mask opening 500 to form a second opening 110 surrounded by the remaining sacrificial structure 800, the second sub-sidewall layer 1072, and the target layer 100.

[0090] In this embodiment, by only removing a partial width of the sacrificial structure 800 in contact with the sidewall of the second sub-sidewall layer 1072, the process window for forming the second mask opening 500 is increased, and correspondingly, the process window for forming the second opening 110 is increased.

[0091] It should be noted that in this embodiment, the situation of the second opening 110 surrounded by the remaining sacrificial structure 800, the second sub-sidewall layer 1072, and the target layer 100 is shown.

[0092] In other embodiments, a partial width of the sacrificial structure in contact with the sidewall of the first sub-sidewall layer may also be removed to form a second opening surrounded by the remaining sacrificial structure, the first sub-sidewall layer, and the target layer.

[0093] Correspondingly, the step of forming the second opening may further include: forming a third mask layer having a second mask opening on the top surface of the second sacrificial layer, the second mask opening being located at the top of the first sub-sidewall layer and extending along the second direction to both sides of the first sub-sidewall layer to the top of a part of the pattern definition layer and a part of the first sacrificial layer; using the third mask layer as a mask, etching the exposed second sacrificial layer and first sacrificial layer along the second mask opening to form a second opening surrounded by the remaining sacrificial structure, the first sub-sidewall layer, and the target layer.

[0094] In this embodiment, in the step of forming the second opening 110, the etching selectivity between the sacrificial structure 800 and the first sidewall layer 107 is greater than 10:1.

[0095] It should be noted that in the step of forming the second opening 110, the etching selectivity between the sacrificial structure 800 and the first sidewall layer 107 should not be too small. If the etching selectivity between the sacrificial structure 800 and the first sidewall layer 107 is too small, it is easy to cause damage to the first sidewall layer 107, making it difficult to accurately transfer the pattern of the first sidewall layer 107 into the target layer 100. Therefore, in this embodiment, in the step of forming the second opening 110, the etching selectivity between the sacrificial structure 800 and the first sidewall layer 107 is greater than 10:1.

[0096] In this embodiment, a dry etching process is used to remove a partial width of the sacrificial structure 800 in contact with the sidewall of the second sub-sidewall layer 1072.

[0097] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching. Therefore, its longitudinal etching rate is much greater than the lateral etching rate, enabling quite accurate pattern transfer and improving the morphological quality of the remaining second sacrificial layer 108 and first sacrificial layer 101.

[0098] It should be noted that in other embodiments, a dry etching process can be used to remove a portion of the width of the sacrificial structure 800 that is in contact with the sidewalls of the first sub-sidewall layer 1071.

[0099] Reference Figure 9 , a filling layer 111 is formed in the second opening 110. The filling layer 111 covers the sidewalls of the first sidewall layer 107 and exposes a portion of the sidewalls of the sacrificial structure 800.

[0100] The filling layer 111 provides a process basis for the subsequent formation of the third sidewall layer.

[0101] Among them, when the filling layer 111 covers the first sidewall layer 107 and a second sidewall layer is subsequently formed on the sidewalls of the sacrificial structure 180 exposed in the second opening 110, it can prevent the formation of the second sidewall layer on the sidewalls of the first sidewall layer 107. And the portion of the sidewalls of the sacrificial structure 800 exposed by the filling layer 111 provides a process platform for the subsequent formation of the second sidewall layer on the exposed sidewalls of the sacrificial structure 800.

[0102] In this embodiment, in the step of forming the filling layer 111 in the second opening 110, the top of the filling layer 111 is flush with the top of the first sidewall layer 107.

[0103] It should be noted that since the top of the filling layer 111 is flush with the top of the first sidewall layer 107, there is enough space on the sidewalls of the exposed sacrificial structure 800 to form the second sidewall layer, such that the height of the second sidewall layer is large enough. Thus, during the subsequent process of etching the filling layer 111 to form the third sidewall layer using the second sidewall layer as a mask, the accuracy of pattern transfer is improved.

[0104] In this embodiment, the material of the filling layer 111 includes one or more of spin-on glass, ion-enhanced silicon oxide, and tetraethyl orthosilicate, which results in a high etching selectivity between the target layer 100 and the filling layer 111, facilitating the subsequent etching of the target layer 100 using the remaining filling layer 111 (i.e., the third sidewall layer) as a mask. As an example, the material of the filling layer 111 is spin-on glass.

[0105] Reference Figure 10, a second sidewall layer 112 is formed on the sidewall of the sacrificial structure 800 exposed at the second opening 110.

[0106] Subsequently, the patterns of the first sidewall layer 107 and the second sidewall layer 112 are transferred into the target layer 100 to form a target pattern.

[0107] Specifically, the second sidewall layer 112 provides an etching mask for forming a third sidewall layer subsequently.

[0108] In this embodiment, in the step of forming the second sidewall layer 112 on the sidewall of the sacrificial structure 800 exposed at the second opening 110, the second sidewall layer 112 is formed on the sidewall of the second sacrificial layer 108 exposed by the filling layer 111.

[0109] In this embodiment, the step of forming the second sidewall layer 112 includes: forming a second sidewall material layer (not shown in the figure) on the top and sidewalls of the second sacrificial layer 108 and on the top of the filling layer 111; removing the second sidewall material layer on the top of the second sacrificial layer 108 and the filling layer 111, and the remaining second sidewall material layer serves as the second sidewall layer 112.

[0110] In this embodiment, along the second direction, the size of the second sidewall layer 112 is 10 nanometers to 20 nanometers.

[0111] It should be noted that along the second direction, the size of the second sidewall layer 112 should not be too large or too small. The second sidewall layer 112 provides an etching mask for forming a third sidewall layer subsequently. If the size of the second sidewall layer 112 is too large, it is likely to cause the size of the formed third sidewall layer to be too large, and then the interval between the target patterns cannot reach the minimum design interval, thus affecting the performance of the metal interconnects. Or, if the size of the formed third sidewall layer is too large, it is likely to occupy too much of the spatial position of the first opening 106, and then it is likely to cause the size of the subsequently formed target pattern to be too small, resulting in not meeting the requirements of the target pattern line width. If the size of the second sidewall layer 112 is too small, it is likely to cause the size of the formed third sidewall layer to be too small, and then it is likely to make the remaining space of the first opening 106 too large, and it is likely to cause the size of the subsequently formed target pattern to be too large, not meeting the requirements of the target pattern line width. Therefore, in this embodiment, along the second direction, the size of the second sidewall layer 112 is 10 nanometers to 20 nanometers. For example, the size of the second sidewall layer 112 is 13 nanometers, 15 nanometers or 17 nanometers.

[0112] In this embodiment, the process of forming the second sidewall layer 112 includes an atomic layer deposition process.

[0113] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the second sidewall layer 112, enabling the second sidewall layer 112 to cover the sidewalls of the second sacrificial layer 108. In other embodiments, a chemical vapor deposition (CVD) process may also be used to form the second sidewall layer.

[0114] The material of the second sidewall layer 112 is selected such that the second sidewall layer 112 can be retained during the subsequent removal of the sacrificial structure 800, and the second sidewall layer 112 can also serve as an etching mask during the subsequent etching of the filling layer 111.

[0115] In this embodiment, the material of the second sidewall layer 112 may include titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the second sidewall layer 112 is titanium oxide. The etching selectivity of the titanium oxide material with respect to amorphous silicon or spin-on glass is relatively large.

[0116] Reference Figure 11 After forming the second sidewall layer 112, the sacrificial structure 800 is removed.

[0117] Specifically, removing the sacrificial structure 800 provides a process basis for etching the filling layer 111 to form a third sidewall layer using the second sidewall layer 112 as a mask in the subsequent process.

[0118] In this embodiment, after forming the second sidewall layer 112, a wet etching process is used to remove the sacrificial structure 800.

[0119] During the process of removing amorphous silicon by the wet etching process, it has the characteristics of high efficiency, low cost, etc., and can reduce the damage to the underlying film layer.

[0120] Reference Figures 12 to 13 After removing the sacrificial structure 800, the patterns of the first sidewall layer 107 and the second sidewall layer 112 are transferred to the target layer 100 to form a target pattern 120.

[0121] As can be seen from the foregoing description, this embodiment can meet the requirement of continuously reducing the line width of the target pattern 120 while increasing the process window of the lithography process, and is beneficial to further reducing the pitch between the target patterns 120, which correspondingly improves the pattern accuracy and pattern quality of the target pattern 120.

[0122] In this embodiment, the steps of forming the target pattern 120 include: etching the filling layer 111 using the second sidewall layer 112 as a mask to form a third sidewall layer 310; etching the target layer 100 using the first sidewall layer 107 and the third sidewall layer 310 as masks.

[0123] In this embodiment, after removing the sacrificial structure 800, the filling layer 111 is etched using the second sidewall layer 112 as a mask to form a third sidewall layer 310.

[0124] In other embodiments, the filling layer may first be etched using the second sidewall layer as a mask to form a third sidewall layer, and then the sacrificial structure may be removed.

[0125] In this embodiment, the target layer 100 is a dielectric layer. Therefore, after etching the target layer 100 using the first sidewall layer 107 and the third sidewall layer 310 as masks, the target pattern 130 is an interconnect trench.

[0126] In this embodiment, a hard mask material layer (not shown in the figure) and an etch stop layer (not shown in the figure) are further formed on the target layer 100, and the bottom of the first opening 106 and the second opening 110 exposes the etch stop layer.

[0127] In this embodiment, using the first sidewall layer 107 and the third sidewall layer 310 as masks, the etch stop layer and the hard mask material layer on the top of the target layer 100 are etched in sequence. After the remaining hard mask material layer serves as a hard mask layer (not shown in the figure), the target layer 100 is etched using the hard mask layer as a mask.

[0128] Reference Figure 14 , the forming method further includes: after forming the interconnect trench, a metal interconnect 121 is formed in the interconnect trench.

[0129] The metal interconnect 121 is used to achieve the electrical connection between the semiconductor structure and an external circuit or other interconnect structures.

[0130] As can be seen from the foregoing description, this embodiment can meet the requirement of continuously reducing the line width of the interconnect trench while increasing the process window of the lithography process, and the spacing between adjacent interconnect trenches is easy to meet the design minimum pitch. Correspondingly, it is beneficial to make the spacing between the metal interconnects 121 meet the design minimum pitch, which is beneficial to further reducing the pitch between the metal interconnects 121, and is also beneficial to improving the pattern accuracy of the metal interconnects 121, and further beneficial to improving the electrical connection performance of the metal interconnects 121.

[0131] In this embodiment, the material of the metal interconnect 121 is copper. In other embodiments, the material of the metal interconnect may also be a conductive material such as aluminum.

[0132] In this embodiment, the metal interconnect 121 is formed in the interconnect trench by electroplating.

[0133] Correspondingly, the process of forming the metal interconnect 121 includes a step of filling a conductive material and a step of planarizing the conductive material, and the planarizing step is used to remove the conductive material above the top of the dielectric layer.

[0134] In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.

[0135] The chemical mechanical polishing process makes the surface of the metal interconnect 121 formed in the interconnect trench flat, improving the electrical connection effect of the metal interconnect 121.

[0136] In this embodiment, during the process of forming the metal interconnect 121, the remaining pattern definition layer 103, the first sidewall layer 107, the third sidewall layer 310, the etch stop layer, and the hard mask layer are also removed, thereby exposing the top surface of the target layer 100 to prepare for subsequent processes.

[0137] The specific description of the metal interconnect 121 will not be elaborated here.

[0138] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, including a target layer for forming a target pattern, a pattern definition layer is formed on the target layer, a first sacrificial layer extending in a first direction and penetrating the pattern definition layer is formed in the pattern definition layer, and the etching rates between the first sacrificial layer and the pattern definition layer are different; Along a second direction, removing a part of the width of the first sacrificial layer at the junction of the pattern definition layer and the first sacrificial layer to form a first opening surrounded by the pattern definition layer, the target layer and the remaining first sacrificial layer, and the second direction is perpendicular to the first direction; Forming a first sidewall layer on the sidewalls of the first opening, and the first sidewall layer includes a first sub-sidewall layer and a second sub-sidewall layer alternately arranged along the second direction; After forming the first sidewall layer, filling a second sacrificial layer in the remaining space of the first opening, and the second sacrificial layer and the first sacrificial layer constitute a sacrificial structure; Removing a part of the width of the sacrificial structure in contact with the sidewall of the first sub-sidewall layer or the sidewall of the second sub-sidewall layer to form a second opening surrounded by the remaining sacrificial structure, the first sub-sidewall layer and the target layer, or forming a second opening surrounded by the remaining sacrificial structure, the second sub-sidewall layer and the target layer; Forming a second sidewall layer on the sidewalls of the sacrificial structure exposed in the second opening; After forming the second sidewall layer, removing the sacrificial structure; After removing the sacrificial structure, transferring the patterns of the first sidewall layer and the second sidewall layer into the target layer to form a target pattern.

2. The method for forming a semiconductor structure as described in claim 1, wherein, In the step of filling the second sacrificial layer in the remaining space of the first opening, the second sacrificial layer also covers the tops of the pattern definition layer, the first sacrificial layer and the first sidewall layer; Before forming the second sidewall layer, it further includes: forming a filling layer in the second opening, and the filling layer covers the sidewalls of the first sidewall layer and exposes a part of the sidewalls of the sacrificial structure; In the step of forming the second sidewall layer on the sidewalls of the sacrificial structure exposed in the second opening, the second sidewall layer is formed on the sidewalls of the second sacrificial layer exposed by the filling layer; The step of forming the target pattern includes: using the second sidewall layer as a mask to etch the filling layer to form a third sidewall layer; using the first sidewall layer and the third sidewall layer as masks to etch the target layer.

3. The method for forming a semiconductor structure according to claim 2, wherein, In the step of forming the filling layer in the second opening, the top of the filling layer is flush with the top of the first sidewall layer.

4. The method for forming a semiconductor structure according to claim 2, wherein, The step of forming the second sacrificial layer includes: forming a second sacrificial material layer on the tops of the pattern definition layer, the first sacrificial layer and the first sidewall layer, and in the first opening; planarizing the second sacrificial material layer, and the remaining second sacrificial material layer is used as the second sacrificial layer.

5. The method for forming a semiconductor structure according to claim 2, wherein, The step of forming the second sidewall layer includes: forming a second sidewall material layer on the top and sidewalls of the second sacrificial layer, and on the top of the filling layer; removing the second sidewall material layer on the tops of the second sacrificial layer and the filling layer, and the remaining second sidewall material layer is used as the second sidewall layer.

6. The method for forming a semiconductor structure according to claim 1, wherein, The steps of forming the first sacrificial layer and the pattern definition layer include: forming a pattern material layer on the top of the target layer; Dope the graphic material layer in some regions. The graphic material layer doped with ions serves as the graphic definition layer, and the remaining graphic material layer not doped with ions serves as the first sacrificial layer.

7. The method for forming a semiconductor structure according to claim 6, wherein, Use an ion implantation process to dope the graphic material layer in some regions.

8. The method for forming a semiconductor structure according to claim 6, wherein In the steps of the doping process, the doped ions include boron ions, phosphorus ions, or argon ions.

9. The method for forming a semiconductor structure according to claim 1, wherein, Use a dry etching process to remove part of the first sacrificial layer at the junction of the graphic definition layer and the first sacrificial layer.

10. The method for forming a semiconductor structure according to claim 1, wherein, Along the second direction, the size of the second opening accounts for one-half to two-thirds of the size of the first opening.

11. The method for forming a semiconductor structure as described in claim 1, wherein, Along the second direction, the size of the first sidewall layer is 10 nanometers to 20 nanometers.

12. The method for forming a semiconductor structure according to claim 1, wherein, The process for forming the first sidewall layer includes an atomic layer deposition process.

13. The method for forming a semiconductor structure according to claim 1, wherein, Along the second direction, the size of the second sidewall layer is 10 nanometers to 20 nanometers.

14. The method for forming a semiconductor structure according to claim 1, wherein, The process for forming the second sidewall layer includes an atomic layer deposition process.

15. The method for forming a semiconductor structure according to claim 1, wherein, Use a dry etching process to remove part of the width of the sacrificial structure in contact with the sidewall of the first sub-sidewall layer or the sidewall of the second sub-sidewall layer.

16. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the second opening, the etching selectivity between the sacrificial structure and the first sidewall layer is greater than 10:

1.

17. The method for forming a semiconductor structure according to claim 1, wherein, After forming the second sidewall layer, use a wet etching process to remove the sacrificial structure.

18. The method for forming a semiconductor structure according to claim 1, wherein, The material of the first sacrificial layer includes amorphous silicon, and the material of the second sacrificial layer includes amorphous silicon.

19. The method for forming a semiconductor structure according to claim 2, wherein The material of the filling layer includes one or more of spin-on glass, spin-on glass, and tetraethyl orthosilicate.

20. The method for forming a semiconductor structure according to claim 1, wherein The target layer is a dielectric layer, and the target graphic is an interconnect trench; The forming method further includes: after forming the interconnect trench, forming a metal interconnect line in the interconnect trench.

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