A semiconductor structure

Abstract

The present application provides a semiconductor structure comprising: a semiconductor substrate; a through-silicon via (TSV) structure located within the semiconductor substrate, the TSV structure having a first side; and at least one first capacitor trench unit vertically distributed within the semiconductor substrate on the first side. The first capacitor trench unit comprises a plurality of parallel capacitor trench groups and a plurality of tilted capacitor trench groups, wherein the capacitor trench group opposite the TSV structure is a tilted capacitor trench group. The semiconductor structure of the present application's technical solution can address local stress issues at TSVs during fabrication, enabling integrated fabrication of DTCs and TSVs in a 2.5D interposer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure. Background Art

[0002] As the drive strength of semiconductor devices increases, the devices have higher current density and larger current transients, making the chips increasingly sensitive to fluctuations in power supply voltage. Circuits need to reduce PDN impedance through decoupling capacitors and suppress noise through decoupling or bypass circuits. Therefore, parasitic resistance and inductance must be controlled. Decoupling capacitors must be close to the circuits, so it is necessary to integrate a large number of capacitor trenches (DTCs) and TSVs in a packaging structure (2.5D Interposer) that uses vertical interconnect through-via (TSV) interposers.

[0003] In order to obtain a higher capacitance density, the depth of the capacitor trench is usually increased, the surface area of the dielectric layer is expanded, and the number of dielectric layers and electrode layers is increased. When preparing the DTC electrode, the amorphous silicon filled in the trench is annealed at high temperature and transformed into polycrystalline silicon, which releases a large stress and causes severe deformation of the silicon wafer. Especially for TSV surrounded by DTC, the stress generated after the DTC process and the influence of the TSV process will cause local stress in the TSV, causing the TSV to deform. After the stress is released in the subsequent process, void defects will exist when the TSV is filled. In addition, the large local stress squeezes the TSV, causing the internal filling metal to deform or even destroy the structure. Summary of the Invention

[0004] The technical problem to be solved by this application is to solve the local stress problem at TSV during the manufacturing process and realize the integrated manufacturing of DTC and TSV in 2.5D Interposer.

[0005] To solve the above technical problems, the present application provides a semiconductor structure, comprising: a semiconductor substrate; a through-silicon via (TSV) structure located in the semiconductor substrate, the TSV structure having a first side; and at least one first capacitor trench unit vertically distributed in the semiconductor substrate on the first side, the first capacitor trench unit comprising a plurality of parallel capacitor trench groups and a plurality of inclined capacitor trench groups, wherein the capacitor trench group opposite to the TSV structure is an inclined capacitor trench group.

[0006] In an embodiment of the present application, the through-silicon via structure further has a second side opposite to the first side; the semiconductor structure further includes at least one second capacitor trench unit, vertically distributed in the semiconductor substrate on the second side, the second capacitor trench unit including a plurality of parallel capacitor trench groups and a plurality of inclined capacitor trench groups, and the capacitor trench group opposite to the through-silicon via structure is an inclined capacitor trench group.

[0007] In an embodiment of the present application, the plurality of parallel capacitor trench groups and the plurality of inclined capacitor trench groups in the first capacitor trench unit and the second capacitor trench unit are mirror-imaged.

[0008] In the embodiment of the present application, in the first capacitor trench unit and the second capacitor trench unit, the capacitor trench groups located in the same row include at least one parallel capacitor trench group and one inclined capacitor trench group.

[0009] In an embodiment of the present application, the through silicon via structure further has a third side and a fourth side relative to each other, wherein the third side and the fourth side are perpendicular to the first side and the second side, and the semiconductor structure further includes a third capacitor trench unit adjacent to the third side and the fourth side, respectively, and the third capacitor trench unit includes a plurality of horizontally distributed parallel capacitor trench groups.

[0010] In the embodiment of the present application, the first capacitor trench unit, the second capacitor trench unit, and the third capacitor trench unit are distributed around the through silicon via structure.

[0011] In the embodiment of the present application, the inclined capacitor trench group opposite to the through silicon via structure is surrounded to form a recessed angle, and the angle of the recessed angle does not exceed 90°.

[0012] In an embodiment of the present application, the parallel capacitor groove group includes a plurality of first capacitor grooves distributed in parallel along a first direction, the inclined capacitor groove group includes a plurality of second capacitor grooves distributed in parallel along a second direction, and the acute angle between the straight lines of the first direction and the second direction is greater than 0° and less than 90°.

[0013] In the embodiment of the present application, the first direction is a horizontal direction.

[0014] In the embodiment of the present application, the spacing between adjacent first capacitor trenches and the spacing between adjacent second capacitor trenches are 0.3 μm-0.6 μm.

[0015] In an embodiment of the present application, a distance between the first capacitor trench unit and the through silicon via structure does not exceed 60 μm.

[0016] In an embodiment of the present application, the through silicon via structure includes at least two through silicon vias, and the bump interconnection pitch of the through silicon vias is 10 μm-20 μm.

[0017] Compared with the prior art, the semiconductor structure of the technical solution of the present application rationally arranges the through-silicon via structure and the first capacitor trench unit, so that the first capacitor trench unit is vertically distributed in the semiconductor substrate on the first side of the through-silicon via structure, and the first capacitor trench unit is composed of a plurality of parallel capacitor trench groups and a plurality of inclined capacitor trench groups, wherein the inclined capacitor trench group can decompose the direction of stress, thereby reducing the stress magnitude in a certain direction, and at the same time can also reduce the distance between the capacitor trench and the through-silicon via, which is conducive to improving the unit device integration; the presence of the parallel capacitor trench group ensures the effective area of the capacitor trench, thereby ensuring the capacitance value. Furthermore, the capacitor trench group opposite to the through-silicon via structure is an inclined capacitor trench group, which can further reduce the distance between the capacitor trench and the through-silicon via. At the same time, the second capacitor trench of the inclined capacitor trench group has a second direction, so that the stress generated when making the second capacitor trench is released along the second direction, significantly reducing the stress on the through-silicon via.

[0018] The inclined capacitor trench group opposite to the through-silicon via structure is surrounded by a recessed angle, and the angle of the recessed angle does not exceed 90°. The existence of the recessed angle can avoid excessive stress on the through-silicon via when making the second capacitor trench due to the distance between the second capacitor trench and the through-silicon via being too close, effectively balancing the effect of stress on the through-silicon via, which is conducive to increasing the number of through-silicon vias and reducing the spacing between the through-silicon vias and the capacitor trenches, further improving the integration of the unit device.

[0019] The distance between the first capacitor trench unit and the through-silicon via structure of the technical solution of the present application is shortened to no more than 60 μm, which is 50% shorter than that of the prior art, thereby greatly improving the integration of the unit device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0021] Figure 1 A schematic structural diagram of a semiconductor structure according to an embodiment of the present application;

[0022] Figure 2 A schematic structural diagram of another semiconductor structure according to an embodiment of the present application;

[0023] Figure 3 This is a schematic structural diagram of another semiconductor structure according to an embodiment of the present application;

[0024] Figure 4 This is a schematic structural diagram of a semiconductor structure according to a specific example of an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0026] The technical solution of the present application balances the stress generated in the process by arranging the distribution of capacitor trenches and silicon via structures, so as to solve the local stress problem at the silicon vias during the manufacturing process.

[0027] The semiconductor structure of the technical solution of the present application is described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] refer to Figure 1 The semiconductor structure of the embodiment of the present application includes: a semiconductor substrate 100, a through-silicon via structure 2, and a first capacitor trench unit 3. The material of the semiconductor substrate 100 may include at least one of the following: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, and may also include a multilayer structure composed of layers of the above materials, or a silicon-on-insulator (SOI) or stacked silicon-on-insulator (SSOI) structure. In the embodiment of the present application, the constituent material of the semiconductor substrate 100 is single crystal silicon.

[0029] The TSV structure 2 is located in the semiconductor substrate 100 and includes at least two TSVs to meet current device performance requirements and improve the integration of a unit device. For example, the TSV structure 2 may include two, four, seven, or more TSVs. Figure 1 shows a schematic diagram of a semiconductor structure with four through-silicon vias, Figure 2 A schematic diagram of a semiconductor structure with seven through-silicon vias is shown.

[0030] The TSVs can be evenly or unevenly distributed within the semiconductor substrate 100. The bump interconnect pitch L between adjacent TSVs is 10 μm to 20 μm. Under process conditions, a smaller bump interconnect pitch increases the number of TSVs that can be integrated, facilitating device miniaturization. In the embodiments of the present application, the bump interconnect pitch L refers to the distance between the centers of two circular cross-sections obtained by sectioning two TSVs on the same horizontal plane.

[0031] The TSV structure 200 has opposite first and second sides and opposite third and fourth sides, wherein the third and fourth sides are perpendicular to the first and second sides.

[0032] The semiconductor substrate 100 of the embodiment of the present application includes at least one first capacitor trench unit 300. For example, the number of the first capacitor trench units 300 can be three, four, five, etc. The number of the capacitor trench units 300 is determined by the device's capacitance requirements and the device size. The greater the device's capacitance requirements, the greater the number of the first capacitor trench units 300. However, the number of the first capacitor trench units 300 is limited by the device size. In the embodiment of the present application, three first capacitor trench units are used as an example for illustration.

[0033] The first capacitor trench unit 300 is distributed in the semiconductor substrate 100 and is located on a first side of the through silicon via structure 200. Figure 1 and Figure 2 In the figure, the first capacitor trench unit 300 is schematically located on the left side of the through silicon via structure 200. At the same time, the first capacitor trench units 300 are arranged in a vertical direction to minimize the distance between the through silicon via and the capacitor trench, thereby improving the unit device integration.

[0034] The first capacitor trench unit 300 includes a plurality of parallel capacitor trench groups 310 and a plurality of inclined capacitor trench groups 320, wherein the parallel capacitor trench group 310 includes a plurality of first capacitor trenches distributed in parallel along a first direction, for example, the first capacitor trenches are distributed in a horizontal direction. The number of the first capacitor trenches can be determined according to actual conditions. In the embodiment of the present application, six first capacitor trenches are used to form a parallel capacitor trench group 310 as an example. The distance between adjacent first capacitor trenches can be 0.3μm-0.6μm, for example, the distance between adjacent first capacitor trenches is 0.5μm.

[0035] The inclined capacitor groove group 320 includes a number of second capacitor grooves distributed in parallel along the second direction, and the acute angle between the second direction and the straight line of the first direction is greater than 0° and less than 90°. For example, the size of the acute angle is 20°, 30°, 45°, 50°, 60°, 80°, etc. The number of the second capacitor grooves is also determined according to the required capacitance size. The embodiment of the present application is described as follows: each inclined capacitor groove group 320 includes six second capacitor grooves. The spacing between adjacent second capacitor grooves is 0.3μm-0.6μm. The length of the second capacitor grooves of the inclined capacitor groove group 320 gradually increases from both sides to the middle to meet the design requirements of the layout.

[0036] The embodiment of the present application adopts a combination of a parallel capacitor trench group and an inclined capacitor trench group. On the one hand, the inclined capacitor trench group can decompose the direction of stress, thereby reducing the stress magnitude in a certain direction. At the same time, the inclined capacitor trench group can reduce the distance between the capacitor trench and the silicon through-via, which is beneficial to improving the unit device integration. On the other hand, the presence of the parallel capacitor trench group ensures the effective area of the capacitor trench, thereby ensuring the capacitance value.

[0037] In an embodiment of the present application, the capacitor trench group relative to the through-silicon via structure 200 is an inclined capacitor trench group 320, which can further reduce the distance between the capacitor trench and the through-silicon via. At the same time, since the second capacitor trench in the inclined capacitor trench group 320 has a second direction, the stress generated when making the second capacitor trench will be released along the second direction, greatly reducing the stress on the through-silicon via. In some embodiments, the inclined capacitor trench group 320 relative to the through-silicon via structure 200 can be surrounded by a recessed angle, and the angle of the recessed angle does not exceed 90°. The presence of the recessed angle can avoid the excessive stress on the through-silicon via when making the second capacitor trench due to the distance between the second capacitor trench and the through-silicon via being too close, effectively balancing the effect of stress on the through-silicon via, which is conducive to increasing the number of through-silicon vias and reducing the spacing between the through-silicon vias and the capacitor trenches, further improving the integration of the unit device.

[0038] In the first capacitor trench unit, the specific distribution of the parallel capacitor trench groups and the tilted capacitor trench groups is not particularly limited; it is sufficient that the capacitor trench group opposite the through-silicon via structure 200 is a tilted capacitor trench group. In some embodiments, the first capacitor trench unit includes two parallel capacitor trench groups and two tilted capacitor trench groups, arranged in a "field" shape.

[0039] Currently, the distance between the capacitor trench and the TSV is at least 120μm. However, in this embodiment, the parallel capacitor trench group and the angled capacitor trench group are rationally arranged to reduce the distance between the first capacitor trench unit 300 and the TSV structure 200 to no more than 60μm. Compared with the prior art, this embodiment reduces the distance between the capacitor trench and the TSV by 50%, significantly improving the integration density of the unit device.

[0040] In the first capacitor trench unit 300 , the capacitor trench groups located in the same row include at least one parallel capacitor trench group 310 and an inclined capacitor trench group 320 , so as to avoid the capacitor trenches being arranged in a single direction, which is not conducive to stress dispersion.

[0041] Continue to refer Figure 1 The semiconductor structure further includes at least one second capacitor trench unit 400, which is vertically distributed in the semiconductor substrate 100 on the second side of the through-silicon via structure 200. The second capacitor trench unit 400 includes a plurality of parallel capacitor trench groups and a plurality of inclined capacitor trench groups, and the capacitor trench group opposite the through-silicon via structure 200 is an inclined capacitor trench group. The number of the second capacitor trench units 400 is determined based on actual conditions. In the embodiment of the present application, the number of the second capacitor trench units 400 is the same as that of the first capacitor trench units 300.

[0042] The plurality of parallel capacitor trench groups and the plurality of inclined capacitor trench groups in the first capacitor trench unit 300 and the second capacitor trench unit 400 are mirror-imaged. Therefore, the specific distribution of the second capacitor trench unit 400 can refer to that of the first capacitor trench unit 300 and will not be further described here. The distance between the second capacitor trench unit 400 and the through-silicon via structure 200 does not exceed 60 μm.

[0043] The semiconductor structure further includes a third capacitor trench unit 500 adjacent to the third side and the fourth side, respectively. The third capacitor trench unit 500 includes a plurality of horizontally distributed parallel capacitor trench groups. The number of the parallel capacitor trench groups is determined based on actual conditions. For example, the third capacitor trench unit 500 may include two, three, four, or more parallel capacitor trench groups. The present embodiment uses two parallel capacitor trench groups as an example.

[0044] The capacitor trench group of the third capacitor trench unit 500 is a parallel capacitor trench group to increase the effective area of the entire capacitor trench. Of course, in some embodiments, the third capacitor trench unit 500 may also include a plurality of inclined capacitor trench groups, and the inclined capacitor trench groups opposite to the through silicon via structure 200 are surrounded to form a recessed angle, and the angle of the recessed angle does not exceed 90°. Figure 3 shown.

[0045] The first capacitor trench unit 300 , the second capacitor trench unit 400 , and the third capacitor trench unit 500 are distributed around the through silicon via structure 200 to improve the integration of unit devices.

[0046] The following further explains the layout of the semiconductor structure according to the embodiment of the present application through specific examples.

[0047] refer to Figure 4 The semiconductor structure is arranged in a nine-square grid, which includes nine grids, namely grid 1, grid 2, grid 3, grid 4, grid 5, grid 6, grid 7, grid 8 and grid 9. The grid 5 is used to distribute the through-silicon via structure. Grid 1, grid 4 and grid 7 are vertically distributed on the first side of the grid 5, and each of the grids 1, 4 and 7 is distributed with a first capacitor trench unit. The first capacitor trench unit includes four capacitor trench groups distributed in a "field" shape, two of which are parallel capacitor trench groups and the remaining two are inclined capacitor trench groups. The two parallel capacitor trench groups in grid 1 are diagonally distributed, and the remaining two inclined capacitor trench groups are diagonally distributed, and the two inclined capacitor trench groups are inclined in different directions. The two parallel capacitor trench groups in lattice 4 are located on the side away from lattice 5, and the remaining two inclined capacitor trench groups are located on the side close to lattice 5. The two inclined capacitor trench groups are inclined in different directions and form a recessed angle towards lattice 5. The distribution of the capacitor trench units in lattice 7 is a mirror image of that in lattice 1. The distribution of the capacitor trench units in lattice 3 is a mirror image of that in lattice 1, the distribution of the capacitor trench units in lattice 6 is a mirror image of that in lattice 4, and the distribution of the capacitor trench units in lattice 9 is a mirror image of that in lattice 1. Grids 2 and 8 are each distributed with a third capacitor trench unit, and the third capacitor trench unit includes two horizontally distributed parallel capacitor trench groups. The parallel capacitor trench group includes six first capacitor trenches distributed in parallel along the horizontal direction, and the inclined capacitor trench group includes six second capacitor trenches distributed in parallel along the second direction, and the angle between the second direction and the horizontal direction is 45°.

[0048] In the entire nine-square grid arrangement, the capacitor trenches in each row and column are not set along a single direction, and are symmetrically arranged around the through-silicon via structure, effectively balancing the impact of stress on the through-silicon via structure. At the same time, it is also beneficial to increase the number of through-silicon vias, reduce the distance between the through-silicon vias and the capacitor trenches, and further improve the unit device integration of Interposer.

[0049] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0050] It should be understood that the term "and / or" used in this embodiment includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0051] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" indicates the absence of intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0052] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

Claims

1. A semiconductor structure, characterized in that include: semiconductor substrates; a through silicon via structure located in the semiconductor substrate, the through silicon via structure having a first side; At least one first capacitor trench unit is vertically distributed in the semiconductor substrate on the first side, the first capacitor trench unit includes a plurality of parallel capacitor trench groups and a plurality of inclined capacitor trench groups, wherein the capacitor trench group opposite to the through-silicon via structure is an inclined capacitor trench group, the parallel capacitor trench group includes a plurality of first capacitor trenches distributed in parallel along a first direction, the inclined capacitor trench group includes a plurality of second capacitor trenches distributed in parallel along a second direction, and an acute angle between a straight line including the first direction and the second direction is greater than 0° and less than 90°.

2. The semiconductor structure according to claim 1, wherein: The through-silicon via structure also has a second side opposite to the first side; the semiconductor structure also includes at least one second capacitor trench unit, vertically distributed in the semiconductor substrate on the second side, the second capacitor trench unit includes a plurality of parallel capacitor trench groups and a plurality of inclined capacitor trench groups, and the capacitor trench group opposite to the through-silicon via structure is an inclined capacitor trench group.

3. The semiconductor structure according to claim 2, wherein: The plurality of parallel capacitor trench groups and the plurality of inclined capacitor trench groups in the first capacitor trench unit and the second capacitor trench unit are mirror-imaged.

4. The semiconductor structure according to claim 2, wherein: In the first capacitor trench unit and the second capacitor trench unit, the capacitor trench groups located in the same row include at least one parallel capacitor trench group and one inclined capacitor trench group.

5. The semiconductor structure according to claim 2, wherein: The through silicon via structure also has a third side and a fourth side relative to each other, and the third side and the fourth side are perpendicular to the first side and the second side. The semiconductor structure also includes a third capacitor trench unit adjacent to the third side and the fourth side respectively, and the third capacitor trench unit includes a plurality of horizontally distributed parallel capacitor trench groups.

6. The semiconductor structure according to claim 5, wherein: The first capacitor trench unit, the second capacitor trench unit and the third capacitor trench unit are distributed around the through silicon via structure.

7. The semiconductor structure according to claim 1, wherein: The inclined capacitor trench groups surround the through silicon via structure, and adjacent inclined capacitor trench groups form a recessed angle facing the through silicon via structure, wherein the angle of the recessed angle does not exceed 90°.

8. The semiconductor structure according to claim 1, wherein: The first direction is a horizontal direction.

9. The semiconductor structure according to claim 1, wherein: The spacing between adjacent first capacitor trenches and the spacing between adjacent second capacitor trenches are 0.3 μm-0.6 μm.

10. The semiconductor structure according to claim 1, wherein: The distance between the first capacitor trench unit and the through silicon via structure does not exceed 60 μm.

11. The semiconductor structure according to claim 1, wherein: The through silicon via structure includes at least two through silicon vias, and the bump interconnection pitch of the through silicon vias is 10 μm-20 μm.

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