Semiconductor device and method of manufacturing the same, integrated circuit

Abstract

A semiconductor device includes a first active region disposed on a first side of a substrate, extending along a first lateral direction. The semiconductor device includes a second active region disposed on the first side, extending along the first lateral direction. The first active region has a first conductivity type, and the second active region has a second conductivity type opposite the first conductivity type. The semiconductor device includes a first interconnect structure formed on a second side of the substrate opposite the first side, the first interconnect structure including a first portion extending along the first lateral direction and disposed vertically below the first active region, and a second portion extending along a second lateral direction. The second lateral direction is perpendicular to the first lateral direction. Embodiments of the invention also relate to methods of manufacturing a semiconductor device and integrated circuits.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same, and integrated circuits. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs.

[0003] This scaling down also increases the complexity of IC structures (such as 3D transistors) and processing, and similar advancements in IC processing and manufacturing are needed to achieve these progresses. For example, as device dimensions continue to shrink, device performance (such as device performance degradation associated with various defects) and the manufacturing cost of field-effect transistors become more challenging. While the methods used to address these challenges are generally sufficient, they are not entirely satisfactory in every aspect. Summary of the Invention

[0004] An embodiment of the present invention provides a semiconductor device, comprising: a first active region disposed on a first side of a substrate, the first active region extending along a first lateral direction; a second active region disposed on the first side, the second active region extending along the first lateral direction, wherein the first active region has a first conductivity type and the second active region has a second conductivity type opposite to the first conductivity type; and a first interconnect structure formed on a second side of the substrate opposite to the first side, the first interconnect structure comprising: a first portion extending along the first lateral direction and perpendicularly disposed below the first active region; and a second portion extending along a second lateral direction, wherein the second lateral direction is perpendicular to the first lateral direction.

[0005] Another embodiment of the present invention provides an integrated circuit, comprising: a first row extending along a first direction and having a first height along a second direction perpendicular to the first direction, wherein the first row includes a first active region formed on a first side of a substrate; a second row extending along the first direction and having a second height along the second direction, wherein the second height is greater than the first height, and wherein the second row includes a second active region formed on the first side of the substrate; a signal line structure formed on a second side of the substrate opposite to the first side, wherein the signal line structure is disposed within the first row; and a first power line structure formed on the second side of the substrate, wherein the first power line structure is disposed within the second row.

[0006] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a plurality of transistors on a first side of a substrate; coupling the plurality of transistors by forming a plurality of first interconnect structures extending along a first lateral direction or a second lateral direction on the first side, the first lateral direction and the second lateral direction being perpendicular to each other; forming a plurality of third interconnect structures on a second side of the substrate opposite to the first side, wherein at least one of the third interconnect structures includes a first portion and a second portion extending along the first lateral direction and the second lateral direction, respectively; and forming a plurality of power rail structures extending along the first lateral direction on the second side. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of a non-planar transistor device including back-side power lines and signal lines is shown according to some embodiments.

[0009] Figure 2 The layout design of a semiconductor device including back-side power lines and signal lines is shown according to some embodiments.

[0010] Figure 3A , Figure 3B and Figure 3C Various embodiments of the layout of the back-side signal lines according to some examples are shown.

[0011] Figure 4 A circuit diagram of an example AOI logic circuit according to some embodiments is shown.

[0012] Figure 5A , Figure 5B and Figure 5C The diagram shows a correspondence according to some embodiments. Figure 4 The example AOI logic circuit shows the various layout levels of the cells.

[0013] Figure 6A , Figure 6B and Figure 6C The diagram shows a correspondence according to some embodiments. Figure 4 The example AOI logic circuit shows the various layout levels of another unit.

[0014] Figure 7 The layout hierarchy of cells corresponding to the example OAI logic circuit according to some embodiments is shown.

[0015] Figure 8 The layout hierarchy of another cell corresponding to the example OAI logic circuit is shown according to some embodiments.

[0016] Figure 9 A circuit diagram of an example SDF circuit according to some embodiments is shown.

[0017] Figure 10A , Figure 10B , Figure 10C and Figure 10D The diagram shows a correspondence according to some embodiments. Figure 9 The example SDF circuit shows the various layout levels of the cells.

[0018] Figure 11 The layout hierarchy of cells corresponding to an example inverter circuit according to some embodiments is shown.

[0019] Figure 12 The layout design of a semiconductor device including multiple back-side metallization layers is shown according to some embodiments.

[0020] Figure 13 A cross-sectional view of a reference semiconductor device according to some embodiments is shown.

[0021] Figure 14 A flowchart of a method for manufacturing a semiconductor device according to some embodiments is shown.

[0022] Figure 15 A block diagram of a system for generating IC layout designs according to some embodiments is shown.

[0023] Figure 16 A block diagram of an IC manufacturing system and its associated IC manufacturing process is shown according to some embodiments.

[0024] Figure 17A flowchart illustrating an example method for manufacturing a nonplanar transistor device according to some embodiments is shown. Detailed Implementation

[0025] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the individual embodiments and / or configurations discussed.

[0026] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0027] In semiconductor IC design, the standard cell approach is commonly used to design semiconductor devices on a chip (or wafer). The standard cell approach uses standard cells as abstract representations of certain functions to integrate millions or billions of devices on a single chip. As ICs continue to scale down, more and more devices are integrated into a single chip. This scaling process typically provides benefits by increasing production efficiency and reducing associated costs.

[0028] In modern semiconductor device manufacturing processes, each unit can include a number of semiconductor devices, such as field-effect transistors (“FETs”). Non-planar transistor device architectures (such as fin-based transistors, often referred to as “FinFETs”) can offer higher device density and higher performance compared to planar transistors. Some advanced non-planar transistor device architectures (such as nanosheet (or nanowire) transistors) can further improve performance relative to FinFETs. Compared to FinFETs, where the channel is partially enclosed (e.g., spanned) by the gate structure, nanosheet transistors typically include a gate structure that can enclose the entire periphery of one or more nanosheets to improve control over channel current flow. For example, in FinFETs and nanosheet transistors of similar size, nanosheet transistors can exhibit a larger drive current (Id).on Smaller subthreshold leakage current (I) off Transistors with a gate structure that encloses their channel are typically called gate all-around (GAA) transistors or GAAFETs.

[0029] Given this gate structure enclosing the channel, at least some interconnect structures (typically formed on the front side of the chip in FinFET configurations) can be formed on the back side of the chip, which can further reduce the area of ​​the corresponding cell (e.g., cell height). However, in the prior art, those interconnect structures typically extend along a one-dimensional direction and are dedicated to serving as power rails (sometimes called power grids or power lines). This can potentially limit the flexibility and scalability of layout design for integrated circuits employing the GAA transistor architecture.

[0030] This invention provides various embodiments of semiconductor devices (or integrated circuits) that can be represented by (or formed based on) multiple standard cells. As disclosed herein, each cell includes multiple GAA transistors, and it should be understood that any of a variety of other transistor architectures that allow interconnect structures to be formed on the back side can be included in each cell. For example, the cell may include multiple transistors formed in a complementary field-effect transistor (CFET) configuration, wherein two active regions having correspondingly different conductivity types (e.g., n-type and p-type) are disposed at two vertically aligned layers.

[0031] According to various embodiments, some cells may have one or more back-side interconnect structures that allow extension in more than one direction. Such back-side interconnect structures can be configured to carry signals, not just power supply voltages (e.g., VDD, VSS). Back-side interconnect structures configured to carry signals other than power supply voltages and allowed to extend in more than one direction, as disclosed herein, are sometimes referred to as “multidimensional (MD) signal lines.” For example, some cells with relatively short cell heights may include one or more of these MD signal lines. Other back-side interconnect structures can still be configured to carry power supply voltages. Such back-side interconnect structures configured to carry power supply voltages can be allowed to extend in one direction. Back-side interconnect structures configured to carry power supply voltages and not allowed to extend in more than one direction, as disclosed herein, are sometimes referred to as “one-dimensional (SD) power lines.” For example, some cells with relatively high cell heights may include one or more of these SD power lines. The disclosed MD signal lines significantly improve the flexibility of integrated circuit design and thus further expand the scalability of integrated circuits.

[0032] Figure 1A perspective view of an example GAA FET device 100, comprising one or more multidimensional (MD) signal lines and one or more one-dimensional (SD) power lines according to various embodiments, is shown. It should be noted that... Figure 1 The illustrated GAA FET device 100 is inverted, such that the MD signal line and SD power line are positioned on top of the formed GAA transistor. For example, the GAA FET device 100 includes multiple semiconductor layers (e.g., nanosheets, nanowires, or other nanostructures) 102 perpendicularly spaced from each other, which can collectively serve as a (conductive) channel for the GAA FET device 100. The channel can extend along a first direction (e.g., the X-axis). The GAA FET device 100 includes a (e.g., metal) gate structure 104 that encloses each semiconductor layer 102 (e.g., the outer periphery of each semiconductor layer 102). The gate structure 104 can extend along a second direction perpendicular to the first direction (e.g., the Y-axis). The GAA FET device 100 includes source / drain structures disposed on opposite sides of the gate structure 104 (along the extension direction of the channel), such as one of such source / drain structures 106, as... Figure 1 As shown. When viewed upside down. Figure 1 In this case, the GAA FET device 100 includes an interlayer dielectric (ILD) 108 located above the source / drain structure 106.

[0033] On the back side of the GAA FET device 100 (e.g., Figure 1 Above the top (of the image), an SD power line 110 and an MD signal line 112 are shown. The SD power line 110 may extend along the X-axis. The MD signal line 112 may include multiple portions, one or more of which may extend along the X-axis, and one or more of which may extend along the Y-axis. As will be discussed (and shown) below, the SD power line 110, configured to carry a power supply voltage (e.g., VDD, VSS), may be electrically coupled to one or more source / drain structures via one or more back-side via structures. This power supply voltage is sometimes referred to as a power signal. The MD signal line 112, configured to carry a signal other than a power supply voltage, may be electrically coupled to one or more source / drain structures via one or more back-side via structures. Such a signal other than a power supply voltage is sometimes referred to as a non-power supply signal.

[0034] Simplified Figure 1 The GAA FET device shown is an example of a device that may not contain one or more components of a complete GAA FET device. Figure 1As shown in the diagram. For example, the gate structure 104 is not shown in the diagram. Other examples include the gate spacer between the gate structure 104 and the source / drain structure 106, the internal spacer between the source / drain structure 106 and each semiconductor layer 102, and the back-side via structure connecting the MD signal line / SD power line. Figure 1 As shown in the image. Furthermore, it should be understood that... Figure 1 The spatial arrangement of the SD power line 110, MD signal line 112 and other structures of the GAA FET device 100 shown is provided for illustrative purposes and should not be limited thereto.

[0035] Figure 2 Example layout designs 200 according to various embodiments of the present invention are shown. Layout design 200 can be used to fabricate at least a portion of a semiconductor device (e.g., an integrated circuit having multiple circuits operatively coupled to each other). However, not all components shown are necessary, and some embodiments of the invention may include... Figure 2 Additional components are not shown. The arrangement and type of components may be changed without departing from the scope of the invention set forth herein. Additional, different, or fewer components may be included.

[0036] Semiconductor devices corresponding to layout design 200 can be fabricated based on forming multiple transistor components / structures (e.g., channel structures, source structures, drain structures) along one or more active regions above the front side of a substrate. Although Figure 2 The layout design 200 includes multiple patterns to form multiple parts / structures respectively on the back side of the substrate. Therefore, it should be understood that the layout design 200 may also include multiple patterns to form multiple parts / structures respectively on the front side of the substrate, as will be discussed below. It should be noted that the layout design 200 is viewed from its back side; therefore, in… Figure 2 In the middle, the pattern forming the back side component / structure is located on top of the pattern to form the front side component / structure.

[0037] Layout design 200 includes multiple cell rows 201 and 203, which are arranged (e.g., layout) relative to a space, grid, or planar arrangement for a design of an integrated circuit. In some embodiments, such a planar arrangement may correspond to a substrate for fabricating a semiconductor device. The cell rows of layout design 200 may have at least two corresponding different row heights, cell heights, or heights. As shown, cell row 201 may have a first row height, and cell row 203 may have a second row height, wherein the first row height is greater than the second row height. As a non-limiting example, the first row height may be between about 10 nanometers (nm) and about 85 nm, and the second row height may be between about 10 nm and about 40 nm. Hereinafter, cell row 201 and cell row 203 may sometimes be referred to as a high cell (TC) row and a short cell (SC) row, respectively. The row height may correspond to the cell height of the cell (sometimes called a standard cell) to be placed therein. Figure 2 In the example shown, cell rows 201 and 203 are arranged alternately, but it should be understood that cell rows with different row heights can be arranged in any of a variety of other configurations (e.g., two SC rows adjacent to one TC row) while still within the scope of the invention.

[0038] Each TC / SC row includes a plurality of active region patterns extending along the X-axis. As a non-limiting example, TC row 201 includes active region patterns 202 and 204, and SC row 203 includes active region patterns 206 and 208. Each of the active region patterns 202, 204, 206, and 208 is configured to form an active region over a substrate, and is hereinafter referred to as "active region 202", "active region 204", "active region 206", and "active region 208", respectively. In some embodiments, active regions 202 to 208 are formed over the front side of the substrate.

[0039] The active regions in each cell row can be characterized by opposite conductivity types. For example, in TC row 201, active region 202 can be characterized by a first conductivity type (e.g., n-type), while active region 204 can be characterized by a second conductivity type (e.g., p-type); and in SC row 203, active region 206 can be characterized by a first conductivity type (e.g., p-type), and active region 208 can be characterized by a second conductivity type (e.g., n-type).

[0040] In a non-limiting example of layout design 200 for forming a GAA FET, active region 202 may include one or more nanosheets stacked on top of each other over a substrate to form a plurality of n-type transistors; active region 204 may include one or more nanosheets stacked on top of each other over a substrate to form a plurality of p-type transistors; active region 206 may include one or more nanosheets stacked on top of each other over a substrate to form a plurality of p-type transistors; and active region 208 may include one or more nanosheets stacked on top of each other over a substrate to form a plurality of n-type transistors.

[0041] In one embodiment, the cell height may correspond to the width along the Y-axis of the active regions included therein. For example, rows SC and TC may each have multiple active regions, wherein the active regions of row TC have a wider width than the active regions of row SC. In another embodiment, the cell height may correspond to the number of bottommost interconnect structures (e.g., M0 tracks) disposed therein (as will be discussed below). For example, rows SC and TC may each have multiple M0 tracks, wherein the number of M0 tracks in row TC is greater than the number of M0 tracks in row SC. In yet another embodiment, the cell height may correspond to the number of active regions included therein. For example, rows SC may have a smaller number of active regions, while rows TC may have a larger number of active regions.

[0042] According to various embodiments of the present invention, each TC row may include a plurality of first patterns extending along the X-axis to form a first interconnect structure on the back side; each SC row may include a plurality of second patterns to form a second interconnect structure on the back side, each second interconnect structure being formed as a pad adjacent to one of the first interconnect structure patterns in the TC row; and each SC row may further include a plurality of third patterns to form a third interconnect structure on the back side. Some of the third interconnect structure patterns may have multiple portions, some of which extend along the X-axis and some of which extend along the Y-axis.

[0043] As Figure 2In an illustrative example, TC row 201 includes interconnect structure patterns 210 and 212 extending along the X-axis. In some embodiments, interconnect structure patterns 210 and 212 may almost completely span the planar extension of layout design 200. Therefore, interconnect structure patterns 210 and 212 may completely overlap with active regions (patterns) 202 and 204, respectively. SC row 203 includes interconnect structure patterns 214 and 216 formed as pads or segments, and interconnect structure pattern 218 having portions extending along the X-axis and portions extending along the Y-axis. In some embodiments, interconnect structure patterns 214 and 216 may not completely span the planar extension of the layout design. Specifically, interconnect structure patterns 214 and 216 may be adjacent to one of the fully extending interconnect structure patterns 210 and 212 in adjacent TC rows. In some embodiments, interconnect structure pattern 218 may not completely span the planar extension of the layout design. Therefore, interconnection structure patterns 214 and 216 may partially overlap with active regions (patterns) 206 and 208, respectively, and interconnection structure pattern 218 may partially overlap with both active regions (patterns) 206 and 208. Specifically, interconnection structure pattern 218 may include features that can... Figure 3A The three parts 218A, 218B and 218C are better seen in the middle.

[0044] exist Figure 3A In this configuration, portion 218A extends a distance along the X-axis (e.g., less than the width of the plane along the X-axis). Portion 218C extends a distance along the X-axis (e.g., less than the width of the plane along the X-axis) and is laterally offset from portion 218A along the X-axis. In some embodiments, portions 218A and 218C may overlap with active regions 206 and 208, respectively. Portion 218B, having its ends connected to portions 218A and 218C, extends along the Y-axis. Thus, each of portions 218A and 218C, together with portion 218B, can form an L-shaped profile. By extending in a direction different from the extending direction of active regions 206 and 208, portion 218B can couple active regions 206 and 208 to each other via a plurality of through-hole structures 219 (discussed below).

[0045] Figure 3B and Figure 3C Other embodiments of the interconnect structure pattern 218 are depicted respectively. Figure 3B In this configuration, the interconnect structure pattern 218 extends along the Y-axis to overlap with portions of active region 206 and active region 208, thereby coupling active regions 206 and 208 to each other through multiple via structures 219 (discussed below). Figure 3CIn this embodiment, the interconnect structure pattern 218 extends along the direction between the X and Y axes to overlap with portions of active region 206 and active region 208, thereby coupling active regions 206 and 208 to each other through a plurality of via structures 219 (discussed below). In such an embodiment, the interconnect structure pattern 218 may be tilted relative to the edge of either active region 206 or 208.

[0046] Refer again Figure 2 Each of interconnect structure patterns 210 and 212 is configured to form a first type of SD power line (hereinafter referred to as "SD power line 210" and "SD power line 212") above the back side of the substrate; each of interconnect structure patterns 214 and 216 is configured to form a second type of SD power line (hereinafter referred to as "SD power line 214" and "SD power line 216") above the back side of the substrate; and interconnect structure pattern 218 is configured to form an MD signal line of the disclosed type (hereinafter referred to as "MD signal line 218") above the back side of the substrate.

[0047] As described above, each of the SD power lines and MD signal lines can be coupled to an active region via a via structure (e.g., electrically). Figure 2 As shown, the layout design 200 may include a plurality of patterns 219 configured to form a via structure (hereinafter referred to as "via structure 219"). In some embodiments, the via structure 219 is formed on the back side of the substrate to electrically couple each of the SD power lines and MD signal lines to one or more portions of a corresponding active region.

[0048] For example, SD power line 210 can be electrically coupled to active region 202 through multiple via structures 219 (e.g., 219-1); SD power line 212 can be electrically coupled to active region 204 through multiple via structures 219 (e.g., 219-2); SD power line 214 can be electrically coupled to active region 206 through multiple via structures 219 (e.g., 219-3); SD power line 216 can be electrically coupled to active region 208 through multiple via structures 219 (e.g., 219-4); and MD signal line 218 can be electrically coupled to active regions 206 and 208 respectively through multiple via structures (e.g., via structures 219-5 and 219-6).

[0049] Layout design 200 may include multiple cells arranged above one or more cell rows. For example, in Figure 2In this layout design 200, there are units 220, 230, 240, 250, 260, 270, 280, and 290. Unit 220 is arranged above a single unit row (e.g., one SC row 203); unit 230 is arranged above a single unit row (e.g., one SC row 203); unit 240 is arranged above a single unit row (e.g., one SC row 210); unit 250 is arranged above three unit rows (e.g., two TC rows 201 and one SC row 203); unit 260 is arranged above two unit rows (e.g., one TC row 201 and one SC row 203); unit 270 is arranged above a single unit row (e.g., one SC row 203); unit 280 is arranged above a single unit row (e.g., one SC row 203); and unit 290 is arranged above a single unit row (e.g., one TC row 201).

[0050] Each unit can correspond to a circuit (e.g., a logic gate, a logic circuit). For example, unit 220 can correspond to a single-stage inverter; unit 230 can correspond to a multi-stage NAND gate; unit 240 can correspond to a multi-stage inverter; unit 250 can correspond to another multi-stage inverter; unit 260 can correspond to a flip-flop circuit; unit 270 can correspond to an AND-OR-NOT (AOI) logic circuit; unit 280 can correspond to an OR-AND-NOT (OAI) logic circuit; and unit 290 can correspond to another AND-OR-NOT (AOI) logic circuit.

[0051] Each cell may correspond to at least one layout having multiple patterns overlapping the active regions in the corresponding cell row. Some patterns may be configured to form components / structures on the front side of the substrate (referred to herein as "front-side patterns"), while some patterns may be configured to form components / structures on the back side of the substrate (referred to herein as "back-side patterns"). The layout of each cell occupying a portion of the footprint area of ​​the layout design 200 can therefore have Figure 2 A portion of one or more patterns shown.

[0052] In the following discussion, cell 260 (corresponding to a flip-flop circuit placed above a row of SC and a row of TC), cell 270 (corresponding to an AOI logic circuit placed above a row of SC), and cell 290 (corresponding to an AOI logic circuit placed above a row of TC) are selected as representative examples to illustrate their respective front-side and back-side patterns, while cell 250 (corresponding to a multi-stage inverter) and cell 280 (corresponding to an OAI logic circuit placed above a row of SC) are selected as representative examples to illustrate their respective back-side patterns.

[0053] refer to Figure 4The diagram depicts a circuit diagram of example circuit 400. Circuit 400 includes AND-OR-NOT (AOI) logic circuitry. AOI logic circuitry typically consists of a combination of one or more AND gates and one NOR gate. Figure 4 As shown, circuit 400 has four inputs: A1, A2, B1, and B2; and one output ZN, configured to execute the following Boolean function: To perform this function, circuit 400 may include eight transistors 402, 404, 406, 408, 410, 412, 414, and 416 electrically coupled to each other and located between supply voltages VDD and VDD. Each of transistors 402 to 408 may be implemented as a p-type transistor; and each of transistors 410 to 416 may be implemented as an n-type transistor. However, it should be understood that each of transistors 402 to 416 may be implemented as any of a variety of other transistors of conductivity type.

[0054] Figures 5A to 5B and Figure 5C This shows the AOI logic circuit 400 corresponding to the one to be placed above row 203 of SC (SMS cell). Figure 4 ) units (e.g., Figure 2 The layout design of unit 270) is 500. Figures 6A to 6B and Figure 6C This shows the AOI logic circuit 400 corresponding to the one to be placed above row 201 of TC (high cell). Figure 4 ) units (e.g., Figure 2 The layout design of unit 290) is 600.

[0055] Figures 5A to 5C The layout design 500 depicts the various layout levels of cell 270, wherein two layout levels include patterns of structures / components formed on the front side of the substrate, and one layout level includes patterns of structures / components formed on the back side of the substrate. Similarly, Figures 6A to 6C The layout design 600 depicts the various layout levels of cell 290, wherein two layout levels include patterns of structures / components formed on the front side of the substrate, and one layout level includes patterns of structures / components formed on the back side of the substrate. It should be noted that... Figures 5A to 5C and Figures 6A to 6C The layout designs shown 500 and 600 are viewed from their tops, therefore, in Figures 5A to 5C and Figures 6A to 6C In the middle, the pattern forming the front part / structure is located on top of the pattern to form the back part / structure.

[0056] First refer to Figure 5AThe diagram illustrates a first layout layer 500A of a layout design 500 according to various embodiments, the first layout layer 500A including multiple patterns forming multiple active regions and multiple interconnect structures on the front side of a substrate.

[0057] As shown in the figure, the first layout level 500A includes active regions (patterns) 206 and 208, wherein multiple patterns 501A, 501B, 501C, 501D, 501E, and 501F extend along the Y-axis to span the active regions 206 and 208. Patterns 501A to 501F are configured to form gate structures, hereinafter referred to as "gate structure 501A", "gate structure 501B", "gate structure 501C", "gate structure 501D", "gate structure 501E", and "gate structure 501F", respectively. Gate structure 501A may be disposed along or above a first boundary of layout design 500 (or cell), and gate structure 501F may be disposed along or above a second boundary of layout design 500 (or cell). Gate structures 501A and 501F may not provide electrical or conductive paths and may prevent or at least reduce / minimize current leakage across components, and gate structures 501A and 501F are located between components. Gate structures 501A and 501F may include pseudo-polysilicon lines, sometimes referred to as PODEs. Each of the remaining gate structures 501B to 501E, formed of one or more conductive materials (e.g., polysilicon, metal), may be located above corresponding portions of active regions 206 and 208 to define one or more of transistors 402-416 (e.g.,...). Figure 4 (As shown). As a representative example, the gate structure 501B can define the gate of the transistor 412, and portions of the active region 208 disposed on the left-hand and right-hand sides of the gate structure 501B can respectively define the source and drain of the transistor 412.

[0058] The first layout level 500A includes patterns 502A, 502B, 502C, 502D, 502E, 502F, 502G, 502H, 502I, and 502J. Each of patterns 502A to 502J may extend along the Y direction and is configured to form a source / drain interconnect structure (e.g., MD), hereinafter referred to as "MD 502A", "MD 502B", "MD 502C", "MD 502D", "MD 502E", "MD 502F", "MD 502G", "MD 502H", "MD 502I", and "MD 502J". Each of MD 502A to 502J may be electrically coupled to the source or drain of the corresponding transistor.

[0059] The first layout level 500A includes patterns 503A, 503B, 503C, 503D, 503E, 503F, 503G, and 503H. Patterns 503A to 503H can be configured to form through-hole interconnect structures (e.g., VD), hereinafter referred to as "VD 503A", "VD 503B", "VD 503C", "VD 503D", "VD 503E", "VD 503F", "VD 503G", and "VD 503H". Each of VD 503A to 503H can extend a corresponding height along a vertical direction (e.g., a direction perpendicular to the X and Y axes) to electrically couple the corresponding MD to the interconnect structure.

[0060] The first layout level 500A includes patterns 504A, 504B, 504C, and 504D. Patterns 504A to 504D can be configured to form via interconnect structures (e.g., VG), hereinafter referred to as "VG504A", "VG504B", "VG504C", and "VG504D". Each of VG504A to 504D can extend a corresponding height along a vertical direction (e.g., a direction perpendicular to the X and Y axes) to electrically couple the corresponding gate structure to the interconnect structure.

[0061] The first layout layer 500A includes patterns 505A, 505B, 505C, 505D, and 505E. Each of patterns 505A to 505E may extend along the X-axis and is configured to form an interconnect structure in the bottommost metallization layer (e.g., the M0 layer) above the front side of the substrate. Patterns 505A to 505E are referred to herein as “M0 track 505A”, “M0 track 505B”, “M0 track 505C”, “M0 track 505D”, and “M0 track 505E”, respectively.

[0062] In some embodiments, an M0 track 505A, positioned along or above the third boundary of the layout design (cell), can be configured to carry a power supply voltage (e.g., VDD) and serve as a shielded metal track. An M0 track 505E, positioned along or above the fourth boundary of the layout design (cell), can be configured to carry a power supply voltage (e.g., VSS) and serve as a shielded metal track. In some embodiments, such a shielded metal track may not be connected to any active area. Figure 4 As shown in the diagram, some M0 tracks can be "cut" into multiple parts by one or more M0 cutting patterns. For example, M0 track 505B can be cut into multiple parts by cutting patterns 506A and 506C; and M0 track 505C can be cut into multiple parts by cutting pattern 506B.

[0063] Next reference Figure 5BAccording to various embodiments, a second layout level 500B of layout design 500 is shown, the second layout level 500B including multiple patterns to form multiple interconnect structures on the front side of the substrate. For reference purposes, M0 orbitals 505A to 505E ( Figure 5A Again in Figure 5B As shown in the image.

[0064] The second layout layer 500B includes patterns 506A, 506B, 506C, 506D, and 506E. Each of patterns 506A to 506E may extend along the Y-axis and be configured to form an interconnect structure at the next upper metallization layer (e.g., M1 layer). Patterns 506A to 506E are referred to herein as “M1 track 506A”, “M1 track 506B”, “M1 track 506C”, “M1 track 506D”, and “M1 track 506E”, respectively.

[0065] Each of the M1 rails 506A to 506E can be electrically coupled to at least one M0 rail via a through-hole structure (e.g., V0) to receive one of inputs A1, A2, B1, and B2. Figure 4 ), or provide output ZN ( Figure 4 For example, track M1 506A is electrically coupled to a cut portion of track M0 505B via through-hole structure 507A (hereinafter "V0 507A") to receive input A2; track M1 506B is electrically coupled to a cut portion of track M0 505C via through-hole structure 507B (hereinafter "V0 507B") to receive input A1; track M1 506C is electrically coupled to a cut portion of track M0 505B via through-hole structure 507C (hereinafter "V0 507C") to provide output ZN; track M1 506D is electrically coupled to a cut portion of track M0 505C via through-hole structure 507D (hereinafter "V0 507D") to receive input B1; and track M1 506E is electrically coupled to a cut portion of track M0 505B via through-hole structure 507E (hereinafter "V0 507E") to receive input B2.

[0066] Then refer to Figure 5C According to various embodiments, a third layout level 500C of layout design 500 is shown, the third layout level 500C including multiple patterns to form multiple interconnect structures on the back side of a substrate. For reference, in Figure 5C The image again shows the formation on the front side ( Figure 5A The gate structures 501A to 501F and active regions 206 to 208 on the device.

[0067] The third layout layer 500C includes patterns 508, 510, 512, and 514. Each of patterns 508, 510, and 514 can be an example of interconnect structure pattern 214 or 216; and pattern 512 can be... Figure 2 An example of interconnect structure pattern 218 is shown. Each of patterns 508 to 514 can be configured to form an interconnect structure at the bottommost metallization layer (e.g., a BMO layer) above the back side of the substrate. Patterns 508 to 514 are referred to herein as “BM0 track 508”, “BM0 track 510”, “BM0 track 512”, and “BM0 track 514”, respectively. In some embodiments, each of BMO tracks 508 and 514 can carry a first power supply voltage (e.g., VSS), and BMO track 510 can carry a second power supply voltage (e.g., VDD), while BMO track 512 can carry a signal other than any power supply voltage. Each of BMO tracks 508, 510, and 514 can be an implementation of SD power lines 214 or 216, and BMO track 512 can be an implementation of MD signal line 218, as per [reference to...]. Figure 2 The layout design of 200 is discussed.

[0068] The BM0 track 508 can be electrically coupled to a portion of the active region 208 (e.g., via a back-side via structure (hereinafter "BV0 513A") formed by pattern 513A) (e.g., Figure 4 The source of transistor 412); the BVO track 510 can be electrically coupled to a portion of the active region 206 (e.g., the source of transistor 412); the BVO track 510 can be electrically coupled to a portion of the active region 206 (e.g., the source of transistor 412) through a back-side via structure (hereinafter “BVO 513B”) formed by pattern 513B. Figure 4 The respective sources of transistors 402 and 406); and the BVO track 514 can be electrically coupled to a portion of the active region 208 (e.g., via a back-side via structure (hereinafter "BVO 513E") formed by pattern 513E. Figure 4 (The source of transistor 416). Therefore, depending on the circuit design, each of the BMO tracks 508, 510, and 514 can transmit or otherwise provide VDD or VSS to the corresponding node.

[0069] The BM0 track 512 can utilize a portion of the active region 208 (e.g., as shown in the image) through a back-side via structure formed by pattern 513C (hereinafter "VB513C") and a back-side via structure formed by pattern 513D (hereinafter "VB513D"). Figure 4 The corresponding drains of transistors 410 and 414 shown are electrically coupled to portions of the active region 206 (e.g., as shown in the diagram). Figure 4(The corresponding drains of transistors 404 and 408 are shown). Specifically, the BMO track 512 has three portions 512A, 512B, and 512C. Portion 512A overlaps with active region 208 by extending in the same direction, while VB 513C is further disposed between active region 208 and portion 512A; and portion 512C overlaps with active region 206 by extending in the same direction, while VB 513D is further disposed between active region 206 and portion 512C. Depending on the circuit design, portion 512B extends in a different direction and can connect portions 512A and 512C to couple the corresponding (internal) nodes to each other.

[0070] Now for reference Figure 6A The diagram illustrates a first layout layer 600A of a layout design 600 according to various embodiments, the first layout layer 600A including multiple patterns to form multiple active regions and multiple interconnect structures on the front side of a substrate.

[0071] As shown in the figure, the first layout level 600A includes active regions (patterns) 202 and 204, wherein multiple patterns 601A, 601B, 601C, 601D, 601E, and 601F extend along the Y-axis to span the active regions 202 and 204. Patterns 601A to 601F are configured to form gate structures, hereinafter referred to as "gate structure 601A", "gate structure 601B", "gate structure 601C", "gate structure 601D", "gate structure 601E", and "gate structure" 601F, respectively. Gate structure 601A may be disposed along or above a first boundary of layout design 600 (or cell), and gate structure 601F may be disposed along or above a second boundary of layout design 600 (or cell). Gate structure 601A Gate structures 601A and 601F may not provide an electrical or conductive path and may prevent or at least reduce / minimize current leakage across the component. Gate structures 601A and 601F are located between the components. Gate structures 601A and 601F may include pseudo-polysilicon lines, sometimes referred to as PODEs. Each of the remaining gate structures 601B to 601E, formed of one or more conductive materials (e.g., polysilicon, metal), may be located above the corresponding portions of active regions 202 and 204 to define one or more of transistors 402-416 (e.g., ...). Figure 4 As shown in the figure, as a representative example, the gate structure 601B can define the gate of the transistor 412, and portions of the active region 204 disposed on the left-hand side and the right-hand side of the gate structure 601B can respectively define the source and drain of the transistor 412.

[0072] The first layout layer 600A includes patterns 602A, 602B, 602C, 602D, 602E, 602F, 602G, 602H, 602I, and 602J. Each of patterns 602A to 602J may extend along the Y direction and is configured to form a source / drain interconnect structure (e.g., MD), hereinafter referred to as "MD 602A", "MD 602B", "MD 602C", "MD 602D", "MD 602E", "MD 602F", "MD 602G", "MD 602H", "MD 602I", and "MD 602J". Each of MD 602A to 602J may be electrically coupled to the source or drain of a corresponding transistor.

[0073] The first layout layer 600A includes patterns 603A, 603B, 603C, 603D, 603E, 603F, 603G, and 603H. Patterns 603A to 603H can be configured to form via interconnect structures (e.g., VDs), hereinafter referred to as "VD 603A", "VD 603B", "VD 603C", "VD 603D", "VD 603E", "VD 603F", "VD 603G", and "VD 603H". Each of VDs 603A to 603H can extend a corresponding height along a vertical direction (e.g., a direction perpendicular to the X and Y axes) to electrically couple the corresponding MD to the interconnect structure.

[0074] The first layout level 600A includes patterns 604A, 604B, 604C, and 604D. Patterns 604A to 604D can be configured to form via interconnect structures (e.g., VG), hereinafter referred to as "VG 604A", "VG 604B", "VG 604C", and "VG 604D". Each of VG 604A to 604D can extend a corresponding height along a vertical direction (e.g., a direction perpendicular to the X and Y axes) to electrically couple the corresponding gate structure to the interconnect structure.

[0075] The first layout layer 600A includes patterns 605A, 605B, 605C, 605D, 605E, and 605F. Each of patterns 605A to 605F may extend along the X-axis and be configured to form an interconnect structure in the bottommost metallization layer (e.g., M0 layer) above the front side of the substrate. Patterns 605A to 605F are referred to herein as "M0 track 605A", "M0 track 605B", "M0 track 605C", "M0 track 605D", "M0 track 605E", and "M0 track 605F", respectively.

[0076] In some embodiments, an M0 track 605A, positioned along or above the third boundary of the layout design (cell), can be configured to carry a power supply voltage (e.g., VDD) and serve as a shielded metal track. An M0 track 605F, positioned along or above the fourth boundary of the layout design (cell), can be configured to carry a power supply voltage (e.g., VSS) and serve as a shielded metal track. In some embodiments, such a shielded metal track may not be connected to any active area. Figure 4 As shown, in order to connect transistors, some M0 tracks can be "cut" into multiple parts by one or more M0 cutting patterns. For example, M0 tracks 605C and 605E can be cut into multiple parts by cutting pattern 606A, respectively; M0 track 605D can be cut into multiple parts by cutting pattern 606B; and M0 track 605E can be cut into multiple parts by cutting pattern 606C.

[0077] Next reference Figure 6B This illustrates a second layout level 600B of a layout design 600 according to various embodiments, the second layout level 600B including multiple patterns to form multiple interconnect structures on the front side of a substrate. For reference purposes, M0 tracks 605A to 605F ( Figure 6A Again in Figure 6B As shown in the image.

[0078] The second layout layer 600B includes patterns 606A, 606B, 606C, 606D, and 606E. Each of patterns 606A to 606E may extend along the Y-axis and be configured to form an interconnect structure at the next upper metallization layer (e.g., M1 layer). Patterns 606A to 606E are referred to herein as “M1 track 606A”, “M1 track 606B”, “M1 track 606C”, “M1 track 606D”, and “M1 track 606E”, respectively.

[0079] Each of the M1 rails 606A to 606E can be electrically coupled to at least one M0 rail via a through-hole structure (e.g., V0) to receive one of inputs A1, A2, B1, and B2. Figure 4 ), or provide output ZN ( Figure 4For example, track M1 606A is electrically coupled to the cut portion of track M0 605C via through-hole structure 607A (hereinafter "V0 607A") to receive input A2; track M1 606B is electrically coupled to the cut portion of track M0 605D via through-hole structure 607B (hereinafter "V0 607B") to receive input A1; track M1 606C is electrically coupled to the cut portions of track M0 605C and track M0 605E via through-hole structures 607C (hereinafter "V0 607C") and 607D (hereinafter "V0 607D") respectively to provide output ZN; track M1 606D is electrically coupled to the cut portion of track M0 605C via through-hole structure 607E (hereinafter "V0 607D"). The M1 track 606E is electrically coupled to the cut portion of the M0 track 605D to receive input B1; and the M1 track 606E is electrically coupled to the cut portion of the M0 track 605B through the through-hole structure 607F (hereinafter referred to as "V0 607F") to receive input B2.

[0080] Then refer to Figure 6C This illustrates a third layout level 600C of a layout design 600 according to various embodiments, the third layout level 600C including multiple patterns to form multiple interconnect structures on the back side of a substrate. For reference purposes, Figure 6C The middle section again shows the formation on the front side ( Figure 6A The gate structures 601A to 601F and active regions 202 to 204 on the )

[0081] The third layout layer 600C includes patterns 608 and 610. Each of patterns 608 and 610 may be an example of a portion of the interconnect structure pattern 210 or 212, such as... Figure 2 As shown. Each of patterns 608 and 610 can be configured to form an interconnect structure at the bottommost metallization layer (e.g., a BMO layer) above the back side of the substrate. Patterns 608 to 610 are referred to herein as "BMO track 608" and "BMO track 610," respectively. In some embodiments, BMO track 608 can carry a first power supply voltage (e.g., VDD), and BMO track 610 can carry a second power supply voltage (e.g., VSS). Each of BMO tracks 608 and 610 can be an implementation of SD power lines 210 or 212, as described regarding Figure 2 The layout design of 200 is discussed.

[0082] BM0 track 608 can be electrically coupled to a portion of active region 204 (e.g., via a back-side via structure (hereinafter "VB613A") formed by pattern 613A) (e.g., Figure 4The respective sources of transistors 402 and 406); and the BMO track 610 can be electrically coupled to a portion of the active region 202 (e.g., via a back-side via structure (hereinafter "VB 613B") formed by pattern 613B. Figure 4 The source of transistor 412, and electrically coupled to a portion of active region 202 (e.g., via a back-side via structure (hereinafter "VB613C") formed by pattern 613C) Figure 4 (The source of transistor 416). Therefore, depending on the circuit design, each of the BM0 tracks 608 and 610 can transmit VDD or VSS or otherwise provide it to the corresponding node.

[0083] Figure 7 The cell corresponding to the OAI logic circuit to be placed above row 203 of SC (SMS cell) is shown (e.g., Figure 2 The layout design of unit 290) is 700. Figure 8 The layout design 800 of the cells corresponding to the OAI logic circuit to be placed above row 201 of TC (high cell) is shown. The OAI logic circuit is similar to that of... Figure 4 The AOI logic circuit discussed, apart from replacing the internal connections between p-type transistors with internal connections between n-type transistors, can essentially maintain the same pattern to form the front-side structure / components. Therefore, in Figure 7 and Figure 8 In the layout designs 700 and 800, each includes a layout hierarchy showing a pattern forming a back-side interconnect structure, while patterns for forming active regions and gate structures on the front side are also present for reference.

[0084] First refer to Figure 7 With active regions 206-208 and gate structures 701A to 701F present, the layout design (hierarchy) 700 includes patterns 702, 704, 706, and 708. Each of patterns 702, 704, and 708 may be an example of interconnect structure pattern 214 or 216; and pattern 706 may be... Figure 2An example of interconnect structure pattern 218 is shown. Each of patterns 702 to 708 can be configured to form an interconnect structure at the bottommost metallization layer (e.g., BMO layer) above the back side of the substrate. Patterns 702 to 708 are referred to herein as “BM0 track 702”, “BM0 track 704”, “BM0 track 706”, and “BM0 track 708”, respectively. In some embodiments, BMO track 702 can carry a first power supply voltage (e.g., VSS), and each of BMO tracks 704 and 708 can carry a second power supply voltage (e.g., VDD), while BMO track 706 can carry a signal other than any power supply voltage. Each of BMO tracks 702, 704, and 708 can be an implementation of SD power lines 214 or 216, and BMO track 706 can be an implementation of MD signal line 218, as per [reference to...]. Figure 2 The layout design of 200 is discussed.

[0085] BM0 track 702 can be electrically coupled to a portion of active region 208 via a back-side via structure (hereinafter “VB 709A”) formed by pattern 709A; BM0 track 704 can be electrically coupled to a portion of active region 206 via a back-side via structure (hereinafter “VB709B”) formed by pattern 709B; and BM0 track 708 can be electrically coupled to a portion of active region 206 via a back-side via structure (hereinafter “VB 709E”) formed by pattern 709E. Therefore, depending on the circuit design, each of BM0 tracks 702, 704, and 708 can transmit or otherwise provide VDD or VSS to the corresponding node.

[0086] BM0 track 706 can electrically couple a portion of active region 206 to a portion of active region 208 via a back-side via structure formed by pattern 709C (hereinafter “VB 709C”) and a back-side via structure formed by pattern 709D (hereinafter “VB 709D”). Specifically, BM0 track 706 has three portions 706A, 706B, and 706C. Portion 706A overlaps with active region 208 by extending in the same direction, and VB 709D is further disposed between active region 208 and portion 706A; and portion 706C overlaps with active region 206 by extending in the same direction, and VB 709C is further disposed between active region 206 and portion 706C. Depending on the circuit design, portion 706B extends in a different direction and can connect portions 706A and 706C to couple the corresponding (internal) nodes to each other.

[0087] Then refer to Figure 8There are active regions 202-204 and gate structures 801A to 801F. The layout design (layer) 800 includes patterns 802 and 804. Each of patterns 802 and 804 can be... Figure 2 Examples of portions of interconnect structure patterns 210 or 212 are shown. Each of patterns 802 and 804 can be configured to form an interconnect structure at the bottommost metallization layer (e.g., a BMO layer) above the back side of the substrate. Patterns 802 and 804 are referred to herein as “BMO track 802” and “BMO track 804”, respectively. In some embodiments, BMO track 802 can carry a first power supply voltage (e.g., VDD), and BMO track 804 can carry a second power supply voltage (e.g., VSS). Each of BMO tracks 802 and 804 can be an implementation of SD power lines 210 or 212, as described above. Figure 2 The layout design of 200 is discussed.

[0088] BM0 track 802 can be electrically coupled to a portion of active region 204 via a back-side via structure (hereinafter "VB 805A") formed by pattern 805A, and to a portion of active region 204 via a back-side via structure (hereinafter "VB 805C") formed by pattern 805C; and BM0 track 804 can be electrically coupled to a portion of active region 202 via a back-side via structure (hereinafter "VB 805B") formed by pattern 805B. Therefore, depending on the circuit design, each of BM0 tracks 802 and 804 can transmit or otherwise provide VDD or VSS to the corresponding node.

[0089] refer to Figure 9 The diagram depicts a circuit diagram of example circuit 900. Circuit 900 includes a scan D flip-flop circuit, or a D flip-flop circuit with a scan input (hereinafter referred to as an "SDF" circuit). An SDF circuit is typically composed of a combination of multiple transistors, such as... Figure 9 As shown. The SDF circuit includes a D flip-flop with a multiplexer (MUX), one input of which serves as the function input "D", and the other input as the "scan input (SI)". A "scan / test enable (SE / TE)" is used to control the selection bit of the MUX. Additionally, a clock signal is fed in through the input "CP", and the SDF circuit has an output "Q". To perform the function of the SDF circuit (e.g., allowing its inputs to be from selectable sources of D flip-flops), the transistors are electrically coupled to each other and located between the supply voltages VDD and VDD. Figure 9 As shown, some transistors can be implemented as p-type transistors, while others can be implemented as n-type transistors. However, it should be understood that each transistor can be implemented as any of a variety of other conduction types.

[0090] Figure 10A , Figure 10B , Figure 10C and Figure 10D The diagram shows the SDF circuit 900 corresponding to the row 203 of SC (short cells) and the row 201 of TC (high cells). Figure 9 ) units (e.g., Figure 2 The layout design of unit 260) is 1000. Figures 10A to 10D The layout design depicts the various layout levels of cell 260, where three layout levels include patterning of structures / components on the front side of the substrate, and one layout level includes patterning of structures / components on the back side of the substrate. It should be noted that... Figure 10A The layout designs shown 1000 are viewed from their tops, therefore, in Figures 10A to 10D In the middle, the pattern forming the front part / structure is located on top of the pattern to form the back part / structure.

[0091] First refer to Figure 10A The diagram illustrates a first layout layer 1000A of a layout design 1000 according to various embodiments. The first layout layer 1000A includes multiple patterns to form multiple active regions and multiple interconnect structures on the front side of a substrate.

[0092] As shown in the figure, the first layout layer 1000A includes active regions (patterns) 202-204 (of the high cell row 201) and 206-208 (of the short cell row 203), wherein multiple patterns 1001A, 1001B, 1001C, 1001D, 1001E, 1001F, 1001G, 1001H, 1001I, 1001J and 1001K extend along the Y-axis to span active regions 202 to 208. Patterns 1001A to 1001K are configured to form gate structures, hereinafter referred to as "gate structure 10A", "gate structure 1001B", "gate structure 1001C", "gate structure 1001D", "gate structure 1001E", "gate structure 1001F", "gate structure 1001G", "gate structure 1001H", "gate structure 1001I", "gate structure 1001J" and "gate structure 1001K".

[0093] Gate structure 1001A may be disposed along or above a first boundary of layout design 1000 (or cell), and gate structure 1001K may be disposed along or above a second boundary of layout design 1000 (or cell). Gate structures 1001A and 1001K may not provide an electrical or conductive path and may prevent or at least reduce / minimize current leakage across the component, and gate structures 1001A and 1001K are located between components. Gate structures 1001A and 1001K may include pseudo polysilicon lines, sometimes referred to as PODEs. Each of the remaining gate structures 1001B to 1001J formed of one or more conductive materials (e.g., polysilicon, metal) may be located above a corresponding portion of active regions 202 to 208 to define a transistor (e.g., a transistor in the SDF circuit 900). Figure 9 (As shown).

[0094] The first layout level 1000A includes a plurality of patterns 1003. Each of the patterns 1003 may extend along the Y direction and is configured to form a source / drain interconnect structure (e.g., MD), hereinafter referred to as "MD 1003". Each MD may be electrically coupled to the source or drain of a corresponding transistor, for example, a portion of each of the active regions 202 to 208 that is not covered by the gate structure.

[0095] The first layout layer 1000A includes a plurality of patterns 1005. Each of the patterns 1005 may be configured to form a via interconnect structure (e.g., VD), hereinafter referred to as "VD 1005". Each VD 1005 may extend a corresponding height along a vertical direction (e.g., a direction perpendicular to the X and Y axes) to electrically couple the corresponding MD to the interconnect structure.

[0096] The first layout layer 1000A includes a plurality of patterns 1007. Each of the patterns 1007 can be configured to form a via interconnect structure (e.g., VG), hereinafter referred to as "VG 1007". Each VG 1007 can extend a corresponding height along a vertical direction (e.g., a direction perpendicular to the X and Y axes) to electrically couple a corresponding gate structure to the interconnect structure.

[0097] Next reference Figure 10B This illustrates a second layout layer 1000B of a layout design 1000 according to various embodiments. The second layout layer 1000B includes multiple patterns to form multiple interconnect structures on the front side of a substrate. For reference purposes, gate structures 1001A to 1001K ( Figure 10A Again in Figure 10B As shown in the image.

[0098] The second layout layer 1000B includes patterns 1010A, 1010B, 1010C, 1010D, 1010E, 1010F, 1010G, 1010H, 1010I, and 1010J. Each of patterns 1010A to 1010J may extend along the X-axis and be configured to form an interconnect structure in the bottommost metallization layer (e.g., the M0 layer) above the front side of the substrate. Patterns 1010A to 1010J are referred to herein as “M0 track 1010A”, “M0 track 1010B”, “M0 track 1010C”, “M0 track 1010D”, “M0 track 1010E”, “M0 track 1010F”, “M0 track 10G”, “M0 track 1010H”, “M0 track 1010I”, and “M0 track 1010J”, respectively.

[0099] In some embodiments, an M0 track 1010A, positioned along or above the third boundary of the layout design (cell), can be configured to carry a power supply voltage (e.g., VDD) and serve as a shielded metal track. An M0 track 1010J, positioned along or above the fourth boundary of the layout design (cell), can be configured to carry a power supply voltage (e.g., VSS) and serve as a shielded metal track. In some embodiments, such a shielded metal track may not be connected to any active area. Figure 9 As shown, in order to connect transistors, some M0 tracks can be "cut" into multiple parts by one or more M0 cutting patterns (e.g., 1011).

[0100] Next reference Figure 10C This illustrates a third layout layer 1000C of a layout design 1000 according to various embodiments, the third layout layer 1000C including multiple patterns to form multiple interconnect structures on the front side of a substrate. For reference purposes, gate structures 1001A to 1001K ( Figure 10A Again in Figure 10C As shown in the image.

[0101] The third layout layer 1000C includes patterns 1012A, 1012B, 1012C, 1012D, 1012E, 1012F, 1012G, 1012H, 1012I, 1012J, and 1012K. Each of patterns 1012A to 1012K may extend along the Y-axis and be configured to form an interconnect structure at the next upper metallization layer (e.g., M1 layer). Patterns 1012A to 1012K are referred to herein as “M1 track 1012A”, “M1 track 1012B”, “M1 track 1012C”, “M1 track 1012D”, “M1 track 1012E”, “M1 track 1012F”, “M1 track 1012G”, “M1 track 1012H”, “M1 track 1012I”, “M1 track 1012J”, and “M1 track 1012K”, respectively.

[0102] Each of the M1 rails 1012A to 1012K can be electrically coupled to at least one M0 rail via a through-hole structure (e.g., V0) to receive one of the inputs S1, D, SE, and CP. Figure 9 ), or provide output Q( Figure 9 For example, M1 track 1012A is electrically coupled to the cut portion of M0 track 1010C via through-hole structure 1013A (hereinafter "1013A") to receive input SI; M1 track 1012B is electrically coupled to the cut portion of M0 track 1010I via through-hole structure 1013B (hereinafter "1013B") to provide output Q; M1 track 1012D is electrically coupled to the cut portion of M0 track 1010C via through-hole structure 1013C (hereinafter "1013C") to receive input D; M1 track 1012E is electrically coupled to the cut portion of M0 track 1010E via through-hole structure 1013D (hereinafter "1013D") to receive input SE; M1 track 1012K is electrically connected to the cut portion of M0 track 1010H via through-hole structure 1013E (hereinafter "1013E") to receive input CP.

[0103] Then refer to Figure 10D This illustrates a fourth layout level 1000D of a layout design 1000 according to various embodiments, the fourth layout level 1000D including multiple patterns to form multiple interconnect structures on the back side of a substrate. For reference purposes, Figure 10D The middle section again shows the formation on the front side ( Figure 10A The gate structures 1001A to 1001K and active regions 202 to 208 on the device.

[0104] The fourth layout layer 1000D includes patterns 1014, 1016, 1018, 1020, 1022, 1024, 1026, and 1028. Each of patterns 1014, 1018, 1022, and 1024 can be an example of interconnect structure pattern 214 or 216; patterns 1016 and 1020 can be examples of interconnect structure pattern 218; and each of patterns 1026 and 1028 can be... Figure 2 Examples of portions of interconnect structure patterns 210 or 212 are shown. Each of patterns 1014 to 1028 can be configured to form an interconnect structure at the bottommost metallization layer (e.g., a BMO layer) above the back side of the substrate. Patterns 1014 to 1028 are referred to herein as “BM0 track 1014”, “BM0 track 1016”, “BM0 track 1018”, “BM0 track 1020”, “BM0 track 1022”, “BM0 track 1024”, “BM0 track 1026”, and “BM0 track 1028”, respectively. BM0 tracks 1022 and 1024 can be adjacent to BM0 track 1026, as shown below. Figure 10D As shown. In some embodiments, each of BMO tracks 1022, 1024, and 1026 may carry a first power supply voltage (e.g., VSS), and BMO tracks 1014, 1018, and 1028 may carry a second power supply voltage (e.g., VDD), while each of BMO tracks 1016 and 1020 may carry a signal other than any power supply voltage. Each of BMO tracks 1014, 1018, 1022, 1024, 1026, and 1028 may be an implementation of SD power lines 214 or 216, and BMO tracks 1016 and 1020 (even extending in a single direction) may be an implementation of MD signal lines 218, as per [reference to...]. Figure 2 The layout design of 200 is discussed.

[0105] BM0 track 1014 can be electrically coupled to a portion of active region 206 via a back-side via structure (hereinafter "VB 1031A") formed by pattern 1031A; BM0 track 1018 can be electrically coupled to a portion of active region 206 via a back-side via structure (hereinafter "VB 1031D") formed by pattern 1031D; BM0 track 1022 can be electrically coupled to a portion of active region 208 via a back-side via structure (hereinafter "VB 1031E") formed by pattern 1031E; BM0 track 1024 can be electrically coupled to a portion of active region 208 via a back-side via structure (hereinafter "VB 1031H") formed by pattern 1031H; BM0 track 1026 can be electrically coupled to a portion of active region 208 via a back-side via structure (hereinafter "VB 1031I") formed by pattern 1031I and a back-side via structure (hereinafter "VB 1031I") formed by pattern 1031J, respectively. Pattern 1031J) and a back-side via structure formed by pattern 1031K (hereinafter referred to as "VB1031K") are electrically coupled to multiple portions of the active region 202; and BMO track 1028 can be electrically coupled to multiple portions of the active region 204 through a back-side via structure formed by pattern 1031L (hereinafter referred to as "VB 1031L"), a back-side via structure formed by pattern 1031M (hereinafter referred to as "VB1031M"), and a back-side via structure formed by pattern 1031N (hereinafter referred to as "VB 1031N"), respectively. Therefore, depending on the circuit design, each of BMO tracks 1014, 1018, 1022, 1024, 1026, and 1028 can transmit or otherwise provide VDD or VSS to the corresponding node.

[0106] BM0 track 1016 can electrically couple a portion of active region 206 to another portion of active region 206 via a back-side via structure formed by pattern 1031B (hereinafter "VB 1031B") and a back-side via structure formed by pattern 1031C (hereinafter "VB 1031C"). BM0 track 1020 can electrically couple a portion of active region 208 to another portion of active region 208 via a back-side via structure formed by pattern 1031F (hereinafter "VB 1031F") and a back-side via structure formed by pattern 1031G (hereinafter "VB 1031G"). Depending on the circuit design, each of BM0 tracks 1016 and 1020 can couple different portions of the active region to couple the corresponding (internal) nodes to each other.

[0107] Figure 11 The diagram shows the cell corresponding to the multi-stage inverter to be placed above one SC row 203 and two TC rows 201 (e.g. Figure 2The layout design 1100 of cell 250 is as follows. The layout design 1100 includes a layout hierarchy showing a pattern forming a back-side interconnect structure, while a pattern forming an active region and a gate structure on the front side is also present for reference.

[0108] As shown in the figure, the active region 204 of one of the TC rows 201 (e.g., the upper TC row 201) and the active region 206 of the SC row 203 are merged to form a first wider active region in the layout design 1100. Similarly, the active region 202 of another of the TC rows 201 (e.g., the lower TC row 201) and the active region 208 of the SC row 203 are merged to form a second wider active region in the layout design 1100. In the presence of the active region 202, the active region 204 merged with the active region 206, the active region 208 merged with the active region 202, and the gate structures 1101A to 1101F, the layout design (hierarchy) 1100 includes patterns 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, and 1120. Each of patterns 1102 to 1120 can be configured to form an interconnect structure at the bottommost metallization layer (e.g., BMO layer) above the back side of the substrate. Patterns 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, and 1120 are referred to herein as “BM0 track 1102”, “BM0 track 1104”, “BM0 track 1106”, “BM0 track 1108”, “BM0 track 1110”, “BM0 track 1112”, “BM0 track 1114”, “BM0 track 1116”, “BM0 track 1118”, and “BM0 track 1120”, respectively.

[0109] In some embodiments, each of BM0 rails 1102, 1112, 1114, 1116, and 1118 may carry a first power supply voltage (e.g., VSS), and BM0 rails 1104, 1006, 1108, 1110, and 1120 may carry a second power supply voltage (e.g., VDD). In some embodiments, each of BM0 rails 1106, 1108, and 1100 may be adjacent to M0 rail 1104, and each of BM0 rails 1112, 1114, and 1116 may be adjacent to M0 rail 1118, as shown. Each of BM0 rails 1102 to 1120 may be an implementation of SD power lines 210 or 212, as described regarding... Figure 2 The layout design of 200 is discussed.

[0110] The adjacent portions 1104 and 1106, 1104 and 1108, and 1104 and 1110 of the BM0 tracks can be electrically coupled to the corresponding portions of the merged active regions 204 and 206 through multiple back-side via structures formed by patterns 1109A (hereinafter "VB 1109A"), 1109B (hereinafter "VB 1109B"), and 1109C (hereinafter "VB 1109C"), respectively. The adjacent portions 1118 and 1112, 1118 and 1114, and 1118 and 1116 of the BM0 tracks can be electrically coupled to the corresponding portions of the merged active regions 208 and 202 through multiple back-side via structures formed by patterns 1109D (hereinafter "VB1109D"), 1109E (hereinafter "VB 1109E"), and 1109F (hereinafter "VB 1109F"), respectively. Therefore, depending on the circuit design, each of the BM0 tracks 1102 to 1120 can transmit or otherwise provide VDD or VSS to the corresponding node.

[0111] While the layout designs discussed above show the bottommost metallization layer (BM0 layer) above the back side of the substrate, it should be understood that each layout design may include any number of metallization layers disposed above the back side of the substrate. Figure 12 Layout design 1200 is shown, which includes multiple patterns for forming a back-side interconnect structure on top of the BMO layer. Layout design 1200 can be layout design 200 (…). Figure 2 ( ) part. For example, in Figure 12 In the layout design 1200, there is an SC row 203 sandwiched between two TC rows 201, and multiple BM0 tracks 210 to 218.

[0112] Furthermore, the layout design 1200 includes patterns 1210A, 1210B, 1210C, 1210D, 1210E, 1210F, 1210G, 1210H, 1210I, and 1210J. Each of patterns 1210A to 1210J can be configured to form an interconnect structure at the next upper metallization layer (e.g., BM1 layer) relative to the BM0 layer. Patterns 1210A, 1210B, 1210C, 1210D, 1210E, 1210F, 1210G, 1210H, 1210I, and 1210J are referred to herein as “BM1 track 1210A”, “BM1 track 1210B”, “BM1 track 1210C”, “BM1 track 1210D”, “BM1 track 1210E”, “BM1 track 1210F”, “BM1 track 1210G”, “BM1 track 1210H”, “BM1 track 1210I”, and “BM1 track 1210J”, respectively. In some embodiments, each of the BM1 tracks 1210A to 1210J may extend along a direction perpendicular to the extension direction of the BM0 track (e.g., the Y-axis), which is configured to carry a power supply voltage, such as BM0 tracks 210 and 212. In some embodiments, each of BM1 rails 1210A, 1210C, 1210E, 1210G, and 1210I can carry a first power supply voltage (e.g., VDD), and BM1 rails 1210B, 1210D, 1210F, 1210H, and 1210J can carry a second power supply voltage (e.g., VSS). Each of the BM1 rails can be electrically coupled to one or more of the BM0 rails via one or more back-side via structures (e.g., VB0) formed by pattern 1213 (hereinafter “VB0 1213”).

[0113] Figure 13 A cross-sectional view of a semiconductor device 1300 including the above-described components / structures is shown. Figure 13 The cross-sectional view is cut along the longitudinal direction of the channel of semiconductor device 1300, which is implemented as a GAA FET device. Figure 13 The above structures are simplified to show their relative spatial configuration; therefore, it should be understood that one or more components / structures of the completed GAA FET device may not be present in the diagram. Figure 13 As shown in the image.

[0114] On the front side of the substrate (surrounded by dashed lines, as it was removed during the formation of the back-side interconnect structure), the semiconductor device 1300 includes an active region 1302 having portions formed as a channel 1304 and portions formed as source / drain structures 1306. In various embodiments, the channel 1304 includes one or more nanostructures (e.g., nanosheets, nanowires) perpendicularly spaced from each other. The semiconductor device 1300 includes a plurality of (e.g., metal) gate structures 1308, each gate structure 1308 enclosing the nanostructures of a corresponding channel 1304. Above the source / drain structures 1306, the semiconductor device 1300 includes a plurality of gate elements (MDs) 1310, some of which are coupled to VDs 1312 formed thereon. Above the gate structures 1308, the semiconductor device 1300 includes a plurality of gate groups (VGs) 1314. The VDs 1312 can couple the MDs 1310 to a first MO orbital 1316. VG 1314 can couple the gate structure 1308 to the second M0 rail 1316. Above the M0 rail 1316, the semiconductor device 1300 includes a plurality of V0 1318 to couple the M0 rail 1316 to a plurality of M1 rails 1320. On the back side of the substrate, the semiconductor device 1300 includes a plurality of VB 1322, each of which can couple the source / drain structure 1306 to the BM0 rail 1324. Furthermore, above the BM0 rail 1324, the semiconductor device 1300 includes a plurality of VB0 1326, each of which can couple the BM0 rail 1324 to the BM1 rail 1328.

[0115] Figure 14 This is a flowchart of a method 1400 for forming or manufacturing a semiconductor device according to some embodiments. It should be understood that... Figure 14 Additional operations are performed before, during, and / or after the method 1400 shown. In some embodiments, the method 1400 can be used to form a semiconductor device according to various layout designs disclosed herein.

[0116] In operation 1410 of method 1400, a layout design for the semiconductor device is generated (e.g., Figure 2 Layout design 200). Operation 1410 is performed by a processing device configured to execute instructions for generating the layout design (e.g., Figure 15 The processor 1502 executes the operation. In one method, a layout design is generated by placing a layout design of one or more standard cells through a user interface. In another method, the layout design is automatically generated by a processor executing a synthesis tool that converts a logic design (e.g., Verilog) into a corresponding layout design. In some embodiments, the layout design is presented in a Graphical Database System (GDSII) file format.

[0117] In operation 1420 of method 1400, a semiconductor device is manufactured based on a layout design. In some embodiments, operation 1420 of method 1400 includes manufacturing at least one mask based on a layout design, and manufacturing a semiconductor device based on the at least one mask. The following will discuss... Figure 17 Method 1700 discusses several example manufacturing operations of operation 1420.

[0118] Figure 15 This is a schematic diagram of a system 1500 for designing and manufacturing IC layout designs according to some embodiments. As described herein, system 1500 generates or places one or more IC layout designs. In some embodiments, as described herein, system 1500 manufactures one or more semiconductor devices based on one or more IC layout designs. System 1500 includes a hardware processor 1502 and a non-transitory computer-readable storage medium 1504, which encodes (e.g., stores) computer program code 1506, an executable instruction set. Computer-readable storage medium 1504 is configured to interface with a manufacturing machine for producing semiconductor devices. Processor 1502 is electrically coupled to computer-readable storage medium 1504 via bus 1508. Processor 1502 is also electrically coupled to I / O interface 1510 via bus 1508. Network interface 1512 is also electrically connected to processor 1502 via bus 1508. Network interface 1512 is connected to network 1514, enabling processor 1502 and computer-readable storage medium 1504 to be connected to external components via network 1514. Processor 1502 is configured to execute computer program code 1506 encoded in computer-readable storage medium 1504 so that system 1500 can be used to perform some or all of the operations as described in method 1400.

[0119] In some embodiments, the processor 1502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0120] In some embodiments, the computer-readable storage medium 1504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1504 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In some embodiments using optical disks, the computer-readable storage medium 1504 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0121] In some embodiments, storage medium 1504 stores computer program code 1506 configured to cause system 1500 to execute method 1400. In some embodiments, storage medium 1504 also stores information required to execute method 1400 and information generated during the execution of method 1400, such as layout design 1516, user interface 1518 and manufacturing unit 1520, and / or executable instruction set to perform the operation of method 1400.

[0122] In some embodiments, storage medium 1504 stores instructions (e.g., computer program code 1506) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 1506) enable processor 1502 to generate manufacturing instructions readable by the manufacturing machine to efficiently implement method 1400 during the manufacturing process.

[0123] System 1500 includes an I / O interface 1510. The I / O interface 1510 is coupled to external circuitry. In some embodiments, the I / O interface 1510 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor arrow keys for transmitting information and commands to processor 1502.

[0124] System 1500 also includes a network interface 1512 coupled to processor 1502. Network interface 1512 allows system 1500 to communicate with network 1514, to which one or more other computer systems are connected. Network interface 1512 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, WCDMA, etc.; or wired network interfaces such as Ethernet, USB, or IEEE-13154. In some embodiments, method 1400 is implemented in two or more systems 1500, and information such as layout design, user interface, and manufacturing unit information is exchanged between different systems 1500 via network 1514.

[0125] System 1500 is configured to receive layout design-related information via I / O interface 1510 or network interface 1512. This information is transmitted via bus 1508 to processor 1502 to determine a layout design for IC production. The layout design is then stored as layout design 1516 in computer-readable medium 1504. System 1500 is also configured to receive user interface-related information via I / O interface 1510 or network interface 1512. This information is stored in computer-readable medium 1504 as user interface 1518. System 1500 is further configured to receive manufacturing unit-related information via I / O interface 1510 or network interface 1512. This information is stored in computer-readable medium 1504 as manufacturing unit 1520. In some embodiments, manufacturing unit 1520 includes manufacturing information utilized by system 1500.

[0126] In some embodiments, method 1400 is implemented as a standalone software application executed by a processor. In some embodiments, method 1400 is implemented as a software application that is part of an additional software application. In some embodiments, method 1400 is implemented as a plug-in to a software application. In some embodiments, method 1400 is implemented as a software application that is part of an EDA tool. In some embodiments, method 1400 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of an integrated circuit device. In some embodiments, the layout design is stored on a non-transitory computer-readable medium. In some embodiments, a medium such as that available from CADENCE DESIGN SYSTEMS is used. Tools or other suitable layout generation tools are used to generate layout designs. In some embodiments, the layout design is generated based on a netlist created based on a schematic design. In some embodiments, method 1400 is implemented by a manufacturing device to manufacture an integrated circuit using a mask set manufactured based on one or more layout designs generated by system 1500. In some embodiments, system 1500 includes a manufacturing device (e.g., manufacturing tool 1522) to manufacture an integrated circuit using a mask set manufactured based on one or more layout designs of the present invention. In some embodiments, Figure 15 The System 1500 generates a layout design for a smaller IC than other methods. In some embodiments, Figure 15 The system 1500 generates the layout design of integrated circuit structures, which occupies less area compared to other methods.

[0127] Figure 16 This is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system 1600 and its associated IC manufacturing process according to at least one embodiment of the present invention.

[0128] exist Figure 16In this IC manufacturing system 1600, entities such as design studio 1620, mask room 1630, and IC vendor / manufacturer (“fab”) 1640 interact with each other in the design, development, and manufacturing cycle and / or in services related to the manufacture of IC devices (semiconductor devices) 1660. The entities in system 1600 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design studio 1620, mask room 1630, and IC manufacturer 1640 are owned by a single, larger company. In some embodiments, two or more of design studio 1620, mask room 1630, and IC manufacturer 1640 coexist in a shared facility and use shared resources.

[0129] Design studio (or design team) 1620 generates IC design layout 1622. IC design layout 1622 includes various geometric patterns designed for IC device 1660. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1660 to be manufactured. The various layers are combined to form various IC components. For example, portions of IC design layout 1622 include various IC components such as active regions, gate structures, source and drain structures, interconnect structures, and openings for forming bonding pads that will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 1620 performs appropriate design steps to form IC design layout 1622. Design steps include one or more of logic design, physical design, or place-and-route. IC design layout 1622 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1622 may be represented in GDSII file format or DFII file format.

[0130] Mask chamber 1630 includes data preparation 1632 and mask fabrication 1634. Mask chamber 1630 uses IC design layout 1622 to fabricate one or more masks for manufacturing various layers of IC device 1660 according to IC design layout 1622. Mask chamber 1630 implements mask data preparation 1632, in which IC design layout 1622 is converted into a representative data file (“RDF”). Mask data preparation 1632 provides the RDF to mask fabrication 1634. Mask fabrication 1634 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) or a semiconductor wafer. The design layout is manipulated by mask data preparation 1632 to conform to the specific characteristics of the mask writer and / or the requirements of IC manufacturer 1640. Figure 16 In this diagram, mask data preparation 1632 and mask manufacturing 1634 are shown as separate elements. In some embodiments, mask data preparation 1632 and mask manufacturing 1634 may be collectively referred to as mask data preparation.

[0131] In some embodiments, mask data preparation 1632 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout 1622. In some embodiments, mask data preparation 1632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution aids, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, where ILT treats OPC as an inverse imaging problem.

[0132] In some embodiments, mask data preparation 1632 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout that has undergone the process in the OPC. These mask creation rules include certain geometric and / or connectivity constraints to ensure sufficient margin to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 1634, which can undo some modifications implemented by the OPC to satisfy the mask creation rules.

[0133] In some embodiments, mask data preparation 1632 includes lithography process inspection (LPC), an LPC simulation performed by IC manufacturer 1640 to manufacture IC device 1660. The LPC simulates this process based on IC design layout 1622 to create a simulated manufactured device, such as IC device 1660. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, or combinations thereof. In some embodiments, after creating the simulated manufactured device via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1622.

[0134] It should be understood that, for clarity, the above description of mask data preparation 1632 has been simplified. In some embodiments, mask data preparation 1632 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to the IC design layout 1622 during mask data preparation 1632 can be performed in various different sequences.

[0135] After mask data preparation 1632 and during mask fabrication 1634, a mask or a set of masks is fabricated based on a modified IC design layout. In some embodiments, a pattern is formed on the mask (photomask or intermediate mask) using a mechanism of electron beams (e-beams) or multiple electron beams based on the modified IC design layout. The mask can be formed using various techniques. In some embodiments, a binary technique is used to form the mask. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam (such as an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer is blocked by the opaque regions and passes through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form the mask. In a phase-shifting mask (PSM), various components in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase-shifting mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1634 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form various doped regions in a semiconductor wafer, in etching processes to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0136] IC manufacturer 1640 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturer 1640 is a semiconductor foundry. For example, there may be a first manufacturing facility for front-end manufacturing of multiple IC products (e.g., source / drain structures, gate structures), a second manufacturing facility that can provide intermediate manufacturing for interconnects of IC products (e.g., MD, VD, VG), a third manufacturing facility that can provide back-end manufacturing for interconnects and packaging of IC products (e.g., M0 rail, M1 rail, BM0 rail, BM1 rail), and a fourth manufacturing facility that can provide additional services for the foundry entity.

[0137] IC manufacturer 1640 uses a mask (or multiple masks) manufactured by mask chamber 1630 to manufacture IC device 1660. Therefore, IC manufacturer 1640 uses IC design layout 1622 at least indirectly to manufacture IC device 1660. In some embodiments, semiconductor wafer 1642 is manufactured by IC manufacturer 1640 using a mask (or multiple masks) to form IC device 1660. Semiconductor wafer 1642 includes a silicon substrate or other suitable substrate on which a material layer is formed. The semiconductor wafer also includes one or more of various doped regions, dielectric components, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0138] System 1600 is shown as having a design room 1620, a mask room 1630, or an IC manufacturer 1640 as independent components or entities. However, it should be understood that one or more of the design room 1620, mask room 1630, or IC manufacturer 1640 are part of the same component or entity.

[0139] Figure 17 This is a flowchart illustrating an example method 1700 for manufacturing a semiconductor device including the disclosed back-side SD power lines and / or back-side MD signal lines according to various aspects of the present invention. Method 1700 may be method 1400 ( Figure 14 This relates to the operation of part 1420. Therefore, semiconductor devices can be manufactured based on at least a portion of the layout design disclosed herein.

[0140] At least some operations of method 1700 can be used to form a semiconductor device with a non-planar transistor configuration. For example, the semiconductor device may include one or more gate-all-around (GAA) transistors. However, it should be understood that each transistor of the semiconductor device may be configured as any of a variety of other types of transistors, such as CFETs, while still remaining within the scope of this invention. It should be noted that method 1700 is merely an example and is not intended to limit the invention. Therefore, it should be understood that additional operations may be provided before, during, and / or after method 1700, and some other operations may be described only briefly herein. The following discussion of method 1700 may refer to... Figures 1 to 16 One or more components.

[0141] In summary, method 1700 begins with operation 1702, which involves providing a semiconductor substrate. Method 1700 proceeds to operation 1704, where a plurality of GAA transistors are formed on the front side of the semiconductor substrate. Method 1700 proceeds to operation 1706, where a plurality of first interconnect structures are formed on the front side. Method 1700 proceeds to operation 1708, where a plurality of second interconnect structures are formed on the back side of the semiconductor substrate. The second interconnect structures may include the disclosed SD power lines and MD signal lines.

[0142] Corresponding to operation 1702, the semiconductor substrate can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., having p-type or n-type dopants) or undoped. The substrate can be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0143] Corresponding to operation 1704, a plurality of GAA transistors are formed on the front side of a semiconductor substrate. Each GAA transistor can be formed by at least some of the following process steps: forming a fin structure protruding from the substrate, wherein the fin structure includes a plurality of first semiconductor nanostructures and a plurality of second semiconductor nanostructures alternately stacked on top of each other; forming a dummy gate structure across the fin structure; forming gate spacers disposed along opposite sidewalls of the dummy gate structure; recessing the portion of the fin structure not covered by the dummy gate structure (and gate spacers); replacing the corresponding ends of each second semiconductor nanostructure with a dielectric material to form a plurality of internal spacers; forming a source / drain structure in the fin structure, the source / drain structure being located on opposite sides of the dummy gate structure; removing the dummy gate structure; removing the remaining second semiconductor nanostructures; and forming an active (e.g., metal) gate structure to enclose each first semiconductor nanostructure. In some embodiments, the first semiconductor nanostructures may be collectively referred to as the channel of the GAA transistor, while the second semiconductor nanostructures replaced by the active gate structure may be referred to as sacrificial nanostructures.

[0144] Corresponding to operation 1706, a first interconnect structure is formed on the front side of the semiconductor substrate. The first interconnect structure may include multiple mid-processing-on-the-loop (MEOL) interconnect structures (e.g., MD, VD, VG) and multiple back-processing-on-the-loop (BEOL) interconnect structures (e.g., M0 track, V0, M1 track, etc.), as described above. In some embodiments, each of the MEOL and BEOL interconnect structures may extend along a single direction. For example, MD may extend entirely along a first lateral direction parallel to the gate structure; M0 track may extend entirely along a second lateral direction perpendicular to the first lateral direction (parallel to the longitudinal direction of the channel); and M1 track may extend entirely along the first lateral direction. Each first interconnect structure disposed on the front side may include one or more metallic materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or combinations thereof.

[0145] Corresponding to operation 1708, a second interconnect structure is formed on the back side of the substrate. In some embodiments, the second interconnect structure can serve as a power line (carrying a power signal) or a signal line (carrying a non-power signal), wherein the power line can extend along one of a first lateral direction or a second lateral direction, while the signal line can extend in more than one direction. The second interconnect structure can be formed by at least some of the following process steps: flipping the semiconductor substrate; thinning the semiconductor substrate from the back side until the bottom surface of the source / drain structure is exposed (or the bottom surface of the dielectric layer beneath the source / drain structure, which is formed before the epitaxial growth of the source / drain structure); forming a plurality of via structures (e.g., VB) coupled to each source / drain structure; and forming the second interconnect structure (e.g., the respective BMO tracks discussed above). Each second interconnect structure disposed on the back side can include one or more metallic materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or combinations thereof.

[0146] In one aspect of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a first active region disposed on a first side of a substrate and extending along a first lateral direction. The semiconductor device also includes: a second active region disposed on the first side and extending along the first lateral direction. The first active region has a first conductivity type, and the second active region has a second conductivity type opposite to the first conductivity type. The semiconductor device further includes: a first interconnect structure formed on a second side of the substrate opposite to the first side, the first interconnect structure including: a first portion extending along the first lateral direction and perpendicularly disposed below the first active region; and a second portion extending along a second lateral direction. The second lateral direction is perpendicular to the first lateral direction.

[0147] In the aforementioned semiconductor device, the first interconnect structure is configured to carry a non-power supply signal.

[0148] In the semiconductor device described above, the first end of the second portion of the first interconnect structure is connected to the first portion of the first interconnect structure.

[0149] In the aforementioned semiconductor device, a first end of the second portion of the first interconnect structure is connected to the first portion of the first interconnect structure, and the first interconnect structure includes a third portion extending along the first lateral direction and disposed vertically below the second active region.

[0150] In the above-described semiconductor device, a first end of the second portion of the first interconnect structure is connected to the first portion of the first interconnect structure, the first interconnect structure includes a third portion extending along the first lateral direction and disposed vertically below the second active region, and a second end of the second portion of the first interconnect structure is connected to the third portion of the first interconnect structure.

[0151] In the aforementioned semiconductor device, the semiconductor device further includes: a third active region disposed on the first side, the third active region extending along the first lateral direction, wherein the third active region has the first conductivity type; a fourth active region disposed on the first side, the fourth active region extending along the first lateral direction, wherein the fourth active region has the second conductivity type; a plurality of second interconnect structures formed on the first side above the first active region to the fourth active region, the plurality of second interconnect structures extending along the first lateral direction; a third interconnect structure formed on the second side, the third interconnect structure extending along the first lateral direction and vertically located below the third active region; and a fourth interconnect structure formed on the second side, the fourth interconnect structure extending along the first lateral direction and vertically located below the fourth active region.

[0152] In the aforementioned semiconductor device, the semiconductor device further includes: a third active region disposed on the first side, the third active region extending along the first lateral direction, wherein the third active region has the first conductivity type; a fourth active region disposed on the first side, the fourth active region extending along the first lateral direction, wherein the fourth active region has the second conductivity type; a plurality of second interconnect structures formed on the first side above the first active region to the fourth active region, the plurality of second interconnect structures extending along the first lateral direction; a third interconnect structure formed on the second side, the third interconnect structure extending along the first lateral direction and vertically located below the third active region; and a fourth interconnect structure formed on the second side, the fourth interconnect structure extending along the first lateral direction and vertically located below the fourth active region, wherein the number of a first subset of the third interconnect structures electrically coupled to the first active region and the second active region is less than the number of a second subset of the third interconnect structures electrically coupled to the third active region and the fourth active region.

[0153] In the aforementioned semiconductor device, the semiconductor device further includes: a third active region disposed on the first side, the third active region extending along the first lateral direction, wherein the third active region has the first conductivity type; a fourth active region disposed on the first side, the fourth active region extending along the first lateral direction, wherein the fourth active region has the second conductivity type; a plurality of second interconnect structures formed on the first side above the first active region to the fourth active region, the plurality of second interconnect structures extending along the first lateral direction; a third interconnect structure formed on the second side, the third interconnect structure extending along the first lateral direction and vertically located below the third active region; and a fourth interconnect structure formed on the second side, the fourth interconnect structure extending along the first lateral direction and vertically located below the fourth active region, wherein the number of a first subset of the third interconnect structures electrically coupled to the first active region and the second active region is less than the number of a second subset of the third interconnect structures electrically coupled to the third active region and the fourth active region, each of the third interconnect structure and the fourth interconnect structure being configured to carry a power supply signal.

[0154] In the above-described semiconductor device, the semiconductor device further includes: a plurality of fourth interconnect structures formed on the second side, each of the plurality of fourth interconnect structures being vertically disposed between the first active region or the second active region and the first interconnect structure.

[0155] In the aforementioned semiconductor device, each of the first active region and the second active region includes a plurality of nanostructures that are perpendicularly separated from each other.

[0156] In another aspect of the invention, an integrated circuit is disclosed. The integrated circuit includes: a first row extending along a first direction and having a first height along a second direction perpendicular to the first direction. The first row includes a first active region formed on a first side of a substrate. The integrated circuit includes: a second row extending along the first direction and having a second height along the second direction. The second height is greater than the first height, and the second row includes a second active region formed on the first side of the substrate. The integrated circuit includes: a signal line structure formed on a second side of the substrate opposite to the first side. The signal line structure is disposed within the first row. The integrated circuit includes: a first power line structure formed on a second side of the substrate. The first power line structure is disposed within the second row.

[0157] In the aforementioned integrated circuit, the signal line structure partially overlaps with the first active region, and the first power line structure completely overlaps with the second active region.

[0158] In the aforementioned integrated circuit, the signal line structure includes a first portion extending along the first direction and a second portion extending along the second direction.

[0159] In the aforementioned integrated circuit, the signal line structure includes a first portion extending along the first direction and a second portion extending along the second direction, the first portion overlapping the first active region and the second portion not overlapping the first active region.

[0160] In the aforementioned integrated circuit, the signal line structure includes a first portion extending along the first direction and a second portion extending along the second direction, with the respective ends of the first portion and the second portion connected to each other to form an L-shaped profile.

[0161] In the aforementioned integrated circuit, the integrated circuit further includes a second power line structure located on the second side of the substrate, wherein the second power line structure is adjacent to the first power line structure.

[0162] In the aforementioned integrated circuit, each of the first active region and the second active region includes a plurality of nanostructures that are perpendicularly separated from each other.

[0163] In another aspect of the invention, a method for manufacturing a semiconductor device is disclosed. The method includes forming a plurality of transistors on a first side of a substrate. The method includes coupling the plurality of transistors by forming a plurality of first interconnect structures extending along a first lateral direction or a second lateral direction perpendicular to each other on the first side. The method includes forming a plurality of third interconnect structures on a second side of the substrate opposite to the first side. At least one of the third interconnect structures includes a first portion and a second portion extending along the first lateral direction and the second lateral direction, respectively. The method includes forming a plurality of power rail structures extending along the first lateral direction on the second side.

[0164] In the above method, the at least one third interconnect structure is configured to carry a non-power signal.

[0165] In the above method, each of the plurality of transistors includes a gate-all-around (GAA) transistor.

[0166] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: A first active region is disposed on a first side of the substrate, and the first active region extends along a first lateral direction; A second active region is disposed on the first side, extending along the first lateral direction, wherein the first active region has a first conductivity type, and the second active region has a second conductivity type opposite to the first conductivity type; and A first interconnect structure is formed on a second side of the substrate opposite to the first side. The first interconnect structure includes: a first portion extending along the first lateral direction and disposed perpendicularly below the first active region; and a second portion extending along a second lateral direction, wherein the second lateral direction is perpendicular to the first lateral direction. A third active region is disposed on the first side, the third active region extends along the first lateral direction, wherein the third active region has the first conductivity type; A fourth active region is disposed on the first side, the fourth active region extending along the first lateral direction, wherein the fourth active region has the second conductivity type; A plurality of second interconnect structures are formed on the first side above the first active region to the fourth active region, and the plurality of second interconnect structures extend along the first lateral direction; A third interconnect structure is formed on the second side, the third interconnect structure extending along the first lateral direction and located vertically below the third active region; and A fourth interconnect structure is formed on the second side, the fourth interconnect structure extending along the first lateral direction and located vertically below the fourth active region.

2. The semiconductor device according to claim 1, wherein, The first interconnect structure is configured to carry non-power signals.

3. The semiconductor device according to claim 1, wherein, The first end of the second portion of the first interconnect structure is connected to the first portion of the first interconnect structure.

4. The semiconductor device according to claim 3, wherein, The first interconnect structure includes a third portion that extends along the first lateral direction and is disposed vertically below the second active region.

5. The semiconductor device according to claim 4, wherein, The second end of the second portion of the first interconnect structure is connected to the third portion of the first interconnect structure.

6. The semiconductor device according to claim 1, wherein: The semiconductor device includes a D flip-flop with a scan input.

7. The semiconductor device according to claim 1, wherein, The number of the first subset of the third interconnect structure electrically coupled to the first active region and the second active region is less than the number of the second subset of the third interconnect structure electrically coupled to the third active region and the fourth active region.

8. The semiconductor device according to claim 7, wherein, Each of the third interconnect structure and the fourth interconnect structure is configured to carry a power signal.

9. The semiconductor device according to claim 1, wherein, The first active region comprises one or more nanosheets stacked on top of each other over the substrate.

10. The semiconductor device according to claim 1, wherein, Each of the first and second active regions includes a plurality of nanostructures that are perpendicularly separated from each other.

11. An integrated circuit, comprising: The first row extends along a first direction and has a first height along a second direction perpendicular to the first direction and parallel to the substrate, wherein the first row includes a first active region formed on a first side of the substrate; The second row extends along the first direction and has a second height along the second direction, wherein the second height is greater than the first height, and wherein the second row includes a second active region formed on the first side of the substrate; A signal line structure is formed on a second side of the substrate opposite to the first side, wherein the signal line structure is disposed within the first row; and A first power line structure is formed on the second side of the substrate, wherein the first power line structure is disposed within the second row.

12. The integrated circuit according to claim 11, wherein, The signal line structure partially overlaps with the first active region, and the first power line structure completely overlaps with the second active region.

13. The integrated circuit according to claim 11, wherein, The signal line structure includes a first portion extending along the first direction and a second portion extending along the second direction.

14. The integrated circuit according to claim 13, wherein, The first portion overlaps with the first active region, and the second portion does not overlap with the first active region.

15. The integrated circuit according to claim 13, wherein, The corresponding ends of the first part and the second part are connected to each other to form an L-shaped profile.

16. The integrated circuit of claim 11, further comprising a second power line structure located on the second side of the substrate, wherein, The second power line structure is adjacent to the first power line structure.

17. The integrated circuit according to claim 11, wherein, Each of the first active region and the second active region includes a plurality of nanostructures that are perpendicularly separated from each other.

18. A method for manufacturing a semiconductor device, comprising: Multiple transistors are formed on the first side of the substrate; The plurality of transistors are coupled by forming a plurality of first interconnect structures extending along a first lateral direction or a second lateral direction on the first side, wherein the first lateral direction and the second lateral direction are perpendicular to each other; A plurality of third interconnect structures are formed on a second side of the substrate opposite to the first side, wherein at least one of the third interconnect structures includes a first portion and a second portion extending along the first lateral direction and the second lateral direction, respectively; as well as Multiple power rail structures extending along the first lateral direction are formed on the second side.

19. The method according to claim 18, wherein, The at least one third interconnect structure is configured to carry non-power signals.

20. The method according to claim 18, wherein, Each of the plurality of transistors includes a gate-all-around (GAA) transistor.

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