Functional chips for 3D chips

Abstract

The present invention provides a functional chip for a 3D chip, comprising: a substrate layer; a metal layer, the metal layer comprising a first surface and a second surface disposed oppositely, the second surface of the metal layer being disposed on the substrate layer; a metal layer through-hole assembly disposed within the metal layer, the metal layer through-hole assembly comprising: a first conductor, a second conductor, and a conductor connection hole, the first conductor being formed on the first surface of the metal layer, the second conductor being formed on the second surface of the metal layer, the conductor connection hole being formed within the metal layer, the second conductor being connected to the first conductor via the conductor connection hole; a substrate through-hole disposed on the substrate layer; and a functional circuit connected to at least one of the first conductor and the second conductor. This functional chip reduces the difficulty of etching, reduces the area occupied by the metal layer, reduces resistance parasitics and capacitance parasitics, shortens the preparation cycle of the functional chip, and reduces production costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a functional chip for a 3D chip. Background Art

[0002] With the advancement of chip technology and the increasing demand for information technology, 3D chips are increasingly appearing in the integrated circuit industry. 3D chips can include multiple functional chips stacked together. Due to signal transmission requirements, signal connections within a 3D chip must pass through the functional chips that make up the 3D chip. These signal connections are achieved through the entire chip from the front to the back using perforations, currently primarily achieved using through-silicon vias (TSVs).

[0003] Because TSVs must penetrate the entire chip, not only through the various materials that make up the stacked circuits but also through the very thick silicon substrate, they place high demands on the etching technology used to create the vias. Furthermore, the TSVs are large in diameter and length, resulting in a significant increase in chip area, high parasitic resistance and capacitance parameters, a long manufacturing cycle, and high costs. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0005] In view of this, according to an embodiment of the present application, a functional chip for a 3D chip is proposed, comprising: a substrate layer; a metal layer, the metal layer comprising a first surface and a second surface arranged opposite to each other, the second surface of the metal layer being arranged on the substrate layer; a metal layer through-hole component, arranged in the metal layer, the metal layer through-hole component comprising: a first conductor, a second conductor and a conductor connection hole, the first conductor being formed on the first surface of the metal layer, the second conductor being formed on the second surface of the metal layer, the conductor connection hole being formed in the metal layer, the second conductor being connected to the first conductor through the conductor connection hole, so that the signal can be transmitted to the first surface through the substrate layer; a substrate through-hole, opened on the substrate layer and connected to the second conductor; a functional circuit, the functional circuit being connected to at least one of the first conductor and the second conductor.

[0006] In a first possible implementation of an embodiment of the present application, the metal layer through-hole assembly further includes: an on-chip conductor part, located between the first conductor part and the second conductor part; wherein, there are multiple conductor connection holes, the second conductor part is connected to the on-chip conductor part through some of the multiple conductor connection holes, and the on-chip conductor part is connected to the first conductor part through some of the multiple conductor connection holes.

[0007] In a second possible implementation of the embodiment of the present application, the functional circuit is connected to at least one of the first conductor, the second conductor, and the on-chip conductor.

[0008] In a third possible implementation of the embodiment of the present application, when the signal input end and the signal output end of the functional circuit are connected to the same one of the first conductor, the second conductor and the on-chip conductor, the access points of the signal input end and the signal output end of the functional circuit are different.

[0009] In a fourth possible implementation of the embodiment of the present application, the function chip for the 3D chip further includes: an internal signal input terminal connected to the functional circuit.

[0010] In a fifth possible implementation of an embodiment of the present application, the functional circuit includes a switching circuit, which includes: at least two parallel switching modules, the signal input end and / or the signal output end of each switching module being connected to at least one of the first conductor, the second conductor and the on-chip conductor; a first control switch, each switching module is provided with at least one first control switch, and the first control switch is used to control the working state of the signal input end or the signal output end of the switching module.

[0011] In a sixth possible implementation of the embodiment of the present application, multiple switching modules are connected to the same signal input end; and / or multiple switching modules are connected to the same signal output end.

[0012] In a seventh possible implementation of the embodiment of the present application, the functional circuit includes a driving circuit, and the driving circuit includes: a driving module, and the signal input end and / or the signal output end of the driving module are connected to at least one of the first conductor part, the second conductor part and the on-chip conductor part.

[0013] In an eighth possible implementation of an embodiment of the present application, the functional circuit includes a conversion circuit, and the conversion circuit includes: a conversion module, and the signal input end and / or the signal output end of the conversion module are connected to at least one of the first conductor part, the second conductor part and the on-chip conductor part.

[0014] In a ninth possible implementation of the embodiment of the present application, the conversion module is a serial-to-parallel conversion module or a parallel-to-serial conversion module.

[0015] In a tenth possible implementation of an embodiment of the present application, the functional circuit includes an operation circuit, and the operation circuit includes: an operation module, and the signal input end and / or signal output end of the operation module are connected to at least one of the first conductor part, the second conductor part and the on-chip conductor part.

[0016] In an eleventh possible implementation of the embodiment of the present application, the function chip for the 3D chip further includes: a second control switch connected to the operation module, for controlling the working states of the signal input and signal output ends of the operation module.

[0017] In a twelfth possible implementation of the embodiment of the present application, there are multiple on-chip conductor parts, and the multiple on-chip conductor parts are arranged at intervals between the first conductor part and the second conductor part, and adjacent on-chip conductor parts are connected through some of the multiple conductor connection holes.

[0018] In a thirteenth possible implementation manner of the embodiment of the present application, a conductor connection hole is provided between two adjacent on-chip conductor parts.

[0019] In a fourteenth possible implementation manner of the embodiment of the present application, a conductor connection hole is provided between the first conductor component and an adjacent on-chip conductor component.

[0020] In a fifteenth possible implementation manner of the embodiment of the present application, a conductor connection hole is provided between the second conductor component and the adjacent on-chip conductor component.

[0021] In a sixteenth possible implementation manner of the embodiment of the present application, the difference between the number of conductor connection holes and the number of conductor connection members is 1.

[0022] In a seventeenth possible implementation of the embodiment of the present application, the cross-section of the substrate through hole along the substrate height direction is a polygon, and the length of the first side of the polygon close to the metal layer is smaller than the length of the second longest side of the polygon away from the metal layer.

[0023] In an eighteenth possible implementation manner of the embodiment of the present application, a cross-section of the substrate through hole along the substrate height direction is trapezoidal.

[0024] In a nineteenth possible implementation manner of the embodiment of the present application, the short side of the trapezoid is located on a side of the substrate layer close to the metal layer, and the long side of the trapezoid is located on a side of the substrate layer far from the metal layer.

[0025] In a twentieth possible implementation of the embodiment of the present application, the substrate through hole is in a truncated cone shape.

[0026] In the twenty-first possible implementation of the embodiment of the present application, the frustum includes a first end face and a second end face, the diameter of the first end face is smaller than the diameter of the second end face, the first end face is located on the side of the substrate layer close to the metal layer, and the second end face is located on the side of the substrate layer away from the metal layer.

[0027] In a twenty-second possible implementation of the embodiment of the present application, the conductor connection hole is columnar.

[0028] In the twenty-third possible implementation of the embodiment of the present application, the functional chip for the 3D chip also includes: a substrate conductor part, which is arranged in the substrate layer; the substrate through hole includes a bottom through hole and an intermediate connecting hole, the bottom through hole is opened at the bottom of the substrate and is connected to the substrate conductor part, the intermediate connecting hole is located between the substrate conductor part and the second conductor part, and the substrate conductor part is connected to the second conductor part through the intermediate connecting hole.

[0029] In a twenty-fourth possible implementation manner of the embodiment of the present application, the middle connecting hole is processed along the direction from the first surface to the substrate layer.

[0030] Compared with the prior art, the present invention has at least the following beneficial effects:

[0031] (1) The functional chip for a 3D chip provided in an embodiment of the present application has a substrate through-hole formed in the substrate layer; a first conductor is formed on the first surface of the metal layer, and a second conductor is formed on the second surface of the metal layer, and the first conductor and the second conductor are connected via a conductor connection hole in the metal layer; the second surface of the metal layer is disposed on the substrate layer, and the substrate through-hole is connected to the second conductor. During operation of the functional chip, a signal access terminal can be disposed in the substrate through-hole and connected to the second conductor, and the signal can be transmitted to the first conductor through the conductor connection hole; the signal access terminal can also be connected to the first conductor, connected to the second conductor through the conductor connection hole, and then the signal can be output through the substrate through-hole. This arrangement allows the signal to pass through the functional chip to manufacture a 3D chip and realize the function of the 3D chip. The functional chip for a 3D chip provided in the embodiment of the present application realizes signal transmission through the functional chip by sequentially connecting a first conductor member, a conductor connection hole, and a second conductor member from the top to the bottom of the functional chip. There is no need to set up a through-silicon via. It is only necessary to open a substrate through hole on the substrate and form a conductor connection hole in the metal layer to realize signal transmission through the functional chip, which greatly reduces the diameter and length of the hole, thereby reducing the difficulty of the etching process, reducing the area occupied by the metal layer, reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the functional chip, and reducing the production cost.

[0032] (2) The functional chip for a 3D chip provided in the embodiment of the present application can provide a functional circuit in the metal layer by providing a first conductor and a second conductor in the metal layer. The functional circuit can be connected to at least one of the first conductor and the second conductor. The first conductor and / or the second conductor connected to the functional circuit can transmit a signal to the functional circuit, and the functional circuit can further process the signal, thereby making the type and layout of the functional circuit in the metal layer more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0034] Figure 1 is a schematic structural diagram of a chip in an example;

[0035] Figure 2 A schematic structural diagram of a functional chip for a 3D chip according to an embodiment of the present application;

[0036] Figure 3 A schematic structural diagram of a functional chip for a 3D chip according to another embodiment of the present application;

[0037] Figure 4 A schematic structural diagram of a switching circuit for a functional chip of a 3D chip according to an embodiment of the present application;

[0038] Figure 5 A schematic structural diagram of a switching circuit for a functional chip of a 3D chip according to another embodiment of the present application;

[0039] Figure 6 A schematic structural diagram of a driving circuit for a functional chip of a 3D chip according to an embodiment of the present application;

[0040] Figure 7 A schematic structural diagram of a conversion circuit for a functional chip of a 3D chip according to an embodiment of the present application;

[0041] Figure 8 A schematic structural diagram of an arithmetic circuit of a functional chip for a 3D chip according to an embodiment of the present application;

[0042] Figure 9 A schematic structural diagram of a substrate through hole for a functional chip of a 3D chip according to another embodiment of the present application;

[0043] Figure 10 A schematic diagram of the lead connection structure of a functional chip for a 3D chip according to an embodiment of the present application;

[0044] Figure 11 A schematic diagram of a lead connection structure of a functional chip for a 3D chip according to another embodiment of the present application;

[0045] Figure 12 A schematic diagram of a lead connection structure of a functional chip for a 3D chip according to another embodiment of the present application;

[0046] Figure 13 A schematic structural diagram of a conductive dielectric filling layer for a functional chip of a 3D chip according to an embodiment of the present application;

[0047] Figure 14 This is a schematic structural diagram of a metal layer perforation component for a functional chip of a 3D chip according to an embodiment of the present application.

[0048] in, Figures 1 to 14 The corresponding relationship between the reference numerals and component names is as follows:

[0049] 100' through silicon via, 200' metal layer, 300' substrate layer;

[0050] 1 substrate layer, 2 metal layer, 3 first conductor, 4 second conductor, 5 substrate through hole, 6 conductor connection hole, 7 intra-chip conductor, 8 substrate conductor, 9 functional circuit, 10 lead, 11 metal filling layer, 12 conductor dielectric filling layer, 13 heat dissipation layer, 14 metal layer through-hole component;

[0051] 501 bottom through hole, 502 middle connecting hole;

[0052] 601 first through hole, 602 second through hole, 60N Nth through hole;

[0053] 701 first inner conductor, 702 second inner conductor, 703 Mth inner conductor;

[0054] 901 switching circuit, 9011 first switching module, 9012 second switching module, 9013 third switching module, 9014 fourth switching module;

[0055] 902 drive circuit, 9021 drive module;

[0056] 903 conversion circuit, 9031 parallel-to-serial conversion module;

[0057] 904 operation circuit, 9041 operation module. DETAILED DESCRIPTION

[0058] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0059] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0060] like Figure 1As shown, in some examples, a through-silicon via 100' (TSV) can be formed to penetrate the metal layer 200' and the substrate layer 300' to enable signal transmission through the functional chip. However, since the TSV 100' needs to pass through the entire functional chip, the diameter and length (or height) of the TSV 100' are relatively large, which may lead to high etching requirements, a very large chip area, large resistance and capacitance parasitic parameters, a long manufacturing cycle, and high costs.

[0061] In response to the above problems, an embodiment of the present application provides a functional chip for a 3D chip, which solves the problems that the chip through-hole structure has high requirements for etching technology, occupies a very large chip area, has large resistance parasitic parameters and capacitance parasitic parameters, has a long manufacturing cycle and high cost.

[0062] like Figure 2 and Figure 3 As shown, an embodiment of the present invention provides a functional chip for a 3D chip, including: a substrate layer 1, a metal layer 2, a metal layer through-hole component 14, a substrate through-hole 5 and a functional circuit 9.

[0063] The metal layer through-hole assembly 14 includes: a first conductor 3 , a second conductor 4 and a conductor connection hole 6 .

[0064] The metal layer 2 includes a first surface and a second surface arranged opposite to each other, and the second surface of the metal layer 2 is arranged on the substrate layer 1. It should be noted here that the metal layer 2 refers to the portion above the substrate layer 1. The second surface of the metal layer 2 refers to the side close to the substrate layer 1, and the first surface of the metal layer 2 refers to the side away from the substrate layer 1. The following parts are the same. The first conductor 3 is formed on the first surface of the metal layer 2; the second conductor 4 is formed on the second surface of the metal layer 2; the substrate through hole 5 is opened on the substrate layer 1 and connected to the second conductor 4 on the metal layer 2; the conductor connection hole 6 is formed in the metal layer 2, and the second conductor 4 is connected to the first conductor 3 through the conductor connection hole 6, so that the signal can be transmitted to the first surface through the substrate layer 1. The functional circuit is connected to at least one of the first conductor and the second conductor; the functional circuit 9 is connected to at least one of the first conductor 3 and the second conductor 4.

[0065] like Figure 2 and Figure 3As shown, in the functional chip for the 3D chip provided in the embodiment of the present application, during operation, the signal access end can be set in the substrate through hole 5 and connected to the second conductor part 4, and the signal can be transmitted to the first conductor part 3 through the conductor connection hole 6; based on the same principle, the signal access end can also be connected to the first conductor part 3, connected to the second conductor part 4 through the conductor connection hole 6, and then the signal is output through the substrate through hole 5. Such a setting can allow the signal to pass through the functional chip, which is convenient for the formation and construction of the 3D chip, that is, it is convenient to form a 3D chip by stacking the functional chips.

[0066] like Figure 2 and Figure 3 As shown, the functional chip for 3D chip provided in the embodiment of the present application realizes signal passing through the functional chip by sequentially connecting the first conductor part 3, the conductor connection hole 6, and the second conductor part 4 from the top to the bottom of the functional chip. There is no need to set up a through-silicon via. It is only necessary to open a substrate through hole 5 on the substrate and a metal layer perforation component 14 in the metal layer 2, which greatly reduces the diameter and length of the hole, thereby reducing the difficulty of the etching process, reducing the area occupied by the metal layer 2, reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the functional chip, and reducing the production cost.

[0067] like Figure 2 and Figure 3 As shown, the functional chip for the 3D chip provided in the embodiment of the present application can provide a functional circuit 9 in the metal layer 2 by providing a first conductor 3 and a second conductor 4 in the metal layer 2. The functional circuit 9 can be connected to at least one of the first conductor 3 and the second conductor 4. The first conductor 3 and / or the second conductor 4 connected to the functional circuit 9 can transmit signals to the functional circuit 9, and the functional circuit 9 can further process the signals, so that the type and layout of the functional circuit 9 in the metal layer 2 are more flexible.

[0068] In some examples, such as Figure 14 As shown, there can be multiple conductor connection holes 6. Figure 3 The middle dots represent the conductor connection holes that are partially omitted. Figure 3 The middle conductor connection hole 6 includes a first through hole 601 , a second through hole 602 , and an Nth through hole 60N. The first conductor 3 is connected to the second conductor 4 through the first through hole 601 , the second through hole 602 , and the Nth through hole 60N in sequence.

[0069] In some examples, the functional chip may be a component composed of multiple planar chips, or may be a separate planar chip.

[0070] In some examples, the first conductor 3 may be a metal wire or a metal surface formed on the first surface of the metal layer 2 ; the second conductor 4 may be a metal wire or a metal surface formed on the second surface of the metal layer 2 .

[0071] In some examples, the conductor connection hole 6 may include a through hole and a connection column, wherein the through hole is opened in the metal layer 2 and the connection column is a metal column filled in the through hole. The first conductor 3 and the second conductor 4 can be connected by the metal column to achieve signal transmission.

[0072] It is understood that the thickness of the substrate layer 1 is usually greater than the thickness of the metal layer 2. Figure 2 、 Figure 3 and Figures 9 to 14 The thickness of the middle metal layer 2 is greater than that of the substrate layer 1 in order to clearly show the internal structure of the metal layer 2 .

[0073] In some examples, the metal layer perforation component 14 also includes: an on-chip conductor part 7, arranged in the metal layer 2, located between the first conductor part 3 and the second conductor part 4; wherein, there are multiple conductor connection holes 6, the second conductor part 4 is connected to the on-chip conductor part 7 through some of the multiple conductor connection holes 6, and the on-chip conductor part 7 is connected to the first conductor part 3 through some of the multiple conductor connection holes 6.

[0074] like Figure 2 、 Figure 3 and Figures 9 to 14 As shown, the on-chip conductor 7 is disposed between the first conductor 3 and the second conductor 4. The second conductor 4 is connected to the on-chip conductor 7 via a conductor connection hole 6, and the on-chip conductor 7 is connected to the first conductor 3 via a conductor connection hole 6. During operation of the functional chip, an external signal input terminal can be disposed within the substrate through-hole 5 and transmitted to the second conductor 4. The second conductor 4 is then connected to the on-chip conductor 7 and then to the first conductor 3. Alternatively, an external signal input terminal can be connected to the first conductor 3 and then transmitted to the second conductor 4 via the conductor connection hole 6 and the on-chip conductor 7. This arrangement allows signals to pass through the functional chip, facilitating the formation and construction of 3D chips.

[0075] like Figure 2 and Figure 3 As shown, the on-chip conductor part 7 is arranged between the first conductor part 3 and the second conductor part 4, so that the first conductor part 3 and the second conductor part 4 can be connected to the on-chip conductor part 7 through multiple conductor connection holes 6, further shortening the length of the conductor connection hole 6, and reducing the diameter of the conductor connection hole 6, further reducing the difficulty of the etching process, reducing the area occupied by the metal layer 2, reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the functional chip, and reducing the production cost.

[0076] In some examples, such as Figure 14 As shown, there may be multiple conductor connection holes 6 and multiple conductor parts 7 on the chip. Figure 3 The middle dots represent the conductor connection holes and conductor parts on the chip that are partially omitted. Figure 3 The conductor connection holes 6 include a first through-hole 601, a second through-hole 602, and finally an Nth through-hole 60N. The on-chip conductive component 7 includes a first on-chip conductive component 701, a second on-chip conductive component 702, and finally an Mth on-chip conductive component 70M. One side of the first on-chip conductive component 701 is connected to the second on-chip conductive component 4 via the first through-hole 601, and the other side of the first on-chip conductive component 701 is connected to the second on-chip conductive component 702 via the second through-hole 602. This arrangement is repeated, with adjacent on-chip conductive components connected via the conductor connection holes, until the Mth on-chip conductive component 70M is connected to the first conductive component 3 via the Nth through-hole 60N. This connects the first conductive component 3 to the second conductive component 4, enabling signal transmission through the functional chip 100. M = N-1.

[0077] In some examples, the conductor connection hole 6 may include a through-hole and a connection pillar. The through-hole is provided in the metal layer 2, and the connection pillar is a metal pillar filled in the through-hole. The first conductor 3 and the on-chip conductor 7 can be connected via the metal pillar; the second conductor 4 and the on-chip conductor 7 can be connected via the metal pillar; and adjacent on-chip conductors 7 can be connected via the metal pillar.

[0078] In some examples, the on-chip conductor 7 may be a metal line or a metal surface formed in the metal layer 2 .

[0079] It is understandable that Figure 2 、 Figure 3 and Figures 9 to 14 The three dots in FIG. 7 represent omitted on-chip conductor parts 7 and conductor connection holes 6 .

[0080] like Figure 2 and Figure 3 As shown, in some examples, the functional circuit 9 is connected to at least one of the first conductor 3 , the second conductor 4 and the on-chip conductor 7 .

[0081] In some examples, a functional circuit can be set in the metal layer 2 by setting at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7 in the metal layer 2. The functional circuit can be connected to at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7. The first conductor 3, the second conductor 4 or the on-chip conductor 7 connected to the functional circuit can transmit signals to the functional circuit, and the functional circuit can further process the signals, making the type and layout of the functional circuit in the metal layer 2 more flexible.

[0082] like Figure 2 and Figure 3 As shown, the functional circuit 9 can be connected to at least one of the first conductor 3, the second conductor 4, and the on-chip conductor 7, facilitating access to the functional circuit 9. At the same time, signals from outside the functional chip can be transmitted to any one of the first conductor 3, the second conductor 4, and the on-chip conductor 7 through the first conductor 3, the second conductor 4, or the on-chip conductor 7, allowing the functional module to process external signals (signals external to the functional chip), making signal processing of the perforation unit more flexible and improving the applicability of the perforation unit.

[0083] In some examples, it is understandable that, in the case where the functional chip includes the substrate conductor 8 , some devices in the functional circuit 9 may also be connected to or located on the substrate conductor 8 .

[0084] In some examples, the signal transmitted to the functional circuit 9 through at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7 can be an internal signal within the metal layer 2, or an external signal from outside the functional chip. The external signal can be introduced into the functional circuit 9 through the metal layer through the first conductor 3 and / or the second conductor 4 and / or the on-chip conductor 7.

[0085] In some examples, when the signal input and output of the functional circuit 9 are connected to the same one of the first conductor 3 , the second conductor 4 and the on-chip conductor 7 , the access points of the signal input and output of the functional circuit 9 are different.

[0086] In this embodiment, the signal input end and the signal output end of the functional circuit 9 can be connected to the same one of the first conductor 3, the second conductor 4 and the on-chip conductor 7, so that more functional circuits 9 can be connected through the first conductor 3, the second conductor 4 and the on-chip conductor 7, which can facilitate signal processing of the functional circuit 9.

[0087] In this embodiment, when the signal input end and the signal output end of the functional circuit 9 are connected to the same one of the first conductor 3, the second conductor 4 and the on-chip conductor 7, the access points of the signal input end and the signal output end of the functional circuit 9 are different, which facilitates the input and output of signals, can prevent the input signal and the output signal from interfering with each other, and further improves the signal processing or transmission performance of the metal layer 2.

[0088] In some examples, the functional chip for the 3D chip further includes: an internal signal input terminal connected to the functional circuit 9 .

[0089] In this embodiment, the internal signal input terminal is provided to transmit the signal inside the metal layer 2 to the functional circuit 9, so that the functional circuit 9 can simultaneously process the signal outside the metal layer 2 and the internal signal, further improving the processing capability of the functional circuit 9.

[0090] like Figure 2 、 Figure 4 and Figure 5 As shown, in some examples, the functional circuit 9 includes a switching circuit 901, and the switching circuit 901 includes: at least two parallel switching modules, the signal input end and / or the signal output end of each switching module is connected to at least one of the first conductor 3, the second conductor 4 and / or the on-chip conductor 7; a first control switch, each switching module is provided with at least one first control switch, and the control switch is used to control the working state of the signal input end or the signal output end of the switching module.

[0091] In this embodiment, the functional circuit 9 includes a switching circuit 901. The external signal is transmitted to at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7 through the first conductor 3 and / or the second conductor 4 and / or the on-chip conductor 7. The signal then enters the switching circuit 901, and the target switching module can be selected through the first control switch to output the signal, making the signal processing or transmission of the functional chip more flexible and improving the applicability of the functional chip.

[0092] In some examples, multiple switching modules are connected to the same signal input terminal; and / or multiple switching modules are connected to the same signal output terminal.

[0093] In some examples, each switching module may be connected to a signal input terminal, and each switching module may be connected to a signal output terminal. Such a configuration can ensure the independence of the signal input.

[0094] In some examples, multiple switching modules or some of the switching modules in multiple switching modules can share a signal input end; multiple switching modules or some of the switching modules in multiple switching modules can also share a signal output end. Such a setting can reduce access points and facilitate the layout of the switching circuit.

[0095] In this embodiment, multiple switching modules are connected to the same signal input terminal. During use, the signal input terminal can be connected to only one of the first conductor 3, the second conductor 4 and the on-chip conductor 7, which facilitates the access of the switching circuit 901.

[0096] In this embodiment, multiple switching modules are connected to the same signal output end. During use, the signal output end can be connected to only one of the first conductor 3, the second conductor 4 and the on-chip conductor 7, so as to facilitate the output of the signal of the switching circuit 901.

[0097] In this embodiment, multiple switching modules are connected to the same signal input end and / or multiple switching modules are connected to the same signal output end, which can reduce the access points of the switching circuit 901 and facilitate the setting of the switching circuit 901. At the same time, more circuits can be arranged through the first conductor 3, the second conductor 4 and the on-chip conductor 7, making the layout of the functional chip more flexible and improving the applicability of the functional chip.

[0098] In some examples, the functional circuit 9 includes a driving circuit 902 , which includes a driving module 9021 , wherein the signal input and / or signal output of the driving module 9021 is connected to at least one of the first conductor 3 , the second conductor 4 and the on-chip conductor 7 .

[0099] like Figure 2 and Figure 6 As shown, in this embodiment, the functional circuit 9 includes a driving circuit 902. Taking into account that the signal may be attenuated during transmission, the signal is connected to the driving module 9021 through at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7. After being driven and enhanced by the driving module 9021, the signal is output through the output end of the driving signal, which can ensure the smoothness of signal transmission and further improve the performance of the functional chip.

[0100] It should be noted that the driving module 9021 in the figure is two inverters connected in series. In practice, the number of inverters can be an odd number, such as one inverter (the signal will be inverted); or an even number, such as two inverters here.

[0101] In some examples, the functional circuit 9 includes a conversion circuit 903 , which includes: a conversion module, wherein the signal input end and / or the signal output end of the conversion module are connected to at least one of the first conductor 3 , the second conductor 4 and the on-chip conductor 7 .

[0102] like Figure 2 and Figure 7 As shown, in this embodiment, the signal can be transmitted to the conversion circuit 903 through at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7. The signal is converted by the conversion circuit 903 and then output through the conversion module, thereby realizing signal processing.

[0103] In some examples, the conversion module is a serial-to-parallel conversion module or a parallel-to-serial conversion module 9031 .

[0104] In this embodiment, the conversion module can be a serial-parallel conversion module. The signal is transmitted to the series signal end through at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7. After passing through the serial-parallel conversion module, the signal is output through the parallel signal port, which can improve the efficiency of signal transmission.

[0105] like Figure 2 and Figure 7 As shown, in this embodiment, the conversion module can also be a parallel-to-serial conversion module 9031. The signal is transmitted to the parallel signal end through at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7. After passing through the parallel-to-serial conversion module 9031, the signal is output through the serial signal end. After multiple signals are converted into parallel-to-serial, the signal transmission line can be reduced, thereby improving the signal transmission efficiency.

[0106] In some examples, the functional circuit includes an operation circuit, which includes: an operation module, wherein a signal input terminal and / or a signal output terminal of the operation module is connected to at least one of the first conductor, the second conductor, and the on-chip conductor.

[0107] like Figure 2 and Figure 8 As shown, in this embodiment, the functional circuit 9 includes an operation circuit 904, and the operation circuit 904 includes: an operation module 9041, and the signal input end and / or signal output end of the operation module 9041 is connected to at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7.

[0108] In some examples, the functional chip for the 3D chip further includes: a second control switch connected to the operation module 9041 , for controlling the working states of the signal input terminal and the signal output terminal of the operation module 9041 .

[0109] like Figure 2 and Figure 8 As shown, by setting the second control switch, the working states of the signal input terminal and the signal output terminal of the operation module 9041 can be controlled, which is used to control the input and output of the signal, making the control method of the operation module 9041 more flexible.

[0110] In some examples, there are multiple on-chip conductor parts 7 , and the multiple on-chip conductor parts 7 are spaced apart between the first conductor part 3 and the second conductor part 4 . Adjacent on-chip conductor parts 7 are connected through some of the multiple conductor connection holes 6 .

[0111] like Figure 2 、 Figure 3 and Figures 9 to 14As shown, there are multiple on-chip conductor parts 7, and the multiple on-chip conductor parts 7 are spaced apart between the first conductor part 3 and the second conductor part 4. The second conductor part 4 is connected to the first conductor part 3 through the multiple on-chip conductor parts 7 and the multiple conductor connection holes 6, which can further shorten the length and diameter of each conductor connection hole 6, further reduce the difficulty of the etching process, reduce the area occupied by the metal layer 2, reduce the resistance parasitic parameters and the capacitance parasitic parameters, shorten the preparation cycle of the functional chip, and reduce the production cost.

[0112] It should be noted that, in practice, the first conductor 3 , the second conductor 4 and the multiple on-chip conductors 7 are different metal layers in the chip, and the conductor connection holes 6 are connection through holes between different metal layers.

[0113] In some examples, a conductor connection hole 6 is provided between two adjacent on-chip conductor members 7 .

[0114] like Figure 2 and Figure 3 As shown, a conductor connection hole 6 is provided between each two adjacent on-chip conductor parts 7. On the one hand, it is convenient for processing the conductor connection hole 6 and preparing the functional chip; on the other hand, the two adjacent on-chip conductor parts 7 can transmit and receive signals through a conductor connection hole 6 to ensure the stability of signal transmission and reception.

[0115] In some examples, a conductor connection hole 6 is provided between the first conductor 3 and the adjacent on-chip conductor 7 .

[0116] like Figure 2 and Figure 3 As shown, the first conductor part 3 is connected to the on-chip conductor part 7 adjacent to the first conductor part 3 through a conductor connection hole 6. On the one hand, it is convenient for processing the conductor connection hole 6 and preparing the functional chip; on the other hand, the first conductor part 3 and the on-chip conductor part 7 can transmit and receive signals through a conductor connection hole 6 to ensure the stability of signal transmission and reception.

[0117] In some examples, a conductor connection hole 6 is provided between the second conductor 4 and the adjacent on-chip conductor 7 .

[0118] like Figure 2 and Figure 3 As shown, the second conductor part 4 is connected to the on-chip conductor part 7 adjacent to the second conductor part 4 through a conductor connection hole 6. On the one hand, it is convenient for processing the conductor connection hole 6 and preparing the functional chip; on the other hand, the second conductor part 4 and the on-chip conductor part 7 can transmit and receive signals through a conductor connection hole 6 to ensure the stability of signal transmission and reception.

[0119] In some examples, the difference between the number of conductor connection holes 6 and the number of conductor connection members is 1.

[0120] like Figure 2 and Figure 3 As shown, a conductor connection hole 6 is provided between each two adjacent on-chip conductor parts 7, a conductor connection hole 6 is provided between the first conductor part 3 and the on-chip conductor part 7, and a conductor connection hole 6 is provided between the second conductor part 4 and the on-chip conductor part 7. The difference between the number of conductor connection holes 6 and the number of conductor connectors is 1, so that the metal layer perforation component 14 can be arranged along the height direction of the metal layer 2, which can reduce the space occupied by the metal layer perforation component 14, further reduce the resistance parasitic parameters and the capacitance parasitic parameters, shorten the preparation cycle of the functional chip, and reduce the production cost.

[0121] In some examples, the cross-section of the substrate through hole 5 along the substrate height direction is a polygon, and the length of the first side of the polygon close to the metal layer 2 is shorter than the length of the second long side of the polygon away from the metal layer 2 .

[0122] like Figure 2 As shown, the cross-section of the substrate through hole 5 is a polygon, and the length of the first side of the polygon close to the metal layer 2 is smaller than the length of the second long side of the polygon away from the metal layer 2, so that one end of the substrate through hole 5 is a flared end and the other end is a closed end, and the closed end is arranged toward the side of the metal layer 2, which is convenient for the opening of the substrate through hole 5 and the filling of the conductor dielectric filling layer 12 into the substrate through hole 5. It can be understood that the conductor dielectric filling can dissipate heat for the functional chip.

[0123] In some examples, the cross-section of the through substrate via 5 along the substrate height direction is trapezoidal.

[0124] like Figure 2 and Figure 3 As shown, the cross section of the substrate through hole 5 is trapezoidal, which further facilitates the opening of the substrate through hole 5 .

[0125] In some examples, the short side of the trapezoid is located on a side of the substrate layer 1 close to the metal layer 2 , and the long side of the trapezoid is located on a side of the substrate layer 1 far from the metal layer 2 .

[0126] like Figure 3 As shown, the short side of the trapezoid is located on the side of the substrate layer 1 close to the metal layer 2, and the long side of the trapezoid is located on the side of the substrate layer 1 away from the metal layer 2. When the conductor dielectric filling layer 12 is filled into the substrate through hole 5, the flared end is set away from the side of the metal layer 2, which is convenient for setting the conductor dielectric filling material into the substrate through hole 5, and at the same time can improve the filling rate of the filling material, which can further ensure the yield rate of the functional chip.

[0127] In some examples, the substrate through hole 5 is truncated cone-shaped, which facilitates the excavation of the substrate through hole 5 and makes the anisotropy of the substrate through hole 5 substantially uniform, thereby further improving the performance of the functional chip.

[0128] In some examples, the truncated cone includes a first end face and a second end face, the diameter of the first end face is smaller than the diameter of the second end face, the first end face is located on the side of the substrate layer 1 close to the metal layer 2, and the second end face is located on the side of the substrate layer 1 away from the metal layer 2.

[0129] like Figure 2 and Figure 3 As shown, the truncated cone shape includes a first end face and a second end face, the diameter of the first end face is smaller than the diameter of the second end face, so that the first end face is a closed end and the second end face is a flared end, and the closed end of the truncated cone is arranged toward the metal layer 2, which is convenient for setting the conductor dielectric filling material into the substrate through hole 5, and at the same time can improve the filling rate of the filling material, which can further ensure the yield rate of the functional chip.

[0130] In some examples, the conductor connection hole 6 is columnar.

[0131] like Figure 2 、 Figure 3 and Figures 9 to 14 As shown, the conductor connection hole 6 is columnar. On the one hand, it is convenient for the production and processing of the conductor connection hole 6. On the other hand, the conductor connection hole 6 serves as a carrier for connecting two adjacent on-chip conductor parts 7, the on-chip conductor part 7 and the first conductor part 3, and the on-chip conductor part 7 and the second conductor part 4. The columnar design can make the signal transmission capabilities at both ends of the conductor connection hole 6 consistent, thereby ensuring the stability of the signal transmission of the functional chip.

[0132] In some examples, the functional chip for the 3D chip also includes: a substrate conductor part, which is arranged in the substrate layer; the substrate through hole includes a bottom through hole and an intermediate connection hole, the bottom through hole is opened at the bottom of the substrate and is connected to the substrate conductor part, the intermediate connection hole is located between the substrate conductor part and the second conductor part, and the substrate conductor part is connected to the second conductor part through the intermediate connection hole.

[0133] like Figure 2 、 Figure 3 、 Figure 9 、 Figure 11 and Figure 13 As shown, the substrate conductor 8 is disposed in the substrate layer 1. The substrate through-hole 5 includes a bottom through-hole 501 and a middle connecting hole 502.

[0134] like Figure 2 、 Figure 3 、 Figure 9 、 Figure 11 and Figure 13As shown, during the operation of the functional chip, the input end of the signal can be set in the bottom through hole 501 and connected to the substrate conductor part 8, the substrate conductor part 8 is connected to the second conductor part 4 through the intermediate connection hole 502, and the second conductor part 4 is connected to the first conductor part 3; the input end of the signal can also be connected to the first conductor part 3, the first conductor part 3 is connected to the second conductor part 4, and the second conductor part 4 is then connected to the substrate conductor part 8 through the intermediate connection hole 502. This arrangement allows the signal to pass through the functional chip, which is convenient for the formation and construction of the 3D chip.

[0135] In some examples, the middle connecting hole is processed along the direction from the first surface to the substrate layer.

[0136] like Figure 2 、 Figure 3 、 Figure 9 、 Figure 11 and Figure 13 As shown, the substrate conductor 8 is arranged in the substrate, dividing the substrate through hole 5 into a bottom through hole 501 and an intermediate connection hole 502. The intermediate connection hole 502 is processed along the first surface toward the substrate layer 1 to facilitate the opening of the intermediate connection hole 502. Figure 2 or Figure 3 The substrate through hole 5 can reduce the length and diameter of the substrate through hole 5, thereby reducing the difficulty of the etching process, reducing the area occupied by the metal layer 2 chip (the plane area of ​​the chip), reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the functional chip, and reducing the production cost.

[0137] It is understandable that in the entire functional chip, the thickness of the substrate is usually very large, so the height of the substrate through hole is much greater than the height of the conductor connection hole 6. By adding a buried metal layer, the height of the bottom through hole 501 can be greatly reduced.

[0138] In this embodiment, the substrate layer 1 typically requires thinning before perforation. However, by providing the substrate conductor 8 in this embodiment, the substrate layer 1 does not need to be thinned very much, and even bottom via 501 can be processed without thinning. Furthermore, because bottom via 501 does not need to pass through the entire substrate layer 1, perforation time is reduced, costs are reduced, and perforation yield and reliability are improved.

[0139] like Figure 2 As shown, the substrate through hole 5 is divided into a bottom through hole 501 and an intermediate connection hole 502 by the substrate conductor 8 , which further reduces the depth of the bottom through hole 501 and facilitates the opening of the bottom through hole 501 .

[0140] In some examples, the middle connection hole 502 may be a connection hole formed by an etching process.

[0141] In some examples, the middle connection hole 502 may include a through hole and a connection column disposed in the through hole, wherein the connection column is a metal column. The second conductor 4 and the substrate conductor 8 may be connected via the metal column.

[0142] In some examples, the function chip for the 3D chip further includes leads, and the leads 10 are connected to the first conductor 3 or the second conductor 4. When the function chip includes the substrate conductor 8, the leads 10 are connected to the second conductor 4 through the substrate conductor 8.

[0143] like Figure 10 As shown, the lead 10 is connected to the first conductor 3 on the front side of the functional chip; Figure 11 As shown, the lead 10 is connected to the second conductor 4 through the substrate conductor 8 on the back of the functional chip; there can also be two leads 10, which are respectively connected to the first conductor 3 and the substrate conductor 8.

[0144] like Figures 10 to 13 As shown, in the functional chip for a 3D chip provided in an embodiment of the present application, the leads 10 are connected to the first conductor 3 and / or the second conductor 4, and the first conductor 3 and the second conductor 4 are connected via the conductor connection hole 6. In this way, the leads 10 are used to input signals into the metal layer 2, to lead signals from the metal layer 2 via the leads 10, and to transmit external signals through the substrate layer 1 and the metal layer 2. The functional chip can lead out the leads 10 via the front surface and / or the back surface of the functional chip, making the wiring method of the functional chip more flexible, especially reducing the area of ​​the front surface of the functional chip occupied by the leads 10, saving the area of ​​the metal layer 2 on the front surface of the functional chip, and making the layout and arrangement of the leads 10 simpler.

[0145] The front side of the functional chip is the first surface of the metal layer 2 ; the back side of the functional chip is the side of the substrate layer 1 that is away from the second surface.

[0146] like Figure 10 and Figure 13 As shown, in this embodiment, a metal filling layer 11 is further included. The arrangement of the metal filling layer 11 facilitates the arrangement of the lead 10 and makes the fixation of the lead 10 more stable.

[0147] In some examples, when the lead 10 is connected to the metal filling layer 11 , the lead 10 and the metal filling layer 11 constitute a pad structure.

[0148] It can be understood that, for the functional chip provided in the embodiment of the present application, since leads 10 can be led out from both the front and back sides of the functional chip, the layout of the leads 10 can be performed based on the different types of leads 10, for example, the data signal can be led out from the first conductor 3, and the command signal can be led out from the second conductor 4.

[0149] like Figure 11 As shown, in this embodiment, when the lead 10 is led out through the back of the functional chip, the lead 10 can be connected to the substrate conductor 8, and the substrate conductor 8 is connected to the second conductor 4 through the intermediate connection hole 502. In this way, it is possible to input signals into the metal layer 2, lead out signals from the metal layer 2 through the lead 10, and transmit external signals through the substrate layer 1 and the metal layer 2. This allows the functional chip to lead out the lead 10 through the front and / or back of the functional chip.

[0150] like Figure 12 As shown, in some examples, the functional chip further includes: a conductor dielectric filling layer 12 filled in the substrate through hole 5 .

[0151] like Figure 13 As shown, when the functional chip includes a substrate conductor member 9 and the substrate through hole 5 includes an intermediate connection hole 502 and a bottom through hole 501 , the conductor dielectric filling layer 12 is filled in the bottom through hole 501 .

[0152] like Figure 12 and Figure 13 As shown, in this embodiment, a conductive dielectric filling layer 12 is further included. The heat dissipation dielectric is filled in the substrate through-hole 5. The heat generated in the metal layer 2 can be transferred to the heat dissipation dielectric layer, and the heat can be dispersed through the heat dissipation dielectric layer. In this way, the functional chip can be cooled and cooled, thereby improving the performance of the functional chip.

[0153] like Figure 12 and Figure 13 As shown, in some examples, the substrate through hole 5 includes a closed end and a flared end, and the closed end is located on one side of the second conductor part 4. Such a setting can, on the one hand, improve the heat dissipation effect of the conductor dielectric filling layer 12 and facilitate the filling of the conductor dielectric filling layer 12; on the other hand, it is convenient for the lead 10 to be connected to the second conductor part 4 or the substrate conductor part 8.

[0154] like Figure 12 and Figure 13 As shown, in some examples, the functional chip further includes: a heat dissipation layer 13 covering the conductive dielectric filling layer 12 .

[0155] like Figure 12 and Figure 13 As shown, in this embodiment, a heat dissipation layer 13 is further included. By covering the heat dissipation medium layer with the heat dissipation layer 13, the heat dissipation effect can be further improved.

[0156] like Figure 12 and Figure 13As shown, in some examples, part of the heat dissipation layer 13 is covered on the substrate layer 1, so that the cross-sectional area of ​​the heat dissipation layer 13 is larger than the cross-sectional area of ​​the conductor dielectric filling layer 12, which can further improve the heat dissipation effect and facilitate the connection of the heat dissipation layer 13 to other fixing parts, specifically the fixing part can be a substrate.

[0157] In some examples, the functional chip further includes: a conductor dielectric filling layer 12 made of a metal material and / or a heat dissipation layer 13 made of a metal material.

[0158] In this embodiment, the conductor dielectric filling layer 12 is made of metal material, so that the conductor dielectric filling layer 12 has the heat dissipation effect while taking into account the signal transmission ability. The lead 10 can be connected to the conductor dielectric filling layer 12, or the lead 10 can be omitted and the conductor dielectric filling layer 12 can be directly used as a signal transmission port.

[0159] In this embodiment, the heat dissipation layer 13 is made of metal material, so that the heat dissipation layer 13 has the heat dissipation effect while taking into account the signal transmission ability. The lead 10 can be connected to the conductor medium filling layer 12, or the lead 10 can be omitted and the heat dissipation layer 13 can be directly used as the signal transmission port.

[0160] It is understandable that Figures 10 to 14 The three dots in FIG. 7 represent omitted on-chip conductor parts 7 and conductor connection holes 6 . Specific embodiment 1

[0162] like Figure 2 and Figure 3 As shown, an embodiment of the present invention provides a functional chip for a 3D chip, including: a substrate layer 1, a metal layer 2, a metal layer through-hole component 14, a substrate through-hole 5, a substrate conductor 8, and a functional circuit 9.

[0163] The metal layer through-hole assembly 14 includes: a first conductor 3 , a second conductor 4 , a conductor connection hole 6 and an on-chip conductor 7 .

[0164] Among them, the metal layer 2 includes a first surface and a second surface arranged opposite to each other, and the second surface of the metal layer 2 is arranged on the substrate layer 1; the first conductor 3 is formed on the first surface of the metal layer 2; the second conductor 4 is formed on the second surface of the metal layer 2; the substrate through hole 5 is opened on the substrate layer 1 and connected to the second conductor 4 of the metal layer 2; the conductor connection hole 6 is formed in the metal layer 2, and the second conductor 4 is connected to the first conductor 3 through the conductor connection hole 6; the on-chip conductor 7 is arranged in the metal layer 2, located between the first conductor 3 and the second conductor 4; the substrate conductor 8 is arranged in the substrate layer 1; the functional circuit 9 is connected to at least one of the first conductor 3, the second conductor 4 and the on-chip conductor 7.

[0165] There are multiple conductor connection holes 6, the second conductor part 4 is connected to the on-chip conductor part 7 through some of the multiple conductor connection holes 6, and the on-chip conductor part 7 is connected to the first conductor part 3 through some of the multiple conductor connection holes 6.

[0166] Among them, there are multiple on-chip conductor parts 7, and the multiple on-chip conductor parts 7 are arranged at intervals between the first conductor part 3 and the second conductor part 4. Adjacent on-chip conductor parts 7 are connected through some of the multiple conductor connection holes 6 so that the signal can be transmitted to the first surface through the substrate layer 1.

[0167] Among them, the substrate through hole 5 includes a bottom through hole 501 and an intermediate connecting hole 502. The bottom through hole 501 is opened at the bottom of the substrate and is connected to the substrate conductor part 8. The intermediate connecting hole 502 is located between the substrate conductor part 8 and the second conductor part 4. The substrate conductor part 8 is connected to the second conductor part 4 through the intermediate connecting hole 502; the intermediate connecting hole 502 is processed along the first surface toward the substrate layer 1.

[0168] In some examples, the functional circuit 9 may include one or more of a switching circuit 901 , a driving circuit 902 , a conversion circuit 903 , and an operation circuit 904 .

[0169] In this embodiment, considering that the first conductor 3, the second conductor 4 and the on-chip conductor 7 are connected through the conductor connection hole 6, the first conductor 3, the second conductor 4 and the on-chip conductor 7 can be used to connect the functional circuit 9 inside the functional chip.

[0170] like Figure 2 and Figure 3 As shown, the functional circuit 9 is connected via the on-chip conductor 7 within the chip, the signal is input to the functional circuit 9 through the on-chip conductor 7, and the output of the functional circuit 9 transmits the signal to other on-chip conductors 7. It is understandable that the input and output of the functional circuit 9 can be connected to the same on-chip conductor 7.

[0171] Furthermore, the function of the switching circuit 901 is to enable the signal of the penetrating functional chip to be output after function switching.

[0172] like Figure 4As shown, the switching circuit 901 includes a first switching module 9011 and a second switching module 9012 arranged in parallel. The first control switch includes a first switch K11, a second switch K12, a third switch K13, and a fourth switch K14. The first switch K11 is provided on the signal input side of the first switching module 9011, and the second switch K12 is provided on the signal output side of the first switching module 9011. The third switch K13 is provided on the signal input side of the second switching module 9012, and the fourth switch K14 is provided on the signal output side of the first switching module 9011. The first switching module 9011 and the second switching module 9012 share a signal input and a signal output. During operation, signal A is selected by the first control switch, processed by the first switching module 9011 or the second switching module 9012, and then output as signal B after selection by the first control switch.

[0173] like Figure 5 As shown, the switching circuit 901 includes a third switching module 9013 and a fourth switching module 9014 arranged in parallel. The first control switch includes a fifth switch K15, a sixth switch K16, a seventh switch K17, and an eighth switch K18. The fifth switch K15 is provided on the signal input side of the third switching module 9013, and the sixth switch K16 is provided on the signal output side of the third switching module 9013. The seventh switch K17 is provided on the signal input side of the fourth switching module 9014, and the eighth switch K18 is provided on the signal output side of the fourth switching module 9014. The first switching module 9011 and the second switching module 9012 each have a signal input terminal, and the first switching module 9011 and the second switching module 9012 share a signal output terminal. During operation, signal C is processed by the third switching module 9013 after being selected by the first control switch, and / or signal D is processed by the fourth switching module 9014 after being selected by the first control switch. The processed signal E is output via the signal output terminal after passing through the first control switch.

[0174] By configuring the switching circuit 901 , the input perforation can be functionally processed, thereby improving the flexibility of the signal and providing more options for signal transmission and processing.

[0175] like Figure 6 As shown, the signal F is driven by the driving module 9021 and then outputted as the signal G, which can increase the driving capability of the signal.

[0176] like Figure 7 As shown, Figure 8The dots between H2 and Hn indicate that some input signals have been omitted. The input signals are parallel signals H1, H2, ..., and Hn. After passing through the parallel-to-serial conversion module, they are converted into a serial signal I for output. Similarly, a serial-to-parallel conversion method can also be employed. In this method, the input signal is serial signal I. After passing through the serial-to-parallel conversion module, it is converted into parallel signals H1, H2, ..., and Hn for output. The configuration of conversion circuit 903 allows for parallel-to-serial conversion of multiple signals, reducing signal transmission lines and improving signal transmission efficiency. Furthermore, it increases signal transmission bandwidth.

[0177] like Figure 8 As shown, the second control switch includes a ninth switch K21, a tenth switch K22, and an eleventh switch K23. The external input signal L is input to the computation module 9041 via the tenth switch K22; the internal signal is input to the computation module 9041 via the ninth switch K21; and after processing by the computation module 9041, it is output as the output signal M via the eleventh switch K23. It is understood that the second control switch can be added as needed. The configuration of the computation circuit 904 allows both the external input signal and the internal signal to be processed and output, improving signal flexibility and adding computational capabilities with internal signals.

[0178] In some examples, the operation module 9041 can be a module with data operation or other processing functions. Specific embodiment 2

[0180] like Figure 2 and Figure 3 As shown, based on the specific embodiment 1, improvements or extensions can be made in the conductor connection hole 6.

[0181] Since the conductor connection holes 6 utilize the metal and through-holes within a typical chip, the conductor connection holes 6 can be connected to an internal circuit to serve as a functional circuit 9 .

[0182] For example, Figure 4 By connecting units with certain functions through metal wires within the chip, the functional circuit 9 can process 3D signals (passing through the chip).

[0183] The function unit can act in the following ways:

[0184] 1. You can add switching circuits to increase your options;

[0185] 2. Driving function modules can be added;

[0186] 3. Can add parallel-serial (serial-parallel) conversion function;

[0187] 4. The internal signal calculation function can be added.

[0188] For switching circuits:

[0189] The core idea of ​​the switching circuit is that the signal that penetrates the chip is output after functional switching. Figure 5 and Figure 6 These are two implementations of the switching circuit. Signals A, C, and D are the input signals of the perforation (which can be signals from another chip or external signals), and signal B is the output signal after the perforation.

[0190] like Figure 4 , signal A is processed by function 1 or function 2 after being selected by the switch, and after processing, it is output by signal B after being selected by the switch.

[0191] like Figure 5 Signal C and signal D are processed by function 1 or function 2 after being selected by the switch, and after processing, they are output by signal E after being selected by the switch.

[0192] This has the advantage of being able to perform functional processing on the signal input to the metal layer through-hole component 14 , thereby improving the flexibility of the signal.

[0193] For the driver function module:

[0194] like Figure 6 , signal F drives the driving unit and then is output by signal G.

[0195] The advantage of this is that the signal driving capability can be increased.

[0196] For the parallel-to-serial (serial-to-parallel) conversion function:

[0197] like Figure 7 As shown, this is a parallel-to-serial conversion mode, where the input signals are parallel signals H1, H2...Hn, which are converted into serial signal I output after passing through the parallel-to-serial conversion processing module.

[0198] Similarly, a serial-to-parallel conversion method may also be used. In this method, the input signal is a serial signal I, which is converted into parallel signals H1, H2, ..., Hn after passing through the serial-to-parallel conversion processing module and then output.

[0199] The benefits of this are: Parallel-to-serial conversion: after multiple signals are converted into serial-to-parallel, the signal transmission lines are reduced and the signal transmission efficiency is improved. Serial-to-parallel conversion: it can increase the bandwidth of signal transmission.

[0200] For internal signal operation functions:

[0201] like Figure 8As shown, an external input signal L is input to the operation module 9041 via switch K21; an internal signal is input to the operation module 9041 via switch K22. The operation module 9041 may perform data calculations or other processing functions. After being processed by the operation module 9041, the signal is output via switch K23 as the output signal M. It is understood that switches K21, K22, and K23 are not essential and can be added as needed.

[0202] The advantage of this is that external input signals and internal signals can be output after functional processing, thereby improving signal flexibility.

[0203] In the description of the present invention, the term "plurality" refers to two or more than two. Unless otherwise expressly defined, the orientations or positional relationships indicated by the terms "upper" and "lower" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention. The terms "connect," "install," and "fix" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0204] In the description of the present invention, the terms "one embodiment," "some embodiments," "specific embodiments," etc., mean that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In the present invention, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0205] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A functional chip for a 3D chip, characterized in that: include: substrate layer; a metal layer, the metal layer comprising a first surface and a second surface opposite to each other, the second surface of the metal layer being disposed on the substrate layer; a metal layer through-hole component, disposed in the metal layer, the metal layer through-hole component comprising: a first conductor, a second conductor, and a conductor connection hole, wherein the first conductor is formed on the first surface of the metal layer, the second conductor is formed on the second surface of the metal layer, the conductor connection hole is formed in the metal layer, and the second conductor is connected to the first conductor through the conductor connection hole, so that a signal can be transmitted through the substrate layer to the first surface; a substrate through hole, formed on the substrate layer and connected to the second conductor; a functional circuit connected to at least one of the first conductor and the second conductor; an on-chip conductor component, located between the first conductor component and the second conductor component; There are a plurality of conductor connection holes, the second conductor member is connected to the on-chip conductor member through some of the plurality of conductor connection holes, and the on-chip conductor member is connected to the first conductor member through some of the plurality of conductor connection holes; One conductor connection hole is provided between each two adjacent on-chip conductor parts, one conductor connection hole is provided between the first conductor part and the on-chip conductor part, and one conductor connection hole is provided between the second conductor part and the on-chip conductor part, and the difference between the number of the conductor connection holes and the number of the on-chip conductor parts is 1; A substrate conductor member, disposed in the substrate layer; The substrate through hole includes a bottom through hole and an intermediate connecting hole, wherein the bottom through hole is opened at the bottom of the substrate and is connected to the substrate conductor member, and the intermediate connecting hole is located between the substrate conductor member and the second conductor member, and the substrate conductor member is connected to the second conductor member through the intermediate connecting hole, wherein the cross-section of the substrate through hole along the height direction of the substrate is a polygon, the length of the first side of the polygon close to the metal layer is less than the length of the second long side of the polygon away from the metal layer, one end of the substrate through hole is a flared end, and the other end is a closed end, and the closed end is arranged toward the metal layer side, wherein the conductor dielectric filling layer is filled in the bottom through hole; The functional circuit is connected to at least one of the first conductor, the second conductor, and the on-chip conductor; A heat dissipation layer is covered on the conductor dielectric filling layer, and the cross-sectional area of ​​the heat dissipation layer is larger than the area of ​​the conductor dielectric filling layer.

2. The functional chip for 3D chip according to claim 1, characterized in that: The functional circuit includes a switching circuit, and the switching circuit includes: at least two switching modules connected in parallel, wherein a signal input terminal and / or a signal output terminal of each switching module is connected to at least one of the first conductor, the second conductor, and the on-chip conductor; A first control switch: each switching module is provided with at least one first control switch, and the first control switch is used to control the working state of the signal input end or the signal output end of the switching module.

3. The functional chip for 3D chip according to claim 1, characterized in that: The functional circuit includes a driving circuit, and the driving circuit includes: A driving module, wherein a signal input terminal and / or a signal output terminal of the driving module is connected to at least one of the first conductor, the second conductor, and the on-chip conductor.

4. The functional chip for 3D chip according to claim 1, characterized in that: The functional circuit includes a conversion circuit, and the conversion circuit includes: A conversion module, wherein a signal input terminal and / or a signal output terminal of the conversion module is connected to at least one of the first conductor, the second conductor, and the on-chip conductor.

5. The functional chip for 3D chip according to claim 4, characterized in that: The conversion module is a serial-to-parallel conversion module or a parallel-to-serial conversion module.

6. The functional chip for 3D chip according to claim 1, characterized in that: The functional circuit includes an operation circuit, and the operation circuit includes: A computing module, wherein a signal input terminal and / or a signal output terminal of the computing module is connected to at least one of the first conductor, the second conductor, and the on-chip conductor.

7. The functional chip for 3D chip according to claim 1, characterized in that: There are a plurality of on-chip conductor parts, and the plurality of on-chip conductor parts are spaced apart and arranged between the first conductor part and the second conductor part. Adjacent on-chip conductor parts are connected through some of the plurality of conductor connection holes.

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