Memory chips and 3D memory chips

Abstract

The embodiments of the present application provide a memory chip and a 3D memory chip to solve the problems of large parasitic resistance and capacitance of existing memory chips, high manufacturing cost, large RC delay, high power consumption, and poor heat dissipation caused by the use of silicon through-hole via technology. The above-mentioned memory chip includes a memory part and a control part stacked on each other, and the above-mentioned memory part is connected to the above-mentioned control part by a hybrid bonding method. The above-mentioned hybrid bonding method is to connect the connection pad of the above-mentioned memory part and the connection pad of the above-mentioned control part by a metal conductor.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of memory technology, and in particular, to a memory chip and a 3D memory chip. Background Art

[0002] At present, memory chips, especially DRAM memory chips, are mainly divided into planar DRAM and three-dimensional stacked DRAM formed by using 3DS (3-Dimensional Stack) technology.

[0003] For planar DRAM, see Figure 1 In the example of planar DRAM shown, the memory array part (Bank1-Bank4) and the control circuit are on one chip. The memory array part usually includes memory cells, and the control circuit usually includes functional circuits such as decoding circuit, data writing circuit and data reading circuit.

[0004] Due to manufacturing process limitations, especially the manufacturing process limitations of storage capacitors, planar DRAM has large parasitic resistance and capacitance in the memory chip, which affects the processing performance of the functional circuits in the memory chip. Therefore, it has the defects of slow speed, high power consumption, and poor ability to process data in parallel.

[0005] In three-dimensional stacked DRAM, the more common method is to connect various storage parts based on TSV (Through-Silicon-Via) technology. TSV technology can be used to stack various storage layers, and there will be metal layers between the layers. The most typical examples are HBM (High Bandwidth Memory) and HMC (Hybrid Memory Cube). However, both HBM and HMC use silicon interposers, so the cost is very high, and there are also problems such as large RC delay, high power consumption, and poor heat dissipation. Summary of the invention

[0006] A series of simplified concepts are introduced in the summary of the invention, which will be further described in detail in the detailed description of the embodiments. The summary of the invention of the embodiment of the present application does not mean to attempt to define the key features and essential technical features of the technical solution claimed for protection, nor does it mean to attempt to determine the scope of protection of the technical solution claimed for protection.

[0007] The embodiments of the present application provide a memory chip and a 3D memory chip to solve the problems of large parasitic resistance and capacitance of existing memory chips, high manufacturing cost, large RC delay, high power consumption, and poor heat dissipation caused by the use of silicon through via technology.

[0008] To at least partially solve the above problems, in a first aspect, an embodiment of the present application provides a memory chip, which may include:

[0009] A storage part and a control part are stacked on each other, and the storage part and the control part are connected by a hybrid bonding method, wherein the hybrid bonding method is to connect the connection pads of the storage part and the connection pads of the control part by a metal conductor.

[0010] In a first possible implementation of the first aspect, the control part includes a control part chip, the storage part includes a storage part chip, the control part chip and / or the storage part chip include a metal layer perforation component arranged in the chip metal layer, and the connecting pad is arranged in the first conductor part of the metal layer perforation component away from the substrate layer.

[0011] In a second possible implementation manner of the first aspect, the first conductor is the connecting pad.

[0012] In a third possible implementation manner of the first aspect, the metal layer through-hole assembly further includes a second conductor member close to the substrate layer;

[0013] The substrate layer includes a substrate through hole, the substrate through hole is connected to the second conductor, and the connecting pad is arranged on the second conductor.

[0014] In a fourth possible implementation of the first aspect, a conductor connection hole is provided between the first conductor member and the second conductor member, and the second conductor member is connected to the first conductor member through the conductor connection hole, so that a signal can be transmitted to the first conductor member through the substrate layer.

[0015] In a fifth possible implementation of the first aspect, the second conductor is the connecting pad.

[0016] In a sixth possible implementation of the first aspect, the substrate through hole is filled with a filling conductor layer, the connecting pad is arranged on a side of the filling conductor layer away from the metal layer, and the connecting pad is connected to the second conductor member through the filling conductor layer.

[0017] In a seventh possible implementation of the first aspect, the connecting pad is circular or polygonal in shape.

[0018] In an eighth possible implementation of the first aspect, the connecting pad is circular or polygonal in shape.

[0019] In a ninth possible implementation of the first aspect, the functional circuit of the storage chip is arranged in the control part.

[0020] In a tenth possible implementation of the first aspect, the functional circuit includes an SRAM repair unit circuit, and the SRAM repair unit circuit is used to replace a failed storage unit in the storage array to repair the storage array.

[0021] In an eleventh possible implementation manner of the first aspect, the storage portion is further provided with a sensitive amplifier;

[0022] Other functional circuits of the memory chip are arranged in the control part.

[0023] In a twelfth possible implementation manner of the first aspect, the storage part is further provided with a row-column decoding circuit;

[0024] Other functional circuits of the memory chip are arranged in the control part.

[0025] In a thirteenth possible implementation manner of the first aspect, the storage part is further provided with a storage part power supply circuit;

[0026] Other functional circuits of the memory chip are arranged in the control part.

[0027] In a fourteenth possible implementation of the first aspect, the functional circuit includes a computing function module.

[0028] In a fifteenth possible implementation of the first aspect, the computing function module is a CPU or a GPU.

[0029] In a sixteenth possible implementation of the first aspect, the storage part includes two or more storage part chips; and / or,

[0030] The control part includes two or more control part chips.

[0031] In a seventeenth possible implementation of the first aspect, the hybrid bonding method is to connect the connection pads of the storage part chip and the connection pads of the control part chip through a metal conductor.

[0032] In an eighteenth possible implementation manner of the first aspect, the storage part chips are connected by a hybrid bonding method; and / or,

[0033] The control part chips are connected with each other by hybrid bonding.

[0034] In a nineteenth possible implementation of the first aspect, the storage part includes two or more storage part chips having storage arrays of the same capacity; and / or,

[0035] The storage part includes two or more storage part chips having storage arrays with different capacities.

[0036] In a twentieth possible implementation of the first aspect, the two or more storage part chips are arranged on the same plane, and each of the storage part chips is independent of each other.

[0037] In a twenty-first possible implementation of the first aspect, two or more of the storage part chips have the same stacking direction.

[0038] In a twenty-second possible implementation of the first aspect, the two or more storage part chips include at least one volatile storage chip and one non-volatile storage chip.

[0039] In a twenty-third possible implementation of the first aspect, the volatile memory chip is a DRAM chip, and the non-volatile memory chip is a NAND flash chip.

[0040] In a twenty-fourth possible implementation of the first aspect, two or more of the storage part chips are stacked, and adjacent storage part chips are connected to the control part chip by hybrid bonding.

[0041] In a twenty-fifth possible implementation of the first aspect, two or more of the control part chips are stacked, and adjacent storage part chips are connected to the control part chip by hybrid bonding.

[0042] In a twenty-sixth possible implementation of the first aspect, at least one control part chip is stacked between two or more of the storage part chips, and the number of storage part chips on both sides of the control part chip is the same.

[0043] In a twenty-seventh possible implementation of the first aspect, two or more of the storage part chips are stacked without any interval.

[0044] In the twenty-eighth possible implementation of the first aspect, two or more of the control part chips include at least one analog function circuit chip and at least one digital function circuit chip, wherein the analog function circuit chip is only provided with analog function circuits, and the digital function circuit chip is only provided with digital function circuits.

[0045] In a twenty-ninth possible implementation of the first aspect, the two or more storage partial chips include two adjacent storage partial chips with the same orientation.

[0046] In a thirtieth possible implementation of the first aspect, the two or more control part chips include two adjacent control part chips with the same orientation.

[0047] In a thirty-first possible implementation of the first aspect, the two or more storage partial chips include two adjacent storage partial chips arranged opposite to each other.

[0048] In a thirty-second possible implementation of the first aspect, the two or more control part chips include two adjacent memory control part chips that are arranged opposite to each other.

[0049] In a thirty-third possible implementation of the first aspect, adjacent storage part chips and control part chips are connected by hybrid bonding.

[0050] In a thirty-fourth possible implementation of the first aspect, the connecting pad is also used for bonding the memory chip package leads.

[0051] In a second aspect, a 3D memory chip is provided, comprising the memory chip in any possible implementation of the first aspect.

[0052] Compared with the prior art, the memory chip and 3D memory chip provided in the embodiments of the present invention have at least the following beneficial effects:

[0053] The memory chip and 3D memory chip provided by the embodiments of the present invention, wherein the memory chip comprises a memory part and a control part stacked on each other, and the memory part and the control part are connected by a hybrid bonding method. The hybrid bonding method is to connect the connection pad of the memory part and the connection pad of the control part by a metal conductor. By expanding a single memory chip into two chips of a memory part and a control part stacked on each other, and using a metal conductor to connect the connection pads of the memory part and the control part respectively, there is no need to drive an interface circuit or module (PHY) between the two chips of the memory part and the control part of the same memory chip, so that the chip density of the memory chip stack can be made very high, and the hybrid bonding parasitic parameters (parasitic resistance value, parasitic capacitance value) of the memory part chip and the control part chip constituting the memory chip are very small, so the RC delay is small, and then there is no loss in data transmission speed, and high-bandwidth data transmission of the memory chip can be achieved.

[0054] Correspondingly, the 3D memory chip including the above memory chip also has corresponding technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work:

[0056] Figure 1 is a schematic structural diagram of a planar DRAM in some examples;

[0057] Figure 2 A schematic structural diagram of a memory chip provided in an embodiment of the present invention;

[0058] Figure 3 A schematic structural diagram of a single chip in a memory chip provided in an embodiment of the present invention;

[0059] Figure 4a A schematic structural diagram of a single chip in another memory chip provided in an embodiment of the present invention;

[0060] Figure 4b A schematic structural diagram of a single chip in another memory chip provided in an embodiment of the present invention;

[0061] Figure 5 A schematic structural diagram of a 3D memory chip having multiple memory parts provided in an embodiment of the present invention;

[0062] Figure 6 A schematic structural diagram of another 3D memory chip having multiple memory parts provided in an embodiment of the present invention;

[0063] Figure 7 A schematic structural diagram of another 3D memory chip having multiple memory parts provided in an embodiment of the present invention;

[0064] Figure 8 A schematic structural diagram of a 3D memory chip with multiple control parts provided in an embodiment of the present invention;

[0065] Fig. 9 A schematic structural diagram of another 3D memory chip with multiple control parts provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0066] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments so that those skilled in the art can implement the invention with reference to the description.

[0067] It should be understood that the terms such as “having”, “including” and “comprising” used herein do not exclude the existence or addition of one or more other elements or combinations thereof.

[0068] In addition, it should be noted that, unless otherwise clearly specified and limited, the terms "setting" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an integral connection or the internal connection of two elements. It can also be that signal transmission and data communication can be carried out between the two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0069] At present, in order to obtain higher bandwidth, the traditional TSV structure is usually used to connect the HBM chips and HMC chips of various storage parts. Among them, the HBM chip stacks multiple DDR double-rate synchronous dynamic random access memory chips and a PLD (Programmable Logic Device) together and packages them together with the GPU, and uses silicon through vias and micro-bumps to achieve chip-to-chip connection, realizing a large-capacity, high-bit-width DDR combination array. The HMC chip stacks multiple DRAM layers on a basic logic layer, realizing the best combination of logic and DRAM processes in a heterogeneous package. The DRAM layer only processes data, while the logic layer handles all control functions in the HMC.

[0070] However, it is very difficult to achieve a stacked structure of dozens of layers. Due to the immaturity of the technology, there are also problems such as high operational risk and poor stability. In addition, both HBM and HMC use silicon interposers, so the cost is very high and the shipment volume is very limited. In addition, due to the large number of DRAM stacks and GPU packages being packaged together, their heat dissipation performance will also be seriously affected.

[0071] In response to the above problems, an embodiment of the present application provides a 3D memory chip, which solves the problems of high manufacturing cost, poor circuit flexibility, high operation risk, poor stability, large RC delay and high power consumption brought about by existing planar memory chips or stacked memory chips realized by technologies such as through silicon via technology.

[0072] Figure 2 A schematic structural diagram of a memory chip provided by an embodiment of the present invention, such as Figure 2 As shown, the above-mentioned storage chip may include:

[0073] The control part 100 and the storage part 200 are stacked on each other, and the storage part 200 is connected to the control part 100 by a hybrid bonding method, wherein the hybrid bonding method is to connect the connection pads of the storage part 200 and the connection pads of the control part 100 by a metal conductor.

[0074] It should be noted that the above-mentioned memory chip can be a part of a 3D memory chip, and can also be regarded as a 3D memory chip itself.

[0075] In some examples, the control part 100 and the storage part 200 may be separate planar chips or wafers, for example, they may be stacked planar chips (C2C, Chip to Chip), that is, 3D chips stacked up and down; or they may be stacked wafers (W2W, wafer to wafer), which are cut to form 3D chips stacked up and down.

[0076] In some examples, the hybrid bonding method may be used such that two ends of the metal conductor 300 are connected to connection pads on the storage part 200 and the control part 100 respectively.

[0077] Exemplarily, the control part may include a control part chip, the storage part may include a storage part chip, the control part chip and / or the storage part chip may include a metal layer perforation component arranged in the metal layer of the chip, and the connecting pad is arranged in the first conductor part of the metal layer perforation component away from the substrate layer.

[0078] like Figure 3 As shown, in some examples, the control part 100 and the storage part 200 can be planar chips or wafers. Therefore, when the control part 100 and the storage part 200 are manufactured and produced separately, they can include a substrate layer 20 and a metal layer 10, which can also be called a device layer and a metal wiring layer. The metal layer 10 can include a first surface and a second surface that are arranged opposite to each other. The second surface of the metal layer 10 is arranged on the substrate layer 20. A metal layer perforation component can be arranged in the metal layer 10. The metal layer perforation component can include: a first conductor 11, a second conductor 12 and a conductor connection hole. The first conductor 11 can be formed on the first surface of the metal layer 10. The second conductor 12 can be formed on the second surface of the metal layer 10. For the convenience of explanation, the surface on the side where the substrate layer of the chip is located can be called the reverse side or back side of the chip; the surface on the side where the metal layer is located can be called the front side of the chip. The front or back side of the storage part 200 or the control part 100 may be provided with connection pads, which may be used for hybrid bonding between the control part 100 and the storage part 200 or for bonding of package leads of the storage chip.

[0079] Exemplary, reference Figure 3 The connection pad can be arranged on the front side of the control part chip or the storage part chip. It can be understood that the above-mentioned connection pad is arranged on the first conductor part 11 of the above-mentioned metal layer through-hole component.

[0080] Exemplarily, the shape of the connection pad can match the shape of the first conductor and / or the second conductor, so as to ensure sufficient contact between the connection pad and the metal conductor during hybrid bonding. Exemplarily, the shape of the connection pad can be rectangular or circular, or other polygonal or other shapes, which are not limited here.

[0081] Exemplarily, the above-mentioned connecting pad can also be the above-mentioned first conductor. It can be understood that the first conductor represented by the top metal in the above-mentioned metal layer can be directly used as the above-mentioned connecting pad. The above-mentioned connecting pad can also be used for hybrid bonding and can further simplify the chip manufacturing process.

[0082] According to some embodiments, Figure 4a As shown, the substrate layer 20 may include a substrate through hole 21 , the substrate through hole 21 is connected to the second conductor 12 , and the connection pad may be disposed on the second conductor 12 .

[0083] Exemplarily, a conductor connection hole is provided between the first conductor member and the second conductor member, and the second conductor member is connected to the first conductor member through the conductor connection hole, so that a signal can be transmitted to the first conductor member through the substrate layer.

[0084] Exemplarily, the connection pads can be arranged on the back side of the control part chip or the storage part chip, and the substrate layer is bored from the back side of the chip to form the substrate through-hole to the second conductor represented by the bottom metal of the metal layer, and then the connection pads are arranged on the bottom metal. The bottom metal and the first conductor represented by the top metal of the metal layer can be connected through the conductor connection hole, so that the signal can be transmitted to the first conductor through the second conductor in the substrate layer.

[0085] Exemplarily, there are two ways to set the connection pad on the bottom metal layer:

[0086] The first method can refer to Figure 4a , the bottom metal layer can be set directly as a connection pad.

[0087] The second method can refer to Figure 4b After the substrate layer through hole 21 is dug and filled with conductors, a connection pad 23 is set on the back of the chip with metal. The connection pad 23 here is connected to the second conductor 12 represented by the bottom metal through the filled conductor layer 22 filled in the dug substrate through hole 21. After the connection pad 23 at the bottom of the substrate through hole is connected to the second conductor 12 through the filled conductor layer 22, it can be connected to the first conductor through the conductor connection hole, so that the signal can be transmitted through the substrate layer 20 to the top metal of the metal layer 10, so that the signal connects the entire chip.

[0088] Exemplarily, the form of the connecting pad provided on the second conductor member in the bottom metal layer or the form of the connecting pad connected to the second conductor member through the filling conductor layer can be consistent with the shape of the first conductor member or the connecting pad in the top metal layer, and is also used to meet the requirement of sufficient contact between the connecting pad and the metal conductor during hybrid bonding. Exemplarily, the shape of the above-mentioned connecting pad can be rectangular or circular, or other polygonal or other shapes, which are not limited here. For example, when the above-mentioned connecting pad is on the front side of the above-mentioned storage part or the above-mentioned control part, the connecting pad is provided on the top metal layer, and when the above-mentioned connecting pad is on the back side of the above-mentioned storage part or the above-mentioned control part, the above-mentioned connecting pad is directly or indirectly connected to the bottom metal layer through the filling conductor layer, and the connecting pads on both sides can adopt the same size of circle.

[0089] It should be noted that the purpose of setting the connection pad is to facilitate the connection between the chip and the metal conductor in the hybrid bonding. When the connection pad is set on the front side of the chip, it is connected to the top metal of the metal layer perforation component in the metal layer, wherein the top metal can be directly set in the form of a connection pad; when the connection pad is set on the back side of the chip, it is connected to the bottom metal of the metal layer. Because it is necessary to dig holes in the substrate to set the connection pad on the back side of the chip, it is relatively easier and more reliable to set the connection pad on the top metal for hybrid bonding when the chip is not in the middle of the stacked chips.

[0090] Exemplarily, the storage part includes two or more storage part chips, which are connected by hybrid bonding; and / or the control part includes two or more control part chips, which are connected by hybrid bonding. The stacking method between control part chips, between storage part chips, and between control part and storage part chips can be in various forms, which are not limited here.

[0091] Specifically, the storage part and the control part of the above-mentioned 3D memory chip are connected by hybrid bonding. Because the RC parasitic parameters of the hybrid bonding are very small, there is no need for a driving interface circuit or module (PHY) between the two chips of the storage part and the control part. Further, the circuit module originally in the planar DRAM can be flexibly placed in the storage part or the control part as needed; the storage part can even be expanded to a stack of multiple storage function chips, so that the chip density of the stacked memory chips can be very high, and the parasitic parameters (parasitic resistance value, parasitic capacitance value) of the hybrid bonding connecting the storage part chip and the control part are very small, therefore, the RC delay is small, and thus there is no loss in data transmission speed, and high-bandwidth data transmission of the memory chip can be achieved.

[0092] Combined with the above examples, refer to Figure 2 The control part 100 and the storage part 200 stacked on each other may be provided with a connection pad on the surface of the storage part 200 connected to the control part 100 for hybrid bonding, that is, a hybrid bonding metal conductor is grown on the connection pad. Correspondingly, a connection pad is also provided on the surface of the control part 100 connected to the storage part 200 for hybrid bonding, that is, a hybrid bonding metal conductor is grown on the connection pad. The control part 100 and the storage part 200 are connected and data communication is performed through the hybrid bonding metal conductor.

[0093] Exemplarily, the aforementioned connection pads may be provided on the front or back of the storage part 200 or the control part 100. In some examples, the control part 100 and the storage part 200 stacked on each other may be face-to-face, that is, the front of the chip of the control part 100 and the front of the chip of the storage part 200 are opposite, the front of the chips of the two parts are connected by hybrid bonding, and the back of the chip of the control part 100 and the back of the chip of the storage part 200 are on the outside. In this way, it is only necessary to set connection pads on the top metal of the control part 100 and the storage part 200 for hybrid bonding and connect them with the metal conductor 300. As mentioned above, it is easier to set connection pads on the top metal for hybrid bonding and the reliability is higher. Therefore, it is preferred to use a face-to-face hybrid bonding method here, and the 3D storage chip manufactured has higher reliability and better yield.

[0094] In some examples, since the above-mentioned connecting pads are also used for bonding the packaging leads of the above-mentioned storage chip, after the above-mentioned stacked control part 100 and storage part 200 are connected through the hybrid bonded metal conductor 300, the storage part chip and / or the control part chip in the above-mentioned stacked control part 100 and storage part 200 can be provided with connecting pads on the side facing away from the above-mentioned metal conductor, wherein the above-mentioned connecting pads can be used to lead out the packaging pin connections to facilitate the packaging of the 3D chip.

[0095] It should be noted that the holes in the metal layer perforated components on the above-mentioned storage part and the above-mentioned control part are non-through holes. When packaging the chip, unlike the traditional TSV, although the signal can be transmitted through the entire chip, the holes on the chip do not need to penetrate the entire chip. The above-mentioned connecting pads can be used to lead out pin connections. After the above-mentioned storage chip is packaged, it can be connected to the external circuit through the pin leads led out from the above-mentioned connecting pads, so as to serve as a functional unit and cooperate with the integrated circuit connected to it to realize the overall function of its own electronic device.

[0096] The above example describes in detail the hybrid bonding method between the storage part and the control part and the perforation structure in a single chip to ensure data transmission after the 3D memory chip is split into the stacked storage part and the control part. The following will combine some examples to specifically describe the functional allocation of the storage part and the control part in the above 3D memory chip.

[0097] According to some embodiments, the above-mentioned 3D storage chip may include: a storage part and a control part stacked on each other, the above-mentioned storage part and the above-mentioned control part are connected by a hybrid bonding method, wherein the above-mentioned hybrid bonding method can be to connect the connection pads of the above-mentioned storage part and the connection pads of the above-mentioned control part by a metal conductor, the above-mentioned storage part is provided with a storage array, and the functional circuit of the above-mentioned storage chip is arranged in the above-mentioned control part.

[0098] In some examples, the storage part may be provided with the most basic storage unit, such as a storage array, and the functional circuit of the 3D storage chip may be provided on the control part.

[0099] Exemplarily, the functional circuit may include: a row-column decoding circuit, a power supply circuit, a data processing circuit and an interface circuit. In the 3D memory chip, when data is read from the storage part, the control part receives the command related to the data reading, and the row-column decoding circuit decodes the address, selects the data in the corresponding storage array in the storage part, and the data enters the control part from the storage part, and then the data is read out in the control part through the driving of the interface circuit and the clock control of the data processing circuit. In the 3D memory chip, when data is written to the storage part, the data is written into the storage array of the storage part after being driven by the interface circuit and allocated by the data processing circuit in the control part, so that the basic functions of the memory chip can be fully realized.

[0100] Because the smallest memory cell in the memory array of the storage part uses a special process that can store data, its manufacturing process is very complex and difficult to control. Placing the memory array in the storage part can ensure the consistency of the process, and because other circuits have been placed in the control part, the special nature of its process will not affect other circuits.

[0101] According to some embodiments, the functional circuit may further include an SRAM repair unit circuit, and the SRAM repair unit circuit is used to replace the failed storage cells in the storage array to repair the storage array. Usually, redundant cells are provided in the storage array for the purpose of repairing the failed cells in the storage array. In the present invention, the functional circuit may further include an SRAM repair unit circuit for replacing the redundant cells in the storage array. The advantage of this is that the control part can use the logic process to produce an SRAM circuit with better performance, and use the SRAM circuit to repair the failed cells in the storage array.

[0102] According to some embodiments, the control part can use a special logic process, and the logic process can also meet the performance requirements of some analog circuits, so that it is not affected by the special process of the storage unit. The logic process can well enable other circuits including row and column decoding circuits, power supply circuits, data processing circuits, interface circuits and SRAM repair unit circuits to perform better. For example, pure digital logic such as row and column decoding circuits and data processing circuits can achieve higher data frequency and bandwidth using logic processes, and may also save power consumption.

[0103] According to some embodiments, in the above-mentioned storage chip, the above-mentioned storage part is provided with a storage array and a sense amplifier, and other functional circuits of the above-mentioned storage chip are provided in the above-mentioned control part. When the above-mentioned storage part is read out, the control part receives the above-mentioned command related to the data reading, and the above-mentioned row and column decoding circuit decodes the address, and then selects the data in the corresponding storage array in the storage part, and the data enters the control part after being amplified by the sense amplifier from the storage part, and then the data is read out in the control part through the driving of the interface circuit and the clock control of the data processing circuit. Because the storage unit in the storage array uses a special process that can store data, its manufacturing process is very complicated and difficult to control. Placing it and the sense amplifier in the storage part can ensure the consistency of the process, and because other circuits have been placed in the control part, the particularity of its process will not affect other circuits. At the same time, the sense amplifier is directly connected to the storage unit in the storage array, and the sense amplifier and the storage unit are placed in the same chip as the storage part to ensure the matching of data reading, and the data reading accuracy is higher.

[0104] According to some embodiments, the storage part may also be provided with a row-column decoding circuit, and other functional circuits of the storage chip are provided in the control part. Here, the row-column decoding circuit is added to the storage part. It can be understood that in the storage part, the row-column decoding circuit will frequently operate and control the storage array, and is closely connected with the storage array, and there are many connections between them. Placing the row-column decoding circuit in the storage part can effectively reduce the mixed bonding connections between the storage part and the control part, reduce the complexity of 3D chip manufacturing and improve the yield. At the same time, placing the row-column decoding circuit and the storage array together can reduce the error caused by process mismatch.

[0105] Exemplarily, the storage part is also provided with a storage part power supply circuit, and other functional circuits of the storage chip are provided in the control part. Specifically, during data reading and writing and other necessary operations, the storage array and the sense amplifier need to consume a large amount of electricity. The storage part power supply circuit with a basic power supply unit circuit required by the storage array and the sense amplifier is placed in the storage part. The basic power supply function can well meet the needs of the functional circuits in the storage part for electric energy during data reading and writing. The stability and reliability of the operation of the storage part are improved.

[0106] It should be noted that, while the power supply circuit is provided in the storage part, the control part may also be provided with a basic control part power supply circuit, and the two power supply circuits may respectively supply power to the storage part and the control part. Of course, in the solution in which the power supply circuit is provided in the storage part, the power supply circuit may no longer be provided in the control part, but when the control part needs power supply, the power supply circuit of the storage part may be reused. In this solution, since the storage part is provided with a power supply circuit for power supply, the technical effect of improving the stability and reliability of the storage part is still achieved.

[0107] The control part mentioned above can be understood as the control part in a common memory chip, which can perform row and column decoding and simple data processing operations, but does not have a computing function. Accordingly, in some examples, the control part of the memory chip mentioned above may not be limited to the control functions of a common memory chip, but may also include other more powerful logic functions, for example, the control part may be expanded into a processor.

[0108] According to some embodiments, in the above-mentioned 3D storage chip, a computing function module can also be set in the above-mentioned control part. The above-mentioned operation function module can be a CPU (Central Processing Unit / Processor) or a GPU (Graphics Processing Unit). In this way, the data of the above-mentioned storage part can be directly processed in the above-mentioned control part. Since the above-mentioned control part and the above-mentioned storage part are connected by hybrid bonding, the parasitic parameters of the signal transmission between them are small, so the system composed of them can overcome the storage obstacle and greatly improve the data processing capability.

[0109] It should be noted that the storage part and the control part in the 3D storage chip can still be used as follows Figure 2 The hybrid bonding method shown in the figure, and the transmission of signals in the planar chip that constitutes the 3D memory chip can be realized by the above-mentioned chip perforation scheme that does not penetrate the entire chip. There is no need to set up through-silicon vias, only substrate through holes need to be opened on the substrate, and metal layer perforation components need to be opened in the metal layer, which greatly reduces the diameter and length of the hole, thereby reducing the difficulty of the etching process, reducing the area occupied by the metal layer, reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the chip unit, and reducing the production cost.

[0110] In the scheme of splitting a 3D memory chip into a storage part and a control part stacked on each other, the above example provides a detailed description of the hybrid bonding method between the storage part and the control part, the perforation structure for ensuring data transmission within a single chip, and the respective functional allocation of the storage part and the control part. The following will further provide a specific description of the stacking method of the storage part and the control part stacked on each other in the 3D chip.

[0111] like Figure 2 As shown, the above 3D memory chip may include:

[0112] The control part 100 and the storage part 200 are stacked on each other, and the storage part 200 is connected to the control part 100 by hybrid bonding. The storage part may include two or more storage part chips, and / or the control part may include two or more control part chips. For example, the 3D storage chip may include a storage part composed of three storage part chips and a control part composed of a control part chip, or the 3D storage chip may include a storage part composed of one storage part chip and a control part composed of three control part chips, or the 3D storage chip may include a storage part composed of three storage part chips and a control part composed of three control part chips. The control part chip or storage part chip here refers to a separate chip (Die) or a wafer (Wafer), the chip here refers to a 2D planar chip, and the wafer here refers to a 2D planar wafer. The storage part and the control part can be connected by hybrid bonding to form a variety of combinations.

[0113] The storage part and the control part of the above-mentioned 3D memory chip are connected by a hybrid bonding method. As the storage part and the control part of the same memory chip, no driving interface circuit or module (PHY) is required between the two chips. Further, the chip density of the memory chip stack can be made very high, and more chips can be stacked. The parasitic parameters (parasitic resistance value, parasitic capacitance value) of the hybrid bonding connecting the storage part and the control part are very small. Therefore, the RC delay is small, and the data transmission speed is not lost, so that high-bandwidth data transmission of the memory chip can be achieved.

[0114] Exemplarily, the storage part chip and / or the control part chip may be connected by a hybrid bonding method. The hybrid bonding method may be to connect the connection pads of the storage part and the connection pads of the control part by a metal conductor. The storage part may be regarded as a chip mainly used for storage function among multiple stacked chips of a 3D storage chip, and the control part may be regarded as a chip mainly used for control function among multiple stacked chips of a 3D storage chip.

[0115] According to some embodiments, in the above-mentioned storage chip, in addition to the storage part chip and the control part chip being connected by the above-mentioned hybrid bonding method, the above-mentioned storage part chips can also be connected by a hybrid bonding method, and the above-mentioned control part chips can also be connected by a hybrid bonding method.

[0116] In some examples, the storage part includes two or more storage part chips having storage arrays of the same capacity; and / or, the storage part includes two or more storage part chips having storage arrays of different capacities.

[0117] According to some embodiments, two or more storage part chips may be arranged in the same plane, and each of the above storage part chips is independent of each other. The storage part chip here may be a storage unit with a storage array, and these storage units may be connected to the above control part by metal conductors through hybrid bonding. Here, multiple storage units in the same plane chip may have no physical connection relationship, that is, they are not connected by pin wiring or metal conductors.

[0118] Figure 5 The schematic structural diagram of a 3D memory chip with multiple memory cells provided by an embodiment of the present invention. Here, having multiple memory cells means that the memory part has multiple memory cells in the same plane chip. Figure 5 As shown, the storage part may include a first storage unit, a second storage unit, and finally an nth storage unit, and the n storage units may be respectively connected to the control part by hybrid bonding with metal conductors. There may be no physical connection between the n storage units, that is, the n storage units are not connected by pin wiring or metal conductors, but the n storage units are not stacked on each other, but are arranged in the same plane.

[0119] Specifically, the surface of one side of the n storage units connected to the control part is provided with a connection pad for connecting with the metal conductor in the hybrid bonding, and then a metal conductor (hybrid bonding) is grown on the connection pad. Correspondingly, the surface of one side of the control part connected to the n storage units can also be provided with a connection pad, and then connected through the metal conductor of the hybrid bonding, so that the control part and the n storage units are respectively connected and perform data communication. With this structure, it is relatively easy for the control part to control the storage part, and the reliability is relatively high. The n storage units can be storage arrays of the same capacity (or different capacities), independent of each other. Exemplarily, the independent storage units can replace each other when necessary. The advantage of this is that if a storage unit fails and malfunctions, other storage units can be replaced as redundant units, thereby improving the reliability of the entire 3D storage chip.

[0120] For example, see Figure 5, a control part composed of a planar chip and multiple storage units are used as a planar storage part. As mentioned above, because setting connection pads on the back of the chip requires digging holes in the substrate, it is relatively easier and more reliable to set connection pads on the top metal layer for hybrid bonding. Therefore, the storage part and the control part preferably use a face-to-face hybrid bonding method, that is, the front side of the chip of the control part 100 and the front side of the chip of the storage part 200 are opposite, and the front sides of the chips of the two parts are connected by hybrid bonding, and the back side of the chip of the control part 100 and the back side of the chip of the storage part 200 are on the outside.

[0121] According to some embodiments, in the above-mentioned memory chip, the above-mentioned two or more memory part chips are stacked, and two adjacent chips are connected by hybrid bonding. It can be understood that not only the memory part chip and the control part chip can be connected by hybrid bonding, but also the memory part chip and the memory part chip can be connected by hybrid bonding. When the above-mentioned two or more memory part chips are stacked and two adjacent chips are connected by hybrid bonding, the above-mentioned memory chip solution can have multiple situations, and of course each situation also has corresponding functions and characteristics.

[0122] Exemplarily, two or more of the above-mentioned storage part chips can be stacked without any interval. Figure 6 A schematic structural diagram of another 3D memory chip having multiple memory parts provided by an embodiment of the present invention, such as Figure 6 As shown, the control part of the memory chip may include a control part chip 110, and the control part chip has the function of data and signal processing. The storage part of the memory chip may include a first storage part chip 210 and a second storage part chip 220. The control part chip 110, the first storage part chip 210 and the second storage part chip 220 are stacked from top to bottom. The first storage part chip 210 and the second storage part chip 220 are stacked with the control part chip 110. Specifically, a connection pad is provided on the surface of one side of the first storage part chip 210 connected to the control part chip 110 for connecting with the metal conductor in the hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding mode. Correspondingly, a connection pad may also be provided on the surface of one side of the control part chip 110 connected to the first storage part chip 210 for connecting with the metal conductor in the hybrid bonding, and then a metal conductor is grown on the metal pad to connect the control part chip 110 and the storage part chip 210 in a hybrid bonding mode and perform data communication.

[0123] It should be noted here that, as mentioned above, since it is relatively easier and more reliable to set connection pads on the top metal layer of the chip for hybrid bonding, the control part chip 110 faces the first storage part chip 210. Correspondingly, since the above-mentioned storage part chip 210 needs to continue to be connected to the above-mentioned storage part chip 220, the second storage part chip 220 is also set to face the first storage part chip 210. That is, connection pads are set on the front of the control part chip 110 and the second storage part chip 220 for connecting with the metal conductor in the hybrid bonding.

[0124] For the first storage part chip 210 placed between the control part chip 110 and the second storage part chip 220, since both its front and back sides are connected to the control part chip 110 and the second storage part chip 220 by hybrid bonding, its front direction can be placed according to the situation. However, in order to ensure the consistency of the first storage part chip 210 and the second storage part chip 220, it is usually best to have the first storage part chip 210 and the second storage part chip 220 have the same front direction, so that the consistency of the first storage part chip 210 and the second storage part chip 220 will be very good, and relative to the entire 3D chip, the first storage part chip 210 and the second storage part chip 220 of the storage part will have a good matching, so that the reliability of the chip manufactured thereby, the reliability of the chip operation, and the reliability of data reading and writing will be very good.

[0125] It is understandable that the storage part can be a stack of multiple storage part chips. The storage chip has the advantages of convenient expansion of storage capacity and simple form. When the storage part is a stack of multiple storage part chips, the multiple storage part chips are stacked in the same direction, that is, the front sides of the multiple storage part chips are all facing upward or downward.

[0126] Exemplarily, the plurality of storage part chips stacked in the above storage part can be the same chip or different chips. When the plurality of storage part chips stacked in the above storage part are different chips, they can include at least one volatile storage chip, such as a DRAM storage chip, and at least one non-volatile storage chip, such as a NAND flash storage chip. The advantage of this is that the data access speed can be guaranteed by the DRAM storage chip, and the data on the non-volatile storage chip can be ensured not to be lost when the chip loses power by the NAND flash storage chip.

[0127] According to some embodiments, in the above-mentioned memory chip, at least one control chip is stacked between two or more of the above-mentioned memory chips, and the number of memory chips on both sides of the above-mentioned control chips is the same. Figure 7A schematic structural diagram of another 3D memory chip having multiple memory parts provided by an embodiment of the present invention is shown in FIG. Figure 7 As shown, the control part of the memory chip may include a control part chip 110, and the control part chip has the function of data and signal processing. The memory part may include a first memory part chip 210 and a second memory part chip 220. The memory chip may also form other structures, for example, the control part chip 110 of the control part is arranged between the first memory part chip 210 and the second memory part chip 220.

[0128] Specifically, a connection pad is provided on the surface of the side where the first storage part chip 210 is connected to the control part chip 110, and then a metal conductor is grown on the connection pad to form a hybrid bonding. Correspondingly, a connection pad can also be provided on the surface where the control part chip 110 is connected to the first storage part chip 210, and then a metal conductor is grown on the connection pad to form a hybrid bonding, so that the control part chip 110 and the first storage part chip 210 are connected and data communication is performed. Correspondingly, since the control part chip 110 needs to continue to connect to the second storage part chip 220, a connection pad needs to be provided on the side of the control part chip 110 away from the metal conductor, and then a metal conductor is grown on the connection pad to form a hybrid bonding, and then the second storage part chip 220 is continued to be connected by hybrid bonding to form a chip stacking structure. The storage chip has the advantages of convenient storage capacity expansion, simple form and good symmetry. It should be noted that the above storage part is not limited to having the first storage part chip 210 and the second storage part chip 220, and may also have more storage part chips and continue to form a chip stacking structure.

[0129] Similarly, the above-mentioned storage chip has the advantages of convenient expansion of storage capacity and simple form. The multiple storage part chips stacked in the above-mentioned storage part can be the same chip or different storage chips. When the multiple storage part chips stacked in the above-mentioned storage part are different chips, at least one of them can be a volatile storage chip, such as a DRAM storage chip, and at least one other can be a non-volatile storage chip, such as a NAND flash storage chip. The advantage of this is that the data access speed can be guaranteed through the DRAM storage chip, and the data on the non-volatile storage chip can be ensured not to be lost when the chip loses power through the NAND flash storage chip.

[0130] According to some embodiments, in the above-mentioned memory chip, the above-mentioned two or more control part chips are stacked and arranged, and two adjacent chips are connected by metal conductors in a mixed bonding manner. When the above-mentioned two or more control part chips are stacked and arranged, and two adjacent chips are connected by metal conductors, the above-mentioned memory chip solution can exist in multiple situations, and of course each situation also has corresponding functions and characteristics.

[0131] Exemplarily, among the above-mentioned storage chips, two or more of the above-mentioned control part chips may include at least one analog function circuit chip and at least one digital function circuit chip, wherein the above-mentioned analog function circuit chip is only provided with analog function circuits, and the above-mentioned digital function circuit chip is only provided with digital function circuits. Figure 8 A schematic structural diagram of a 3D memory chip having multiple control parts provided by an embodiment of the present invention, such as Figure 8 As shown, the storage part of the above-mentioned memory chip may include a storage part chip 210. The control part of the above-mentioned memory chip may include a first control part chip 110 and a second control part chip 120. The first control part chip 110 has the function of data and signal processing, and the second control part chip 120 has the function of power supply. The first control part chip 110 and the second control part chip 120 are stacked with the above-mentioned storage part chip 210. The first control part chip 110, the second control part chip 120 and the storage part chip 210 are stacked in sequence from top to bottom.

[0132] Specifically, a connection pad is provided on the surface of the side of the second control part chip 120 connected to the storage part chip 210 for connecting with the metal conductor in the hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding; correspondingly, a connection pad can also be provided on the surface of the side of the storage part chip 210 connected to the second control part chip 120 for connecting with the metal conductor in the hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding. The second control part chip 120 and the storage part chip 210 are connected and data communication is performed. Correspondingly, since the second control part chip 120 needs to continue to connect to the first control part chip 110, a connection pad needs to be provided on the side of the second control part chip 120 away from the storage part chip 210 for connecting with the metal conductor in the hybrid bonding, and then a metal conductor (hybrid bonding) is grown on the connection pad; and the second control part chip 110 is continued to be connected to the control part chip 110 through the hybrid bonding method to form a chip stacking structure.

[0133] It should be noted that the storage part is not limited to the storage part chip 210, and the control part is not limited to the first control part chip 110 and the second control part chip 120. There may be more control part chips and a chip stacking structure may be formed. Since the control part of the storage chip is divided into multiple chips, analog functions and digital functions may be set separately, so that the control part can be compatible with analog function processes and digital function processes, and can combine the advantages of each process to achieve stronger performance.

[0134] Similarly, except for Figure 8 The stacking method of the first control part chip 110, the storage part chip 210 and the second control part chip 220 from top to bottom shown in the figure may also be other methods, and their stacking order is not limited.

[0135] The storage part chip 210 of the storage part can be provided with the most basic storage unit, for example, a storage array. The functional circuit of the storage chip can be provided in the control part chip 110 and the control part chip 120. The functional circuit of the control part chip 110 can include: a row and column decoding circuit, a data processing circuit and an interface circuit. The functional circuit of the control part chip 120 can include: a power supply circuit. In the storage chip, when reading data from the storage part, the control part receives the command related to the data reading, and the row and column decoding circuit decodes the address, selects the data in the corresponding storage array in the storage part, and the data enters the control part from the storage part, and then the data is read out in the control part through the driving of the interface circuit and the clock control of the data processing circuit. In the storage chip, when writing data to the storage part, the data is written into the storage array of the storage part after the data line is allocated by the driving of the interface circuit and the data processing circuit in the control part, so that the basic function of the storage chip can be fully realized. Because the memory cells in the memory array use a special process that can store data, its manufacturing process is very complex and difficult to control. Placing the memory array in the storage part can ensure the consistency of the process, and because other circuits have been placed in the control part, the special nature of its process will not affect other circuits.

[0136] Fig. 9 A schematic structural diagram of another 3D memory chip with multiple control parts provided by an embodiment of the present invention, such as Fig. 9As shown, the control part of the memory chip may include a memory chip 210. The control part of the memory chip may include a first control chip 110 and a second control chip 120. The first control chip 110 may have the function of data and signal processing, and the second control chip 120 may have the function of power supply. The first control chip 110 and the second control chip 120 are stacked with the memory chip 210. Specifically, a connection pad is provided on the surface of one side of the second control chip 120 connected to the memory chip 210 for connecting with the metal conductor in the hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding. Correspondingly, a connection pad may also be provided on the surface of one side of the memory chip 210 connected to the second control chip 120 for connecting with the metal conductor in the hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding. The second control chip 120 and the memory chip 210 are connected and data communication is performed. Accordingly, since the storage part chip 210 needs to continue to be connected to the first control part chip 110, it is necessary to set a connection pad on the side of the storage part chip 210 away from the metal conductor for connecting with the metal conductor in the hybrid bonding, and then grow the metal conductor on the connection pad to form a hybrid bonding, and continue to connect with the first control part chip 110 through hybrid bonding to form a chip stacking structure. It should be noted that the storage part is not limited to the storage part chip 210, and the control part is not limited to having control part chips 110 and 120, and can also have more control part chips and continue to form a chip stacking structure. Since the control part of the storage chip is divided into multiple chips, analog functional circuits and digital functional circuits can be set separately, so that the control part can be compatible with analog functional processes and digital functional processes, and can combine the advantages of each process to achieve stronger performance.

[0137] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0138] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A memory chip, characterized in that: include: A storage part and a control part stacked on each other, wherein the storage part and the control part are connected by a hybrid bonding method, wherein the hybrid bonding method is to connect the connection pads of the storage part and the connection pads of the control part by a metal conductor; The control part includes a control part chip, the storage part includes a storage part chip, the control part chip and / or the storage part chip include a metal layer perforation component arranged in the metal layer of the chip, wherein the hole in the metal layer perforation component is a non-through hole; The metal layer through-hole assembly comprises a first conductor, a second conductor close to the substrate layer, and a conductor connection hole, wherein the conductor connection hole is provided between the first conductor and the second conductor, and the second conductor is connected to the first conductor through the conductor connection hole, so that a signal can be transmitted to the first conductor through the substrate layer; The first conductor member is the connecting pad; The second conductor is the connecting pad; A connection pad is provided on a side of the storage part chip and / or the control part chip facing away from the metal conductor; The storage part is provided with a storage array, and the functional circuit of the storage chip is provided in the control part.

2. The memory chip according to claim 1, characterized in that: The connecting pad is arranged in the first conductor member of the metal layer through-hole component away from the substrate layer.

3. The memory chip according to claim 2, characterized in that: The substrate layer includes a substrate through hole, the substrate through hole is connected to the second conductor, and the connecting pad is arranged on the second conductor.

4. The memory chip according to claim 1, characterized in that: The storage part includes two or more than three storage part chips; and / or, The control part includes two or more control part chips.

5. The memory chip according to claim 1, characterized in that: The connecting pads are also used for bonding the memory chip package leads.

6. A 3D memory chip, characterized in that: include: A memory chip as claimed in any one of claims 1 to 5.

Images