Three-dimensional memory and methods of making the same, memory systems, electronic devices

Abstract

The application provides a three-dimensional memory, a preparation method thereof, a storage system and an electronic device. The preparation method of the three-dimensional memory comprises the following steps: forming a stack structure and forming a channel structure penetrating through the stack structure, wherein the channel structure is arranged in multiple columns and multiple rows along a first direction and a second direction respectively; forming multiple bit lines corresponding to the multiple columns of the channel structure respectively and extending along the first direction, wherein multiple bit lines are electrically connected to first ends of the channel structures in the corresponding columns respectively; and forming multiple source lines corresponding to the multiple rows of the channel structure respectively and extending along the second direction, wherein multiple source lines are electrically connected to second ends of the channel structures in the corresponding rows respectively, the second ends being opposite to the first ends.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory, its fabrication method, memory system, and electronic device. Background Technology

[0002] As the market demands for memory storage density continue to increase, the reduction of the key dimensions of two-dimensional memory has reached the limit of mass production technology. In order to further increase storage capacity and reduce costs, three-dimensional memory structures have been proposed.

[0003] Three-dimensional memory includes bit lines that are electrically connected to the channel layers in the channel structure. In partition-controlled three-dimensional memory, to ensure that each bit line connects to a string of memory cells, the number of bit lines needs to be increased, which further increases the density of adjacent bit lines and reduces the spacing between adjacent bit lines. This not only increases the difficulty of the manufacturing process but also increases the risk of short circuits between adjacent bit lines. Summary of the Invention

[0004] This application provides a method for fabricating a three-dimensional memory, the method comprising: forming a stacked structure and forming a channel structure passing through the stacked structure, wherein the channel structure is arranged in multiple columns and multiple rows along a first direction and a second direction, respectively; forming a plurality of bit lines extending along the first direction corresponding to the multiple columns of the channel structure, wherein the plurality of bit lines are electrically connected to a first end of the channel structure in the corresponding column; and forming a plurality of source lines extending along the second direction corresponding to the multiple rows of the channel structure, wherein the plurality of source lines are electrically connected to a second end of the channel structure in the corresponding row, opposite to the first end.

[0005] In one implementation, any channel structure is addressed by supplying power to the plurality of bit lines and the plurality of source lines.

[0006] In one embodiment, the distance between two adjacent bit lines is greater than or equal to the spacing between two adjacent columns of the channel structure; and the distance between two adjacent source lines is greater than or equal to the spacing between two adjacent rows of the channel structure.

[0007] In one embodiment, the angle between the first direction and the second direction is less than or equal to 90°.

[0008] In one embodiment, the stacked structure is formed on a substrate, wherein forming a channel structure through the stacked structure includes: forming a channel via through the stacked structure and extending to the substrate; forming an epitaxial layer within the channel via; and forming a channel structure on the epitaxial layer, wherein the channel structure includes a functional layer and a channel layer.

[0009] In one embodiment, the bit line and the source line are electrically connected to a first end and a second end of the channel layer, respectively, wherein the first end of the channel layer is away from the substrate, and the second end of the channel layer is close to the substrate.

[0010] In one embodiment, forming a source line extending in a second direction at the second end of each row of the channel layer includes: removing at least a portion of the substrate, the epitaxial layer, and the functional layer to expose the second end of the channel layer; and forming a source line extending in a second direction at the second end of each row of the channel layer.

[0011] In one embodiment, the method further includes doping a second end of the channel layer.

[0012] In one embodiment, the method further includes: forming a conductive layer at a second end of the channel layer and planarizing the conductive layer; and forming a source line extending along the second direction on the conductive layer.

[0013] In one embodiment, forming the stacked structure includes: alternately stacking insulating layers and sacrificial layers on a substrate to form the stacked structure.

[0014] In one embodiment, the method further includes: processing the insulating layer and the sacrificial layer to form a plurality of stepped steps, wherein a portion of the sacrificial layer is exposed as the upper surface of the stepped steps; forming vias through the stacked structure and virtual channel structures through the stepped steps; and replacing the sacrificial layer with a gate layer via the vias.

[0015] In one embodiment, the method further includes forming a word line contact connected to the gate layer on the surface of the exposed portion of the gate layer.

[0016] In one embodiment, the method further includes: connecting a peripheral circuit chip to the side of the stacked structure away from the substrate, wherein the peripheral circuit chip includes peripheral circuitry.

[0017] This application also provides a three-dimensional memory, comprising: a stacked structure; a channel structure passing through the stacked structure, wherein the channel structure is arranged in multiple columns and multiple rows along a first direction and a second direction, respectively; a plurality of bit lines corresponding to multiple columns of the channel structure and electrically connected to a first end of the corresponding column of the channel structure, and extending along the first direction; and a plurality of source lines corresponding to multiple rows of the channel structure and electrically connected to a second end of the corresponding row of the channel structure opposite to the first end, and extending along the second direction.

[0018] In one implementation, the plurality of bit lines and the plurality of source lines address any channel structure.

[0019] In one embodiment, the distance between two adjacent bit lines is greater than or equal to the spacing between two adjacent columns of the channel structure; and the distance between two adjacent source lines is greater than or equal to the spacing between two adjacent rows of the channel structure.

[0020] In one embodiment, the angle between the first direction and the second direction is less than or equal to 90°.

[0021] In one embodiment, the three-dimensional memory further includes a conductive layer located at a second end of the channel layer of the channel structure, wherein the source line is connected to the conductive layer.

[0022] This application also provides a storage system. The storage system includes a controller and the aforementioned three-dimensional memory, the controller being coupled to the three-dimensional memory and used to control the storage of data in the three-dimensional memory.

[0023] Another aspect of this application provides an electronic device, including the aforementioned storage system.

[0024] According to one or more embodiments of this application, a bit line is provided at the first end of each column channel structure and a source line is provided at the second end of each row channel structure, which helps to reduce the number of bit lines, thereby increasing the width of the bit lines and reducing the difficulty of the manufacturing process.

[0025] According to one or more embodiments of this application, a bit line is provided at the first end of each column channel structure and a source line is provided at the second end of each row channel structure, which helps to reduce the density of bit lines, make the spacing between adjacent bit lines larger, and reduce the short circuit risk between adjacent bit lines.

[0026] According to one or more embodiments of this application, a bit line extending in a first direction is formed at the first end of each column channel structure and a source line extending in a second direction is formed at the second end of each row channel structure, which is beneficial to select a memory cell string by simultaneously controlling a bit line in the first direction and a source line in the second direction.

[0027] According to one or more embodiments of this application, the channel structure can be addressed by bit lines and source lines, which facilitates the selection of a certain memory cell string without the need to form a top select gate cutout and a bottom select gate cutout structure as in conventional processes in order to achieve the purpose of selecting the memory cell string. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0029] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0030] Figures 2 to 6 This is a process step diagram of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0031] Figure 7 This is an enlarged view of the channel structure according to an exemplary embodiment of this application;

[0032] Figure 8 This is a simplified schematic diagram after bit lines are formed in a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0033] Figures 9 to 15 This is a process step diagram of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application; and

[0034] Figure 16 This is a simplified schematic diagram after the source line is formed in the fabrication method of a three-dimensional memory according to an exemplary embodiment of this application;

[0035] Figure 17 This is a simplified top view schematic diagram after the source line is formed in the fabrication method of a three-dimensional memory according to an exemplary embodiment of this application;

[0036] Figure 18 This is a schematic diagram of the structure of a storage system according to one embodiment of this application; and

[0037] Figure 19 This is a schematic diagram of the structure of an electronic device according to one embodiment of this application. Detailed Implementation

[0038] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0039] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first end discussed herein may also be referred to as the second end, and vice versa.

[0040] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0041] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0042] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0043] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0044] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a range smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can contain multiple layers.

[0045] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application.

[0046] like Figure 1As shown, the fabrication method 1000 of the three-dimensional memory provided in this application may include: S1, forming a stacked structure and forming a channel structure passing through the stacked structure, wherein the channel structure is arranged in multiple columns and multiple rows along a first direction and a second direction, respectively; S2, forming multiple bit lines extending along the first direction corresponding to multiple columns of the channel structure, wherein the multiple bit lines are electrically connected to the first end of the channel structure in the corresponding column; and S3, forming multiple source lines extending along the second direction corresponding to multiple rows of the channel structure, wherein the multiple source lines are electrically connected to the second end of the channel structure in the corresponding row, opposite to the first end. Steps S1 to S3 will be described in detail below.

[0047] Step S1

[0048] like Figures 2 to 6 As shown, a stacked structure 100 can be formed. Figure 4 ), and can form a channel structure 200 passing through the stacked structure 100 ( Figure 6 The stacked structure 100 may include a first sub-stack 110 and a second sub-stack 120. Exemplarily, the stacked structure 100 may first be formed on one side of the substrate 300, and then a channel structure 200 may be formed through the stacked structure 100. Exemplarily, an insulating layer 111 and a sacrificial layer 112 may be alternately stacked on the substrate 300 to form the first sub-stack 110.

[0049] In exemplary embodiments of this application, the substrate 300 may be, for example, a polycrystalline silicon (Si) substrate, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs or InP. In one embodiment, the substrate 300 may also be a stacked structure, such as Si / SiGe. In another embodiment, the substrate 300 may also be other epitaxial structures, such as silicon-germanium-on-insulator (SGOI).

[0050] Forming the stacked structure 100 on the substrate 300 can be achieved through one or more deposition processes. The deposition processes for forming the stacked structure 100 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of the insulating layer 111 and the sacrificial layer 112 are not limited to... Figure 4The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to create any number and thickness of insulating layers 111 and sacrificial layers 112 as needed. Furthermore, the materials of insulating layers 111 and sacrificial layers 112 may be selected from suitable materials known in the art. For example, insulating layer 111 may be an oxide layer (such as silicon oxide), and sacrificial layer 112 may be a nitride layer (such as silicon nitride).

[0051] In an exemplary embodiment of this application, forming a channel structure 200 through the stacked structure 100 may include: first, forming a channel via 210 through the stacked structure 100 and extending to the substrate 300; second, forming an epitaxial layer 400 within the channel via 210; and then forming the channel structure 200 on the epitaxial layer 400, wherein the channel structure 200 may include a functional layer 220 and a channel layer 230. Exemplarily, the channel structure 200 may be arranged in an array along a first direction Y and a second direction X. For example, the channel structure 200 may be arranged in multiple columns and multiple rows along the first direction Y and the second direction X, respectively. Specifically, the channel structure 200 may be distributed in multiple columns along the first direction Y and in multiple rows along the second direction X.

[0052] In an exemplary embodiment of this application, the stacked structure 100 may include multiple sub-stacks, that is, the stacked structure 100 may be formed by sequentially stacking multiple sub-stacks. For example, the stacked structure 100 may be formed by sequentially stacking a first sub-stack 110 and a second sub-stack 120. Exemplarily, firstly, an insulating layer 111 and a sacrificial layer 112 may be alternately stacked on a substrate 300 to form the first sub-stack 110 (… Figure 2 Secondly, a first sub-channel hole 10 can be formed in the first sub-layer 110, extending through the first sub-layer 110 and reaching the substrate 300, and the first sub-channel hole 10 can be filled with an insulating material. Figure 3 Then, insulating layers 111 and sacrificial layers 112 may be alternately stacked on the first sub-stack 110 to form a second sub-stack 120, and a second sub-channel hole 20 may be formed in the second sub-stack 120, extending through the second sub-stack 120 and into the first sub-channel hole 10. Figure 4 For example, an etching process can be used to remove the insulating material filling the first sub-channel hole 10 via the second sub-channel hole 20, so that the first sub-channel hole 10 and the second sub-channel hole 20 together form the channel hole 210. Figure 5 ).

[0053] As the demand for 3D memory storage continues to increase, the size of memory stacks is gradually increasing. To overcome the limitations of traditional processes, dual-stack or multi-stack techniques can be used. This involves sequentially stacking multiple sub-stacks along the thickness of the stack to form a layered structure. Each sub-stack may include multiple alternately stacked insulating layers 111 and sacrificial layers 112. The number of layers in each sub-stack may be the same or different. However, those skilled in the art will understand that subsequent fabrication processes can be performed based on either multi-stack or single-stack structures.

[0054] In an exemplary embodiment of this application, an epitaxial layer 400 may be formed within the channel via 210. Figure 5 Exemplarily, an epitaxial layer 400 may be formed within a portion of the channel via 210 extending into the substrate 300. Exemplarily, the epitaxial layer 400 may be formed within the channel via 210 using a selective epitaxial growth (SEG) process; specifically, the epitaxial layer 400 may be formed by filling the area near the bottom of the channel via 210 with a semiconductor material epitaxially grown from the substrate 300. The fabrication process for epitaxially growing the epitaxial layer 400 may include, but is not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. The epitaxial layer 400 may be at least one of epitaxial silicon, silicon-germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials.

[0055] In an exemplary embodiment of this application, a channel structure 200 may be formed on the epitaxial layer 400. Figure 6 For example, after forming the epitaxial layer 400, a channel structure 200 can be formed on the epitaxial layer 400 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Specifically, a functional layer 220 and a channel layer 230 can be sequentially formed on the upper surface of the epitaxial layer 400 away from the substrate 300 and within the channel via 210 to form the channel structure 200. Figure 7 ).

[0056] Functional layer 220 may include a barrier layer 221 formed within the channel via 210 to prevent charge outflow, a charge trapping layer 222 within the barrier layer 221 to store charge during operation of the 3D memory, and a tunneling layer 223 within the charge trapping layer 222. The barrier layer 221 may include one or more layers, which may include one or more materials. Materials for the barrier layer 221 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as alumina or hafnium oxide, or other wide-bandgap materials. The charge trapping layer 222 may include one or more layers, which may include one or more materials. Materials for the charge trapping layer 222 may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, or other wide-bandgap materials. The tunneling layer 223 may include one or more layers, which may include one or more materials. Materials for the tunneling layer 223 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as alumina or hafnium oxide, or other wide-bandgap materials. For example, functional layer 220 may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that functional layer 220 may also have a structure different from the ONO configuration. For example, functional layer 220 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0057] The channel layer 230 may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer 230 includes, but is not limited to, p-type doped polycrystalline silicon. Specifically, the channel via 210 may be filled with a filling semiconductor layer to form the channel layer 230. The filling dielectric layer may include an oxide dielectric layer, such as silicon oxide. Further, during the filling process, multiple insulating gaps may be formed in the filling dielectric layer by controlling the channel filling process to alleviate structural stress. The channel layer 230 can be used to transport the required charge (electrons or holes). Exemplarily, the channel layer 230 may be formed on the surface of the tunneling layer 223 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0058] In an exemplary embodiment of this application, the insulating layer 111 and the sacrificial layer 112 may be processed to form a plurality of stepped steps 500. Figure 6It should be understood that the channel structure 200 can be used to form array memory cell strings, which can be multiple interconnected memory cells formed in a direction perpendicular to the substrate 300; the stepped region can be used to form word line contacts 510 on the gate layer (the gate layer can be formed by replacing the sacrificial layer) to draw current therefrom. The three-dimensional memory provided in this application can have a core region and a staircase structure along the second direction X, wherein the staircase structure SS can be used to form multiple stepped sections 500, and the core region can be used to form a memory array composed of multiple channel structures 200 arranged and distributed. In addition, the first direction Y, the second direction X, and the third direction Z are perpendicular to each other.

[0059] In an exemplary embodiment of this application, a plurality of stepped steps 500 are first formed by repeatedly etching and trimming the stacked structure 100 using a patterned mask (not shown). The patterned mask may include a photoresist or a carbon-based polymer material and may be removed after the stepped steps 500 are formed. The top surface of each formed stepped step 500 first exposes at least a portion of the insulating layer 111 located in the corresponding layer; then, the exposed portion of the insulating layer 111 of each stepped step 500 may be removed to expose at least a portion of the sacrificial layer 112 of each stepped step 500. In other words, each stepped step 500 may include at least one level, and each level may include a sacrificial layer 112 and an insulating layer 111 from top to bottom. Exemplarily, each level may include a sacrificial layer 112 and an insulating layer 111 sequentially from top to bottom.

[0060] In exemplary embodiments of this application, the stepped steps 500 may be formed at the center of the stacked structure 100, or on one or more edges of the stacked structure 100. As an example, the following description primarily focuses on stepped steps 500 formed on one or more edges of the stacked structure 100. Furthermore, it should be noted that, for the sake of clarity and conciseness, the accompanying drawings only show the case where each stepped step 500 comprises one level. It should also be noted that the number of stepped steps 500 can be adjusted as needed, depending on the number of sacrificial layers 112 in the stacked structure 100 and the number of levels contained in each stepped step 500.

[0061] For example, such as Figure 6As shown, a dielectric layer 520 can also be formed on the stepped step 500 to cover the stepped step 500. Exemplarily, while forming the via 210, multiple virtual vias can also be formed in the stacked structure 100. The virtual vias can pass through the dielectric layer 520 and the stepped step 500 and extend to the substrate 300. The formation process of the virtual vias is the same as that of the via 210 and will not be described in detail here. Exemplarily, insulating material can be filled into the virtual vias to form a virtual channel structure 530. The virtual channel structure 530 is typically disposed around the word line contacts 510 formed in subsequent process steps to provide protection and support for the word line contacts 510. Exemplarily, vias 240, such as gate line gaps, can be formed in the stacked structure 100 between the channel structures 200. The gate line gaps 240 can pass through the stacked structure 100 along the thickness direction of the stacked structure 100 and extend into the substrate 300. The sacrificial layer 112 can be removed via the gate line gap 240, and the removed space can be filled with conductive material to form the gate layer 113. Figure 6 Then, the gate line gap 240 can be filled to form a gate line gap structure 241. The gate layer 113 can extend laterally (perpendicular to the thickness direction of the stack structure 100) as a word line and terminate at one or more step 500 of the stack structure 100.

[0062] In an exemplary embodiment of this application, word line contacts 510 connected to the gate layer 113 may be formed on the surface of the exposed portion of the gate layer 113. Exemplarily, a plurality of contact holes (not shown) may be formed along a direction perpendicular to the thickness of the stacked structure 100, passing through the dielectric layer 520 and extending to the gate layer 113. The formed contact holes are then filled with conductive material to form word line contacts 510 connected to the top surface of each gate layer 113. The word line contacts 510 can be used to electrically connect to the gate layer 113 to draw current from the gate layer 113.

[0063] In an exemplary embodiment of this application, a channel plug 250 may be formed at a first end of the channel layer 230 away from the substrate 300. The channel plug 250 may be made of a conductive material, such as p-type doped polysilicon. Exemplarily, a first terminal line contact 260 may be formed on the channel plug 250. Figure 6 ), used to electrically connect the channel plug 250 to the back-end process (BEOL) metal line.

[0064] Step S2

[0065] Multiple bit lines 610, each corresponding to multiple columns of the channel structure 200 and extending along the first direction Y, can be formed. For example, a bit line 610 extending along the first direction Y can be formed at the first end (the end away from the substrate 300) of each column of the channel structure 200. Figure 8 ).like Figure 8 As shown, the channel structure 200 can be arranged in multiple columns along the first direction Y, and multiple bit lines 610 can be connected to the first end of the corresponding column of the channel structure 200. For example, a bit line 610 extending along the first direction Y can be formed at the first end of the channel layer 230 of each column of the channel structure 200, such as a bit line 610 extending along the first direction Y can be formed on each column of channel plugs 250. A first end bit line contact 260 can be used to electrically connect the bit line 610 to the channel plug 250. The first end bit line contact 260 electrically connects the bit line 610 to the channel plug 250 at the upper end of the corresponding memory cell string, and can be used to individually address the corresponding memory cell string. For example, the distance between two adjacent bit lines 610 can be greater than or equal to the spacing between two adjacent columns of the channel structure 200. In conventional processes, at least two bit lines need to be provided at the first end of each column of the channel structure to achieve addressing of memory cell strings. This would severely limit the width of the bit lines, increase the difficulty of the manufacturing process, and also increase the bit line density, resulting in smaller intervals between adjacent bit lines and increasing the risk of short circuits between them. However, in this application, by setting a bit line 610 at the first end of each channel structure, not only can the width of the bit lines be increased and the difficulty of the manufacturing process be reduced, but the density of the bit lines can also be reduced, resulting in larger intervals between adjacent bit lines and reducing the risk of short circuits between them.

[0066] In an exemplary embodiment of this application, such as Figure 9 As shown, a peripheral circuit chip 700 can be connected to the side of the stacked structure 100 away from the substrate 300, wherein the peripheral circuit chip 700 may include peripheral circuitry 710. One surface of the peripheral circuit chip 700 is bonded to the top surface of the array chip (including the substrate 300 and the stacked structure). Exemplarily, the peripheral circuitry 710 may include one or more of page buffers, decoders (e.g., row decoders and / or column decoders), drivers, charge pumps, current and / or voltage references, and / or any active and / or passive components (e.g., transistors, diodes, resistors, and / or capacitors) required in the circuitry. In some embodiments, the peripheral circuitry may be formed using CMOS technology, but is not limited thereto.

[0067] Figure 10 To be Figure 9 A schematic diagram of a structure that has been thinned after being flipped 180°. (Reference) Figure 10 The substrate 300 can be thinned from the bottom using a planarization process, such as using a chemical mechanical polishing (CMP) process to thin the substrate 300 and form the surface 310 of the thinned substrate 300.

[0068] For example, such as Figure 11 and Figure 12 As shown, the epitaxial layer 400 can be removed based on surface 310 by employing multiple etching processes, such as dry etching or a combination of dry and wet etching processes. Figure 11 ), and continue removing the tunneling layer 223, charge trapping layer 222, and barrier layer 221 downwards to expose the second end of the channel layer 230 near the substrate 300. Figure 12 It should be understood that in this removal process, exposing the second end of the channel layer 230 near the substrate 300 achieves the purpose of this application. Therefore, this application only exemplarily describes one removal process and does not specifically limit the removal process used. Alternatively, a portion of the sidewall region of the second end of the channel layer 230 may be removed. Alternatively, removal may be performed along the direction where subsequent source line addition is desired to expose the second end of the channel layer 230 near the substrate 300. In the exemplary embodiments of this application, as... Figure 13 As shown, the second end of the channel layer 230 exposed after removing the epitaxial layer 400, tunneling layer 223, charge trapping layer 222, and barrier layer 221 can be highly doped. For example, the second end of the channel layer 230 exposed on the surface 310 can be highly N-type doped. Specifically, the channel layer 230 can be N-type doped via the substrate surface 310 using a process such as ion implantation (IMP). The aforementioned N-type doping can include any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), to increase the conductivity of the end of the channel layer 230 near the original substrate.

[0069] In an exemplary embodiment of this application, multiple air gaps are generated during the removal of the epitaxial layer 400, tunneling layer 223, charge trapping layer 222, and barrier layer 221. After highly doping the end of the channel layer 230 near the original substrate, a new substrate can be formed by filling the air gaps with conductive material (i.e., forming a conductive layer 800 at the second end of the channel layer 230) using, for example, a deposition process. A planarization process, such as mechanical chemical polishing (CMP), is then used to planarize the newly formed substrate 320. Figure 14 The conductive layer 800 can be made of a conductive material, such as polycrystalline silicon or doped polycrystalline silicon. For example, a second source terminal contact 810 can be formed on the conductive layer 800. Figure 15 ), used to electrically connect the conductive layer 800 to the subsequently formed source line.

[0070] Step S3

[0071] Multiple source lines 620 extending along the second direction X, corresponding to multiple rows of channel structures 200, can be formed. For example, source lines 620 extending along the second direction X can be formed at the second end (the end closer to the substrate 300) of each row of channel structures 200 opposite to the first end. Figure 16 ).like Figure 16 As shown, the channel structure 200 can be arranged in multiple rows along the second direction X, and multiple source lines 620 can be connected to the second end of the corresponding row of channel structure 200. For example, a source line 620 extending along the second direction X can be formed at the second end of the channel layer 230 of each row of channel structure 200, such as a source line 620 extending along the second direction X can be formed on the conductive layer 800. The second-end source line contact 810 can be used to electrically connect the source line 620 to the conductive layer 800. The second-end source line contact 810 electrically connects the source line 620 to the conductive layer 800 at the upper end of the corresponding memory cell string, and can be used to individually address the corresponding memory cell string. For example, the channel structure 200 (memory cell string) can be addressed via the bit line 610 and the source line 620. For example, power can be supplied to multiple bit lines 610 and multiple source lines 620 to address any channel structure 200. Figure 16 As shown, the corresponding channel structure 200' can be addressed by supplying power to bit line 610' and source line 620'.

[0072] For example, the distance between two adjacent source lines 620 can be greater than or equal to the spacing between two adjacent rows of channel structures 200. In this application, by providing a bit line 610 at the first end of each column of channel structures and a source line 620 at the second end of each row of channel structures 200, the channel structure 200 is addressed through the bit line 610 and the source line 620. This not only helps to reduce the number of bit lines, increase the width of the bit lines, and reduce the difficulty of the manufacturing process, but also reduces the density of bit lines, makes the spacing between adjacent bit lines larger, and reduces the short-circuit risk between adjacent bit lines.

[0073] like Figure 16 and Figure 17 As shown, the channel structure 200 is arranged in an array in the first direction Y and the second direction X, that is, the channel structure 200 is distributed in multiple columns in the first direction Y and in multiple rows in the second direction X. This application provides a bit line 610 at the first end of the channel structure 200 in the first direction Y and a source line 620 at the second end of the channel structure 200 in the second direction X, which facilitates the selection of a specific channel structure 200 by simultaneously controlling one bit line 610 and one source line 620. For example, the angle between the first direction Y and the second direction X can be less than or equal to 90°.

[0074] In an exemplary embodiment of this application, insulating material 820 can be filled into the air gap between a plurality of second-end source line contacts 810 to insulate the plurality of second-end source line contacts 810 from each other. The top surface of the insulating material 820 may be on the same horizontal line as the top surface of the second-end source line contacts 810. It should be understood that the purpose of this application can be achieved by insulating the plurality of second-end source line contacts 810 from each other in the process of filling the insulating material 820. Therefore, this application only describes one removal process by example and does not specifically limit the filling process used. Alternatively, insulating material 820 can be filled into the area removed by the above removal process.

[0075] Exemplarily, a metal layer 830 may also be formed on the insulating material 820 and the second source line contact 810 to electrically connect the second source line contact 810. It should be understood that the purpose of the metal layer 830 in this application is to electrically connect the metal layer 830 to the second source line contact 810. Therefore, the metal layer 830 can be disposed at any suitable location to electrically connect the second source line contact 810. For example, the metal layer 830 may be formed only on the second source line contact 810. This application only exemplarily describes one way of forming the metal layer 830 and does not specifically limit the method of forming the metal layer 830. Exemplarily, a passivation layer 840 may also be formed on the metal layer 830 to passivate and protect the three-dimensional memory. It should be understood that the second terminal line contact 810, insulating material 820, metal layer 830 and passivation layer 840 can be sequentially formed on the substrate surface 320 by thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0076] This application also provides a three-dimensional memory. Figure 15 A schematic diagram of the structure of a three-dimensional memory according to an exemplary embodiment of this application is shown.

[0077] A three-dimensional memory may include a stacked structure, a channel structure 200, multiple bit lines 610, and multiple source lines 620. Figure 16 ).

[0078] In an exemplary embodiment of this application, the stacked structure may include an insulating layer 111 and a gate layer 113 stacked alternately.

[0079] The channel structure 200 can pass through the stacked structure. The channel structure 200 can be arranged in multiple columns and multiple rows along the first direction Y and the second direction X, respectively. Specifically, the channel structure 200 can be distributed in multiple columns along the first direction Y and in multiple rows along the second direction X. For example, the angle between the first direction Y and the second direction X can be less than or equal to 90°.

[0080] The channel structure 200 may include a functional layer 220 and a channel layer 230. Figure 7 The functional layer 220 may include a barrier layer 221 that blocks charge outflow, a charge trapping layer 222 within the barrier layer 221 for storing charge during operation of the three-dimensional memory, and a tunneling layer 223 within the charge trapping layer 222. The barrier layer 221 may include one or more layers, which may include one or more materials. Materials for the barrier layer 221 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as alumina or hafnium oxide, another wide-bandgap material, etc. The charge trapping layer 222 may include one or more layers, which may include one or more materials. Materials for the charge trapping layer 222 may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide-bandgap material, etc. The tunneling layer 223 may include one or more layers, which may include one or more materials. Materials for the tunneling layer 223 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as alumina or hafnium oxide, another wide-bandgap material, etc. Exemplarily, the functional layer 220 may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that functional layer 220 may also have a structure different from the ONO configuration. For example, functional layer 220 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer. Channel layer 230 may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of channel layer 230 includes, but is not limited to, p-type doped polycrystalline silicon.

[0081] Multiple bit lines 610 can correspond to multiple columns of the channel structure 200, and can be electrically connected to the first end of the corresponding column of the channel structure 200, and can extend along the first direction Y. Multiple source lines 620 can correspond to multiple rows of the channel structure 200, and can be electrically connected to the second end of the corresponding row of the channel structure 200, and can extend along the second direction X. The second end is opposite to the first end, and the channel structure 200 can be addressed through the bit lines 610 and the source lines 620. For example, by setting the bit line 610 at the first end of the channel structure 200 in the first direction X and the source line 620 at the second end of the channel structure 200 in the second direction Y, this application is advantageous in that a specific channel structure 200 can be selected by simultaneously controlling one bit line 610 and one source line 620.

[0082] In an exemplary embodiment of this application, bit line 610 can be electrically connected to the channel layer 230 of the corresponding column channel structure 200, such as bit line 610 can be electrically connected to the corresponding column channel plug 250. A first terminal bit line contact 260 can be used to electrically connect bit line 610 to the channel plug 250. The first terminal bit line contact 260 connects bit line 610 to the channel plug 250 at the upper end of the corresponding memory cell string, and can be used to individually address the corresponding memory cell string. Exemplarily, the distance between two adjacent bit lines 610 can be greater than or equal to the spacing between two adjacent column channel structures 200. In conventional processes, at least two bit lines need to be provided at the first end of each column channel structure to achieve addressing of memory cell strings. This severely limits the width of the bit lines, increases the difficulty of the manufacturing process, and also increases the bit line density, resulting in smaller spacing between adjacent bit lines and increasing the risk of short circuits between adjacent bit lines. However, in this application, by setting a bit line 610 at the first end of each channel structure, not only can the width of the bit line be increased and the difficulty of the manufacturing process be reduced, but the density of the bit line can also be reduced, making the interval between adjacent bit lines larger and reducing the risk of short circuit between adjacent bit lines.

[0083] In an exemplary embodiment of this application, the three-dimensional memory further includes a conductive layer 800 located at the second end of the channel layer 230. Exemplarily, a source line 620 may be electrically connected to the second end of the channel layer 230 of a corresponding row channel structure 200, such as a source line 620 extending in a second direction X formed on the conductive layer 800. A second-end source line contact 810 may be used to electrically connect the source line 620 to the conductive layer 800. A second-end bit line contact 810 electrically connects the source line 620 to the conductive layer 800 at the upper end of the corresponding memory cell string, and may be used to individually address the corresponding memory cell string. Exemplarily, the channel structure 200 (memory cell string) can be addressed via the bit line 610 and the source line 620. Exemplarily, any channel structure 200 can be addressed by supplying power to multiple bit lines 610 and multiple source lines 620. For example, as... Figure 16 As shown, the corresponding channel structure 200' can be addressed by supplying power to bit line 610' and source line 620'.

[0084] For example, the distance between two adjacent source lines 620 can be greater than or equal to the spacing between two adjacent rows of channel structures 200. In this application, by providing a bit line 610 at the first end of each column of channel structures and a source line 620 at the second end of each row of channel structures 200, the channel structure 200 is addressed through the bit line 610 and the source line 620. This not only helps to reduce the number of bit lines, increase the width of the bit lines, and reduce the difficulty of the manufacturing process, but also reduces the density of bit lines, makes the spacing between adjacent bit lines larger, and reduces the short-circuit risk between adjacent bit lines.

[0085] In an exemplary embodiment of this application, the three-dimensional memory may further include a stepped step 500 located in the stacked structure 100'. The stepped step 500 may be formed by processing an insulating layer 111 and a sacrificial layer 112. Each stepped step 500 may include at least one level, each level including the sacrificial layer 112 and the insulating layer 111 sequentially from top to bottom. Exemplarily, the three-dimensional memory may further include a virtual channel structure 530 passing through the stepped step 500. Exemplarily, the three-dimensional memory may further include word line contacts 510 connecting the surface of the exposed portion of the gate layer 113. The word line contacts 510 may be used to electrically connect to the gate layer 113 to draw current from the gate layer 113. The virtual channel structure 530 is typically disposed around the word line contacts 510 formed in subsequent process steps to provide protective support for the word line contacts 510.

[0086] In an exemplary embodiment of this application, the three-dimensional memory may further include a peripheral circuit chip 700 connected to the side of the stacked structure 100 remote from the substrate 300. The peripheral circuit chip 700 may include peripheral circuitry 710. One surface of the peripheral circuit chip 700 is joined and bonded to the top surface of the array chip (including the substrate 300 and the stacked structure). Exemplarily, the peripheral circuitry 710 may include one or more of a page buffer, a decoder (e.g., a row decoder and / or a column decoder), a driver, a charge pump, a current and / or voltage reference, and / or any active or passive components required in the circuitry (e.g., transistors, diodes, resistors, and / or capacitors).

[0087] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated here.

[0088] Figure 18 This is a schematic diagram of the structure of a storage system 2000 according to one embodiment of this application.

[0089] like Figure 18 As shown, at least one embodiment of this application also provides a storage system 2000. The storage system 2000 may include a controller 2200 and at least one three-dimensional memory 2100. The three-dimensional memory 2100 may be the same as the three-dimensional memory described in any of the embodiments above, and will not be described again in this application.

[0090] The controller 2200 can be coupled to the 3D memory 2100 via channel CH to control the 3D memory 2100 to store data. The 3D memory 2100 can receive commands CMD and addresses ADDR from the controller 2200 via channel CH and access the region selected from the memory cell array in response to the address. In other words, the 3D memory 2100 can perform internal operations corresponding to commands on the region selected by the address.

[0091] In some implementations, the storage system 2000 may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0092] Figure 19 This is a schematic diagram of the structure of the electronic device 3000 provided in the embodiments of this application.

[0093] like Figure 19 As shown, at least one embodiment of this application also provides an electronic device 3000. The electronic device 3000 includes a storage system 3100. The storage system 3100 may be the same as the storage system described in any of the embodiments above, and will not be repeated here. The electronic device 3000 may be a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, power bank, or other device with storage functionality. Therefore, other modules of the electronic device 3000, such as a controller, can be determined according to the specific device type of the electronic device 3000. Other modules can be coupled to the storage system 3100 via channels and interact with the storage system 3100.

[0094] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely exemplary.

[0095] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A layered structure is formed, and a channel structure is formed through the layered structure, wherein the channel structure is arranged in multiple columns and multiple rows along a first direction and a second direction, respectively; Multiple bit lines are formed that correspond one-to-one with multiple columns of the channel structure and extend along the first direction, wherein the multiple bit lines are electrically connected to the first end of the channel structure of the corresponding column. as well as Multiple source lines are formed that correspond one-to-one with multiple rows of the channel structure and extend along the second direction, wherein the multiple source lines are electrically connected to the second end of the corresponding row of the channel structure opposite to the first end.

2. The preparation method according to claim 1, characterized in that, Any channel structure can be addressed by supplying power to the plurality of bit lines and the plurality of source lines.

3. The preparation method according to claim 1, characterized in that, The distance between two adjacent bit lines is greater than or equal to the spacing between two adjacent columns of channel structures; and The distance between two adjacent source lines is greater than or equal to the spacing between two adjacent rows of channel structures.

4. The preparation method according to claim 1, characterized in that, The angle between the first direction and the second direction is less than or equal to 90°.

5. The preparation method according to claim 1, characterized in that, The stacked structure is formed on a substrate, wherein forming a channel structure through the stacked structure includes: Forming channel holes that penetrate the stacked structure and extend to the substrate; An epitaxial layer is formed within the channel hole; and A channel structure is formed on the epitaxial layer, wherein the channel structure includes a functional layer and a channel layer.

6. The preparation method according to claim 5, characterized in that, The bit line and the source line are electrically connected to the first end and the second end of the channel layer, respectively, wherein the first end of the channel layer is far away from the substrate, and the second end of the channel layer is close to the substrate.

7. The preparation method according to claim 5, characterized in that, Forming a source line extending along the second direction at the second end of each row of the channel layer includes: At least a portion of the substrate, the epitaxial layer, and the functional layer is removed to expose the second end of the channel layer; and A source line extending along the second direction is formed at the second end of each row of the channel layer.

8. The preparation method according to claim 7, characterized in that, The method further includes: The second end of the channel layer is doped.

9. The preparation method according to claim 7 or 8, characterized in that, The method further includes: A conductive layer is formed at the second end of the channel layer, and the conductive layer is planarized; and The source line extending along the second direction is formed on the conductive layer.

10. The method according to claim 5, characterized in that, The formation of a layered structure includes: The insulating layer and the sacrificial layer are alternately stacked on the substrate to form the stacked structure.

11. The preparation method according to claim 10, characterized in that, The method further includes: The insulating layer and the sacrificial layer are processed to form a plurality of stepped steps, wherein a portion of the sacrificial layer is exposed as the upper surface of the stepped steps; Forming through-holes through the stacked structure and virtual channel structures through the stepped steps; and The sacrificial layer is replaced with a gate layer via the via.

12. The preparation method according to claim 11, characterized in that, The method further includes: A word line contact connected to the gate layer is formed on the surface of the exposed portion of the gate layer.

13. The preparation method according to any one of claims 10-12, characterized in that, The method further includes: The side of the stacked structure away from the substrate is connected to a peripheral circuit chip, wherein the peripheral circuit chip includes peripheral circuitry.

14. A three-dimensional memory, characterized in that, include: Stacked structure; A channel structure passing through the stacked structure, wherein the channel structure is arranged in multiple columns and multiple rows along a first direction and a second direction, respectively; Multiple bit lines correspond one-to-one with multiple columns of the channel structure, and are electrically connected to the first end of the channel structure of the corresponding column, and extend along the first direction; as well as Multiple source lines correspond one-to-one with multiple rows of the channel structure, and are electrically connected to the second end of the corresponding row of the channel structure opposite to the first end, and extend along the second direction.

15. The three-dimensional memory according to claim 14, characterized in that, The plurality of bit lines and the plurality of source lines address any channel structure.

16. The three-dimensional memory according to claim 14, characterized in that, The distance between two adjacent bit lines is greater than or equal to the spacing between two adjacent columns of channel structures; and The distance between two adjacent source lines is greater than or equal to the spacing between two adjacent rows of channel structures.

17. The three-dimensional memory according to claim 14, wherein the angle between the first direction and the second direction is less than or equal to 90°.

18. The three-dimensional memory according to claim 14, characterized in that, The three-dimensional memory also includes: A conductive layer is located at the second end of the channel layer of the channel structure, wherein the source line is connected to the conductive layer.

19. A storage system, characterized in that, The storage system includes a controller and a three-dimensional memory according to any one of claims 14-18, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

20. An electronic device, characterized in that, include: The storage system of claim 19.

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