Semiconductor device and method of manufacturing the same

Abstract

The present application relates to semiconductor devices and methods of manufacturing the same. A method for manufacturing a semiconductor device includes forming a lower structure including an interconnect, forming a first contact plug coupled to the interconnect, forming an alternating stack of a dielectric layer and a sacrificial layer over the first contact plug and the lower structure. The method also includes forming an opening through the alternating stack and exposing the first contact plug, forming a sacrificial plug including a void in the opening, forming a contact hole exposing the first contact plug by etching a portion of the sacrificial plug, and forming a second contact plug in the contact hole.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to semiconductor devices, and more particularly, to vertical semiconductor devices and methods for fabricating the vertical semiconductor devices. Background Art

[0002] A semiconductor device such as a three-dimensional (3D) NAND memory device has a structure in which a plurality of memory cells are arranged in a direction of a vertical channel by covering the vertical channel with a memory layer. Summary of the Invention

[0003] Some embodiments of the present disclosure relate to a semiconductor device having improved reliability and a method for manufacturing the semiconductor device.

[0004] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a lower structure including an interconnect; forming a first contact plug connected to the interconnect; forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the lower structure; forming an opening that penetrates the alternating stack and exposes the first contact plug; forming a sacrificial plug including a gap in the opening; forming a contact hole exposing the first contact plug by etching a portion of the sacrificial plug; and forming a second contact plug in the contact hole.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a source structure including a first contact plug over a lower structure including an interconnect, wherein the first contact plug is connected to the interconnect; forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the source structure; forming a vertical channel structure that penetrates a portion of the alternating stack; forming a sacrificial plug embedded with a void that is spaced apart from the vertical channel structure, penetrates the alternating stack and is connected to the first contact plug; replacing a portion of the sacrificial layer with a gate electrode to surround the vertical channel structure; forming a contact hole exposing the first contact plug by etching a portion of the sacrificial plug embedded with the void; forming a pad contact hole exposing an edge of the gate electrode; forming a contact plug in the contact hole; and forming a gate contact plug in the pad contact hole.

[0006] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a source structure including a first contact plug over a lower structure including an interconnect, wherein the first contact plug is connected to the interconnect; forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the source structure; forming a vertical channel structure passing through the alternating stack; forming a hole-type opening exposing the first contact plug and a line-type opening adjacent to the hole-type opening, the hole-type opening and the line-type opening being spaced apart from the vertical channel structure and passing through the alternating stack; forming a sacrificial plug embedded with a void in the hole-type opening; filling the line-type opening with a void-free support member; replacing a portion of the sacrificial layer with a gate electrode to surround the vertical channel structure; forming a contact hole exposing the first contact plug by etching a portion of the sacrificial plug embedded with the void; forming a pad contact hole exposing an edge of the gate electrode; forming a contact plug in the contact hole; and forming a gate contact plug in the pad contact hole.

[0007] According to another embodiment of the present disclosure, a semiconductor device includes: a lower structure including an interconnect; a source contact structure above the lower structure; a first contact plug connected to the interconnect and extending through the source contact structure; a first alternating stack located above the first contact plug and including an alternating first dielectric layer and a gate-level dielectric layer; a second alternating stack located adjacent to the first alternating stack and including an alternating second dielectric layer and a gate electrode; linear supports without gaps between the first alternating stack and the second alternating stack; a second contact plug connected to the first contact plug and extending through the first alternating stack between the linear supports without gaps; a conformal sidewall liner surrounding the sidewalls of the second contact plug; and a gate contact plug connected to an edge of a gate electrode of the second alternating stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2A It is along Figure 1 A cross-sectional view taken along line AA' shown in FIG.

[0010] Figure 2B It is along Figure 1 A cross-sectional view taken along line BB' shown in FIG.

[0011] Figure 2C It is along Figure 1 A cross-sectional view taken along line CC' shown in FIG.

[0012] Figures 3 to 21 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] Some embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the present teachings can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to enable those skilled in the art to implement the present disclosure. Throughout this disclosure, throughout the various figures and embodiments, like reference numerals refer to like parts.

[0014] The drawings are not necessarily drawn to scale, and in some cases, proportions may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on a substrate," it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the presence of a third layer between the first layer and the second layer or substrate.

[0015] Figure 1 is a layout diagram illustrating a semiconductor device 100 according to an embodiment. Figure 2A It is along Figure 1 A cross-sectional view taken along line AA' shown in FIG. Figure 2B It is along Figure 1 A cross-sectional view taken along line BB' shown in FIG. Figure 2C It is along Figure 1 A cross-sectional view taken along line CC' shown in FIG.

[0016] Reference Figure 1 and Figures 2A to 2C , the semiconductor device 100 may include a lower structure 100L disposed on a semiconductor substrate 101. The lower structure 100L may include a transistor (not shown) and an interconnect 102. The transistor may include, for example, an NMOSFET, a PMOSFET, a CMOSFET, etc. The transistor and the interconnect 102 may be covered with an interlayer dielectric layer 103. The lower structure 100L may serve as a circuit for operating a memory cell included in the memory device. The lower structure 100L may be referred to as a peripheral circuit portion. The semiconductor device 100 may include a vertical NAND.

[0017] The source structure 110 may be formed above the lower structure 100L. The source structure 110 may include source conductive layers 111 and 113, and a source horizontal contact layer 112 located between the source conductive layers 111 and 113. The source conductive layers 111 and 113 and the source horizontal contact layer 112 may include semiconductor materials. The source horizontal contact layer 112 may be doped with conductive impurities such as phosphorus, arsenic, boron, etc. For example, the source horizontal contact layer 112 may include phosphorus-doped polysilicon. According to another embodiment, the source horizontal contact layer 112 may be doped with non-conductive impurities or with both conductive and non-conductive impurities. For example, the source horizontal contact layer 112 may include carbon-doped polysilicon. According to another embodiment, the source horizontal contact layer 112 may include a double layer of phosphorus-doped polysilicon and carbon-doped polysilicon. The source conductive layers 111 and 113 and the source horizontal contact layer 112 may include polysilicon.

[0018] A first contact plug 114 may be formed penetrating the source structure 110, and a spacer 115 may be formed on a sidewall of the first contact plug 114. The first contact plug 114 may be coupled to at least one of the interconnections 102 of the lower structure 100L.

[0019] The upper structure 120 may be formed above the source structure 110. The upper structure 120 may include a first alternating stack ON and a second alternating stack OW. In the second alternating stack OW, the dielectric layer 121 and the gate electrode 122 may be alternately stacked in the vertical direction D2. In the first alternating stack ON, the dielectric layer 121 and the gate-level dielectric layer 122R may be alternately stacked in the vertical direction D2. The second alternating stack OW may include two end portions, and the first alternating stack ON may be located between the end portions of the second alternating stack OW. The two end portions of the second alternating stack OW may be regions where the pad portion of the gate electrode 122 is formed. The height of the second alternating stack OW and the height of the first alternating stack ON may be the same. The second alternating stack OW may be located in the cell array region AR, and the first alternating stack ON may be located in the contact region CR. The contact region CR may include a region where the pad portion of the gate electrode 122 is formed. The contact region CR may further include a region in which a first contact plug 114 coupled to the interconnection 102 is formed.

[0020] A plurality of supports 131 and 131P may be formed extending through the upper structure 120. The supports 131 and 131P may include linear supports 131 and column supports 131P. The linear supports 131 may be formed between the ends of the second alternating stack OW and the first alternating stack ON, and may extend in the first direction D1. The column supports 131P may extend through the ends of the second alternating stack OW in the second direction D2. The first alternating stack ON may be located between the linear supports 131.

[0021] The conformal liner 128L may be formed on the sidewall of the linear support member 131. The linear support member 131 and the columnar support member 131P may be support members without a void.

[0022] A second contact plug 153 may be formed to penetrate the first alternating stack ON. The second contact plug 153 may be formed above the first contact plug 114. The first contact plug 114 and the second contact plug 153 may be formed of the same material. The first contact plug 114 may have a greater width than the second contact plug 153. A conformal sidewall liner 128S may be formed on the sidewalls of the second contact plug 153. A non-conformal layer 126 may be formed above the conformal sidewall liner 128S. The non-conformal layer 126 may be formed above the uppermost dielectric layer 121.

[0023] A plurality of channel structures VC may be formed through the second alternating stack OW of the upper structure 120. The channel structure VC may include a memory layer V1 and a channel layer V2. The memory layer V1 may include an oxide-nitride-oxide (ONO) structure. An ONO structure may include a stack of oxides, nitrides, and oxides. The memory layer V1 may include a stack of a blocking layer, a charge trapping layer, and a tunnel dielectric layer. The blocking layer and the tunnel dielectric layer may include an oxide, and the charge trapping layer may include a nitride. The channel layer V2 may include a polysilicon layer. According to another embodiment, the blocking layer may include a high-k material, and the high-k material may include aluminum oxide or hafnium oxide. The channel layer V2 may have a cylindrical shape with an interior space. The memory layer V1 may surround the outer wall of the channel layer V2. The channel structure VC may also include a core dielectric layer V3. The interior space of the channel layer V2 may be completely filled with the core dielectric layer V3. The core dielectric layer V3 may include silicon oxide or silicon nitride. Although not illustrated, a conductive pad coupled to the upper end of the channel layer V2 may be further formed after the core dielectric layer V3 is recessed. The gate electrode 122 may surround the channel structure VC. The channel structure VC may penetrate the dielectric layer 121 and the gate electrode 122.

[0024] A lower sidewall of the channel structure VC may be coupled to the source structure 110. For example, the channel layer V2 of the channel structure VC may be directly coupled to the source horizontal contact layer 112. The memory layer V1 may be cut for direct contact between the channel layer V2 and the source horizontal contact layer 112.

[0025] The ends of the gate electrode 122 may be gate pad portions and may be formed into a stepped structure. The ends of the gate electrode 122 may be respectively connected to the gate contact plugs 154. The interlayer dielectric layer 150 may cover the stepped structure, and the gate contact plugs 154 may penetrate the interlayer dielectric layer 150 to be connected to the ends of the gate electrode 122. The columnar support member 131P may penetrate the stepped structure of the ends of the gate electrode 122.

[0026] The source horizontal contact layer 112 may be coupled to the source contact plug 142. A sealing layer 141 may be formed between the source contact plug 142 and the second alternating stack OW. The sealing layer 141 and the source contact plug 142 may fill the vertical slit 140. The sealing layer 141 may be formed on the sidewalls of the vertical slit 140, and the source contact plug 142 may be formed on the sealing layer 141.

[0027] Figures 3 to 21 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. Figures 3 to 21 , the structure of the lower structure 100L except for the semiconductor substrate 101, the interconnection 102 and the interlayer dielectric layer 103 is omitted. Figures 3 to 21 In, with Figures 1 to 2C The same reference numerals as those in the drawings may denote the same constituent elements.

[0028] Reference Figure 3 , a source structure 110 may be formed over a lower structure 100L including a semiconductor substrate 101 , an interconnection 102 , and an interlayer dielectric layer 103 .

[0029] The semiconductor substrate 101 may include a silicon substrate, a single crystal silicon substrate, a polycrystalline silicon substrate, an amorphous silicon substrate, a silicon germanium substrate, a single crystal silicon germanium substrate, a polycrystalline silicon germanium substrate, a carbon-doped silicon substrate, a combination thereof, or a multilayer thereof. The semiconductor substrate 101 may also include another semiconductor material such as germanium. The semiconductor substrate 101 may include a Group III / V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The semiconductor substrate 101 may include a silicon-on-insulator (SOI) substrate. Although not shown, a transistor including a gate electrode may be formed on the semiconductor substrate 101.

[0030] The source structure 110 may have a multi-layer structure in which a sacrificial source layer 112B is located between source conductive layers 111 and 113. The source structure 110 may further include a plurality of liner layers 112A and 112C. The liner layers 112A and 112C may be located between the source conductive layers 111 and 113 and the sacrificial source layer 112B.

[0031] The source conductive layers 111 and 113 and the sacrificial source layer 112B may have an etching selectivity relative to the liner layers 112A and 112C. The source conductive layers 111 and 113 and the sacrificial source layer 112B may include a semiconductor material, and the liner layers 112A and 112C may include a dielectric material. The source conductive layers 111 and 113 and the sacrificial source layer 112B may include polysilicon, and the liner layers 112A and 112C may include silicon oxide. The liner layers 112A and 112C may be thinner than the source conductive layers 111 and 113 and the sacrificial source layer 112B. The sacrificial source layer 112B may have the same thickness as the source conductive layers 111 and 113 or may be thinner than the source conductive layers 111 and 113.

[0032] The liner layers 112A and 112C may protect the source conductive layers 111 and 113 while removing the subsequent sacrificial source layer 112B.

[0033] The liner layers 112A and 112C may include a silicon oxide-based material. At least one of the liner layers 112A and 112C may include SiO 2 , SiCO, or a combination thereof.

[0034] Reference Figure 4 , a first contact plug 114 may be formed through the source structure 110. To form the first contact plug 114, a contact hole (not shown) may be formed to penetrate the source structure 110 and the interlayer dielectric layer 103, and the contact hole may then be filled with a conductive material. The first contact plug 114 may include tungsten. The first contact plug 114 may be referred to as a "tungsten plug." For example, to form the first contact plug 114, a tungsten layer may be deposited, and then a planarization process may be performed. Spacers 115 may be formed on the sidewalls of the first contact plug 114, and the spacers 115 may be formed on the sidewalls of the contact hole before forming the first contact plug 114.

[0035] The first contact plug 114 may penetrate the source structure 110 to be electrically connected to the interconnection 102 .

[0036] Reference Figure 5 The upper structure 120 may be formed on the first contact plug 114 . The upper structure 120 may include an alternating stack in which dielectric layers 121 and sacrificial layers 122 ′ are alternately stacked. The height of the upper structure 120 may be greater than that of the source structure 110 .

[0037] The dielectric layer 121 and the sacrificial layer 122' may be formed of different materials. The dielectric layer 121 may have an etch selectivity relative to the sacrificial layer 122'. The dielectric layer 121 may include silicon oxide, and the sacrificial layer 122' may include silicon nitride. The dielectric layer 121 and the sacrificial layer 122' may have the same thickness. The dielectric layer 121 and the sacrificial layer 122' may be thicker than the liner layers 112A and 112C, and thinner than the source conductive layers 111 and 113.

[0038] The dielectric layers 121 and the sacrificial layer 122 ′ may be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. According to another embodiment, among the dielectric layers 121 , the lowermost and uppermost dielectric layers 121 may be formed thicker than the other dielectric layers 121 .

[0039] The dielectric layer 121 and the liner layers 112A and 112C may be formed of the same material. According to another embodiment, the liner layers 112A and 112C may have an etching selectivity with respect to the dielectric layer 121 .

[0040] Although not shown, after forming the upper structure 120 , a stepped structure (not shown) may be formed in a region of the contact region of the upper structure 120 where a pad portion is to be formed.

[0041] Reference Figure 6 The channel structure VC may be formed to penetrate the cell array region of the upper structure 120. The channel structure VC may have a pillar shape. The lower portion of the channel structure VC may extend to the inside of the source structure 110. The lower portion of the channel structure VC may not penetrate the source conductive layer 111 of the source structure 110.

[0042] The channel structure VC may include a memory layer V1 and a channel layer V2. The memory layer V1 may include an ONO structure. The ONO structure may include a stack of oxides, nitrides, and oxides. The memory layer V1 may include a stack of a blocking layer, a charge trapping layer, and a tunnel dielectric layer. The blocking layer and the tunnel dielectric layer may include oxides, and the charge trapping layer may include nitrides. The channel layer V2 may include a polysilicon layer. According to another embodiment, the blocking layer may include a high-k material, and the high-k material may include aluminum oxide or hafnium oxide.

[0043] The channel layer V2 may have a cylindrical shape including an inner space, and the memory layer V1 may surround an outer wall of the channel layer V2.

[0044] The channel structure VC may further include a core dielectric layer V3. The interior space of the channel layer V2 may be completely filled with the core dielectric layer V3. The core dielectric layer V3 may include silicon oxide or silicon nitride. Although not shown, a conductive pad coupled to the upper end of the channel layer V2 may be further formed after the core dielectric layer V3 is recessed.

[0045] Reference Figure 7 , a plurality of upper horizontal openings 123, 124, and 125 may be formed in the contact region of the upper structure 120. The upper horizontal openings 123, 124, and 125 may include a first upper horizontal opening 123, a second upper horizontal opening 124, and a third upper horizontal opening 125. From a top view perspective, the first upper horizontal opening 123 may be a hole-shaped opening, and the second upper horizontal opening 124 and the third upper horizontal opening 125 may be line-shaped openings having a plurality of branches. The first upper horizontal opening 123 may be located between the second upper horizontal opening 124 and the third upper horizontal opening 125. The first upper horizontal opening 123 may expose the upper surface of the first contact plug 114.

[0046] To form the upper horizontal openings 123 , 124 , and 125 , the upper structure 120 may be etched.

[0047] Reference Figure 8 , a non-conformal layer 126' may be formed over the upper horizontal openings 123, 124, and 125. Non-conformal layer 126' may include an overhang 127', and non-conformal layer 126' may not fill upper horizontal openings 123, 124, and 125. Non-conformal layer 126' may be formed of a material having poor step coverage. Non-conformal layer 126' may include an oxide, and the oxide having poor step coverage may include silicon oxide deposited by a plasma chemical vapor deposition method. Non-conformal layer 126' may include plasma enhanced tetraethyl orthosilicate (PETEOS).

[0048] Reference Figure 9 , conformal layer 128' may be formed on non-conformal layer 126'. Conformal layer 128' may be formed of a material having good step coverage. For example, the material of conformal layer 128' may have better step coverage than the material of non-conformal layer 126'. Conformal layer 128' may be formed by atomic layer deposition (ALD). Conformal layer 128' may include an oxide, such as silicon oxide deposited by ALD.

[0049] After forming conformal layer 128', upper horizontal openings 123, 124, and 125 may each include a void 129'. Void 129' may be formed by overhang 127' of non-conformal layer 126' during deposition of conformal layer 128'. Conformal layer 128' may be a silicon oxide layer embedded with voids. The size of void 129' may be sufficiently large to prevent void 129' from remaining closed during subsequent formation of contact hole 151.

[0050] Reference Figure 10 , conformal layer 128' and non-conformal layer 126' may be planarized. Even after planarization of conformal layer 128' and non-conformal layer 126', each of upper horizontal openings 123, 124, and 125 may include voids 129'. Planarized conformal layer 128 and planarized non-conformal layer 126 may have top surfaces of the same height. Due to the planarization of non-conformal layer 126', the height of overhang 127' may be reduced, and the reduced height overhang 127 may cover the top corners of upper horizontal openings 123, 124, and 125. Planarized conformal layer 128 may be referred to as a sacrificial support.

[0051] Reference Figure 11 , a mask layer 130 may be formed. Mask layer 130 may selectively expose the upper surfaces of conformal layer 128 and non-conformal layer 126. Mask layer 130 may include a photoresist pattern. Mask layer 130 may include a hard mask material having an etch selectivity relative to conformal layer 128 and non-conformal layer 126. Mask layer 130 may selectively expose conformal layer 128 and non-conformal layer 126 in second upper horizontal opening 124 and third upper horizontal opening 125, and cover conformal layer 128 and non-conformal layer 126 in first upper horizontal opening 123.

[0052] Reference Figure 12 The conformal layer 128 and the non-conformal layer 126 formed in the second upper horizontal opening 124 and the third upper horizontal opening 125 can be selectively etched using the mask layer 130. As a result, the second upper horizontal opening 124 and the third upper horizontal opening 125 can be partially exposed. In other words, the conformal liner 128L can remain in the second upper horizontal opening 124 and the third upper horizontal opening 125, and the void 129 can be exposed. The exposed void 129 can be referred to as an open void. The conformal liner 128L can be formed by etching the conformal layer 128 and can cover the sidewalls and bottom surface of the second upper horizontal opening 124 and the third upper horizontal opening 125. The first upper horizontal opening 123 can be filled with the conformal layer 128 and the void 129'. The void 129' in the first upper horizontal opening 123 can be referred to as a closed void or an embedded void. During the etching process using the mask layer 130, the uppermost dielectric layer 121 can be etched.

[0053] Reference Figure 13 After removing the mask layer 130 , the second upper horizontal opening 124 and the third upper horizontal opening 125 may be filled with linear supports 131 , which may then be planarized. The linear supports 131 may be planarized until the upper surface of the non-conformal layer 126 is exposed.

[0054] The linear support member 131 may fill the second upper horizontal opening 124 and the third upper horizontal opening 125 and may not fill the first upper horizontal opening 123. The first upper horizontal opening 123 may be filled with the conformal layer 128 and may include a closed gap 129'. The open gap 129 of the second upper horizontal opening 124 and the third upper horizontal opening 125 (see Figure 12 ) can be filled with linear supports 131.

[0055] The linear support member 131 may be a void-free linear support member and may be referred to as a silicon oxide support member. According to another embodiment, the linear support member 131 may include a material having an etching selectivity relative to the sacrificial layer 122'. The linear support member 131 may include SiO2, SiCO, SiCN, SiBN, or SiBCN. Since the linear support member 131 is void-free, structural stability may be improved. The linear support member 131 may have a T-shape.

[0056] Although not shown, the linear support member 131 may be formed at the same time as the linear support member 131 is formed. Figure 1 For example, Figures 7 to 13 As shown, the column type support member 131P may be formed by forming a hole type opening to be filled with the column type support member while forming the second upper horizontal opening 124 and the third upper horizontal opening 125 and then performing subsequent processes. The column type support member 131P may not have a void.

[0057] As described above, the voids 129 ′ formed by the non-conformal layer 126 ′ and the conformal layer 128 ′ may be replaced with void-free supports 131 .

[0058] The conformal layer 128 and the non-conformal layer 126 including the closed voids 129' retained in the first upper horizontal opening 123 may form a "void-embedded sacrificial plug". Hereinafter, they may be simply referred to as "void-embedded sacrificial plugs 126 / 128 / 129'", and the void-embedded sacrificial plugs 126 / 128 / 129' may contact the first contact plugs 114. The non-conformal layer 126 of the void-embedded sacrificial plugs 126 / 128 / 129' may contact the linear support members 131. The closed voids 129' of the void-embedded sacrificial plugs 126 / 128 / 129' may be embedded in the conformal layer 128 and may not contact the first contact plugs 114.

[0059] Reference Figure 14 , a vertical slit 140 may be formed. The vertical slit 140 may be formed to be spaced apart from the channel structure VC. The vertical slit 140 may be formed by etching the upper structure 120, and the vertical slit 140 may extend downward to a portion of the source structure 110. The bottom surface of the vertical slit 140 may penetrate the source conductive layer 113 and the liner layer 112C. The etching process for forming the vertical slit 140 may stop above the sacrificial source layer 112B. According to another embodiment, when forming the vertical slit 140, the upper surface of the sacrificial source layer 112B may be partially recessed. The vertical slit 140 may also be referred to as a slit or a trench. From a top view perspective, the vertical slit 140 may have a linear shape extending in one direction. The vertical slit 140 may have a high aspect ratio perpendicular to the surface of the lower structure 100L.

[0060] Reference Figure 15 , a source horizontal opening 112 ′ may be formed. The sacrificial source layer 112B may be selectively removed to form the source horizontal opening 112 ′.

[0061] The source horizontal opening 112' may partially expose the lower outer wall of the channel structure VC. The source horizontal opening 112' may be located between the source conductive layers 111 and 113. The source horizontal opening 112' may not expose the first contact plug 114. The first contact plug 114 may be protected from the source horizontal opening 112' by the spacer 115.

[0062] A portion of the source horizontal opening 112' may expose the lower outer wall of the channel structure VC. The source horizontal opening 112' may have a ring shape surrounding the lower outer wall of the channel structure VC. The source horizontal opening 112' may be referred to as a source horizontal air gap.

[0063] Subsequently, the liner layers 112A and 112C may be selectively removed. While removing the liner layers 112A and 112C, portions of the channel structure VC may be removed. For example, a portion of the memory layer V1 may be removed to expose a portion of the channel layer V2. The source horizontal opening 112' and the channel layer V2 may be in direct contact.

[0064] Reference Figure 16A source horizontal contact layer 112 may be formed to fill the source horizontal opening 112'. The source horizontal contact layer 112 may include a conductive material. The source horizontal contact layer 112 may include polycrystalline silicon. The source horizontal contact layer 112 may be doped with conductive impurities such as phosphorus, arsenic, boron, etc. For example, the source horizontal contact layer 112 may include phosphorus-doped polycrystalline silicon. According to another embodiment, the source horizontal contact layer 112 may be doped with non-conductive impurities or with both conductive and non-conductive impurities. For example, the source horizontal contact layer 112 may include carbon-doped polycrystalline silicon. According to another embodiment, the source horizontal contact layer 112 may include a double layer of phosphorus-doped polycrystalline silicon and carbon-doped polycrystalline silicon. The first contact plug 114 and the source horizontal contact layer 112 may be insulated by spacers 115. The source horizontal contact layer 112 and the source conductive layers 111 and 113 may be in contact with each other. The source horizontal contact layer 112 and the source conductive layers 111 and 113 may be referred to as a source horizontal layer.

[0065] Reference Figure 17 , the sacrificial layer 122' of the upper structure 120 may be selectively removed. Thus, a lateral recess 122" may be formed between the dielectric layers 121. The lateral recess 122" may be referred to as a lateral air gap. The lateral recess 122" and the dielectric layers 121 may be alternately stacked. When the sacrificial layer 122' includes silicon nitride, the sacrificial layer 122' may be removed by a chemical including phosphoric acid (H3PO4). The lateral recess 122" may be formed in the cell array region, and the first alternating stack ON may remain in the contact region. In the first alternating stack ON, the dielectric layers 121 and the sacrificial layers 122' may be alternately stacked. During the etching process for forming the lateral recess 122″, a portion of the sacrificial layer 122′ may not be removed due to the presence of the support member 131. The remaining portion of the sacrificial layer 122′ may be simply referred to as a gate-level dielectric layer 122R. The gate-level dielectric layer 122R may remain between the support members 131, and the gate-level dielectric layer 122R and the dielectric layer 121 may form a first alternating stack ON. When the gate-level dielectric layer 122R includes silicon nitride and the dielectric layer 121 includes silicon oxide, the first alternating stack ON may be an alternating stack in which silicon oxide and silicon nitride are alternately stacked, and the first alternating stack ON may be located between the linear supports 131.

[0066] Reference Figure 18 , gate electrodes 122 may be formed. The gate electrodes 122 may fill the lateral recesses 122 ″, respectively. The dielectric layers 121 and the gate electrodes 122 may form a second alternating stack OW. The second alternating stack OW may be stacked by alternating dielectric layers 121 and gate electrodes 122 . Portions of the second alternating stack OW adjacent to the first alternating stack ON may be supported by the support member 131 .

[0067] The gate electrode 122 may include a low-resistance material. The gate electrode 122 may be formed of a metal-based material. The gate electrode 122 may include a metal, a metal silicide, a metal nitride, or a combination thereof. For example, the metal may include nickel, cobalt, platinum, titanium, tantalum, or tungsten. The metal silicide may include nickel silicide, cobalt silicide, platinum silicide, titanium silicide, tantalum silicide, or tungsten silicide. The gate electrode 122 may include a stack of titanium nitride and tungsten.

[0068] Reference Figure 17 and Figure 18 , the sacrificial layer 122 ′ may be replaced with the gate electrode 122 .

[0069] Reference Figure 19 , the sidewalls of the vertical slits 140 may be sealed. The sidewalls of the vertical slits 140 may be sealed by a sealing layer 141. The sealing layer 141 may seal the end of the gate electrode 122. The sealing layer 141 may seal the side surface of the dielectric layer 121. The sealing layer 141 may seal the side surface of the source conductive layer 113. The sealing layer 141 may include a silicon oxide-based material. The sealing layer 141 may include a low-k constant material. According to another embodiment, the sealing layer 141 may include a material resistant to wet etching from subsequent processes. The sealing layer 141 may include SiCN, SiBCN, SiBN, or a combination thereof.

[0070] Subsequently, a source contact plug 142 may be formed in the vertical slit 140. The source contact plug 142 may fill the vertical slit 140. The source contact plug 142 may include a stack of a silicon-containing material and a metal-containing material, and may further include a barrier material between the silicon-containing material and the metal-containing material. The silicon-containing material may include polysilicon, and the metal-containing material may include tungsten. The barrier material may include titanium nitride. According to another embodiment, the source contact plug 142 may be formed solely of tungsten or solely of polysilicon.

[0071] Reference Figure 20 Interlayer dielectric layer 150 may be formed. Contact hole 151 may be formed by etching interlayer dielectric layer 150 to expose a portion of first upper horizontal opening 123 and continuing to etch a portion of sacrificial plugs 126 / 128 / 129' embedded with voids. By partially etching conformal layer 128, conformal sidewall liner 128S may remain on the sidewalls of contact hole 151, and closed void 129' may be removed. The upper end of conformal sidewall liner 128S may be covered by non-conformal layer 126.

[0072] The contact hole 151 may expose an upper surface of the first contact plug 114 .

[0073] When the contact hole 151 is formed, the pad contact hole 152 may be formed at the same time. The pad contact hole 152 may expose an edge portion of the gate electrode 122.

[0074] As described above, in this embodiment, a combined process can be used to simultaneously form contact hole 151 and pad contact hole 152. During the etching process for contact hole 151, closing gap 129' can be used to control the phenomenon of contact failure. In other words, closing gap 129' can prevent contact failure.

[0075] As a comparative example, the void-embedded sacrificial plugs 126 / 128 / 129′ may not include the voids 129′ and the non-conformal layer 126. In this case, the sacrificial plugs may be formed solely from the oxide conformal layer 128. Therefore, all of the conformal layer 128 may be etched during the etching process of the contact hole 151. However, in the comparative example, when etching the conformal layer 128, the etching process may be performed obliquely, and thus the contact hole 151 may not be opened due to the oblique etching, which is a phenomenon of contact non-opening.

[0076] Reference Figure 21 , a second contact plug 153 may be formed to fill the contact hole 151. The second contact plug 153 may include a metal-based material. The second contact plug 153 may include tungsten. For example, to form the second contact plug 153, a tungsten layer may be deposited to fill the contact hole 151, and then planarization such as chemical mechanical polishing (CMP) may be performed. When forming the second contact plug 153, a gate contact plug 154 may be formed simultaneously. The gate contact plug 154 may be coupled to the gate electrode 122.

[0077] As described above, the present embodiment may include: forming a void-embedded sacrificial plug 126 / 128 / 129′ over the first contact plug 114; forming a contact hole 151 to remove the void 129′ while etching a portion of the void-embedded sacrificial plug 126 / 128 / 129′; and forming a second contact plug 153 in the contact hole 151. The void 129′ of the void-embedded sacrificial plug 126 / 128 / 129′ may be replaced by the second contact plug 153.

[0078] According to an embodiment, since the contact hole and the pad contact hole are formed at the same time, the process can be simplified.

[0079] According to an embodiment, since a void is used in an etching process for forming a contact hole, it is possible to prevent a contact from not being opened.

[0080] According to an embodiment, structural stability may be improved by forming a support member without voids.

[0081] While the present teachings have been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications of these embodiments can be made without departing from the spirit and scope of the present teachings as defined in the appended claims.

[0082] CROSS-REFERENCE TO RELATED APPLICATIONS

[0083] This application claims priority to Korean Patent Application No. 10-2021-0013498, filed on January 29, 2021, which is hereby incorporated by reference in its entirety.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a substructure including interconnecting members; forming a first contact plug coupled to the interconnect; forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the lower structure; forming an opening penetrating the alternating stack and exposing the first contact plug; forming a sacrificial plug including a void in the opening; forming a contact hole exposing the first contact plug by etching a portion of the sacrificial plug; as well as forming a second contact plug in the contact hole, The step of forming the sacrificial plug including the gap in the opening comprises the following steps: forming a non-conformal layer covering top corners of the opening; and A conformal layer filling the opening is formed over the non-conformal layer, wherein the conformal layer is formed with a void located inside the opening.

2. The method according to claim 1, wherein The material forming the conformal layer has increased step coverage compared to the material forming the non-conformal layer.

3. The method according to claim 1, wherein The non-conformal layer includes a first oxide and the conformal layer includes a second oxide, wherein the second oxide has increased step coverage than the first oxide.

4. The method according to claim 1, wherein The non-conformal layer includes plasma enhanced tetraethyl orthosilicate (PETEOS).

5. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a source structure including a first contact plug over a lower structure including an interconnect, wherein the first contact plug is coupled to the interconnect; forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the source structure; forming a vertical channel structure through a portion of the alternating stack; forming a sacrificial plug embedded with a void spaced apart from the vertical channel structure, penetrating the alternating stack, and coupled to the first contact plug; replacing a portion of the sacrificial layer with a gate electrode to surround the vertical channel structure; forming a contact hole exposing the first contact plug by etching a portion of the sacrificial plug embedded with the void; forming a pad contact hole exposing an edge of the gate electrode; forming a contact plug in the contact hole; and forming a gate contact plug in the pad contact hole, The step of forming the sacrificial plug embedded with the gap comprises the following steps: forming an opening spaced apart from the vertical channel structure, penetrating the alternating stack and exposing the first contact plug; forming a non-conformal layer covering top corners of the opening; and A conformal layer filling the opening is formed over the non-conformal layer, wherein the conformal layer is formed with a void located inside the opening.

6. The method according to claim 5, wherein: The material forming the conformal layer has increased step coverage compared to the material forming the non-conformal layer.

7. The method according to claim 5, wherein: The non-conformal layer includes a first oxide and the conformal layer includes a second oxide, wherein the second oxide has increased step coverage than the first oxide.

8. The method according to claim 5, wherein The non-conformal layer includes plasma enhanced tetraethyl orthosilicate (PETEOS).

9. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a source structure including a first contact plug over a lower structure including an interconnect, wherein the first contact plug is coupled to the interconnect; forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the source structure; forming a vertical channel structure penetrating the alternating stack; forming a hole-shaped opening exposing the first contact plug and a line-shaped opening adjacent to the hole-shaped opening, wherein the hole-shaped opening and the line-shaped opening are spaced apart from the vertical channel structure and penetrate the alternating stack; forming a sacrificial plug with an embedded void in the hole-shaped opening; Filling the linear opening with a support member without gaps; replacing a portion of the sacrificial layer with a gate electrode to surround the vertical channel structure; forming a contact hole exposing the first contact plug by etching a portion of the sacrificial plug embedded with the void; forming a pad contact hole exposing an edge of the gate electrode; forming a contact plug in the contact hole; and forming a gate contact plug in the pad contact hole, The step of forming the sacrificial plug with the embedded gap in the hole-shaped opening includes the following steps: forming a non-conformal layer covering top corners of the hole-shaped opening; and A conformal layer is formed on the non-conformal layer to fill the hole-shaped opening, wherein the conformal layer is formed with a void located inside the hole-shaped opening.

10. The method according to claim 9, wherein: The material forming the conformal layer has increased step coverage compared to the material forming the non-conformal layer.

11. The method according to claim 9, wherein The non-conformal layer includes a first oxide and the conformal layer includes a second oxide, wherein the second oxide has increased step coverage than the first oxide.

12. The method according to claim 9, wherein The non-conformal layer includes plasma enhanced tetraethyl orthosilicate (PETEOS).

13. The method according to claim 9, wherein: The step of filling the linear opening with the void-free support member comprises the following steps: forming a non-conformal layer covering the top corners of the linear opening; forming a conformal layer on the non-conformal layer, filling the linear opening and including a void; removing the non-conformal layer and the conformal layer from top corners of the linear opening to expose a gap of the linear opening; and The exposed voids of the linear openings are filled with support material.

14. The method according to claim 13, wherein: Each of the non-conformal layer and the conformal layer comprises silicon oxide, The non-conformal layer comprises plasma enhanced tetraethyl orthosilicate (PETEOS), and The conformal layer includes silicon oxide formed by an atomic layer deposition (ALD) process.

15. The method according to claim 9, wherein An edge of the gate electrode is formed into a stepped structure.

16. The method according to claim 15, further comprising the steps of: A plurality of columnar support members are formed to penetrate the stepped structure.

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