Semiconductor structure and method of forming the same

Abstract

Semiconductor structures are provided. The semiconductor structure includes a substrate and a stack structure disposed above the substrate. The stack structure includes a plurality of alternating insulating layers and gate members. A core structure is disposed in the stack structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. Methods for fabricating semiconductor structures are also provided.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] Ferroelectric memories have attracted attention as non-volatile memories capable of high-speed operation. Ferroelectric memories utilize the polarization of ferroelectric materials to store data. A non-limiting example of such a ferroelectric material is hafnium silicate (HfSiO₂). x However, ferroelectric materials can be sensitive to etching processes and other semiconductor processes used to form ferroelectric memories. Therefore, improvements are needed in the manufacturing processes used to form ferroelectric memories. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate having a stacked structure disposed thereon, wherein the stacked structure includes a plurality of alternately stacked insulating layers and sacrificial layers; removing a portion of the stacked structure to form a plurality of first trenches to expose an insulating layer of the insulating layers adjacent to the substrate; conformally forming a pad layer within the first trench; conformally forming a memory layer over the pad layer; conformally forming a channel layer over the memory layer; conformally forming a capping layer over the channel layer; depositing a dielectric layer over the capping layer to fill the first trenches; removing the sacrificial layer to form a plurality of openings in the stacked structure; removing portions of the pad layer exposed by the openings; and depositing a first conductive material to fill the openings.

[0004] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a stacked structure on the substrate including an insulating layer and a sacrificial layer above the insulating layer; forming an isolation structure in the stacked structure; recessing a portion of the stacked structure adjacent to the isolation structure to form a trench; forming a pad layer in the trench; forming a memory layer above the pad layer; forming a channel layer above the memory layer; forming a capping layer above the channel layer; depositing a first dielectric layer above the capping layer; and replacing the sacrificial layer with a gate layer.

[0005] Some embodiments of this application provide a semiconductor structure including: a substrate; a stacked structure disposed on the substrate and including a plurality of alternately stacked insulating layers and gate members; a core structure disposed in the stacked structure, the core structure including: a memory layer; a channel member disposed on the memory layer; a contact member disposed on the channel member; and a pad member surrounding a portion of the core structure. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1A This is a schematic top view of a semiconductor structure according to some embodiments of the present invention.

[0008] Figure 1B It is along some embodiments of the present invention Figure 1A The diagram shows a schematic cross-sectional view of the semiconductor structure taken by line A-A'.

[0009] Figure 2 This is a flowchart illustrating a method for manufacturing the semiconductor structure shown in FIG1 according to some embodiments of the present invention.

[0010] Figure 3 and Figure 4 This illustrates some embodiments according to the present invention. Figure 2 A schematic 3D diagram illustrating the sequential operations of method 200.

[0011] Figure 5 According to some embodiments of the present invention Figure 4 A schematic cross-sectional view.

[0012] Figure 6 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0013] Figure 7A and Figure 7B According to some embodiments of the present invention, respectively along Figure 6 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0014] Figure 8 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0015] Figure 9A and Figure 9B According to some embodiments of the present invention, respectively along Figure 8 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0016] Figure 10 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0017] Figure 11A and Figure 11B According to some embodiments of the present invention, respectively along Figure 10 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0018] Figure 12 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0019] Figure 13A and Figure 13B According to some embodiments of the present invention, respectively along Figure 12 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0020] Figure 14 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0021] Figure 15A and Figure 15B According to some embodiments of the present invention, respectively along Figure 14 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0022] Figure 16 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0023] Figure 17A and Figure 17B According to some embodiments of the present invention, respectively along Figure 16 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0024] Figure 18 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0025] Figure 19A and Figure 19B According to some embodiments of the present invention, respectively along Figure 18 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0026] Figure 20A and Figure 20B This illustrates some embodiments according to the present invention. Figure 2 A schematic cross-sectional view of the sequential operation of method 200 in the diagram.

[0027] Figure 21This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0028] Figure 22A and Figure 22B According to some embodiments of the present invention, respectively along Figure 21 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0029] Figure 23 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0030] Figure 24A and Figure 24B According to some embodiments of the present invention, respectively along Figure 23 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0031] Figure 25 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0032] Figure 26A and Figure 26B According to some embodiments of the present invention, respectively along Figure 25 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0033] Figure 27 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0034] Figure 28A and Figure 28B According to some embodiments of the present invention, respectively along Figure 27 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0035] Figure 29A and Figure 29B This illustrates some embodiments according to the present invention. Figure 2 A schematic cross-sectional view of the sequential operation of method 200 in the diagram.

[0036] Figure 30 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0037] Figure 31A and Figure 31B According to some embodiments of the present invention, respectively along Figure 30 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0038] Figure 32 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0039] Figure 33A and Figure 33B According to some embodiments of the present invention, respectively along Figure 32 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0040] Figure 34 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0041] Figure 35A and Figure 35B According to some embodiments of the present invention, respectively along Figure 34 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0042] Figure 36 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0043] Figure 37A and Figure 37B According to some embodiments of the present invention, respectively along Figure 36 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0044] Figure 38 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view of the sequential operations of method 200.

[0045] Figure 39A and Figure 39B According to some embodiments of the present invention, respectively along Figure 38 The schematic cross-sectional views shown are taken from lines A-A' and B-B'.

[0046] Figure 40 This illustrates some embodiments according to the present invention. Figure 2 A schematic cross-sectional view of the sequential operation of method 200 in the diagram. Detailed Implementation

[0047] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0048] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0049] While the numerical ranges and parameters illustrating the broad scope of the invention are approximate, the values ​​described in specific examples are reported as precisely as possible. However, any numerical value inherently contains some error, which must be caused by the standard deviation found in the corresponding test measurement. Furthermore, as used herein, the terms “basically,” “about,” or “approximately” generally mean values ​​or ranges that would be expected by one of ordinary skill in the art. Optionally, the terms “basically,” “about,” or “approximately” mean within an acceptable standard error of the average as considered by one of ordinary skill in the art. One of ordinary skill in the art will understand that acceptable standard errors will vary depending on the technology. Except in operational / working examples, or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages, such as material quantities, time durations, temperatures, operating conditions, quantity ratios, and similar terms disclosed herein, should be understood to be modified in all cases by the terms “basically,” “about,” or “approximately.” Therefore, unless indicated to the contrary, the numerical parameters set forth in the invention and the appended claims are approximate values ​​that may vary as needed. At a minimum, each numerical parameter should be interpreted based on the number of significant figures reported and by applying ordinary rounding techniques. A range may be expressed in this document as a distance from one endpoint to another or between two endpoints. Unless otherwise stated, all ranges disclosed herein include endpoints.

[0050] The advantage of ferroelectric memory devices lies in the reduction of the voltage drop above the interface layer between the ferroelectric layer and the channel layer in the memory device through the use of ferroelectric materials. This improves the efficiency of voltage application. However, many semiconductor processes, especially etching processes, can damage the ferroelectric materials during the fabrication of ferroelectric memory devices. Therefore, there is a need to improve semiconductor processes using ferroelectric materials.

[0051] This invention provides a semiconductor structure and a method for manufacturing the semiconductor structure. Figure 1A This is a schematic top view of a semiconductor structure 10 according to some embodiments of the present invention. Figure 1B It is along some embodiments of the present invention Figure 1A The diagram shows a schematic cross-sectional view of the semiconductor structure 10 taken along line A-A'. For clarity, some components of the semiconductor structure 10 are not shown in each of the schematic top view and schematic cross-sectional views.

[0052] refer to Figure 1A The semiconductor structure 10 includes a plurality of memory cells 20. The memory cells 20 are separated from each other by insulating layers 112 and dielectric members 122 and 152 along a thickness direction D1. The memory cells 20 extend along a length direction D2 perpendicular to the thickness direction D1. Pad members 124 may surround at least a portion of the memory cells 20. The memory cells 20 include a plurality of core structures 160 and a plurality of layered structures 170. The core structure 160 includes a memory layer 130, a channel member 146 on the memory layer 130, and a contact member 150 on the channel member 146. The channel member 146 may be surrounded by the memory layer 130. The layered structure 170 includes the memory layer 130, the channel member 146 on the memory layer 130, and a cover member 144 on the channel member 146. The cover member 144 may be surrounded by the channel member 146. Dielectric members 142 and 162 are arranged alternately with each other and, in a top view, alternately with the contact members 150, respectively.

[0053] refer to Figure 1B The semiconductor structure 10 includes a substrate 100, a stacked structure 110 on the substrate 100, a core structure 160 in the stacked structure 110, a layered structure 170 in the stacked structure 110, and an interconnect structure 180 on the stacked structure 110. In some embodiments, the semiconductor structure 10 includes a ferroelectric memory device. The stacked structure 110 includes a plurality of alternately stacked insulating layers 112 and gate members 114. Each level of each insulating layer 112 and gate member 114.

[0054] For example, the core structure 160 may correspond to and partially define a vertical stack of individual memory cells 190. A plurality of memory cells 190 are disposed at the interface between the stack structure 110 and the core structure 160. Each of the memory cells 190 includes a gate member 114, a portion of a memory layer 130 facing the gate member 114, a portion of a channel member 146 corresponding to the portion of the memory layer 130, and a portion of a contact member 150 corresponding to the portion of the channel member 146. Referring again... Figure 1A Each memory cell 190 includes a pair of core structures 160, one of which serves as a source line (SL) and the other as a bit line (BL). Furthermore, in each memory cell 190, a channel member 146 extends between the pair of core structures 160.

[0055] A single memory cell 190 may be, for example, a ferroelectric memory cell or some other suitable type of memory cell. Contact members 150 may correspond, for example, to BL or SL, and / or gate members 114 may correspond, for example, to word lines (WL). In some embodiments, the memory cells 190 of the semiconductor structure 110 are electrically coupled to WL, SL, and BL having a NOR-type memory architecture. Furthermore, each memory cell 190 is connected in parallel to multiple contact members 150 (BL). In the NOR-type memory architecture, one end of each memory cell is connected to SL and the other end to BL, similar to a NOR gate. SL is used to connect to a power supply or ground to trigger charge flow. WL is used to control whether an electron channel exists under the gate of the memory cell 190. BL is used to detect whether the memory cell 190 is turned on by reading a data bit as 0 or 1.

[0056] Still referencing Figure 1B An interconnect structure 180 is disposed on a contact member 150 of the core structure 160. The interconnect structure 180 may include a vertical metal member and a horizontal metal member on the vertical metal member. The interconnect structure 180 is electrically coupled to the contact member 150.

[0057] Semiconductor structure 10 includes a plurality of pad members 124 disposed in a stacked structure 110. Pad members 124 are arranged alternately with gate members 114. Each of the pad members 124 surrounds a portion of a core structure 160 or a portion of a layered structure 170. Each of the pad members 124 also surrounds a portion of one of the insulating layers 112. Each of the pad members 124 is substantially located between the core structure 160 or the layered structure 170 and an insulating layer 112. Each of the pad members 124 may contact a memory layer 130. Each of the pad members has a thickness of approximately 1 nanometer (nm) and approximately 50 nm.

[0058] Figure 2This is a flowchart illustrating a method 200 for manufacturing the semiconductor structure 10 in FIG1 according to some embodiments of the present invention. Figures 3 to 40 This illustrates some embodiments according to the present invention. Figure 2 A schematic top view, cross-sectional view, or perspective view of the sequential operation of method 200.

[0059] In operation 201, a substrate 100 is provided, such as Figure 3 As shown. Substrate 100 has a top surface S1. In some embodiments, substrate 100 is a semiconductor substrate, such as a silicon, gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), indium phosphide (InP), germanium (Ge), or silicon germanium (SiGe) substrate. Optionally, substrate 100 may be a p-type semiconductor substrate or an n-type semiconductor substrate.

[0060] In operation 203, such as Figure 4 and Figure 5 As shown, a stacked structure 111 is formed on the substrate 100. Figure 4 This is a schematic perspective view showing the stacked structure 111 disposed on the substrate 100. Figure 5 yes Figure 4 A schematic cross-sectional view of the substrate 100. The stacked structure 111 has a top surface S2 and includes a plurality of insulating layers 112 stacked alternately with a plurality of sacrificial layers 113. In some embodiments, the insulating layer 112 is made of a dielectric material, such as silicon oxide (SiO2). The sacrificial layer 113 is made of a different material than the insulating layer 112. In some embodiments, the sacrificial layer 113 is made of silicon nitride (Si3N4). In such embodiments, the insulating layer 112 has an etch rate significantly different from that of the sacrificial layer 113. For example, the insulating layer 112 and the sacrificial layer 113 can be formed using a variety of deposition processes, such as atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). In some embodiments, the thickness direction D1 of the insulating layer 112 and the sacrificial layer 113 is substantially perpendicular to the top surface S1 of the substrate 100. It should be noted that Figure 4 The number of intermediate insulating layer 112 and sacrificial layer 113 is for reference only and is not limited to. Figure 4 The illustrated embodiment. The number of insulating layers 112 and sacrificial layers 113 in the stacked structure 111 depends on the desired design and density of the memory device. In some embodiments, the stacked structure 111 begins by depositing insulating layers 112 on the top surface S1, as shown. Figure 5 As shown. In other embodiments, the stacked structure 111 may begin by depositing a sacrificial layer 113 on the top surface S1.

[0061] In operation 205, a first etching process is performed on the stacked structure 111, such as... Figure 6As shown. In some embodiments, the first etching process is a dry etching process or a reactive ion etching (RIE) process. The first etching process can vertically remove portions of the insulating layer 112 and the sacrificial layer 113. After the first etching process, a plurality of holes H1 can be formed in the stacked structure 111. In some embodiments, the holes H1 are staggered with each other in the stacked structure 111.

[0062] Figure 7A and Figure 7B They are respectively along Figure 6 The schematic cross-sectional views shown are taken from lines A-A' and B-B'. Figure 7A The portion of the stacked structure 111 shown is protected by a first photoresist (not shown) and therefore not etched during the first etching process. Figure 7B Another portion of the stacked structure 111 is shown, in which an aperture H1 is formed. Aperture H1 penetrates the top surface S2 and exposes the inner sidewall W1 of the stacked structure 111. The inner sidewall W1 comprises sidewalls of alternately stacked insulating layers 112 and sacrificial layers 113. In some embodiments, the first etching process stops at the bottommost insulating layer 112 deposited on the top surface S1 of the substrate 100. The first etching process may partially remove the bottommost insulating layer 112. From a top view, the outline of aperture H1 may be square, rectangular, circular, or some other suitable shape. In some embodiments, aperture H1 exposes the bottommost insulating layer 112 close to the substrate 100.

[0063] In operation 207, such as Figure 8 As shown, a first dielectric material is deposited on the stacked structure 111. The first dielectric material can be formed using deposition processes such as PVD or CVD. In some embodiments, the first dielectric material comprises the same material as the insulating layer 112. In other embodiments, the first dielectric material includes phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, the first dielectric material fills vias H1 to form first dielectric members 122. A plurality of first dielectric members 122 may be formed and alternately arranged in the stacked structure 111. In some embodiments, the first dielectric members 122 are isolation structures in the stacked structure 111.

[0064] Figure 9A and Figure 9B They are respectively along Figure 8 The diagram shows schematic cross-sectional views taken by lines A-A' and B-B'. (Reference) Figure 7B and Figure 9B The first dielectric member 122 covers the inner sidewall W1 and the bottom insulating layer 112 above the substrate 100. After the via H1 is fully filled, a chemical mechanical planarization (CMP) process or an etch-back process can be performed to remove excess first dielectric material above the stacked structure 111.

[0065] In operation 209, a second etching process is performed on the stacked structure 111, such as... Figure 10 As shown. In some embodiments, the second etching process is a dry etching process or a RIE process. The second etching process can vertically remove portions of the insulating layer 112 and the sacrificial layer 113. After the second etching process, a plurality of interleaved trenches T1 can be formed in the stacked structure 111. The trenches T1 can be arranged alternately with the dielectric members 122. In some embodiments, the trenches T1 extend along a length direction D2 perpendicular to the thickness direction D1.

[0066] Figure 11A and Figure 11B They are respectively along Figure 10 The schematic cross-sectional views shown are taken from lines A-A' and B-B'. Figure 11A A cross-sectional view shows a portion of the formation of multiple trenches T1 in the stacked structure 111. The trenches T1 penetrate the top surface S2 and expose the inner sidewalls W2 of the stacked structure 111. In some embodiments, a second etching process stops at the bottommost insulating layer 112 deposited on the top surface S1 of the substrate 100. The second etching process may partially remove the bottommost insulating layer 112. From a top view, the outline of the trenches T1 may be square, rectangular, circular, or some other suitable shape. In some embodiments, the trenches T1 expose the bottommost insulating layer 112 close to the substrate 100. In some embodiments, the depth of the trenches T1 is substantially the same as the depth of the via H1. In some embodiments, the trenches T1 are substantially larger than the via H1. Figure 11B A portion of the dielectric component 122 and stacked structure 111 is shown, which are protected by a second photoresist (not shown) and therefore not etched during the second etching process.

[0067] In operation 211, such as Figure 12 As shown, a liner layer 120 is formed over the stacked structure 111. The liner layer 120 is conformally formed in the trench T1 using a deposition process such as ALD or CVD. In some embodiments, the liner layer is a single-layer structure. In other embodiments, the liner layer can be a multilayer structure formed by multiple deposition processes. In some embodiments, the material of the liner layer 120 includes undoped silicon, silicon carbide (SiC), silicon oxynitride (SiON), titanium oxide (TiO2), hafnium oxide (HfO2), zirconium oxide (ZrO2), or other suitable materials. In some embodiments, the etch rate of the liner layer 120 with respect to various etchants is substantially lower than the etch rate of the insulating layer 112 and the sacrificial layer 113. Based on this, the etchant can be more reactive with respect to the liner layer 120 and the insulating layer 112 or the sacrificial layer 113.

[0068] Figure 13A and Figure 13B They are respectively along Figure 12 The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. In some embodiments, the thickness of the padding layer 120 is between about 1 nm and 50 nm. The padding layer 120 may be formed above the inner sidewall W2 above the substrate 100 and the bottom insulating layer 112, as shown. Figure 13A or Figure 13B As shown. In some embodiments, the liner layer 120 is conformally formed in the trench T1 and completely covers the inner sidewall W2 and the bottom insulating layer 112. Figure 13B As shown, the padding layer 120 may be formed on the first dielectric member 122.

[0069] In operation 213, such as Figure 14 As shown, a memory layer 130 is formed above the stacked structure 111. The memory layer 130 is conformally formed in the trench T1 using a deposition process such as ALD or CVD. In some embodiments, the material of the memory layer 130 includes ferroelectric materials, such as hafnium oxide (HfO2) doped with aluminum (Al), lanthanum (La), silicon (Si), or zirconium (Zr), or indium oxide (IWO) doped with tungsten. In some embodiments, the memory layer 130 exhibits polarization-switching behavior when triggered by an external electric field.

[0070] Figure 15A and Figure 15B They are respectively along Figure 14 The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. In some embodiments, the memory layer 130 is conformally formed on the padding layer 120. In such embodiments, the padding layer 120 surrounds the memory layer 130. Therefore, the memory layer 130 does not directly contact the insulating layer 112 and the sacrificial layer 113.

[0071] In operation 215, a channel layer 140 is formed above the stacked structure 111, such as Figure 16 As shown. A deposition process such as ALD or CVD is used to conformally form a channel layer 140 in trench T1. In some embodiments, the material of the channel layer 140 includes silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon oxide (SiO2), III-V compound semiconductors, or two-dimensional materials such as hexagonal boron nitride (hBN), graphene, or other suitable materials.

[0072] Figure 17A and Figure 17B They are respectively along Figure 16 The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. In some embodiments, the channel layer 140 is conformally formed on the memory layer 130. In such embodiments, the memory layer 130 surrounds the channel layer 140.

[0073] In operation 217, a cover layer 141 is formed above the stacked structure 111, such as Figure 18 As shown. A deposition process such as ALD or CVD is used to conformally form a capping layer 141 in trench T1. In some embodiments, the material of the capping layer 141 includes alumina (Al2O3) or other suitable materials.

[0074] Figure 19A and Figure 19B They are respectively along Figure 18 The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. In some embodiments, the cover layer 141 is conformally formed on the channel layer 140. In such embodiments, the channel layer 140 surrounds the cover layer 141. In some embodiments, the memory layer 130, the channel layer 140, and the cover layer 141 form a layered structure 148 on the stacked structure 111.

[0075] In operation 219, such as Figure 20A and Figure 20B As shown, a second dielectric material is deposited on the stacked structure 111. A deposition process such as PVD or CVD can be used to form the second dielectric material. In some embodiments, the second dielectric material comprises the same material as the first dielectric material used to form the first dielectric member 122. In some embodiments, the second dielectric material completely covers the layered structure 148 and fills the remaining portion of the trench T1. The second dielectric material forms a second dielectric member 142 surrounded by a capping layer 141. In some embodiments, from a top view, a plurality of second dielectric members 142 are arranged alternately in the stacked structure 111.

[0076] In operation 221, a removal process is performed on the stacked structure 111, such as... Figure 21 As shown. In some embodiments, the removal process removes portions of the second dielectric member 142, cover layer 141, channel layer 140, memory layer 130, and pad layer 120 located above the stacked structure 111. The removal process can be performed, for example, by a CMP process, an etch-back process, or some other suitable removal process. An etch-back process can be performed, for example, by dry etching or some other suitable type of etching.

[0077] Figure 22A and Figure 22B They are respectively along Figure 21 The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. After the removal process, the top surface S2 of the stacked structure 111 is exposed.

[0078] In operation 223, a third etching process is performed on the stacked structure 111, such as... Figure 23As shown. In some embodiments, the third etching process is a dry etching process or a RIE process. The third etching process can vertically remove a portion of the first dielectric member 122. After the third etching process, a plurality of vias R1 can be formed in the stacked structure 111.

[0079] Figure 24A and Figure 24B They are respectively along Figure 23 The schematic cross-sectional views shown are taken from lines A-A' and B-B'. Figure 24A The portion of the stacked structure 111 shown is protected by a third photoresist (not shown) and therefore not etched during the third etching process. Figure 24B Another portion of the via R1 forming the stacked structure 111 is shown. The via R1 penetrates the top surface S2 and exposes the inner sidewall W3 of the stacked structure 111. From a top view, the outline of the via R1 can be square, rectangular, circular, or some other suitable shape. In some embodiments, the via R1 exposes the bottommost insulating layer 112 near the substrate 100.

[0080] In operation 225, the sacrificial layer 113 is removed, as follows: Figure 25 As shown. In some embodiments, the method for removing the sacrificial layer 113 includes performing a dry etching process or a wet etching process. The etchant used in a dry etching process can be, for example, nitrogen trifluoride (NF3), hydrogen (H2), oxygen (O2), helium (He), or a combination thereof. The etchant used in a wet etching process can be, for example, hydrobromic acid (HBr) or phosphoric acid (H3PO4). In some embodiments, the sacrificial layer 113 is removed by a reaction between the sacrificial layer 113 and hot phosphoric acid. Reference Figure 24B In some embodiments, hot phosphoric acid is injected into the stacked structure 111 through via R1. The sacrificial layer 113 exposed through via R1 can react laterally with the hot phosphoric acid and becomes easily removed.

[0081] Figure 26A and Figure 26B They are respectively along Figure 25The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. In some embodiments, a lateral opening O1 is formed after the sacrificial layer 113 is removed. The lateral opening O1 may communicate with a via R1 and expose portions of the insulating layer 112 and the pad layer 120. In some embodiments, the sacrificial layer 113 has sufficient etch selectivity over the pad layer 120 such that etching stops on the pad layer 120. The etch rate of the sacrificial layer 113 may be substantially greater than the etch rate of the pad layer 120 relative to hot phosphoric acid. In some embodiments, the pad layer 120, having a thickness of at least 1 nm, surrounds the memory layer 130, thus preventing a reaction between the hot phosphoric acid and the memory layer 130. The pad layer 120 may be an etch stop layer (ESL) that protects the memory layer 130 during the removal of the sacrificial layer 113. As a result, the memory layer 130 remains intact and undamaged when the sacrificial layer 113 is removed. When the thickness of the pad layer 120 is, for example, less than 1 nm, the pad layer 120 may not be able to resist the etchant used to remove the sacrificial layer 113. As a result, the etchant may penetrate the pad layer 120 and damage the memory layer 130.

[0082] In operation 227, a fourth etching process is performed on the stacked structure 111, such as... Figure 27 As shown. In some embodiments, the fourth etching process is a wet etching process or an atomic layer etching (ALE) process. The fourth etching process can laterally remove the portion of the pad layer 120 exposed by the lateral opening O1. After the fourth etching process, a portion of the memory layer 130 is exposed. In some embodiments, the etched pad layer 120 forms a plurality of pad members 124 spaced apart from each other.

[0083] Figure 28A and Figure 28B They are respectively along Figure 27 The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. In some embodiments, each of the padding members 124 is substantially located between the insulating layer 112 and the memory layer 130. Each of the padding members 124 may be a spacer surrounding a portion of the memory layer 130. After the padding layer 120 is partially removed, the lateral opening O1 occupies more space and is referred to as the lateral opening O2. The lateral opening O2 may expose a portion of each of the padding members 124.

[0084] In operation 229, a first conductive material is deposited, such as... Figure 29A and Figure 29BAs shown. A deposition process such as PVD or CVD can be used to form the first conductive material. In some embodiments, the first conductive material includes polysilicon, tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), nickel (Ni), tantalum (Ta), titanium (Ti), molybdenum (Mo), palladium (Pd), platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof. In some embodiments, the first conductive material is filled into the lateral opening O2 to form the gate member 114. After the lateral opening O2 is completely filled, excess first conductive material can be pulled back by a dry etching process or a wet etching process. For example, pullback can position the first conductive material to the lateral opening O2 and / or remove the first conductive material from the top of the stacked structure 110 and / or from the via R1.

[0085] In some embodiments, the sacrificial layer 113 in the stacked structure 111 is replaced with a gate member 114 to form the stacked structure 110; this may be referred to as a gate replacement process or a post-gate process. In some embodiments, a plurality of gate members 114 are alternately arranged in the stacked structure 110 with insulating layers 112 or pad members 124. In some embodiments, the gate member 114 contacts and is electrically coupled to the memory layer 130. In some embodiments, the gate member 114 serves as a word line (WL) in a memory device. In some embodiments, a via R1 exposes the inner sidewall W4 of the stacked structure 110. Figure 29B As shown, the inner sidewall W4 includes the sidewalls of alternating stacked insulating layers 112 and gate members 114.

[0086] In operation 231, a third dielectric material is deposited on the stacked structure 110, such as... Figure 30 As shown. A third dielectric material can be formed using deposition processes such as PVD or CVD. In some embodiments, the third dielectric material comprises the same material as the first dielectric material or the second dielectric material. In some embodiments, the third dielectric material fills the via R1 to form a third dielectric member 152. A plurality of third dielectric members 152 may be formed and arranged alternately in the stack structure 110. In some embodiments, from a top view, the third dielectric member 152 is adjacent to the first dielectric member 122.

[0087] Figure 31A and Figure 31B They are respectively along Figure 30 The schematic cross-sectional views taken along lines A-A' and B-B' are shown. The third dielectric member 152 may cover the inner sidewall W4 and the bottommost insulating layer 112 above the substrate 100. After the via R1 is fully filled, a CMP process or an etch-back process may be performed to remove excess third dielectric material above the stacked structure 110.

[0088] In operation 233, a fifth etching process is performed on the stacked structure 110, such as... Figure 32 As shown. In some embodiments, the fifth etching process is a dry etching process or a RIE process. The fifth etching process can vertically remove portions of the second dielectric member 142 and the cover layer 141. In some embodiments, a plurality of cover members 144 are formed after etching the cover layer 141. After the fifth etching process, a plurality of trenches T2 can be formed in the stack structure 110. In some embodiments, the trenches T2 are separated from each other by the second dielectric member 142 and the cover members 144.

[0089] Figure 33A and Figure 33B They are respectively along Figure 32 The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. In some embodiments, trench T2 exposes a portion of the channel layer 140. From a top view, the outline of trench T2 can be square, rectangular, circular, or some other suitable shape.

[0090] In operation 235, a second conductive material is deposited, such as... Figure 34 As shown. A deposition process such as PVD or CVD can be used to form the second conductive material. In some embodiments, the second conductive material comprises the same material as the first conductive material used to form the gate member 114. In some embodiments, the second conductive material is filled into the trench T2 to form the contact member 150. After the trench T2 is completely filled, excess second conductive material can be pulled back by a CMP process or an etch-back process. In some embodiments, a plurality of contact members 150 are formed in the channel layer 140. The contact members 150 may be arranged alternately with the second dielectric member 142.

[0091] Figure 35A and Figure 35B They are respectively along Figure 34 The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. In some embodiments, the contact member 150 is surrounded by a channel layer 140 and a memory layer 130. The contact member 150 may have, for example, a columnar profile. In some embodiments, the contact member 150 serves as a bit line (BL) or signal line (SL) in a memory device.

[0092] In operation 237, a sixth etching process is performed on the stacked structure 110, such as... Figure 36As shown. In some embodiments, the sixth etching process is a dry etching process or a RIE process. The sixth etching process can vertically remove portions of the second dielectric member 142, the cover member 144, and the channel layer 140. In some embodiments, a plurality of channel members 146 are formed after etching the channel layer 140. After the sixth etching process, a plurality of trenches T3 can be formed in the stack structure 110. In some embodiments, the trenches T3 are separated from the channel members 146 by contact members 150.

[0093] Figure 37A and Figure 37B They are respectively along Figure 36 The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. In some embodiments, trench T3 exposes a portion of memory layer 130. From a top view, the outline of trench T3 can be square, rectangular, circular, or some other suitable shape. In some embodiments, memory layer 130, channel member 146, and cover member 144 form a layered structure 170 within stacked structure 110.

[0094] In operation 239, a fourth dielectric material is deposited on the stacked structure 110, such as... Figure 38 As shown. A fourth dielectric material can be formed using deposition processes such as PVD or CVD. In some embodiments, the fourth dielectric material comprises the same material as the first, second, or third dielectric material. In some embodiments, the fourth dielectric material fills trench T3 to form a fourth dielectric member 162. A plurality of fourth dielectric members 162 may be formed in a stacked structure 110. In some embodiments, the fourth dielectric members 162 are alternately arranged with channel members 146 in the memory layer 130. Each of the channel members 146 may form a cell isolated by the fourth dielectric member 162.

[0095] Figure 39A and Figure 39B They are respectively along Figure 38 The diagram shows schematic cross-sectional views taken along lines A-A' and B-B'. In some embodiments, the fourth dielectric member 162 is surrounded by the memory layer 130. After the trench T3 is fully filled, a CMP process or an etch-back process may be performed to remove excess fourth dielectric material over the stacked structure 110.

[0096] In operation 241, a wiring process is performed on the stacked structure 110, such as... Figure 40As shown. In some embodiments, a wiring process is used to form an interconnect structure 180 on the stacked structure 110. The interconnect structure 180 may include vertical metal members and horizontal metal members on the vertical metal members. In some embodiments, the vertical metal members are formed on and electrically coupled to the contact members 150. PVD or electroplating processes can be used to form the vertical and horizontal metal members. In some embodiments, the vertical and horizontal metal members are made of copper (Cu), tungsten (W), aluminum (Al), or other suitable materials. As a result, a semiconductor structure 10 is formed.

[0097] In some embodiments, the semiconductor structure 10 is a ferroelectric memory device. The ferroelectric memory device may include a core structure 160 and a layered structure 170. In some embodiments, the core structure 160 comprises a memory layer 130, a channel member 146, and a contact member 150. The core structure 160 may have, for example, a columnar profile. In some embodiments, a plurality of core structures 160 are arranged in a stacked structure 110. Each of the padding members 124 at the core structure 160 may surround a portion of the core structure 160 and protect the memory layer 130 within the core structure 160. In some embodiments, a plurality of layered structures 170 are arranged in the stacked structure 110. Each of the padding members 124 at the layered structure 170 may surround a portion of the layered structure 170 and protect the memory layer 130 within the layered structure 170.

[0098] In some embodiments, a plurality of memory cells 190 are disposed at the interface between the stacked structure 110 and the core structure 160. Each of the memory cells 190 includes a gate member 114, a portion of the memory layer 130 facing the gate member 114, a portion of the channel member 146 corresponding to the portion of the memory layer 130, and a portion of the contact member 150 corresponding to the portion of the channel member 146. In some embodiments, the core structure serves as a source line (SL) or a bit line (BL).

[0099] This invention relates to a semiconductor structure used in ferroelectric memory devices and a method for manufacturing the semiconductor structure. Ferroelectric materials are sensitive to certain chemicals and may be damaged during the production of ferroelectric memory devices. In this invention, a gate replacement process is used. During the gate replacement process, a sacrificial layer of the stacked structure is removed and subsequently replaced by the gate layer. However, the etchant used to remove the sacrificial layer may consume the ferroelectric material of the memory layer in the stacked structure. Therefore, a pad layer is formed on the memory layer to prevent the loss of ferroelectric material during the gate replacement process. The pad layer acts as an etch stop layer that completely isolates the memory layer from the etchant. As a result, the ferroelectric material of the memory layer remains intact, and a higher yield of ferroelectric memory devices can be obtained.

[0100] One aspect of the present invention provides a method for forming a semiconductor structure. The method includes: providing a substrate having a stacked structure disposed thereon, wherein the stacked structure includes a plurality of alternately stacked insulating layers and sacrificial layers; removing a portion of the stacked structure to form a plurality of first trenches to expose an insulating layer of the insulating layers adjacent to the substrate; conformally forming a pad layer within the first trenches; conformally forming a memory layer over the pad layer; conformally forming a channel layer over the memory layer; conformally forming a capping layer over the channel layer; depositing a dielectric layer over the capping layer to fill the first trenches; removing the sacrificial layers to form a plurality of openings in the stacked structure; removing portions of the pad layer exposed by the openings; and depositing a first conductive material to fill the openings.

[0101] In some embodiments, the etch rate of the insulating layer is substantially different from the etch rate of the sacrificial layer.

[0102] In some embodiments, the method further includes forming a through-hole between two of the first trenches before removing the adjacent sacrificial layers.

[0103] In some embodiments, the via exposes the sidewalls of the alternating stacked insulating and sacrificial layers.

[0104] In some embodiments, removing the sacrificial layer includes reacting the sacrificial layer with an etchant injected from the via.

[0105] In some embodiments, after the sacrificial layer is removed, the via communicates with the opening.

[0106] In some embodiments, during the removal of the sacrificial layer, the pad layer separates the etchant from the memory layer.

[0107] In some embodiments, the etch rate of the sacrificial layer is substantially greater than the etch rate of the pad layer relative to the etchant.

[0108] In some embodiments, the method further includes: removing the dielectric layer and the capping layer to form a second trench; depositing a second conductive material into the second trench to form a bit line or source line; and forming an interconnect structure on the second conductive material.

[0109] One aspect of the present invention provides another method for forming a semiconductor structure. The method includes: providing a substrate; forming a stacked structure on the substrate including an insulating layer and a sacrificial layer above the insulating layer; forming an isolation structure in the stacked structure; recessing a portion of the stacked structure adjacent to the isolation structure to form a trench; forming a pad layer in the trench; forming a memory layer above the pad layer; forming a channel layer above the memory layer; forming a capping layer above the channel layer; depositing a first dielectric layer above the capping layer; and replacing the sacrificial layer with a gate layer.

[0110] In some embodiments, replacing the sacrificial layer with the gate layer includes: etching the isolation structure to form a via that exposes the sidewalls of the insulating layer and the sacrificial layer; reacting the sacrificial layer with an etchant; removing the sacrificial layer to form an opening in the stacked structure; removing a portion of the pad layer exposed by the opening; filling the opening with the gate layer; and filling the via with a second dielectric layer.

[0111] In some embodiments, during the replacement of the sacrificial layer with the gate layer, the pad layer isolates the memory layer from the etchant.

[0112] Another aspect of the present invention provides a semiconductor structure. The semiconductor structure includes: a substrate, a stacked structure, a core structure, and a padding member. The stacked structure is disposed on the substrate and includes a plurality of alternately stacked insulating layers and gate members. The core structure is disposed in the stacked structure and includes: a memory layer; a channel member disposed on the memory layer; and a contact member disposed on the channel member. The padding member surrounds a portion of the core structure.

[0113] In some embodiments, the semiconductor structure further includes an interconnect structure disposed on the contact member.

[0114] In some embodiments, the padding member includes undoped silicon, silicon carbide (SiC), silicon oxynitride (SiON), titanium oxide (TiO2), hafnium oxide (HfO2), or zirconium oxide (ZrO2).

[0115] In some embodiments, the thickness of the padding member is substantially less than 50 nanometers (nm).

[0116] In some embodiments, the channel member is surrounded by the memory layer, and the contact member is surrounded by the channel member.

[0117] In some embodiments, a portion of the insulating layer is surrounded by the padding member.

[0118] In some embodiments, the pad member is inserted between the gate members.

[0119] In some embodiments, the padding member contacts the memory layer.

[0120] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor structure, comprising: A substrate is provided with a stacked structure, wherein the stacked structure includes a plurality of alternately stacked insulating layers and sacrificial layers; A portion of the stacked structure is removed to form a plurality of first trenches to expose one insulating layer in the insulating layer that is close to the substrate; A liner layer is conformally formed within the first trench; A memory layer is conformally formed above the padding layer; A channel layer is conformally formed above the memory layer; A cover layer is conformally formed above the channel layer; A dielectric layer is deposited over the capping layer to fill the first trench; Remove the sacrificial layer to form multiple openings in the stacked structure; Remove the portion of the liner layer exposed by the opening; and Deposit a first conductive material to fill the opening; Remove the dielectric layer and the capping layer to form a second trench; Depositing a second conductive material into the second trench to form a bit line or source line; and An interconnect structure is formed on the second conductive material.

2. The method according to claim 1, wherein, The etching rate of the insulating layer is fundamentally different from that of the sacrificial layer.

3. The method of claim 1, further comprising forming a through-hole between the two first trenches in the first trench before removing the sacrificial layer, wherein, The two first trenches in the first trench are adjacent to each other.

4. The method according to claim 3, wherein, The via exposes the sidewalls of the alternating stacked insulating and sacrificial layers.

5. The method according to claim 3, wherein, Removing the sacrificial layer involves reacting it with an etchant injected from the via.

6. The method according to claim 3, wherein, After the sacrificial layer is removed, the via is connected to the opening.

7. The method according to claim 5, wherein, During the removal of the sacrificial layer, the pad layer separates the etchant from the memory layer.

8. The method according to claim 5, wherein, The etch rate of the sacrificial layer is substantially greater than that of the pad layer relative to the etchant.

9. The method according to claim 1, wherein, The material of the memory layer includes hafnium oxide doped with aluminum, lanthanum, silicon, zirconium, or indium oxide doped with tungsten.

10. A method for forming a semiconductor structure, comprising: Provide substrate; A stacked structure comprising an insulating layer and a sacrificial layer above the insulating layer is formed on the substrate; An isolation structure is formed in the stacked structure, the isolation structure extending from the top surface of the stacked structure to the bottom surface of the stacked structure; A portion of the stacked structure adjacent to the isolation structure is recessed to form a trench, the trench exposing the sidewall of the isolation structure; A liner layer is formed in the trench, the liner layer being located on the sidewall of the isolation structure; A memory layer is formed above the padding layer; A channel layer is formed above the memory layer; A covering layer is formed above the channel layer; A first dielectric layer is deposited over the capping layer; as well as The sacrificial layer is replaced with a gate layer.

11. The method according to claim 10, wherein, The step of replacing the sacrificial layer with the gate layer includes: The isolation structure is etched to form a via, the via exposing the sidewalls of the insulating layer and the sacrificial layer; The sacrificial layer is reacted with an etchant. Remove the sacrificial layer to form an opening in the stacked structure; Remove a portion of the liner layer exposed by the opening; The opening is filled with the gate layer; and The via is filled with a second dielectric layer.

12. The method according to claim 11, wherein, During the replacement of the sacrificial layer with the gate layer, the pad layer isolates the memory layer from the etchant.

13. A semiconductor structure comprising: Substrate; A stacked structure is disposed on the substrate and includes multiple alternately stacked insulating layers and gate components; A core structure is disposed in the stacked structure, the core structure comprising: Memory layer; Channel components are disposed on the memory layer; and Contact member, disposed on the channel member; and A liner member that surrounds a portion of the core structure.

14. The semiconductor structure according to claim 13 further includes an interconnect structure disposed on the contact member.

15. The semiconductor structure according to claim 13, wherein, The padding components include undoped silicon, silicon carbide (SiC), silicon oxynitride (SiON), titanium oxide (TiO2), hafnium oxide (HfO2), or zirconium oxide (ZrO2).

16. The semiconductor structure according to claim 13, wherein, The thickness of the liner component is generally less than 50 nanometers (nm).

17. The semiconductor structure according to claim 13, wherein, The channel member is surrounded by the memory layer, and the contact member is surrounded by the channel member.

18. The semiconductor structure according to claim 13, wherein, A portion of the insulating layer is surrounded by the padding member.

19. The semiconductor structure according to claim 13, wherein, The pad member is inserted between the gate members.

20. The semiconductor structure according to claim 13, wherein, The padding member is in contact with the memory layer.

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