Method of manufacturing a semiconductor structure and semiconductor structure

Abstract

Embodiments of the present application provide a semiconductor structure manufacturing method and a semiconductor structure. The manufacturing method comprises: providing a substrate; the substrate comprises a substrate, a dielectric structure on the substrate, and a blocking material layer on the dielectric structure; the dielectric structure comprises at least one dielectric layer; forming a first mask layer on the blocking material layer; the first mask layer comprises a first opening exposing a top surface of the blocking material layer; forming a second mask layer in the first opening, and removing the first mask layer; the second mask layer comprises a second opening exposing a top surface of the blocking material layer; using the second mask layer as a mask to pattern the blocking material layer, to form a blocking layer for patterning the dielectric structure; the blocking layer comprises a third opening exposing a top surface of the dielectric structure; the third opening has a size greater than that of the second opening.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for manufacturing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] As semiconductor process dimensions shrink, the precision requirements for the process become increasingly stringent. The wiring layouts become more complex, leading to increasingly complex patterns in the blocking layers used to cut the wires. The blocking layers used to form interconnect layers become particularly important, and the required linewidths for interconnect layers are becoming more stringent, placing ever higher demands on the process technology of the blocking layers. Summary of the Invention

[0003] In view of this, embodiments of this application provide a method for manufacturing a semiconductor structure and a semiconductor structure.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; the substrate comprising a substrate, a dielectric structure located on the substrate, and a blocking material layer located on the dielectric structure; the dielectric structure comprising at least one dielectric layer; forming a first mask layer on the blocking material layer; the first mask layer comprising a first opening exposing a portion of the top surface of the blocking material layer; forming a second mask layer in the first opening; and removing the first mask layer; the second mask layer comprising a second opening exposing a portion of the top surface of the blocking material layer; patterning the blocking material layer using the second mask layer as a mask to form a blocking layer for patterning the dielectric structure; the blocking layer comprising a third opening exposing a portion of the top surface of the dielectric structure; the size of the third opening being larger than the size of the second opening.

[0005] In some embodiments, forming a first mask layer on a blocking material layer includes: forming a first mask material layer on the blocking material layer; performing multiple photolithography etching processes on the first mask material layer to form a first opening including multiple sets of initial openings; wherein each photolithography etching process forms a set of initial openings in the first mask material layer.

[0006] In some embodiments, performing multiple photolithographic etching processes on the first mask material layer to form a first opening including multiple sets of initial openings includes: performing three photolithographic etching processes on the first mask material layer to form a first opening including three sets of initial openings spaced apart from each other.

[0007] In some embodiments, forming a second mask layer in the first opening includes: forming a second mask material layer that fills the first opening and covers the top surface of the first mask layer; and removing the second mask material layer covering the top surface of the first mask layer using a planarization process to obtain a second mask layer that fills the first opening.

[0008] In some embodiments, removing the first mask layer includes: using the second mask layer as a mask, removing the first mask layer with a first etchant to obtain the second mask layer; wherein the etch selectivity ratio of the first etchant to the second mask layer and the first mask layer is greater than or equal to 40.

[0009] In some embodiments, forming a blocking layer for a patterned medium structure includes: using a second mask layer as a mask, removing a portion of the blocking material layer with a second etchant to obtain the blocking layer; wherein the etching selectivity ratio of the second etchant to the second mask layer and the blocking material layer is greater than or equal to 40.

[0010] In some embodiments, removing a portion of the blocking material layer with a second etchant to obtain a blocking layer includes: removing a portion of the blocking material layer with the second etchant for a first duration to obtain a blocking layer with a third opening; wherein the first duration is positively correlated with the size of the third opening.

[0011] In some embodiments, providing a substrate includes: providing a substrate; sequentially forming a dielectric structure and a blocking material layer on the substrate, wherein the dielectric structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked sequentially; the blocking material layer includes silicon, the first dielectric layer and the third dielectric layer are made of silicon oxide or silicon nitride, and the second dielectric layer is made of titanium nitride.

[0012] In some embodiments, the manufacturing method further includes: removing the second mask layer; patterning the dielectric structure using the blocking layer as a mask to form a plurality of trenches located in the dielectric structure; and filling the trenches with conductive material to form an interconnect layer.

[0013] Secondly, embodiments of this application provide a semiconductor structure, the semiconductor structure comprising: a substrate including a transistor; a source-drain contact connected to the source or drain of the transistor; and an interconnect layer obtained according to the manufacturing method of the first aspect, located on the source-drain contact and connected to the source-drain contact.

[0014] In various embodiments of this application, a blocking layer is formed by patterning a blocking material layer using a second mask layer. This effectively utilizes the undercut process characteristics, making the opening size of the blocking layer larger than the opening size of the second mask layer (i.e., the size of the third opening is larger than the size of the second opening). This reduces the exposure limit requirements of photolithography on the feature size of the final formed blocking layer pattern. During the process of forming the blocking layer using the second mask layer as a patterning blocking material layer, the feature size of the final formed blocking layer pattern can also be controlled in a controllable manner (e.g., stepwise in-line detection). This greatly increases the exposure process window of the photolithography process (e.g., the exposure process window for transferring the pattern from the photoresist layer to the first mask material layer), reduces process difficulties, and allows for timely analysis of key parameters of each process step before the final formation of the blocking layer pattern. Adjustability and the timeliness of detection yield are both improved. Attached Figure Description

[0015] Figure 1A , Figure 1B and Figure 1C A cross-sectional schematic diagram of the manufacturing process of the first semiconductor structure provided in the embodiments of this application;

[0016] Figure 2 A schematic flowchart illustrating a method for manufacturing a second semiconductor structure provided in an embodiment of this application;

[0017] Figures 3A to 3J A cross-sectional schematic diagram of the manufacturing process of the second semiconductor structure provided in the embodiments of this application;

[0018] Figure 4 A cross-sectional schematic diagram of the manufacturing process of the third semiconductor structure provided in the embodiments of this application;

[0019] Figure 5 A schematic flowchart illustrating a method for manufacturing a third semiconductor structure provided in an embodiment of this application;

[0020] Figure 6A , Figure 6B and Figure 6C This is a cross-sectional schematic diagram of the manufacturing process of the third semiconductor structure provided in the embodiments of this application. Detailed Implementation

[0021] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0024] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0025] It should be noted that, unless otherwise stated, components / layers / materials / structures identified by the same reference numerals in the following figures shall be understood as the same or similar components / layers / materials / structures.

[0026] In semiconductor fabrication processes, such as in contact (CT) fabrication processes, as the wiring of the layout becomes increasingly complex, the patterns of the blocking layers used to form interconnect layers (such as the zeroth metal interconnect layer (M0)) also become increasingly complex, the linewidth requirements for interconnect layers become more stringent, and the requirements for the blocking layer fabrication processes (such as lithography) become increasingly demanding.

[0027] Figure 1A , Figure 1B and Figure 1C This is a cross-sectional schematic diagram illustrating the manufacturing process of the first semiconductor structure provided in this application embodiment. Figure 1A (b) Figure 1B (b) Figure 1C (b) respectively Figure 1A (a) Figure 1B (a) Figure 1C (a) Enlarged schematic diagram of region PZ.

[0028] refer to Figure 1A and Figure 1B Due to the complexity of the pattern layout in the blocking layer, some implementations employ a pattern formation method that avoids extreme exposure processes through gridding management, uses multiple photolithography processes to obtain multiple masks to form the aperture regions, and then performs ion implantation on the aperture regions. It should be noted that... Figure 1A and Figure 1B The diagram illustrates a process involving three photolithography and ion implantation steps, but in reality, each photolithography and ion implantation step is performed separately. For example, firstly, a first photolithography process is used to form the first aperture region, followed by a first ion implantation process (IMP1) on the first aperture region; then, a second photolithography process is used to form the second aperture region, followed by a second ion implantation process (IMP2) on the second aperture region; finally, a third photolithography process is used to form the third aperture region, followed by a third ion implantation process (IMP3) on the third aperture region. Figure 1A and Figure 1B The diagram illustrates a three-stage lithography process, with each lithography process followed by a corresponding ion implantation process. In optional embodiments, the lithography process may involve fewer than three (e.g., two) or more than three (e.g., four) lithography processes.

[0029] refer to Figure 1B The aperture region is formed by three photolithography processes, and then the aperture region is subjected to an ion implantation process, so that ions, such as boron (B) ions, are implanted into the barrier material layer (e.g., amorphous silicon (α-Si) layer) 106 that is opened by the mask, resulting in a barrier material layer 106 with doped / undoped (e.g., B-doped / undoped) regions 106b / 106a.

[0030] refer to Figure 1CThe wet etching solution (e.g., ADM solution) has a high selectivity for etching between doped / undoped (e.g., B-doped / undoped) regions of the blocking material layer. The undoped region 106a, which has not undergone ion implantation, is wet etched, and the doped region 106b, which is retained after etching, finally yields the desired blocking layer 106p.

[0031] The photolithography and ion implantation processes form the pattern of the barrier layer 106p. However, there are inherent instabilities in the process, including but not limited to the following examples: 1. Ion implantation is used to implant ions into the opening regions. Variations in the ion implantation angle and dosage can cause changes in the critical dimensions of the final interconnect layer. 2. Ion implantation is performed on the barrier material layer 106. Lateral diffusion of implanted ions, such as boron (indicated by arrow F1), is unavoidable during the process, resulting in a final barrier layer 106 morphology exhibiting a "wide center, narrow top and bottom" or "trapezoidal" shape with non-right-angled sidewalls (DEF). Figure 1C (b) shows that the non-right-angled topography DEF is a relatively uncontrollable factor. This uncontrollable factor is detrimental to the final interconnect layer fabrication process.

[0032] It should be noted that, in cases such as Figure 1A , Figure 1B and Figure 1C For details regarding the manufacturing process, the structures, components, or layers shown in the cross-sectional diagrams, and the processes used to realize the semiconductor structure, please refer to the following: Figures 3A to 3J The manufacturing process of the semiconductor structure shown is explained, along with the corresponding structures, components, or layers.

[0033] In view of this, embodiments of this application provide a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method provided by embodiments of this application obtains a blocking layer, and the final pattern of the blocking layer can avoid the ion implantation process in the photolithography and ion implantation processes, thus solving the problems mentioned above. Compared to the patterning methods of photolithography and ion implantation, the manufacturing method provided in this application also has the following features, including but not limited to: 1. Using a second mask layer as a mask to pattern the blocking material layer to form a blocking layer, effectively utilizing the process characteristics of undercutting, the opening size of the blocking layer is larger than the opening size of the second mask layer (i.e., the size of the third opening is larger than the size of the second opening), which can reduce the exposure limit requirements of photolithography on the feature size of the final formed blocking layer pattern; 2. The feature size of the final formed blocking layer pattern can be controlled in a controllable manner, greatly increasing the exposure process window of the photolithography process (e.g., the exposure process window for the photoresist layer to transfer the pattern to the first mask material layer), reducing process difficulties; 3. It is no longer necessary to wait until the blocking layer pattern is finally formed before the feature size of the blocking layer pattern can be seen. Before the blocking layer pattern is finally formed, online detection can be performed step by step during the process of forming the blocking layer using the second mask layer as a mask, and the key parameters of each process step can be analyzed in a timely manner, improving adjustability and the timeliness of detection yield.

[0034] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a second semiconductor structure according to an embodiment of this application.

[0035] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor structure, referring to... Figure 2 The manufacturing method includes the following steps:

[0036] Step S201: Provide a substrate; the substrate includes a substrate, a dielectric structure on the substrate, and a blocking material layer on the dielectric structure; the dielectric structure includes at least one dielectric layer;

[0037] Step S202: Form a first mask layer on the blocking material layer; the first mask layer includes a first opening that exposes a portion of the top surface of the blocking material layer;

[0038] Step S203: Forming a second mask layer in the first opening, and removing the first mask layer; the second mask layer includes a second opening that exposes a portion of the top surface of the blocking material layer;

[0039] Step S204: Using the second mask layer as a mask, pattern the blocking material layer to form a blocking layer for patterning the dielectric structure; the blocking layer includes a third opening that exposes a portion of the top surface of the dielectric structure; the size of the third opening is larger than the size of the second opening.

[0040] For ease of description of the embodiments of this application, the terms first direction and second direction refer to two intersecting directions (e.g., orthogonal directions) parallel to the plane of the substrate (or base); third direction refers to a direction perpendicular to the plane of the substrate (or base), and can also be understood as the stacking direction of elements, components, regions, layers, or portions. The first direction can be represented as the X direction in the figures; the second direction can be represented as the Y direction in the figures; and the third direction can be represented as the Z direction in the figures.

[0041] It should be understood that Figure 2 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 2 The steps shown can be adjusted in order according to actual needs.

[0042] Figures 3A to 3J This is a cross-sectional schematic diagram illustrating the manufacturing process of the second semiconductor structure provided in this application embodiment. The following is in conjunction with... Figure 2 , Figures 3A to 3J The manufacturing method of the semiconductor structure provided in the embodiments of this application will be described in detail.

[0043] Perform step S201 to provide the substrate.

[0044] refer to Figure 3A The substrate includes a substrate 102, which may be made of silicon (Si), germanium (Ge), silicon germanide (SiGe), etc. The substrate 102 may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI). Ion implantation and shallow trench isolation (STI) processes can be used to form well regions in the substrate 102. Figure 3A (not shown) and the well isolation structure of the spaced well region ( Figure 3A (Not shown).

[0045] Shallow trench isolation technology is used to form an active region in the trap region. Figure 3A (not shown) and active region isolation structure with spaced active regions ( Figure 3A (Not shown). The active region protrudes from the substrate along the stacking direction (or a third direction). The active region isolation structure covers the surface of the substrate and part of the sidewalls of the active region. The active region isolation structure can be used for isolation between the substrate and the gate structure. The constituent materials of the well region isolation structure or the active region isolation structure include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride.

[0046] For example, active regions can be formed using one or more patterning processes. These patterning processes include, but are not limited to, double-patterning technology (DPT), quadruple-patterning technology (QPT), or any combination thereof.

[0047] For example, the active region has a protruding portion that protrudes along the stacking direction (or a third direction) and extends along a first direction. An active region isolation structure covers the surface of the substrate and a portion of the sidewalls of the protruding portion, and a gate structure (a first gate structure or a metal gate) extends along a second direction and covers another portion of the sidewalls of the protruding portion and the top surface of the protruding portion. The active region isolation structure can be used for isolation between the substrate and the gate structure.

[0048] For example, by using ion implantation to dope a substrate with a certain amount of P-type impurity ions, a P-type well region can be formed; by using ion implantation to dope a P-type well region with a certain amount of N-type impurity ions, an N-channel metal-oxide-semiconductor (NMOS) transistor can be formed. Alternatively, by doping a substrate with a certain amount of N-type impurity ions, an N-type well region can be formed; by using ion implantation to dope a P-type well region with a certain amount of P-type impurity ions, a P-channel metal-oxide-semiconductor (PMOS) transistor can be formed.

[0049] In some embodiments, a deposition process is used to deposit a dielectric structure 104 and a barrier material layer 106 on a substrate 102. Herein and below, the deposition process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.

[0050] refer to Figure 3A In some embodiments, providing a substrate includes: providing a substrate; and sequentially forming a dielectric structure and a blocking material layer on the substrate 102. The dielectric structure includes a first dielectric layer 1041, a second dielectric layer 1042, and a third dielectric layer 1043 stacked sequentially. The blocking material layer 106 includes silicon, the first dielectric layer 1041 and the third dielectric layer 1043 are made of silicon oxide or silicon nitride, and the second dielectric layer 1042 is made of titanium nitride.

[0051] Exemplarily, silicon nitride material can be deposited using plasma-enhanced chemical vapor deposition (PECVD) or high-density plasma chemical vapor deposition (HDPCVD) processes to obtain a first dielectric layer 1041 and / or a third dielectric layer 1043. Exemplarily, a second dielectric layer 1042 and / or a blocking material layer 106 can be formed using PVD or ALD processes. Exemplarily, the material of the first dielectric layer 1041 is silicon nitride, the material of the second dielectric layer 1042 is titanium nitride, the material of the third dielectric layer 1043 is silicon nitride, and the material of the blocking material layer 106 is amorphous silicon (α-Si). In optional embodiments, the dielectric structure 104 may have fewer than three layers (e.g., one or two layers) or more than three layers (e.g., four layers).

[0052] Perform step S202 to form the first mask layer.

[0053] refer to Figures 3A to 3E In some embodiments, forming a first mask layer on the blocking material layer includes: forming a first mask material layer 108 on the blocking material layer; performing multiple photolithography etching processes on the first mask material layer 108 to form a first opening OP1 including multiple sets of initial openings; wherein each photolithography etching process forms a set of initial openings P1, P2 or P3 in the first mask material layer.

[0054] refer to Figure 3A A first mask material layer 108 can be formed on the blocking material layer 106 using either PVD or ALD processes. The material of the first mask material layer 108 includes silicon oxide or silicon nitride. For example, the material of the first mask material layer 108 is silicon nitride.

[0055] refer to Figure 3B The photoresist layer (also referred to herein as a three-layer photolithography layer) 110 includes a lower layer (or bottom layer) 1101, an intermediate layer 1102, and an upper layer (or top layer) 1103. The first mask material layer 108 is used to carry the pattern transferred by the photoresist layer to form the first mask layer 108p (see reference). Figure 3E The first mask layer 108p is used to form the second mask layer 112p in the first opening OP1 of the first mask layer 108p (reference). Figure 3H The blocking material layer 106 is used to carry the pattern transferred by the second mask layer 112p to form the blocking layer 106p (reference). Figure 3J The blocking layer 106p is used to pattern the dielectric structure 104. In subsequent processes, interconnect layers can be formed in the patterned dielectric structure 104.

[0056] refer to Figure 3B A three-layer photoresist layer (i.e., photoresist layer 110) is formed on the first mask material layer 108, comprising a lower layer 1101, an intermediate layer 1102 above the lower layer 1101, and an upper layer 1103 above the intermediate layer 1102. The materials of the lower layer 1101 and the upper layer 1103 include organic photoresist. The material of the intermediate layer 1102 may include inorganic materials, such as nitrides (e.g., silicon nitride), oxides of nitride (e.g., silicon oxynitride), oxides (e.g., silicon oxide), etc. The intermediate layer 1102 has high etch selectivity compared to the upper layer 1103 and the lower layer 1101. The upper layer 1103 is used as an etch mask for patterning the intermediate layer 1102, and the intermediate layer 1102 is used as an etch mask for patterning the lower layer 1101. For example, the material of the upper layer 1103 can be photoresist (PR), the material of the middle layer 1102 can be a Si-containing anti-reflective coating (Si-ARC), and the material of the lower layer 1101 can be spin-on carbon (SOC).

[0057] refer to Figures 3B to 3E In some embodiments, the first mask material layer is subjected to multiple photolithographic etching processes to form a first opening including multiple sets of initial openings, including: performing three photolithographic etching processes on the first mask material layer to form a first opening including three sets of initial openings spaced apart from each other.

[0058] refer to Figure 3B A set of initial openings P1 can be formed by a lithography-etch (LE) process, exposing a portion of the top surface of the first mask material layer 108. Exemplarily, the initial openings P1 can be obtained through multiple lithography-etch processes. For example, a portion of the initial openings P1 can be formed in the first lithography-etch process, and another portion of the initial openings P1 can be formed in the second lithography-etch process; that is, the openings obtained through two lithography-etch processes together constitute a set of initial openings P1.

[0059] refer to Figure 3C The first mask material layer 108 exposed by a set of initial openings P1 can be removed by an etching process to expose the top surface of a portion of the blocking layer 106.

[0060] refer to Figure 3D Similarly, it can be repeated. Figure 3B and Figure 3C The photolithography etching process shown is repeated multiple times, resulting in multiple sets of initial openings P1, P2, and P3. It should be noted that... Figure 3DThe image shows three photolithography etching processes, but in reality, each photolithography etching process is performed separately. Figure 3D The diagram illustrates a three-stage photolithography etching process. In optional embodiments, fewer than three (e.g., two) or more than three (e.g., four) photolithography etching processes may be used to form the first mask layer 108p. In some embodiments, the multiple sets of initial openings P1, P2, and P3 are spaced apart from each other. In some embodiments, the feature sizes of the multiple sets of initial openings P1, P2, and P3 may be the same or different.

[0061] refer to Figure 3D and Figure 3E In some embodiments, an ashing process or a wet process can be used to remove the undamaged photoresist layer 110 (which can be understood as the portion of the photoresist layer 110 remaining on the first mask layer 108p after obtaining the first mask layer 108p), exposing the first mask layer 108p. (See reference...) Figure 3E The first mask layer 108p includes a first opening OP1 that exposes a portion of the top surface of the blocking material layer 106. Exemplarily, the first opening OP1 may have a first size D1.

[0062] refer to Figures 3F to 3H In some embodiments, forming a second mask layer in the first opening includes: forming a second mask material layer 112 that fills the first opening OP1 and covers the top surface of the first mask layer 108p; and removing the second mask material layer covering the top surface of the first mask layer 108p using a planarization process to obtain a second mask layer 112p that fills the first opening.

[0063] refer to Figure 3F A second mask material layer 112, which fills the first opening OP1 and covers the top surface of the first mask layer 108p, can be formed using a spin-on-glass (SOG) process.

[0064] refer to Figure 3G The second mask material layer covering the top surface of the first mask layer 108p is removed using a chemical mechanical polishing (CMP) process, resulting in a second mask layer 112p that fills the first opening. In an optional embodiment, the first mask layer 108p can serve as an etch stop layer for the CMP process. Exemplarily, the material of the second mask layer 112p is spin-coated glass.

[0065] refer to Figure 3G and Figure 3HIn some embodiments, removing the first mask layer includes: using the second mask layer 112p as a mask, removing the first mask layer 108p with a first etchant to obtain the second mask layer 112p; wherein the first etchant includes an etch selectivity ratio of 40 or greater for the second mask layer 112p and the first mask layer 108p.

[0066] For example, the first etchant may include an etch selectivity ratio of 60, 80, 100, or 120 for the second mask layer 112p and the first mask layer 108p. For instance, the etch selectivity ratio of the first etchant to the second mask layer 112p and the first mask layer 108p may be 40, 50, 60, 70, 80, 90, 100, 110, 120, or 130.

[0067] For example, the first etching solution is a diluted phosphoric acid (H3PO4) solution, which has an etching selectivity greater than 50 between the first mask layer 108p (e.g., silicon nitride) and the second mask layer 112p (e.g., spin-coated glass). For instance, by utilizing the high selectivity of the phosphoric acid solution in a wet etching process, the silicon nitride, which was originally used as a pattern transfer layer in the spin-coated glass, is removed. Since the etching selectivity of the phosphoric acid solution between silicon nitride and spin-coated glass is greater than 50, the spin-coated glass can be guaranteed not to be etched.

[0068] Exemplarily, the second mask layer 112p includes a second opening OP2 that exposes a portion of the top surface of the blocking material layer 106. Exemplarily, the second opening OP2 may have a second size D2. It should be noted that, since the second mask layer is formed in the first opening, under permissible / normal process losses, the pattern of the second mask layer 112p is complementary to the pattern of the first mask layer 108p; that is, under permissible / normal process losses, the second opening OP2 is equivalent to the linewidth of the first mask layer 108p, and the first opening OP1 is equivalent to the linewidth of the second mask layer 112p.

[0069] refer to Figure 3I In some embodiments, forming a blocking layer for patterning a dielectric structure includes: using a second mask layer 112p as a mask, and employing a second etchant to remove a portion of the blocking material layer 106 (see reference). Figure 3H A blocking layer 106p is obtained; wherein, the second etchant is applied to the second mask layer 112p and the blocking material layer 106 (reference). Figure 3H The etching selectivity is greater than or equal to 40.

[0070] For example, the etching selectivity ratio of the second etchant to the second mask layer 112p and the blocking material layer 106 is greater than 60, greater than 80, greater than 100, or greater than 120. For instance, the etching selectivity ratio of the second etchant to the second mask layer 112p and the blocking material layer 106 can be greater than 40, 50, 60, 70, 80, 90, 100, 110, 120, or 130.

[0071] For example, the second etching solution is an ADM solution, which can be an aqueous ammonia solution at a preset temperature (e.g., 70°C). The ADM solution has an etching selectivity greater than 100 between the blocking material layer 106 (e.g., α-Si) and the second mask layer 112p (e.g., silicon oxide). For example, by utilizing the high selectivity of the ADM solution in the wet etching process and the undercutting characteristics inherent in the wet etching process itself, the feature size of the final retained blocking material layer 106 can be adjusted. For example, the feature size can be adjusted by controlling the etching time of the wet etching process to obtain the blocking layer 106p. In subsequent process steps, the desired pattern of the blocking layer 106p is finally obtained for the interconnect layer.

[0072] For example, the blocking layer 106p includes a third opening OP3 that exposes a portion of the top surface of the dielectric structure 104, and the size of the third opening OP3 is larger than the size of the second opening OP2. For example, the third opening OP3 may have a third size D3, which is larger than the second size D2. It should be noted that, under permissible / normal process losses, after etching to obtain the blocking layer 106p, the pattern of the second mask layer 112p is not lost, that is, under permissible / normal process losses, the second size OP2 of the second opening OP2 is considered to remain unchanged.

[0073] refer to Figure 4 and Figure 3I In some embodiments, the feature size of the blocking layer 106p can be adjusted by controlling over-etching (OE). This has the advantage of step-by-step online inspection before the final pattern of the blocking layer 106p is formed, which can effectively protect the key parameters of each step, with a wider range of adjustability and lower process difficulty.

[0074] refer to Figure 3I In some embodiments, a second etchant is used to remove part of the blocking material layer to obtain a blocking layer, including: using the second etchant for a first duration to remove part of the blocking material layer to obtain a blocking layer 106p with a third opening OP3; wherein the first duration is positively correlated with the size of the third opening OP3.

[0075] For example, the size of the third opening OP3 can be adjusted by controlling the etching duration of the wet etching process; a longer etching duration results in a larger size for the third opening OP3. (See reference...) Figure 4 The second etchant was used for etching for a first duration of a first value to remove part of the blocking material layer, resulting in a blocking layer 106p with a fourth opening OP4. However, the size of the fourth opening OP4 did not meet the process requirements, necessitating further wet etching. (Reference) Figure 3I Based on the continuous etching of the first value, a wet etching process is performed, using a second etchant for a continuous etching time (the total etching time is the second value, which is the sum of the first value and the several time periods) to remove a portion of the blocking material layer, resulting in a blocking layer 106p with a third opening OP3; the second value is longer than the first value, and the size of the third opening OP3 is larger than the size of the fourth opening OP4. Specifically, the sizes of both the third opening OP3 and the fourth opening OP4 are larger than the size of the second mask layer 112p. For example, the fourth opening OP4 may have a fourth size D4, which is smaller than the third size D3, wherein both the fourth size D4 and the third size D3 are larger than the second size D2.

[0076] In this embodiment, the first etching solution has an etching selectivity ratio of 40 or greater for the second mask layer 112p and the first mask layer 108p, and the second etching solution has an etching selectivity ratio of 40 or greater for the second mask layer 112p and the blocking material layer 106. Combined with the undercutting characteristics inherent in the wet etching process, the original exposure process window (e.g., the exposure process window for transferring the pattern from the photoresist layer 110 to the first mask material layer 108) is increased. This avoids the inability to maintain key parameters such as the critical dimensions of the blocking layer used to form the interconnect layer due to limitations in the exposure process. By transferring the pattern step by step, it has the advantage of gradually performing online detection before the final formation of the blocking layer pattern. This effectively maintains key parameters at each step, resulting in a wider range of adjustability and lower process difficulty.

[0077] Figure 5 This is a schematic flowchart illustrating a method for manufacturing a third semiconductor structure according to an embodiment of this application.

[0078] refer to Figure 5 In some embodiments, the manufacturing method further includes the following steps:

[0079] Step S205: Remove the second mask layer;

[0080] Step S206: Pattern the dielectric structure using the blocking layer as a mask to form multiple trenches located in the dielectric structure;

[0081] Step S207: Fill the trench with conductive material to form an interconnect layer.

[0082] Execute step S205, refer to Figure 3I and Figure 3J The second mask layer 112p located above the blocking layer 106p is removed by a dry etching process, exposing the blocking layer 106p.

[0083] Figure 6A , Figure 6B and Figure 6C This is a cross-sectional schematic diagram of the manufacturing process of the third semiconductor structure provided in the embodiments of this application.

[0084] Execute step S206, refer to Figure 6A Using the blocking layer 106p as an etching mask for patterning the third dielectric layer 1043, the third dielectric patterned layer 1043p is obtained. (Reference) Figure 6B The third dielectric pattern layer 1043p is used as an etching mask to pattern the second dielectric layer 1042, resulting in the second dielectric pattern layer 1042p. (Reference) Figure 6C The second dielectric pattern layer 1042p is used as an etching mask to pattern the first dielectric layer 1041, resulting in the first dielectric pattern layer 1041p. The first dielectric pattern layer 1041p includes multiple trenches T. It should be noted that, under permissible / normal process losses, the pattern of the blocking layer 106p is transferred to the pattern of the first dielectric pattern layer 1041p. That is, under permissible / normal process losses, the size of the trenches T is considered to be the same as the opening size of the blocking layer 106p, i.e., the trenches T have a third dimension D3.

[0085] In step S207, multiple trenches T deposit conductive material to form an interconnect layer. Figure 6C (Not shown). The interconnect layer material includes copper (Cu), ruthenium (Ru), etc. In some embodiments, a conductive barrier layer such as titanium nitride, titanium, tantalum nitride, tantalum, etc., may also be formed on the sidewalls and bottom of the trench T. Then, the remaining portion of the trench T is filled with a conductive material such as copper or a copper alloy. Subsequently, a CMP process is performed to remove excess of the barrier layer and filler metal, thereby forming an interconnect layer including the conductive barrier layer.

[0086] Secondly, embodiments of this application provide a semiconductor structure, the semiconductor structure comprising: a substrate including a transistor; a source-drain contact connected to the source or drain of the transistor; and an interconnect layer obtained according to the manufacturing method of the first aspect, located on the source-drain contact and connected to the source-drain contact.

[0087] In some embodiments, a dielectric layer is further included on the substrate 102. Figure 6C (not shown) and contact structures formed in the dielectric layer ( Figure 6C(Not shown). The dielectric layer is an inter-metal dielectric (IMD) or an inter-layer dielectric (ILD), which can be formed of a dielectric material, such as a dielectric material with a dielectric constant (k value) less than 3.8. The material of the contact structure can include, but is not limited to, polycrystalline silicon, titanium nitride, tungsten (W), cobalt (Co), etc.

[0088] In some embodiments, the contact structure includes a zero-layer conductive via (V0), which includes a gate contact, a source contact, and a drain contact connected to the gate, source, and drain of a transistor in the substrate 102; the interconnect layer may be a zero-layer metal interconnect layer (M0), which is in contact with the gate contact, source contact, and drain contact located below the interconnect layer.

[0089] This application also provides another semiconductor structure, which includes: a substrate including a transistor; a source-drain contact connected to the source or drain of the transistor; a zeroth metal interconnect layer (M0) connected to the source-drain contact; and an interconnect layer obtained according to any of the manufacturing methods provided in the first aspect of this application, including a first conductive via (V1) and a first metal interconnect layer (M1) located on the first conductive via (V1); the first conductive via (V1) is located on the zeroth metal interconnect layer (M0), and the first metal interconnect layer (M1) is connected to the zeroth metal interconnect layer (M0) through the first conductive via (V1).

[0090] The semiconductor structure provided in this application is similar to the semiconductor structure manufactured by the manufacturing method of the semiconductor structure in the first aspect described above. For the technical features not disclosed in detail in the embodiments of the second aspect of this application, please refer to the embodiments of the first aspect described above for understanding. Here, they will not be repeated.

[0091] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0092] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; The substrate includes a substrate, a dielectric structure located on the substrate, and a blocking material layer located on the dielectric structure; The medium structure includes at least one medium layer; A first mask layer is formed on the blocking material layer; the first mask layer includes a first opening that exposes a portion of the top surface of the blocking material layer; A second mask layer is formed in the first opening, and the first mask layer is removed; The second mask layer includes a second opening that exposes a portion of the top surface of the blocking material layer; The blocking material layer is patterned using the second mask layer as a mask to form a blocking layer for patterning the dielectric structure; the blocking layer includes a third opening that exposes a portion of the top surface of the dielectric structure; The size of the third opening is larger than the size of the second opening.

2. The manufacturing method according to claim 1, characterized in that, Forming a first mask layer on the blocking material layer includes: A first mask material layer is formed on the blocking material layer; The first mask material layer is subjected to multiple photolithography etching processes to form the first opening, which includes multiple sets of initial openings; wherein, each photolithography etching process forms a set of the initial openings in the first mask material layer.

3. The manufacturing method according to claim 2, characterized in that, The first opening, comprising multiple sets of initial openings, is formed by performing multiple photolithography etching processes on the first mask material layer, including: The first mask material layer is subjected to the photolithography etching process three times to form the first opening, which includes three sets of the initial openings spaced apart from each other.

4. The manufacturing method according to any one of claims 1 to 3, characterized in that, Forming a second mask layer in the first opening includes: A second mask material layer is formed to fill the first opening and cover the top surface of the first mask layer; A planarization process is used to remove the second mask material layer covering the top surface of the first mask layer, resulting in a second mask layer that fills the first opening.

5. The manufacturing method according to claim 1, characterized in that, Removing the first mask layer includes: Using the second mask layer as a mask, the first mask layer is removed by a first etchant to obtain the second mask layer; wherein the etching selectivity ratio of the first etchant to the second mask layer and the first mask layer is greater than or equal to 40.

6. The manufacturing method according to claim 1, characterized in that, Forming a blocking layer for graphical representation of the dielectric structure includes: Using the second mask layer as a mask, a second etchant is used to remove part of the blocking material layer to obtain the blocking layer; wherein, the etching selectivity ratio of the second etchant to the second mask layer and the blocking material layer is greater than or equal to 40.

7. The manufacturing method according to claim 6, characterized in that, The blocking layer is obtained by removing a portion of the blocking material layer using a second etching solution, including: The second etching solution is used to remove part of the blocking material layer for a first duration to obtain the blocking layer with the third opening; The first duration is positively correlated with the size of the third opening.

8. The manufacturing method according to claim 1, characterized in that, The substrate includes: Provide the substrate; The dielectric structure and the blocking material layer are sequentially formed on the substrate. The dielectric structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked sequentially. The blocking material layer includes silicon. The first dielectric layer and the third dielectric layer are made of silicon oxide or silicon nitride. The second dielectric layer is made of titanium nitride.

9. The manufacturing method according to any one of claims 1 to 3, 5 to 8, characterized in that, The manufacturing method further includes: Remove the second mask layer; The dielectric structure is patterned using the blocking layer as a mask to form multiple trenches located in the dielectric structure; The trench is filled with conductive material to form an interconnect layer.

10. A semiconductor structure, characterized in that, include: Substrate, including transistors; The source-drain contact is connected to either the source or the drain of the transistor. An interconnect layer, obtained by the manufacturing method according to claim 9, is located on the source-drain contact and connected to the source-drain contact.

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