Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region and a second region; forming a first isolation structure in the first region; forming a second isolation structure in the second region, a top surface of the first isolation structure being higher than a top surface of the second isolation structure; forming a plurality of floating gate structures on the second region, the second isolation structure being located between adjacent floating gate structures; and performing a cleaning process on a top surface of the first region and a top surface of the first isolation structure after forming the floating gate structures. By performing a cleaning process on a top surface of the first region and a top surface of the first isolation structure after forming the floating gate structures, residues formed during previous processes are removed, thereby improving performance of the semiconductor structure formed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] With the continuous development of semiconductor technology, memory is showing a trend of high integration, high speed, and low power consumption.

[0003] Functionally, memory is divided into Random Access Memory (RAM) and Read Only Memory (ROM). When RAM is working, data can be read from any specified address at any time, and data can be written to any specified memory location at any time. RAM offers convenient read and write operations and is highly flexible in use.

[0004] Random access memory (RAM) can be divided into static random access memory (SRAM) and dynamic random access memory (DRAM). SRAM uses flip-flops with positive feedback to store data and relies primarily on a continuous power supply to maintain data integrity. SRAM does not require refreshing during use. SRAM is widely used in computer caches and in applications requiring frequent data processing.

[0005] However, static random access memory (SRAM) in the prior art has poor performance. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a method for forming a semiconductor structure, which can effectively improve the performance of the final semiconductor structure.

[0007] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; forming a first isolation structure in the first region; forming a second isolation structure in the second region, wherein the top surface of the first isolation structure is higher than the top surface of the second isolation structure; forming a plurality of floating gate structures on the second region, wherein the second isolation structures are located between adjacent floating gate structures; and after forming the floating gate structures, cleaning the top surface of the first region and the top surface of the first isolation structure.

[0008] Optionally, the floating gate structure includes a floating gate dielectric layer and a floating gate layer located on the floating gate dielectric layer.

[0009] Optionally, the method for forming the floating gate structure includes: forming a floating gate dielectric film on the substrate, the floating gate dielectric film covering the top surfaces of the first region, the second region, the first isolation structure, and the second isolation structure respectively; forming a floating gate film on the floating gate dielectric film; forming a first patterning layer on the floating gate film, the first patterning layer exposing a portion of the top surface of the floating gate film; etching the floating gate film and the floating gate dielectric film using the first patterning layer as a mask to form initial floating gate structures on the first region and the second region respectively; removing the initial floating gate structure located on the first region, and forming the floating gate structure on the second region.

[0010] Optionally, after the floating grid structure is formed, there are residues on the sidewalls of the first isolation structure above the top surface of the first region, and the cleaning process removes the residues.

[0011] Optionally, the material of the floating gate dielectric layer includes silicon oxide.

[0012] Optionally, the material of the floating gate layer includes polycrystalline silicon.

[0013] Optionally, after forming the floating gate structure, the method further includes: forming an adjacent first well region and a second well region within the first region, wherein the first isolation structure is located between the first well region and the second well region.

[0014] Optionally, the first well region is formed before the second well region is formed.

[0015] Optionally, the cleaning process includes: performing a first cleaning process after forming the first well region; and performing a second cleaning process after forming the second well region.

[0016] Optionally, the method for forming the first well region and performing the first cleaning process includes: forming a second patterned layer on the substrate, the second patterned layer exposing a portion of the top surface of the first region and a portion of the top surface of the first isolation structure; performing a first ion implantation process on the first region using the second patterned layer as a mask to form the first well region; after forming the first well region, performing the first cleaning process on the exposed top surface of the first region and the top surface of the first isolation structure using the second patterned layer as a mask; and removing the second patterned layer after the first cleaning process.

[0017] Optionally, the method for forming the second well region and performing the second cleaning process includes: forming a third patterned layer on the substrate, the third patterned layer exposing a portion of the top surface of the first region and a portion of the top surface of the first isolation structure; performing a second ion implantation process on the first region using the third patterned layer as a mask to form the second well region; after forming the second well region, performing the second cleaning process on the exposed top surface of the first region and the top surface of the first isolation structure using the third patterned layer as a mask; and removing the third patterned layer after the second cleaning process.

[0018] Optionally, the first ion and the second ion have different electrical types.

[0019] Optionally, the first ion includes an N-type ion or a P-type ion; the second ion includes both N-type and P-type ions.

[0020] Optionally, the process parameters for the first cleaning treatment include: the cleaning solution includes hydrofluoric acid, wherein the volume ratio of hydrofluoric acid solution is 1:50 to 1:100; the cleaning temperature is 24.5 degrees Celsius to 25.5 degrees Celsius; and the cleaning time is 1 minute to 2 minutes.

[0021] Optionally, the process parameters for the second cleaning treatment include: the cleaning solution includes hydrofluoric acid, wherein the volume ratio of hydrofluoric acid solution is 1:50 to 1:100; the cleaning temperature is 24.5 degrees Celsius to 25.5 degrees Celsius; and the cleaning time is 1 minute to 2 minutes.

[0022] Optionally, after the cleaning process, the method further includes forming a control grid structure on the floating grid structure.

[0023] Optionally, the control gate structure includes: a control gate dielectric layer and a control gate layer located on the control gate dielectric layer.

[0024] Optionally, the control gate dielectric layer can be a single-layer structure or a multi-layer structure.

[0025] Optionally, when the control gate dielectric layer is a multilayer structure, the control gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0026] Optionally, the material of the control gate layer includes polycrystalline silicon.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0028] In the method for forming the technical solution of the present invention, after forming the floating gate structure, the top surface of the first region and the top surface of the first isolation structure are cleaned. This cleaning process removes residues formed during the preceding processes, thereby improving the performance of the final semiconductor structure.

[0029] Furthermore, the first cleaning process is performed after the formation of the first well region. Using the second patterned layer formed during the formation of the first well region for the first cleaning process effectively reduces process steps and saves manufacturing costs.

[0030] Furthermore, the second cleaning process is performed after the formation of the second well region. Using the third patterned layer formed during the formation of the second well region for the second cleaning process effectively reduces process steps and saves manufacturing costs. Attached Figure Description

[0031] Figures 1 to 2 This is a schematic diagram of a semiconductor structure.

[0032] Figures 3 to 12 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0033] As described in the background section, the performance of static random access memory (SRAM) in the prior art is poor. This will be explained in detail below with reference to the accompanying drawings.

[0034] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a first region I and a second region II; a first isolation structure 101 is formed in the first region I; a second isolation structure 102 is formed in the second region II, the top surface of the first isolation structure 101 is higher than the top surface of the second isolation structure 102.

[0035] Please refer to Figure 2 A plurality of floating gate structures 103 are formed on the second region II, and the second isolation structure 102 is located between adjacent floating gate structures 103; after the floating gate structures 103 are formed, adjacent first well region 104 and second well region 105 are formed in the first region I, and the first isolation structure 101 is located between the first well region 101 and the second well region 105.

[0036] In this embodiment, the first region I is used to form a static random-access memory (SRAM), and the second region II is used to form a flash memory. By integrating the SRAM and flash memory, a special memory that can realize storage functions is formed. It is widely used because of its advantages such as low power consumption, low cost, high density, and high reliability.

[0037] In this embodiment, since there will be many etching processes in the subsequent manufacturing process, these etching processes will continuously wear down the first isolation structure 101 and the second isolation structure 102. In order to ensure the isolation effect of the first isolation structure 101 and the second isolation structure 102 in the end, the top surface of the first isolation structure 101 and the second isolation structure 102 is higher than the top surface of the first region I and the second region II when the first isolation structure 101 and the second isolation structure 102 are initially formed.

[0038] In this embodiment, the formation process of the floating gate structure 103 is as follows: first, initial floating gate structures (not shown) are formed on the first region I and the second region II respectively; then, the initial pseudo-gate structure located on the first region I is removed, and then the floating gate structure 103 is formed on the second region II. However, during the removal of the initial pseudo-gate structure on the first region I, since the top surface of the first isolation structure 101 is higher than the top surface of the first region I, the initial floating gate structure at the interface between the first isolation structure 101 and the first region I will not be completely removed, thus forming residues of the floating gate structure (such as...). Figure 2 As shown in Part A), the residue can affect the performance of the subsequently formed semiconductor structure.

[0039] Based on this, the present invention provides a method for forming a semiconductor structure, which involves cleaning the top surface of the first region and the top surface of the first isolation structure after forming the floating gate structure. This cleaning process removes residues formed during previous processes, thereby improving the performance of the final semiconductor structure.

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 3 to 12 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figure 3A substrate 200 is provided, the substrate 200 including a first region I and a second region II.

[0043] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0044] In this embodiment, the first region I is used to form a static random-access memory (SRAM), and the second region II is used to form a flash memory. By integrating the SRAM and flash memory, a special memory that can realize storage functions is formed. It is widely used because of its advantages such as low power consumption, low cost, high density, and high reliability.

[0045] Please refer to Figure 4 A first isolation structure 201 is formed within the first region I.

[0046] In this embodiment, the method for forming the first isolation structure 201 includes: forming a first isolation trench (not shown) in the first region I; and forming the first isolation structure 201 in the first isolation trench.

[0047] Since the first region I will be etched multiple times in the subsequent manufacturing process, the first isolation structure 201 will be continuously damaged and consumed during the etching process. Therefore, in order to ensure that the final first isolation structure 201 has a better isolation effect, the top surface of the first isolation structure 201 is higher than the top surface of the first region I.

[0048] In this embodiment, the first isolation structure 201 is made of silicon oxide.

[0049] Please continue to refer to this. Figure 4 During the formation of the first isolation structure 201, a second isolation structure 202 is formed in the second region II, wherein the top surface of the first isolation structure 201 is higher than the top surface of the second isolation structure 202.

[0050] In this embodiment, the method for forming the second isolation structure 202 includes: forming a second isolation trench (not shown) in the second region II; and forming the second isolation structure 202 in the second isolation trench.

[0051] Since the second region II will be etched multiple times in the subsequent manufacturing process, the second isolation structure 202 will be continuously damaged and consumed during the etching process. Therefore, in order to ensure that the final second isolation structure 202 has a better isolation effect, the top surface of the second isolation structure 202 is higher than the top surface of the second region II.

[0052] In this embodiment, the material of the second isolation structure 202 is silicon oxide.

[0053] Since the second region II is used to form the flash memory, in order to better distinguish between high level 1 and low level 0, it is necessary to clean out the floating gate tip on the second region II. At this time, the first region I needs to be covered by a mask, and then the second region II is cleaned. In this process, a certain height of the second isolation structure 202 will be lost, so that the top surface of the first isolation structure 201 is higher than the top surface of the second isolation structure 202.

[0054] Since the top surface of the first isolation structure 201 is higher than the top surface of the second isolation structure 202, residues are easily formed on the sidewall of the first isolation structure 201, which is higher than the top surface of the first region I, during subsequent processes.

[0055] Please refer to Figure 5 A plurality of floating grid structures 203 are formed on the second region II, and the second isolation structure 202 is located between adjacent floating grid structures 203.

[0056] In this embodiment, the floating gate structure 203 includes a floating gate dielectric layer and a floating gate layer (not shown) located on the floating gate dielectric layer.

[0057] In this embodiment, the material of the floating gate dielectric layer includes silicon oxide.

[0058] In this embodiment, the material of the floating gate layer includes polycrystalline silicon.

[0059] In this embodiment, the method for forming the floating gate structure 203 includes: forming a floating gate dielectric film (not shown) on the substrate 200, the floating gate dielectric film covering the top surfaces of the first region I, the second region II, the first isolation structure 201, and the second isolation structure 202 respectively; forming a floating gate film (not shown) on the floating gate dielectric film; forming a first patterning layer (not shown) on the floating gate film, the first patterning layer exposing a portion of the top surface of the floating gate film; etching the floating gate film and the floating gate dielectric film using the first patterning layer as a mask to form initial floating gate structures (not shown) on the first region I and the second region II respectively; removing the initial floating gate structure located on the first region I, and forming the floating gate structure 203 on the second region II.

[0060] In this embodiment, after the floating grid structure 203 is formed, there are residues on the sidewall of the first isolation structure 201 above the top surface of the first region I, and the cleaning process removes the residues.

[0061] In this embodiment, the residue is the material of the floating gate dielectric layer that adheres to the sidewall of the first isolation structure 201 when the initial floating gate structure located on the first region I is removed. Therefore, the material of the residue includes silicon oxide.

[0062] After forming the floating gate structure 203, the process further includes: forming adjacent first and second well regions within the first region I, with the first isolation structure 201 located between the first and second well regions; and cleaning the top surface of the first region I and the top surface of the first isolation structure 201, the cleaning process including: performing a first cleaning process after forming the first well region; and performing a second cleaning process after forming the second well region. Please refer to [link / reference needed] for details. Figure 6 to Figure 10 .

[0063] Please refer to Figure 6 A second patterned layer 204 is formed on the substrate 200, the second patterned layer 204 exposing part of the top surface of the first region I and part of the top surface of the first isolation structure 201; the first region I is implanted with first ions using the second patterned layer 204 as a mask to form the first well region 205.

[0064] In this embodiment, the material of the second patterned layer includes photoresist, and the formation process of the second patterned layer includes photolithography patterning.

[0065] In this embodiment, the first well region 205 is formed before the formation of the second well region.

[0066] In this embodiment, the first ion is a P-type ion; in other embodiments, the first ion may also be an N-type ion.

[0067] Please refer to Figure 7 After the first well region 205 is formed, the first cleaning process is performed on the top surface of the exposed first region I and the top surface of the first isolation structure 201 using the second patterning layer 204 as a mask.

[0068] In this embodiment, during the first cleaning process, since the material of the first isolation structure is the same as the material of the residue, although the first cleaning process can remove the residue, it will also cause some damage to the first isolation structure. Therefore, after the first cleaning process, the height of the exposed top surface of the first isolation structure will be reduced.

[0069] Since the first cleaning process is performed after the formation of the first well region 205, using the second patterned layer 204 formed during the formation of the first well region 205 for the first cleaning process can effectively reduce the number of process steps and save manufacturing costs.

[0070] In this embodiment, the process parameters of the first cleaning treatment include: the cleaning solution includes hydrofluoric acid, wherein the volume ratio of hydrofluoric acid solution is 1:50 to 1:100; the cleaning temperature is 24.5 degrees Celsius to 25.5 degrees Celsius; and the cleaning time is 1 minute to 2 minutes.

[0071] Please refer to Figure 8 After the first cleaning process, the second patterning layer is removed.

[0072] In this embodiment, since the second patterned layer is made of photoresist, and the photoresist material has a large etching selectivity ratio with the silicon oxide material used in the first isolation structure, the damage to the first isolation structure is small during the removal of the second pattern, and the height of the top surface of the first isolation structure will not be significantly reduced.

[0073] The process for removing the second patterned layer includes a wet stripping process or an ashing process. In this embodiment, the process for removing the second patterned layer is an ashing process, and the gas used in the ashing process is an oxygen-containing gas, such as oxygen or ozone.

[0074] Please refer to Figure 9A third patterned layer 206 is formed on the substrate 200, the third patterned layer 206 exposing part of the top surface of the first region I and part of the top surface of the first isolation structure 201; the first region I is implanted with second ions using the third patterned layer 206 as a mask to form the second well region 207.

[0075] In this embodiment, the material of the third patterning layer includes photoresist, and the formation process of the third patterning layer includes photolithography patterning.

[0076] In this embodiment, the first ion and the second ion have different electrical types.

[0077] In this embodiment, the second ion is an N-type ion; in other embodiments, the second ion may also be a P-type ion.

[0078] Please refer to Figure 10 After the second well region 207 is formed, the top surface of the exposed first region I and the top surface of the first isolation structure 201 are subjected to the second cleaning process using the third patterning layer 206 as a mask.

[0079] In this embodiment, the second cleaning process also causes some damage to the first isolation structure. Therefore, after the second cleaning process, the height of the exposed top surface of the first isolation structure will be reduced.

[0080] After forming the floating gate structure 203, the top surface of the first region I and the top surface of the first isolation structure 201 are cleaned. This cleaning process removes residues formed during previous processes, thereby improving the performance of the final semiconductor structure.

[0081] Since the second cleaning process is performed after the formation of the second well region 207, using the third patterned layer 206 formed during the formation of the second well region 207 for the second cleaning process can effectively reduce the number of process steps and save manufacturing costs.

[0082] In this embodiment, the process parameters of the second cleaning treatment include: the cleaning solution includes hydrofluoric acid, wherein the volume ratio of hydrofluoric acid solution is 1:50 to 1:100; the cleaning temperature is 24.5 degrees Celsius to 25.5 degrees Celsius; and the cleaning time is 1 minute to 2 minutes.

[0083] Please refer to Figure 11 After the second cleaning process, the third patterning layer is removed.

[0084] In this embodiment, since the third patterning layer is made of photoresist, and the photoresist material has a large etching selectivity ratio with the silicon oxide material used in the first isolation structure, the damage to the first isolation structure is small during the removal of the third patterning layer, and the height of the top surface of the first isolation structure will not be significantly reduced.

[0085] The process for removing the third patterned layer includes a wet stripping process or an ashing process. In this embodiment, the process for removing the third patterned layer is an ashing process, and the gas used in the ashing process is an oxygen-containing gas, such as oxygen or ozone.

[0086] Please refer to Figure 12 After the cleaning process, a control gate structure 208 is formed on the floating gate structure 203.

[0087] In this embodiment, the control gate structure 208 includes: a control gate dielectric layer and a control gate layer (not shown) located on the control gate dielectric layer.

[0088] In this embodiment, the control gate dielectric layer adopts a multilayer structure, and the control gate dielectric layer includes: a first silicon oxide layer located on the floating gate layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer (not shown) located on the silicon nitride layer.

[0089] The first silicon oxide layer and the second silicon oxide layer of the control gate dielectric layer can be well bonded to the base crystal, while the silicon nitride layer is in the middle and can block the extension of defects (such as pinholes). Therefore, the three-layer structure design can complement each other.

[0090] In other embodiments, the control gate dielectric layer may also be a single-layer structure.

[0091] In this embodiment, the material of the control gate layer includes polycrystalline silicon.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A first isolation structure is formed within the first zone; A second isolation structure is formed within the second region, wherein the top surface of the first isolation structure is higher than the top surface of the second isolation structure; A plurality of floating grid structures are formed on the second region, and the second isolation structure is located between adjacent floating grid structures; After the floating grid structure is formed, the top surface of the first region and the top surface of the first isolation structure are cleaned; wherein... After forming the floating gate structure, the method further includes: forming an adjacent first well region and a second well region within the first region, wherein the first isolation structure is located between the first well region and the second well region; The cleaning process includes: performing a first cleaning process after forming the first well region; and performing a second cleaning process after forming the second well region. There are residues on the sidewall of the first isolation structure above the top surface of the first region. The cleaning process removes the residues, which are the material of the floating grid dielectric layer that adhered to the sidewall of the first isolation structure when the initial floating grid structure located on the first region was removed. The first cleaning process is performed using the second patterned layer formed during the formation of the first well region; The second cleaning process is performed using the third patterned layer formed during the formation of the second well region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The floating gate structure includes a floating gate dielectric layer and a floating gate layer located on the floating gate dielectric layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method for forming the floating gate structure includes: forming a floating gate dielectric film on the substrate, the floating gate dielectric film covering the top surfaces of the first region, the second region, the first isolation structure, and the second isolation structure respectively; forming a floating gate film on the floating gate dielectric film; forming a first patterning layer on the floating gate film, the first patterning layer exposing a portion of the top surface of the floating gate film; etching the floating gate film and the floating gate dielectric film using the first patterning layer as a mask to form initial floating gate structures on the first region and the second region respectively; removing the initial floating gate structure located on the first region, and forming the floating gate structure on the second region.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the floating gate dielectric layer includes silicon oxide.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the floating gate layer includes polycrystalline silicon.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first well region is formed before the formation of the second well region.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the first well region and performing the first cleaning process includes: forming a second patterned layer on the substrate, the second patterned layer exposing a portion of the top surface of the first region and a portion of the top surface of the first isolation structure; performing a first ion implantation process on the first region using the second patterned layer as a mask to form the first well region; after forming the first well region, performing the first cleaning process on the exposed top surface of the first region and the top surface of the first isolation structure using the second patterned layer as a mask; and removing the second patterned layer after the first cleaning process.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the second well region and performing the second cleaning process includes: forming a third patterned layer on the substrate, the third patterned layer exposing a portion of the top surface of the first region and a portion of the top surface of the first isolation structure; performing a second ion implantation process on the first region using the third patterned layer as a mask to form the second well region; after forming the second well region, performing the second cleaning process on the exposed top surface of the first region and the top surface of the first isolation structure using the third patterned layer as a mask; and removing the third patterned layer after the second cleaning process.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The first ion and the second ion have different electrical types.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first ion includes N-type ions or P-type ions; the second ion includes N-type ions or P-type ions.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for the first cleaning treatment include: the cleaning solution includes hydrofluoric acid, wherein the volume ratio of hydrofluoric acid solution is 1:50 to 1:100; the cleaning temperature is 24.5 degrees Celsius to 25.5 degrees Celsius; and the cleaning time is 1 minute to 2 minutes.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for the second cleaning treatment include: the cleaning solution includes hydrofluoric acid, wherein the volume ratio of hydrofluoric acid solution is 1:50 to 1:100; the cleaning temperature is 24.5 degrees Celsius to 25.5 degrees Celsius; and the cleaning time is 1 minute to 2 minutes.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, Following the cleaning process, the method further includes forming a control grid structure on the floating grid structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The control gate structure includes: a control gate dielectric layer and a control gate layer located on the control gate dielectric layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The control gate dielectric layer can be a single-layer structure or a multi-layer structure.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, When the control gate dielectric layer is a multilayer structure, the control gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

17. The method for forming a semiconductor structure as described in claim 14, characterized in that, The material of the control gate layer includes polycrystalline silicon.

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