Semiconductor device and manufacturing method

Abstract

Semiconductor devices and manufacturing methods are provided, wherein a memory cell having a dual-sided word line structure is manufactured. In an embodiment, a first word line is located on a first side of the memory cell, and a second word line is located on a second side of the memory cell opposite to the first side.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and manufacturing methods. Background Technology

[0002] Semiconductor memories are used in integrated circuits for electronic applications, including devices such as radios, televisions, mobile phones, and personal computers. One type of semiconductor memory is resistive random access memory (RRAM), which involves storing values ​​in a material with varying resistance. The material with varying resistance can switch between a low-resistance phase and a high-resistance phase to indicate bits. Summary of the Invention

[0003] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a first word line above a substrate; forming a bit line above the first word line; forming a first memory cell and a second memory cell on the opposite side of the bit line after forming the first word line; depositing a second word line adjacent to the first memory cell and electrically connected to the first word line; depositing a third functional word line adjacent to the second memory cell; and forming a fourth word line electrically connected to the third functional word line after depositing the third functional word line.

[0004] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a bottom word line above a substrate; forming a first word line above the bottom word line; forming an RRAM material adjacent to the first word line; forming a selector material adjacent to the RRAM material; forming a first word line on a first side of the first word line, the first word line being electrically connected to the bottom word line; forming a second word line on a second side of the first word line opposite to the first side; and forming a top word line above the second word line and electrically connected to the second word line.

[0005] According to another aspect of the present invention, a semiconductor device is provided, comprising: a bit line disposed on a dielectric layer; a first memory cell disposed on a first sidewall of the bit line; a second memory cell disposed on a second sidewall of the bit line opposite to the first sidewall; a first word line disposed on the dielectric layer, wherein the first memory cell is disposed between the first sidewall of the bit line and the sidewall of the first word line; a second word line disposed on the dielectric layer, wherein the second memory cell is disposed between the second sidewall of the bit line and the sidewall of the second word line; a top word line disposed above the bit line and electrically connected to the first word line; and a bottom word line disposed below the bit line and electrically connected to the second word line. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figure 1A-Figure 1B The formation of a first word line is shown according to some embodiments.

[0008] Figures 2A-2B The formation of bit line material according to some embodiments is shown.

[0009] Figures 3A-3B The formation of bit lines according to some embodiments is shown.

[0010] Figures 4A-4B The formation of RRAM material according to some embodiments is shown.

[0011] Figures 5A-5B The patterning of RRAM material according to some embodiments is shown.

[0012] Figures 6A-6B The formation of a selector according to some embodiments is shown.

[0013] Figures 7A-7B The formation of functional word line material according to some embodiments is shown.

[0014] Figures 8A-8B The formation of function word lines according to some embodiments is shown.

[0015] Figures 9A-9B The formation of a dielectric layer according to some embodiments is shown.

[0016] Figures 10A-10B The formation of an opening through the dielectric layer is shown according to some embodiments.

[0017] Figures 11A-11B The formation of a second letter line material according to some embodiments is shown.

[0018] Figures 12A-12B The formation of the second word line is shown according to some embodiments.

[0019] Figures 13A-13C The formation of a dielectric layer according to some embodiments is shown.

[0020] Figure 14 The formation of a metallization layer according to some embodiments is shown.

[0021] Figure 15 The diagram illustrates a memory region adjacent to a logical region according to some embodiments.

[0022] Figures 16A-16BThe placement of a first hard mask according to some embodiments is shown.

[0023] Figures 17A-17B The formation of a functional word line with a first hard mask in place is shown according to some embodiments.

[0024] Figures 18A-18B The formation of a second word line with a first hard mask in place, according to some embodiments, is shown.

[0025] Figure 19 The formation of selector material prior to patterning RRAM material is shown according to some embodiments.

[0026] Figure 20 The diagram illustrates the patterning of RRAM material with selector material according to some embodiments to form an "L" shape.

[0027] Figure 21 The formation of a second word line of patterned RRAM material with an "L" shape is shown according to some embodiments.

[0028] Figure 22 The diagram illustrates an RRAM material that forms an "L" shape when the first hard mask is in place, according to some embodiments. Detailed Implementation

[0029] The following disclosure provides various embodiments or examples to achieve different features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0030] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0031] Embodiments will now be described with reference to specific examples, wherein a resistive random access memory (RRAM) device is connected to a word line located on the opposite side of the RRAM device to provide individual bit operation capability for a multi-functional vertical RRAM cell on each bit line (e.g., in a 1S1R structure). However, the embodiments described herein are intended to be illustrative, as the presented concepts can be used in a variety of embodiments, and are not intended to limit the embodiments to those specifically described herein.

[0032] Now for reference Figure 1A-Figure 1B The figure shows a first word line 103 formed above a substrate 101. Figure 1A Show Figure 1B The top view of the structure along line A-A'. Figure 1B Show Figure 1A A cross-sectional view along line B-B'. Substrate 101 may include an active layer of doped or undoped bulk silicon or silicon-on-insulator (SOI) substrate. Typically, SOI substrates comprise layers of semiconductor materials such as silicon, germanium, germanium-silicon, SOI, germanium-on-insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0033] Additionally, substrate 101 may include active devices (not shown separately) formed within and / or on substrate 101 and a first metallization layer 102 located above the active devices. Those skilled in the art will recognize that a variety of active and passive devices, such as transistors, capacitors, resistors, combinations thereof, etc., can be used to generate the desired structural and functional requirements for the design of semiconductor devices, and can be formed using any suitable method. For example, in some embodiments, the active device may be a FinFET device, wherein fins of semiconductor material are formed with a gate stack (forming shallow trench isolation (STI) regions between the fins) located above the fins of the FinFET device and a source / drain region formed on the opposite side of the gate stack within the fins. For clarity, the STI regions and source / drain regions are not shown separately.

[0034] The first metallization layer 102 can be formed over active devices and designed to connect the various active devices to form a functional circuit. In an embodiment, the first metallization layer 102 is formed of alternating layers of dielectric (e.g., low-k dielectric, very low-k dielectric, ultra-low-k dielectric, combinations thereof, etc.) and conductive material, and can be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.).

[0035] In an embodiment, the first metallization layer 102 may include a first metal layer, a second metal layer, a third metal layer, and a fourth metal line 111 (only the fourth metal line 111 is shown for clarity). Furthermore, the first metallization layer 102 includes a dielectric layer 110 located above the fourth metal line 111, and also includes a first metallized via 113 extending through the dielectric layer 110. However, any suitable number of metal layers, conductive layers, and vias can be used.

[0036] Once the substrate 101 has been presented or otherwise prepared, a first word line 103 may be formed over the substrate 101 and electrically connected to the first metallized via 113. In an embodiment, the first word line 103 may be formed by initially forming a first dielectric layer 105 over the substrate 101. The first dielectric layer 105 may be formed using processes such as CVD, PVD, PECVD, but other processes such as LPCVD may also be used. The first dielectric layer 105 may include a dielectric material such as doped or undoped silicon oxide, silicon nitride, doped silicate glass, other high-k materials, combinations thereof, etc. In an embodiment, the first dielectric layer 105 may include a material such as borosilicate glass (BPSG), but any suitable dielectric layer may be used for either layer.

[0037] After formation, the first dielectric layer 105 can be planarized using, for example, a chemical mechanical polishing (CMP) process. However, any other suitable planarization process can be used to reduce the first dielectric layer 105 to the desired height and provide a flat profile for the first dielectric layer 105.

[0038] Once the first dielectric layer 105 is formed, the first word line 103 can be formed within the first dielectric layer 105. In an embodiment, the formation of the first word line 103 can begin by first forming an opening within the first dielectric layer 105. In an embodiment, a suitable photolithography masking and etching process can be used to form the opening. However, any suitable process can be used to form the opening.

[0039] Once an opening is formed in the first dielectric layer 105, the formation of the first adhesive layer can begin. Figure 1A-Figure 1B (Not shown separately). In an embodiment, the first adhesive layer is used to help adhere the remainder of the first letter 103 to the underlying structure, and may be, for example, titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, combinations thereof, oxides thereof, etc., formed using processes such as CVD, plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0040] Once the first adhesive layer is formed, a first word line 103 can be deposited to fill the remaining portion of the opening in the first dielectric layer 105. In embodiments, the first word line 103 can be a conductive material such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, molybdenum nitride, or alloys thereof, formed using processes such as CVD, plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). However, any suitable material and manufacturing method can be used.

[0041] Once the material of the first word line 103 has been deposited to fill and / or overfill the opening within the first dielectric layer 105, excess material in the first word line 103 and the first adhesive layer located outside the second dielectric layer 107 is removed. In embodiments, the removal process can be a planarization process, such as a chemical mechanical polishing process. However, any suitable planarization process can be used.

[0042] Additionally, while a specific embodiment has been described above to illustrate how the first word line 103 is manufactured, this description is intended to be illustrative and not limiting. Rather, any suitable manufacturing method may be used. For example, in other embodiments, the material of the first word line 103 may first be deposited, and then patterned using processes such as photolithography masking and etching. Once deposited and patterned, the material of the first dielectric layer 105 may then be deposited and planarized to aid in the formation of the first word line 103. These methods, and all other suitable methods, are fully intended to be included within the scope of the embodiments.

[0043] In an embodiment, the first word line 103 may be formed to have a first thickness T between approximately 80 nm and approximately 180 nm. l And they can be spaced apart by a first gap S between approximately 40 nm and approximately 80 nm. l Furthermore, the first word line 103 can be formed with a first width W1 between approximately 40 nm and approximately 80 nm. However, any suitable size can be used.

[0044] Once the first word line 103 is formed, a second dielectric layer 107 is formed above the first word line 103, and a first via 109 is formed through the second dielectric layer 107. In this embodiment, the second dielectric layer 107 is formed using a similar material and a similar process to the first dielectric layer 105 described above. However, any suitable method and material can be used.

[0045] Once the second dielectric layer 107 is formed, a first via 109 can be formed through the second dielectric layer 107 to connect to the first word line 103. In an embodiment, the first via 109 can be formed using materials and processes similar to those used for the first word line 103 (discussed above), such as forming an opening in the second dielectric layer 107, filling the opening with a conductive material such as copper, and then planarizing the conductive material. However, any suitable method and material can be used.

[0046] Figures 2A-2B The bit line 301 located above and electrically connected to the first through hole 109 is shown (in Figures 2A-2B Not shown in the image, but below about Figures 3A-3B The deposition of bitline material 201 (shown and described). In these figures, Figure 2A Show Figure 2B Top view along line A-A' Figure 2B Show Figure 2A A cross-sectional view along line B-B'. In this embodiment, the bit line material 201 can be a conductive material such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, or their alloys. The conductive material can be formed by an acceptable deposition process (such as ALD or CVD), an acceptable plating process (such as electroplating or electroless plating), etc. However, any suitable material and manufacturing method can be used.

[0047] Once the bitline material 201 is deposited, a first hard mask 203 can be deposited over the bitline material 201. In an embodiment, the first hard mask 203 can be a material such as silicon nitride, but any suitable masking material can also be used, such as silicon oxide, silicon oxynitride, SiCON, SiC, or SiOC. The first hard mask 203 can be formed using deposition processes such as chemical vapor deposition or physical vapor deposition. However, any suitable process or thickness can be used.

[0048] Figures 3A-3B The patterning of bit line material 201 is shown to form bit line 301. In these figures, Figure 3A Show Figure 3B Top view along line A-A' Figure 3B Show Figure 3A A cross-sectional view along line B-B'. In an embodiment, once the first hard mask 203 is deposited over the bit line material 201, the first hard mask 203 can be patterned using, for example, one or more photolithographic masking and etching processes. However, any suitable method for patterning the first hard mask 203 can be used.

[0049] Once the first hard mask 203 is patterned, the pattern of the first hard mask 203 can be transferred to the bit line material 201 to form the bit line 301. In an embodiment, one or more etching processes can be used to transfer the pattern, which uses the first hard mask 203 as a masking material. However, any suitable process can be used.

[0050] Additionally, in some embodiments, the first hard mask 203 can be removed once the bit line 301 is formed (if it has not been removed during the patterning of the bit line 301). In some embodiments, the first hard mask 203 can be removed using a wet etching process or a dry etching process, a combination of these, etc. However, any suitable method can be used.

[0051] In an embodiment, bit lines 301 may be formed with a second thickness T2 between about 80 nm and about 180 nm, and may be spaced apart from each other by a second gap S2 between about 40 nm and about 80 nm. Furthermore, bit lines 301 may be formed with a second width W2 between about 40 nm and about 80 nm. However, any suitable size may be used.

[0052] Finally, by using word lines in different layers, the first spacing P1 between the first vias 109 can be greater than the second spacing P2 between the bit lines 301. In a particular embodiment, the first spacing P1 can be approximately twice the second spacing P, such as the first spacing P1 being between about 160 nm and about 320 nm, while the second spacing P2 can be between about 80 nm and about 160 nm. However, any suitable size can be used.

[0053] Figures 4A-4B The deposition of RRAM material 401 above bit line 301 is shown in these figures. Figure 4A Show Figure 4B Top view, Figure 4B Show Figure 4A A cross-sectional view along line B-B'. In an embodiment, the RRAM material 401 can be formed as a conformal thin oxide film. According to some embodiments, the RRAM material 401 can be formed using one or more layers of an acceptable dielectric material suitable for storing digital values, such as hafnium oxide (HfO2), zirconium hafnium oxide (HfO2), etc. (1-x) Zr x O2), zirconium oxide (ZrO2), titanium oxide (TiO2), nickel oxide (NiO), tantalum oxide (TaO) x Materials such as copper oxide (Cu2O), niobium pentoxide (Nb2O5), and aluminum oxide (Al2O3), or combinations thereof, can be used. RRAM material 401 can be formed using acceptable deposition processes such as ALD, CVD, and PVD. However, any suitable method or material can be used.

[0054] Figures 5A-5B The patterning of RRAM material 401 is shown to form discontinuous RRAM spacers 501 on the opposite side of bit line 301. In these figures, Figure 5A Show Figure 5B Top view along line A-A' Figure 5B Show Figure 5A A cross-sectional view along line B-B'. In an embodiment, the RRAM material 401 can be patterned using an anisotropic etching process, which removes the horizontal portion of the RRAM material 401 while leaving the vertical portion to form the RRAM spacer 501. The RRAM spacer 501 can be formed with a third thickness T3 between about 100 nm and about 180 nm, and a first length L1 between about 3 nm and about 10 nm. However, any suitable method and thickness can be used to form the RRAM spacer 501.

[0055] Figures 6A-6B The formation of the selector 601 adjacent to the RRAM spacer 501 is shown. In these figures, Figure 6A Show Figure 6B Top view, Figure 6B Show Figure 6A A cross-sectional view along line B-B'. In an embodiment, selector 601 may be formed of a bidirectional threshold switch (OTS) layer and may be formed of a chalcogenide material comprising at least chalcogenide anions (e.g., selenium (Se), tellurium (Te), etc.) and positively charged elements (e.g., germanium (Ge), silicon (Si), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), zinc (Zn), nitrogen (N), boron (B), carbon (C), etc.). Acceptable chalcogenide materials include, but are not limited to, GeSb₂Te₅ (GST). The material used for selector 601 is conformally deposited and may be deposited using PVD, CVD, ALD, etc. However, any suitable material and any suitable deposition method may be used.

[0056] Once the material of selector 601 is deposited, the material of selector 601 can be patterned using one or more anisotropic etching processes (if desired, along with any suitable photolithographic masking and etching processes) that remove the horizontal portion of the material of selector 601 along the second dielectric layer 107 while leaving discontinuous vertical portions of the material of selector 601 to form selector 601, and also leaving the horizontal portion of the material of selector 601 along the top surface of bit line 301 and RRAM spacer 501. However, any suitable method can be used to form selector 601.

[0057] In an embodiment, selector 601 may be formed with a fourth thickness T4 between about 100 nm and about 180 nm. Additionally, selector 601 may be formed with a second length L2 adjacent to RRAM spacer 501 between about 5 nm and about 30 nm, and a third length L3 extending above bit line 301 between about 50 nm and about 120 nm. However, any suitable dimensions may be used.

[0058] Figures 7A-7B The deposition of the function word line material 701 around the selector 601 is shown in these figures. Figure 7A Show Figure 7B Top view, Figure 7B Show Figure 7A A cross-sectional view along line B-B'. In an embodiment, the functional word line material 701 can be used with the first word line 103 (as described above). Figure 1A-Figure 1B (Described) Similar materials and similar methods are used for deposition. For example, the material for the first word line 103 could be tungsten deposited using a chemical vapor deposition process. However, any method and / or material can be used.

[0059] Once the functional word line material 701 is deposited, it can be planarized together with the selector 601. In this embodiment, the functional word line material 701 can be planarized using a chemical mechanical polishing process. However, any other suitable process, such as a grinding process or even a series of etching processes, can also be used.

[0060] Figures 8A-8B As shown, once the functional word line material 701 is deposited to fill the area between the bit lines 301, the functional word line material 701 can be patterned into functional word lines 801 between the bit lines 301. In these figures, Figure 8A Show Figure 8B Top view, Figure 8B Show Figure 8A A cross-sectional view along line B-B'. In this embodiment, the functional word line material 701 can be patterned using photolithography masking and etching processes. However, any suitable method can be used.

[0061] In an embodiment, the function word line 801 may be configured to have a first width W greater than that of the first word line 103. l A wider third width W3. In an embodiment, the third width W3 may be between approximately 40 nm and approximately 80 nm. Additionally, a first portion of the function word line 801 may extend between a first distance D1 of approximately 40 nm and approximately 80 nm between different portions of the selector 601, while a second portion may extend beyond the first word line 103 to a second distance D2 of approximately 5 nm and approximately 10 nm. However, any suitable size may be used.

[0062] Additionally, once the function word lines 801 are separated from each other, only some of the function word lines 801 are electrically connected to the first word line 103 below the function word lines 801. For example, in Figure 8B In the illustrated embodiment, two of the three function word lines 801 are in physical contact with the first through-hole 109 that electrically connects the function word lines 801 to the first word line 103. The remaining function word lines 801 (located in...) Figure 8B The two bit lines 301 shown are not electrically connected to the first word line 103 (or any other word line) during manufacturing. Therefore, as further described below, the function word line 801 located between the two bit lines 301 can be individually connected.

[0063] Finally, once the function word line 801 is patterned and formed, the combination of selector 601 and RRAM spacer 501 forms multiple memory cells on the opposite side of bit line 301 (in Figures 8A-8B (This is indicated by the dashed circle marked 800). Additionally, at this stage of the manufacturing process, only one of the memory cells 800 adjacent to any single bit line 301 is controlled by the first word line 103.

[0064] Figures 9A-9B As shown, once the functional word lines 801 are patterned, a third dielectric layer 901 can be deposited to separate and isolate the functional word lines 801 from each other. In these figures, Figure 9A Show Figure 9B Top view, Figure 9B Show Figure 9A A cross-sectional view along line B-B'. In the embodiment, the view described above can be used. Figure 1A-Figure 1B The third dielectric layer 901 is deposited using materials and methods similar to those used for the first dielectric layer 105. However, any materials and methods can be used to form the third dielectric layer 901.

[0065] Once the material of the third dielectric layer 901 has been deposited, the material of the third dielectric layer 901 can be planarized together with the bit line 301. In this embodiment, a chemical mechanical polishing process can be used to planarize the third dielectric layer 901. However, any other suitable process, such as a grinding process or even a series of etching processes, can also be used.

[0066] Figures 10A-10B As shown, once the third dielectric layer 901 is planarized, the fourth dielectric layer 1001 can be deposited over the bit line 301. In these figures, Figure 10A Show Figure 10B Top view along line A-A' Figure 10B Show Figure 10A A cross-sectional view along line B-B'. In the embodiment, the view described above can be used. Figure 1A-Figure 1BThe fourth dielectric layer 1001 is fabricated using materials and methods similar to those used for the first dielectric layer 105 described. However, any suitable methods and materials can be used.

[0067] Figures 10A-10B The patterning of the fourth dielectric layer 1001 is also shown to form the second opening 1003 in order to initiate the formation of the second via 1103. Figures 10A-10B Not shown in the text, but below regarding Figures 11A-11B (Shown and described). In an embodiment, the fourth dielectric layer 1001 may be patterned using, for example, photolithography masking and etching processes. However, any suitable method may be used.

[0068] Figures 11A-11B The diagram shows word line material 1101 being deposited into the second opening 1003 and over the fourth dielectric layer 1001 to form a second via 1103 (shown as separated from the rest of the word line material 1101, but physical separation may or may not be present) and the formation of the second word line 1201 (not shown in the diagram) begins. Figures 11A-11B As shown in the text, but below regarding Figures 12A-12B (Further illustrations and descriptions). In these figures, Figure 11A Show Figure 11B Top view, Figure 11B Show Figure 11A A cross-sectional view along line B-B'. In this embodiment, the word line material 1101 can be deposited using methods and materials similar to those used for the first word line 103, as described above. Figure 1A-Figure 1B As described above. For example, the word line material 1101 can be deposited as tungsten using a chemical vapor deposition process. However, any suitable method and material can be used.

[0069] Once the character line material 1101 has been deposited, it can be planarized to prepare it for further processing. In one embodiment, the character line material 1101 can be planarized using a chemical mechanical polishing process. However, any other suitable process, such as a grinding process or even a series of etching processes, can also be used.

[0070] Additionally, although in Figures 11A-11B While not explicitly shown, multiple second vias 1103 are simultaneously fabricated such that each functional word line 801 is electrically connected to a separate word line that is different from adjacent functional word lines. In such an embodiment, the second vias 1103 may also be separated from each other by a first spacing P1. However, any suitable spacing can be used.

[0071] Figures 12A-12B As shown, once the character line material 1101 is planarized, it can be patterned to form a plurality of second character lines 1201. In these figures, Figure 12A Show Figure 12BTop view, Figure 12B Show Figure 12A A cross-sectional view along line B-B'. In this embodiment, the letter line material 1101 can be patterned using photolithography masking and etching processes. However, any suitable method can be used.

[0072] In an embodiment, the second word line 1201 may be formed with a fourth width W4 that is wider than the third width W3 of the functional word line 801. In an embodiment, the fourth width W4 may be between about 40 nm and about 80 nm. Additionally, the second word lines 1201 may be spaced apart from each other by a third spacing S3 between about 40 nm and about 80 nm. However, any suitable size may be used.

[0073] Once formed, the second word line 1201 is electrically connected to different portions of the functional word line 801, which are not otherwise connected (e.g., not connected to the first word line 103), thus controlling memory cells 800 located on the opposite side of bit line 301, other than those controlled by the first word line 103. Specifically, the second word line 1201 is physically connected to a second via 1103, which electrically connects the second word line 1201 to those portions of the functional word line 801 located between bit lines 301. Thus, each functional word line 801 is connected to either the first word line 103 or the second word line 1201, with the different word lines located on different sides of the functional word line 801.

[0074] Figures 13A-13B The deposition of a fifth dielectric layer 1301 is shown to separate and isolate the second word lines 1201 from each other, completing one embodiment of the double-sided word line structure 1300. In these figures, Figure 13A Show Figure 13B Top view, Figure 13B Show Figure 3A A cross-sectional view along line B-B'. In the embodiment, the view described above can be used. Figure 1A-Figure 1B The fifth dielectric layer 1301 is deposited using materials and methods similar to those used for the first dielectric layer 105 described. However, any suitable deposition method and material can be used.

[0075] Once the material for the fifth dielectric layer 1301 has been deposited, the fifth dielectric layer 1301 can be planarized to prepare it for further processing. In this embodiment, a chemical mechanical polishing process can be used to planarize the fifth dielectric layer 1301. However, any other suitable process, such as a grinding process or even a series of etching processes, can also be used.

[0076] Figure 13CAn enlarged top view is shown, which helps to illustrate the overall cell layout of memory cell 800 and its associated word lines, where other structures have been removed from the figure for clarity. As shown, bit line 301 has memory cells 800 on both sides, with memory cells 800 on one side electrically connected to a first word line 103 via a first via 109, and memory cells 800 on the other side of bit line 301 electrically connected to a second word line 1202 via a second via 1103.

[0077] Figure 14 As shown, once the fifth dielectric layer 1301 is deposited and planarized, a second metallization layer 1401 can be formed over the second word line 1201 to electrically connect the second word line 1201 to other functional circuits. In an embodiment, the second metallization layer 1401 can be connected to the first metallization layer 102 (as described above). Figure 1A-Figure 1B The second metallization layer 1401 may be formed in a similar manner and with similar materials. In a particular embodiment, the second metallization layer 1401 may include a dielectric layer 1407 having a second metallized via 1403 and a fifth metal line 1405 connected to the second metallized via 1403. However, any suitable or desired number of dielectric layers, metallized vias, and metal lines may be used.

[0078] By manufacturing the embodiments described above, individual word lines (e.g., first word line 103 and second word line 1201) are formed as two separate layers above and below the functional word line 801. Therefore, a word line (e.g., first word line 103) can control a memory cell 800 located on one side of bit line 301 via a bottom via, and a second word line (e.g., second word line 1201) can control a memory cell 800 located on the second side of bit line 301 via a top via. Thus, by placing individual word lines in different layers, the number of cells can be doubled in an area of ​​the same size without area loss or the need for dummy cells.

[0079] Figure 15 Another embodiment is shown in which a dual-sided word line structure 1300 is incorporated within the metallization layer of a larger semiconductor device 1500. In this embodiment, the semiconductor device 1500 has a memory region 1501 and a logic region 1503 located above a substrate 101. Within the memory region 1501, the dual-sided word line structure 1300 is fabricated between a first metallization layer 102 and a second metallization layer 1401 (e.g., between a fourth metal line 111 and a fifth metal line 1405). In this embodiment, the dual-sided word line structure 1300 can be as described above regarding… Figures 1A-14 Manufactured as described.

[0080] However, within logic region 1503, semiconductor device 1500 includes active devices and other logic devices. Thus, memory structures such as the dual-sided word line structure 1300 are not present within logic region 1503. Consequently, those regions within logic region 1503 that are at the same level as the dual-sided word line structure 1300 are filled with one or more dielectric materials, including dielectric layer 110, second dielectric layer 107, fourth dielectric layer 1001, dielectric layer 1407, and other dielectric materials. For clarity, these different dielectric layers are not shown separately as individual layers within logic region 1503, but rather as a single general-purpose layer.

[0081] Figure 15 Additionally, a third metallized via 1505 is shown formed through one or more dielectric materials to connect the fourth metal line 111 and the fifth metal line 1405 within the logic region 1503. In embodiments, the third metallized via 1505 may be manufactured using similar materials and methods to the second metallized via 1403 described above. In more specific embodiments, the third metallized via 1505 may be manufactured simultaneously with the second metallized via 1403; however, in other embodiments, the third metallized via 1505 may be manufactured before or after the second metallized via 1403. In such embodiments, suitable photolithography masking and etching techniques may be used, employing one or more anisotropic etching processes, to form the third metallized via 1505 to create an opening through the dielectric material to the fourth metal line 111. Once the opening is formed, it may be filled and / or overfilled with one or more conductive materials and then planarized. However, any suitable method may be used.

[0082] By incorporating the dual-sided word line structure 1300 into the metallization layer, a more robust device can be obtained. Specifically, by integrating the dual-sided word line structure 1300 into the memory region 1501 of the semiconductor device 1500, and by using multiple vertically overlapping word lines, wiring flexibility is increased, allowing different word lines to be connected to different logic metal layers.

[0083] Figures 16A-16B Another embodiment in which a double-sided character line structure 1300 can be manufactured is shown. In these figures, Figure 16A Show Figure 16B Top view, Figure 16B Show Figure 16A A cross-sectional view along line B-B'. In this embodiment, a first hard mask 203 is used to pattern the bit line 301 (instead of removing it after the bit line 301 is patterned, as described above). Figures 3A-3B (as described above), but rather remains in place during subsequent processing. Thus, as... Figures 16A-16B As can be seen, the first hard mask 203 maintains coverage of the top surface of bit line 301.

[0084] In this embodiment, after forming bit line 301, the first hard mask 203 can be formed with a fifth thickness T5 between about 5 nm and about 30 nm. Furthermore, bit line 103 can be formed with a second width W2. However, any suitable size can be used.

[0085] Figures 17A-17B As shown, the manufacturing process can continue as described above while the first hard mask 203 is still in place above the bit line 301. Figure 17A Show Figure 17B Top view, Figure 17B Show Figure 17A A cross-sectional view along line B-B'. In a particular embodiment, as described above... Figures 5A-5B The deposited and patterned RRAM spacer 501, as described above regarding Figures 6A-6B The deposition and patterning selector 601, and as described above regarding Figures 8A-8B The deposition and patterning of the function word line 801. However, in these embodiments, each of the RRAM spacer 501, selector 601, and function word line 801 may have a sixth thickness T6 equal to the combined thickness of bit line 301 and first hard mask 203, such as between about 110 nm and about 200 nm. However, any suitable size may be used.

[0086] Figures 18A-18B Further illustrating the continuation of the manufacturing process, wherein the first hard mask 203 remains in place above bit line 301, wherein Figure 18A Show Figure 18B Top view, Figure 18B Show Figure 18A A cross-sectional view along line B-B'. In a particular embodiment, as described above... Figures 10A-10B The deposition and patterning of the fourth dielectric layer 1001, as described above... Figures 11A-11B The manufacturing of the second through hole 1103, and as described above regarding Figures 12A-12B The second character line 1201 is formed. If necessary, after forming the second character line 1201, it can be done as described above. Figure 14 The formation of the second metallization layer 1401 ( Figures 18A-18B (Not shown in the image). Of course, any other suitable method or procedure may be used.

[0087] As these figures show, as the first hard mask 203 is in place during subsequent manufacturing processes, the fourth dielectric layer 1001 is deposited directly on and in physical contact with the first hard mask 203. Thus, the first hard mask 203 helps to widen the yield window and helps prevent leakage during subsequent manufacturing processes (such as the fabrication of the second via 1103). Even after the first hard mask 203 has been used to fabricate the bit line 301, it remains in place to further electrically isolate the bit line 301. Each of these contributes to increasing the overall yield of the manufacturing process by reducing defects and helps improve the operation of the structure being manufactured.

[0088] Figures 19-21 This demonstrates the use of an "L"-shaped RRAM structure (instead of the above regarding...). Figures 1A-18B Another embodiment of the described "strip" structure. In this embodiment, the initial steps of the manufacturing process are similar to those described above. Figures 1A-4B The process is described. Specifically, a first word line 103 is manufactured, a bit line 301 is manufactured above the first word line 103, and RRAM material 401 is deposited above the bit line 301.

[0089] However, in this embodiment, the RRAM material 401 is not patterned as described above. Figures 5A-5B The aforementioned stripe. Conversely, as... Figure 19 As shown, and without patterned RRAM material 401, selector material 1901 is deposited on top of RRAM material 401. In this embodiment, selector material 1901 is as described above regarding... Figures 6A-6B Deposition as described above, such as by conformal deposition over RRAM material 401. However, any suitable method and material can be used.

[0090] Figure 20 As shown, once selector material 1901 is deposited over unpatterned RRAM material 401, both selector material 1901 and RRAM material 401 can be patterned together. In an embodiment, one or more anisotropic etching methods (e.g., reactive ion etching) can be used to pattern selector material 1901 and RRAM material 401 to remove horizontal portions of selector material 1901 and RRAM material 401, thereby forming RRAM spacer 501 and selector 601.

[0091] However, by waiting for the patterned RRAM material 401 to be deposited until after the selector material 1901 is deposited, a portion of the selector material 1901 is in place to protect the horizontal portion of the RRAM material 401 adjacent to the bit line 301. Therefore, while the selector material 1901 has a “strip” shape separated from the second dielectric layer 107 by the RRAM spacer 501, the RRAM spacer 501 will present an “L” shape, with a portion of the RRAM spacer 501 extending along the second dielectric layer 107.

[0092] Once formed, selector 601 can have a seventh length L7 between about 5 nm and about 30 nm. Additionally, because selector 601 protects the lower portion of RRAM material 401, RRAM spacer 501 will extend along the second dielectric layer 107 by a distance equal to the seventh length L7. However, any suitable size can be used.

[0093] Figure 21 As shown, once the RRAM spacer 501 (with an "L" shaped structure) and the selector 601 are formed, it can be used as described above. Figures 7A-14 Further processing is performed as described above. For example, in some embodiments, a functional word line 801 is fabricated, a fourth dielectric layer 1001 is deposited, and a second word line 1201 is formed. However, any suitable method and structure can be used.

[0094] Figure 22 Another embodiment using an RRAM spacer 501 with an "L"-shaped structure is shown. However, in this embodiment, the first hard mask 203 remains in the appropriate position above the bit line 301. Specifically, as described above regarding... Figures 16A-16B The manufacturing bit line 301 and the first hard mask 203 are thus positioned above the bit line 301.

[0095] Once bit line 301 is formed, RRAM material 401 is deposited over both bit line 301 and the first hard mask 203. Similarly, selector material 1901 is deposited over RRAM material 401 without intermediate patterning of RRAM material 401. After depositing RRAM material 401 and selector material 1901, RRAM material 401 and selector material 1901 are patterned together, as described above. Figure 20 As described above, the RRAM spacer 501 has an "L" shape, and the structure also retains the presence of the first hard mask 203.

[0096] By manufacturing the embodiments described above (e.g., by using separate word lines on opposite sides of the memory cells), the physical limitations of word lines can be removed and the number of cells in a given area can be doubled. Specifically, by manufacturing the first word line 103 and the second word line 1201 as two separate layers above and below the functional word line 801, the limitations typically imposed on adjacent word lines can be removed. Thus, a word line (e.g., the first word line 103) can be connected to one side of the control unit through a bottom through-hole, and a second word line (e.g., the second word line 1201) can be connected to the second side of the control unit through a top through-hole.

[0097] According to an embodiment, a method of manufacturing a semiconductor device includes: forming a first word line over a substrate; forming a bit line over the first word line; forming a first memory cell and a second memory cell on the opposite side of the bit line after forming the first word line; depositing a second word line adjacent to the first memory cell and electrically connected to the first word line; depositing a third functional word line adjacent to the second memory cell; and forming a fourth word line electrically connected to the third functional word line after depositing the third functional word line. In an embodiment, forming the first memory cell further includes: depositing RRAM material; patterning the RRAM material; depositing a selector material after patterning the RRAM material; and patterning the selector material. In an embodiment, forming the first memory cell further includes: depositing RRAM material; depositing a selector material before patterning the RRAM material; patterning the selector material; and patterning the RRAM material. In an embodiment, forming a bit line includes: depositing a bit line material; depositing and patterning a hard mask; patterning the bit line material to form a bit line; and removing the hard mask. In one embodiment, forming a bit line includes: depositing a bit line material; depositing and patterning a hard mask; and patterning the bit line material to form a bit line, wherein forming a first memory cell is performed with the hard mask in place. In one embodiment, the first memory cell is formed within a memory region adjacent to a logic region. In one embodiment, a first word line is formed above a substrate and above a first metallization layer.

[0098] In another embodiment, a method of manufacturing a semiconductor device includes: forming a bottom word line over a substrate; forming a first word line above the bottom word line; forming an RRAM material adjacent to the first word line; forming a selector material adjacent to the RRAM material; forming a first word line on a first side of the first word line, the first word line being electrically connected to the bottom word line; forming a second word line on a second side of the first word line opposite to the first side; and forming a top word line above the second word line and electrically connected to the second word line. In an embodiment, the method further includes patterning the RRAM material into a strip. In an embodiment, the method further includes patterning the RRAM material into an "L" shape. In an embodiment, the method further includes patterning the selector material into a strip. In an embodiment, forming the first word line includes: depositing a first material; depositing and patterning a hard mask; using the hard mask as a mask to pattern the first material; and removing the hard mask. In an embodiment, forming the first word line includes: depositing a first material; depositing and patterning a hard mask; and using the hard mask as a mask to pattern the first material, wherein forming the RRAM material forms an RRAM material adjacent to the hard mask. In one embodiment, the method further includes patterning the RRAM material into an "L" shape.

[0099] In another embodiment, a semiconductor device includes: a bit line disposed on a dielectric layer; a first memory cell disposed on a first sidewall of the bit line; a second memory cell disposed on a second sidewall of the bit line opposite to the first sidewall; a first word line disposed on the dielectric layer, wherein the first memory cell is disposed between the first sidewall of the bit line and the sidewall of the first word line; a second word line disposed on the dielectric layer, wherein the second memory cell is disposed between the second sidewall of the bit line and the sidewall of the second word line; a top word line disposed above the bit line and electrically connected to the first word line; and a bottom word line disposed below the bit line and electrically connected to the second word line. In an embodiment, the first memory cell includes strip-shaped RRAM material. In an embodiment, the first memory cell includes "L"-shaped RRAM material. In an embodiment, the semiconductor device further includes a first hard mask physically contacting the bit line, wherein the first hard mask and the bit line have aligned sidewalls. In an embodiment, the first memory cell includes "L"-shaped RRAM material. In an embodiment, the first memory cell is located within a memory region adjacent to a logic region.

[0100] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: The first letter line is formed above the substrate; A bit line is formed above the first character line; After the first word line is formed, a first memory cell is formed on a first side of the bit line, and a second memory cell is formed on a second side of the bit line opposite to the first side. Deposit a second word line that is adjacent to the first memory cell and electrically connected to the first word line; Deposit a third functional word line adjacent to the second memory cell; as well as After the third functional word line is deposited, a fourth word line is formed that is electrically connected to the third functional word line, wherein the first word line and the fourth word line are located below and above the third functional word line, respectively.

2. The method of claim 1, wherein, The formation of the first memory cell further includes: Deposited resistive random access memory materials; Patterning the resistive random access memory material; After patterning the resistive random access memory material, a selector material is deposited; and Pattern the selector material.

3. The method of claim 1, wherein, The formation of the first memory cell further includes: Deposited resistive random access memory materials; Prior to patterning the resistive random access memory material, selector material is deposited; Patterning the selector material; and Patterning the resistive random access memory material.

4. The method of claim 1, wherein, Forming the bit line includes: Depositional potential line materials; Deposit and pattern hard masks; Patterning the bitline material to form the bitline; and Remove the hard mask.

5. The method of claim 1, wherein, Forming the bit line includes: Depositional potential line materials; Depositing and patterning hard masks; and The bitline material is patterned to form the bitline, wherein the formation of the first memory cell is performed with the hard mask in place.

6. The method of claim 1, wherein, The first memory cell is formed in a memory region adjacent to the logical region.

7. The method of claim 1, wherein, The step of forming the first word line over the substrate is to form the first word line over the first metallization layer.

8. A method for manufacturing a semiconductor device, the method comprising: The bottom lettering is formed above the substrate; A first line is formed above the bottom letter line; Forming a resistive random access memory material adjacent to the first bit line; Form a selector material adjacent to the resistive random access memory material; A first character line is formed on the first side of the first character line, and the first character line is electrically connected to the bottom character line. A second letter line is formed on the second side of the first letter line opposite to the first side; as well as A top word line is formed above the second word line and is electrically connected to the second word line.

9. The method of claim 8, further comprising patterning the resistive random access memory material into stripes.

10. The method of claim 8, further comprising patterning the resistive random access memory material into an "L" shape.

11. The method of claim 10, further comprising patterning the selector material into stripes.

12. The method according to claim 8, wherein, Forming the first bit line includes: Deposition of primary materials; Deposit and pattern hard masks; The first material is patterned using the hard mask as a mask; and Remove the hard mask.

13. The method according to claim 8, wherein, Forming the first bit line includes: Deposition of primary materials; Depositing and patterning hard masks; and The first material is patterned using the hard mask as a mask, wherein the step of forming the resistive random access memory material forms a resistive random access memory material adjacent to the hard mask.

14. The method of claim 13, further comprising patterning the resistive random access memory material into an "L" shape.

15. A semiconductor device, comprising: Bit lines are set on the dielectric layer; A first memory cell is disposed on the first sidewall of the bit line; The second memory cell is disposed on the second sidewall of the bit line, which is opposite to the first sidewall. A first word line is disposed on the dielectric layer, wherein the first memory cell is disposed between the first sidewall of the bit line and the sidewall of the first word line; The second word line is disposed on the dielectric layer, wherein the second memory cell is disposed between the second sidewall of the bit line and the sidewall of the second word line; A top word line is positioned above the bit line and electrically connected to the first word line; The bottom word line is positioned below the bit line and electrically connected to the second word line; and A first hard mask is in physical contact with the bit line, wherein the first hard mask and the bit line have aligned sidewalls.

16. The semiconductor device according to claim 15, wherein, The first memory cell includes bar resistive random access memory material.

17. The semiconductor device according to claim 15, wherein, The first memory unit includes "L"-shaped resistive random access memory material.

18. The semiconductor device according to claim 15, wherein, The first memory cell includes selector material, which is strip-shaped.

19. The semiconductor device according to claim 15, wherein, The first memory unit includes "L"-shaped resistive random access memory material.

20. The semiconductor device according to claim 15, wherein, The first memory cell is located within a memory region adjacent to the logical region.

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