Semiconductor device and method for manufacturing the same

Abstract

The present application relates to the technical field of electronic devices, and more specifically to a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a substrate; a P-type semiconductor layer located on the substrate; a buffer layer located on and in contact with the P-type semiconductor layer; a channel layer located on the buffer layer; a barrier layer located on the channel layer; and a source, a gate, and a drain. The P-type semiconductor layer is connected to the source. The semiconductor device can effectively suppress current collapse and maintain stable performance.

Description

Technical Field

[0001] The present application relates to the technical field of electronic devices, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Semiconductor devices are electronic devices with electrical conductivity between that of good conductors and insulators, utilizing the unique electrical properties of semiconductor materials to perform specific functions. Semiconductor devices can generate, control, receive, transform, amplify signals, and convert energy. Therefore, they are widely used in various fields. For example, in wireless communications, semiconductor devices can be used as power amplifiers (PAs). In wireless charging, semiconductor devices can also serve as power devices in power adapters.

[0003] Gallium nitride (GaN) devices, as third-generation semiconductor devices, boast wide bandgap and high efficiency. In applications such as high-speed miniaturization, GaN devices offer unparalleled advantages over traditional silicon-based power devices. With the advancement of wireless communication technologies and the Internet of Things (IoT), as well as the demand for energy conservation and emission reduction in power supply systems, the widespread use of GaN devices in power conversion and other fields is urgently needed.

[0004] The performance of GaN devices is affected by current collapse. Current collapse, also known as current collapse, is a dynamic conductivity degradation phenomenon, that is, under AC or pulsed operating conditions, the output performance of the device suddenly drops sharply due to the influence of defect states (trapped), and the performance can slowly recover over time. Figure 1 ,The current collapse is manifested as an increase in on-resistance, a decrease in device transconductance, and a decrease in output current, which in turn leads to a decrease in device performance.

[0005] Therefore, suppressing the current collapse of GaN devices helps to improve the performance of GaN devices. Summary of the Invention

[0006] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, which can effectively suppress current collapse and maintain stable performance.

[0007] In a first aspect, a semiconductor device is provided, comprising: a substrate; a P-type semiconductor layer located on the substrate; a buffer layer located on the P-type semiconductor layer and in contact with the P-type semiconductor layer; a channel layer located on the buffer layer; a barrier layer located on the channel layer; and a source, a gate, and a drain; wherein the P-type semiconductor layer and the source are connected.

[0008] In this semiconductor device, a P-type semiconductor is connected to the source electrode, maintaining the same potential as the source electrode or a very small difference. Furthermore, a buffer layer is located above the P-type semiconductor layer. When defect states in the buffer layer capture and bind electrons, the buffer layer has a relatively high negative potential. This creates a high potential difference between the buffer layer and the P-type semiconductor layer. Under the action of the electric field, holes in the P-type semiconductor layer can be injected into the buffer layer and neutralize the negative charge in the buffer layer, releasing the electrons captured by the defect states in the buffer layer. This brings the potential of the buffer layer close to 0V, suppressing the current collapse caused by the defect states in the buffer layer.

[0009] In this semiconductor device, the buffer layer is directly located on the P-type semiconductor layer, providing a large contact surface with the P-type semiconductor layer. Furthermore, the buffer layer can be formed by a single epitaxial growth process on the P-type semiconductor layer. The interface between the buffer layer and the P-type semiconductor layer has high lattice quality, significantly reducing the contact resistance between the P-type semiconductor layer and the buffer layer, thereby increasing the hole current injected into the P-type semiconductor layer.

[0010] Furthermore, the P-type semiconductor layer is located directly below the buffer layer, significantly reducing the distance that holes injected into the buffer layer from the P-type semiconductor layer must drift toward the negative charge accumulation region. This allows for a rapid and effective reduction in the negative potential within the buffer layer, effectively suppressing current collapse caused by defect states in the buffer layer. In particular, the defect states beneath the gate and drain are relatively close to the P-type semiconductor layer. Holes injected into the buffer layer by the P-type semiconductor layer can neutralize the negative charge bound to these defect states, effectively suppressing current collapse caused by defect states in the buffer layer.

[0011] In a possible implementation, the semiconductor device further includes: a P-type ohmic contact electrode in contact with the P-type semiconductor layer, wherein the P-type semiconductor layer is connected to the source electrode through the P-type ohmic contact electrode.

[0012] In this embodiment, the P-type semiconductor layer is connected to the source through a P-type ohmic contact electrode, thereby reducing the resistance between the P-type semiconductor and the source and minimizing the potential difference between the P-type semiconductor layer and the source, so that the P-type semiconductor layer can maintain the same potential as or a very small difference from that of the source.

[0013] In a possible implementation manner, the P-type ohmic contact electrode is disposed on the P-type semiconductor layer.

[0014] In this embodiment, the P-type ohmic contact electrode is located on the P-type semiconductor layer, close to the source, so that the lead between the P-type ohmic contact electrode and the source can be shortened, further reducing the resistance between the P-type semiconductor and the source, and minimizing the potential difference between the P-type semiconductor layer and the source, so that the P-type semiconductor layer can maintain the same potential as the source or a very small difference.

[0015] In a possible implementation, the lower surface of the buffer layer is entirely in contact with the P-type semiconductor layer; wherein the lower surface is the side close to the substrate.

[0016] In this embodiment, the buffer layer is entirely located on the P-type semiconductor layer, with a larger contact surface with the P-type semiconductor layer. This allows the buffer layer to be formed on the P-type semiconductor layer through a single epitaxial growth process, improving the lattice quality of the interface between the buffer layer and the P-type semiconductor layer. This significantly reduces the contact resistance between the P-type semiconductor layer and the buffer layer, resulting in a greater hole current injected into the P-type semiconductor layer.

[0017] Furthermore, the entire buffer layer is located on the P-type semiconductor layer, significantly reducing the distance that holes injected into the buffer layer from the P-type semiconductor layer must drift toward the negative charge accumulation region. This allows for a rapid and effective reduction of the negative potential in the buffer layer, effectively suppressing current collapse caused by defect states in the buffer layer. In particular, the defect states beneath the gate and drain are relatively close to the P-type semiconductor layer. Holes injected into the buffer layer from the P-type semiconductor layer can neutralize the negative charge bound to these defect states, effectively suppressing current collapse caused by defect states in the buffer layer.

[0018] In one possible embodiment, the number of P-type impurity atoms in each cubic centimeter of the P-type semiconductor layer is 10 17 -10 19 .

[0019] In this embodiment, the doping concentration of P-type impurity atoms in the P-type semiconductor layer is 10 17 -10 19 / cm 3 , which can more effectively inject holes into the buffer layer and suppress the current collapse caused by the defect state of the buffer layer.

[0020] In a possible implementation, the buffer layer includes a plurality of first buffer layers, the P-type semiconductor layer includes a plurality of first P-type semiconductor layers, and the plurality of first buffer layers and the plurality of first P-type semiconductor layers are alternately stacked.

[0021] In this embodiment, multiple buffer layers can be provided, with a P-type semiconductor layer located between adjacent buffer layers. In other words, a P-type semiconductor layer is located between the buffer layer and the channel layer in a portion of the semiconductor device. This makes it difficult for defect states in this portion of the buffer layer to affect the two-dimensional electron gas in the channel region, thereby more effectively suppressing current collapse.

[0022] In a possible implementation, the semiconductor device further includes: a P-type ohmic contact electrode that is in contact with the plurality of first P-type semiconductor layers simultaneously, wherein the plurality of first P-type semiconductor layers are connected to the source via the P-type ohmic contact electrode.

[0023] In this embodiment, the P-type ohmic contact electrode and the multiple first P-type semiconductor layers are in contact at the same time, so that the multiple first P-type semiconductor layers can be connected to the source through the P-type ohmic contact electrode, thereby simultaneously reducing the resistance between each first P-type semiconductor and the source, and minimizing the potential difference between each first P-type semiconductor layer and the source, so that each first P-type semiconductor layer can maintain the same potential as the source or a very small difference.

[0024] In a possible implementation, a stress release layer is provided between the P-type semiconductor layer and the substrate.

[0025] In this embodiment, a P-type semiconductor layer may be epitaxially grown on the stress release layer, thereby improving the lattice quality of the P-type semiconductor layer.

[0026] In a possible implementation, the P-type semiconductor layer is P-type gallium nitride, the buffer layer is C-doped gallium nitride, and the channel layer is unintentionally doped gallium nitride.

[0027] That is, in this embodiment, the gallium nitride device can adopt the structure of the semiconductor device provided in the embodiment of the present application, thereby suppressing the current collapse of the gallium nitride device.

[0028] In a second aspect, a power conversion circuit is provided, which includes a capacitor and a semiconductor device as provided in the first aspect.

[0029] In a third aspect, a power supply system is provided, which includes a plurality of power generation units and a high-voltage power supply; wherein each power generation unit includes: a low-voltage power supply, and a power conversion circuit as provided in the second aspect.

[0030] In a possible implementation, the low-voltage power source is a photovoltaic string, and the high-voltage power source is a DC load.

[0031] In a fourth aspect, a method for preparing a semiconductor device is provided, comprising: growing a first semiconductor layer on a substrate, the first semiconductor layer comprising a P-type semiconductor layer; growing a buffer layer on the P-type semiconductor layer; growing a channel layer on the buffer layer; growing a barrier layer on the channel layer; preparing a source, a gate and a drain; and connecting the source and the P-type semiconductor layer.

[0032] In the semiconductor device fabricated by this method, a P-type semiconductor is connected to a source electrode, maintaining the same potential as the source electrode or a very small difference. Furthermore, a buffer layer is located above the P-type semiconductor layer. When defect states in the buffer layer capture and bind electrons, the buffer layer has a relatively high negative potential. This creates a high potential difference between the buffer layer and the P-type semiconductor layer. Under the influence of the electric field, holes in the P-type semiconductor layer can be injected into the buffer layer and neutralize the negative charge in the buffer layer, releasing the electrons captured by the defect states in the buffer layer. This brings the potential of the buffer layer close to 0V, suppressing the current collapse caused by the defect states in the buffer layer.

[0033] Moreover, this method is simple and easy to implement, and can be mass-produced to produce semiconductor devices that can effectively suppress current collapse and have stable performance.

[0034] In a possible implementation, the method further includes: annealing the P-type semiconductor layer; wherein the annealing includes: heating the P-type semiconductor layer to 600-900° C. and keeping the temperature for a preset time.

[0035] In this embodiment, the P-type semiconductor layer can be activated by annealing, so that the P-type semiconductor layer can more effectively inject holes into the buffer layer to suppress current collapse.

[0036] In one possible embodiment, connecting the source and the P-type semiconductor layer includes: starting from the barrier layer, etching in a direction toward the P-type semiconductor layer, and etching to the P-type semiconductor layer to expose a first area of ​​the P-type semiconductor layer; growing a P-type ohmic contact electrode on the first area; and connecting the P-type ohmic contact electrode and the source.

[0037] In the semiconductor device prepared in this embodiment, the P-type semiconductor layer is connected to the source through a P-type ohmic contact electrode, thereby reducing the resistance between the P-type semiconductor and the source, minimizing the potential difference between the P-type semiconductor layer and the source, and allowing the P-type semiconductor layer to maintain the same potential as or a very small difference from that of the source.

[0038] In the semiconductor device provided in the embodiment of the present application, the P-type semiconductor is connected to the source electrode so that the P-type semiconductor maintains the same potential as the source electrode or a very small difference therefrom; and the buffer layer is located above the P-type semiconductor layer. When the defect states in the buffer layer capture and bind electrons, the buffer layer has a relatively high negative potential. This forms a high potential difference between the buffer layer and the P-type semiconductor layer. Under the action of the electric field force, holes in the P-type semiconductor layer can be injected into the buffer layer and neutralized with the negative charge in the buffer layer, releasing the electrons captured by the defect states in the buffer layer, thereby making the potential of the buffer layer approach 0V, thereby suppressing the current collapse caused by the defect states in the buffer layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of current and resistance changes of a semiconductor device with current collapse;

[0040] Figure 2A Schematic diagram of defect state distribution;

[0041] Figure 2B Schematic diagram of defect state distribution;

[0042] Figure 3 Schematic diagram of the structure of a buffer layer of a semiconductor device;

[0043] Figure 4 It is a structural schematic diagram of a semiconductor device;

[0044] Figure 5 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0045] Figure 6 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0046] Figure 7 A schematic diagram of a semiconductor device manufacturing process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0048] Current collapse is usually caused by a defect state (trap) in the material. Specifically, when the periodic arrangement of crystal-forming atoms in the crystalline material is destroyed or the crystalline material is doped with impurities, a defect state may appear in the crystalline material.

[0049] For a typical gallium nitride device, a gallium nitride-based high electron mobility transistor (HEMT), when it is subjected to electrical stress (wherein the drain has a voltage when the HEMT is in the on or off state), defect states near the channel region can capture and bind negative charges. These negative charges lower the potential of the channel region, causing the two-dimensional electron gas (2DEG) in the channel region to be partially or completely depleted. In other words, the negative charges captured and bound by the defect states near the channel region repel electrons in the channel region, causing the two-dimensional electron gas in the channel region to be partially or completely depleted. The two-dimensional electron gas in the channel region is partially or completely depleted, causing the current output by the HEMT to decrease, triggering current collapse.

[0050] Among them, see Figure 2A , the defect states may originate from the surface of the barrier layer. For example, there may be defect states at the interface between the barrier layer and the passivation layer. Figure 2B Defect states can also originate from within the buffer layer. These defect states trap and bind negative charges, causing the two-dimensional electron gas in the channel region to be partially or completely depleted, triggering current collapse.

[0051] Among them, the current collapse caused by defect states on the surface of the barrier layer can be suppressed by technologies such as passivation field plates. However, the current collapse caused by defect states inside the buffer layer is still difficult to suppress.

[0052] In one approach, see Figure 3 , carbon (carbon, C) doped gallium nitride (C-GaN) and unintentionally doped gallium nitride (uid-GaN, u-GaN) are stacked in layers as a buffer layer to suppress the current collapse caused by defect states within the buffer layer. Specifically, electrons in the unintentionally doped gallium nitride are transferred to the carbon doped gallium nitride to compensate for the holes in the defect states in the carbon doped gallium nitride, thereby preventing the defect states from capturing negative charges. This scheme can effectively suppress current collapse under low electrical stress. However, when the device is subjected to high ground stress (for example, when in the off state, the voltage on the drain is high), this scheme is difficult to suppress current collapse.

[0053] In another scenario, see Figure 4 , the buffer layer on the source side of the HEMT is deeply etched, and then P-type gallium nitride is regrown at the etched interface. The P-type gallium nitride is connected to the source through a P-type ohmic contact. Among them, P-type gallium nitride can inject holes into the buffer layer to suppress current collapse. Among them, the crystal quality of the P-type gallium nitride regrown at the etched interface is poor, and there are a large number of defect states at the etched interface, making it difficult for P-type gallium nitride to inject holes into the buffer layer. In addition, P-type gallium nitride is located on the source side, far away from the defect state under the gate, resulting in the holes injected by P-type gallium nitride into the buffer layer being difficult to drift to the bottom of the gate, and the bottom of the gate is the position where the defect state captures electrons most seriously, so this solution is difficult to effectively suppress current collapse.

[0054] The present invention provides a semiconductor device comprising a substrate, a P-type semiconductor layer located on the substrate, a buffer layer located on and in contact with the P-type semiconductor layer, a channel layer located on the buffer layer, a barrier layer located on the channel layer, a source electrode, a gate electrode, and a drain electrode. The P-type semiconductor layer is connected to the source electrode.

[0055] In this semiconductor device, when the defect states in the buffer layer capture and bind electrons, the buffer layer has a relatively high negative potential. The P-type semiconductor layer is connected to the source electrode so that the P-type semiconductor layer maintains the same potential as the source electrode (around 0V). This forms a high potential difference between the buffer layer and the P-type semiconductor layer. Under the action of the electric field force, holes in the P-type semiconductor layer can be injected into the buffer layer and neutralized with the negative charge in the buffer layer, releasing the electrons captured by the defect states in the buffer layer, thereby making the potential of the buffer layer approach 0V, suppressing the current collapse caused by the defect states in the buffer layer.

[0056] Among them, in this device, the buffer layer is entirely or mostly located on the P-type semiconductor layer, and has a large contact surface with the P-type semiconductor layer. In addition, the buffer layer is obtained by epitaxial growth on the P-type semiconductor layer, and the lattice quality of the interface between the buffer layer and the P-type semiconductor layer is high, thereby greatly reducing the contact resistance between the P-type semiconductor layer and the buffer layer, making the hole current injected into the P-type semiconductor layer larger. In addition, the solution of the embodiment of the present application buries the P-type semiconductor layer under the buffer layer through epitaxial growth, greatly reducing the distance that the injected holes drift to the negative charge accumulation area, thereby quickly and effectively reducing the negative potential in the buffer layer, and effectively suppressing the current collapse caused by the defect state of the buffer layer.

[0057] In particular, the defect states under the gate and drain are relatively close to the P-type semiconductor layer. Holes injected from the P-type semiconductor layer into the buffer layer can neutralize the negative charges bound by these defect states, effectively suppressing the current collapse caused by the defect states in the buffer layer.

[0058] In some embodiments, the semiconductor device may specifically be a HEMT.

[0059] The semiconductor device provided in the embodiments of the present application can be applied to wireless communication devices, power adapters, and the like. For example, the semiconductor device provided in the embodiments of the present application can be used as a power amplifier for wireless communication devices, or as a power device for a power adapter. Wireless communication devices may include base stations, mobile terminals, and the like. The power adapter may be a wireless charging power adapter. It should be noted that the foregoing only provides examples of the application scope of the semiconductor device provided in the embodiments of the present application, and is not intended to limit it. The embodiments of the present application do not limit the application scope of the semiconductor device.

[0060] Next, the semiconductor device provided in the embodiments of the present application is described with reference to the accompanying drawings.

[0061] Figure 5A semiconductor device is shown. The semiconductor device includes a substrate 509, which can also be called a substrate layer, and refers to a substrate wafer used for semiconductor epitaxial growth. Epitaxy of the semiconductor is performed on the substrate 509 to grow a semiconductor layer. The substrate 509 has the function of supporting the epitaxial structure and improving the characteristics of the epitaxial structure. In one example, the substrate 509 can be made of silicon (Si). In one example, the substrate 509 can be made of sapphire. In one example, the substrate 509 can be made of silicon carbide (SiC). In one example, the substrate 509 can be made of diamond.

[0062] It can be understood that the substrate 509 is a thin sheet structure. Figure 5 In the embodiment of the present application, the direction perpendicular to the upper surface (or lower surface) of the substrate 509 may be referred to as the vertical direction, and the direction parallel to the upper surface (or lower surface) of the substrate 509 may be referred to as the horizontal direction. Hereinafter, the upper surface of the semiconductor layer refers to the side of the semiconductor layer away from the substrate 509, and the lower surface of the semiconductor layer refers to the side of the semiconductor layer close to the substrate 509.

[0063] Continue reading Figure 5 , a P-type semiconductor layer 507 is provided on the substrate 509. In some embodiments, the thickness of the P-type semiconductor layer 507 is 0.5 microns to 2 microns. In one example, the thickness of the P-type semiconductor layer 507 is 0.5 microns. In one example, the thickness of the P-type semiconductor layer 507 is 0.8 microns. In one example, the thickness of the P-type semiconductor layer 507 is 1 micron. In one example, the thickness of the P-type semiconductor layer 507 is 1.5 microns. In one example, the thickness of the P-type semiconductor layer 507 is 2 microns. The above description only illustrates the thickness of the P-type semiconductor layer 507 by way of example and is not limiting. In other embodiments, the thickness of the P-type semiconductor layer 507 may be other values, which are not listed here one by one.

[0064] In the application examples, unless otherwise specified, the thickness of the semiconductor layer refers to the distance from the upper surface of the semiconductor to the lower surface of the semiconductor.

[0065] A P-type semiconductor is a semiconductor material doped with P-type impurities. P-type impurities, also known as acceptor impurities, are impurities that can provide holes to the semiconductor material, such as magnesium and zinc. For gallium nitride-based semiconductors, magnesium is a common P-type impurity.

[0066] In some embodiments, the P-type semiconductor layer 507 may be specifically P-type gallium nitride. That is, the P-type semiconductor layer 507 is gallium nitride doped with P-type impurities. In an illustrative example, the number of P-type impurity atoms in each cubic centimeter of the P-type semiconductor layer 507 is 10 17 -10 19 In one example, the number of P-type impurity atoms in each cubic centimeter of the P-type semiconductor layer 507 is 10 17 In one example, the number of P-type impurity atoms in each cubic centimeter of the P-type semiconductor layer 507 is 10 18 In one example, the number of P-type impurity atoms in each cubic centimeter of the P-type semiconductor layer 507 is 10 19 The above description only illustrates the concentration of P-type impurity atoms in the P-type semiconductor layer 507 and is not intended to be limiting. In other embodiments, the P-type semiconductor layer 507 may be doped with other concentrations of P-type impurity atoms, which are not listed here.

[0067] In some embodiments, a stress release layer (SRL) 508 is further provided between the substrate 509 and the P-type semiconductor layer 507 to improve the crystal quality of the P-type semiconductor layer 507 and relieve the lattice stress between the substrate 509 and the P-type semiconductor layer 507 .

[0068] A buffer layer 506 is disposed on the P-type semiconductor layer 507, and the P-type semiconductor layer 507 and the buffer layer 506 are in contact. That is, the upper surface of the P-type semiconductor layer 507 is in contact with the lower surface of the buffer layer 506. The entirety or a majority of the buffer layer 506 is located above the P-type semiconductor layer 507 and in contact with the upper surface of the P-type semiconductor layer 507.

[0069] In some embodiments, as Figure 5 As shown, the entire buffer layer 506 is located above the P-type semiconductor layer 507 and contacts the upper surface of the P-type semiconductor layer 507 . That is, the entire lower surface of the buffer layer 506 contacts the P-type semiconductor layer 507 .

[0070] The buffer layer 506 can achieve stress release and dislocation filtering, and can improve the crystal quality of the semiconductor layer located on the buffer layer 506 .

[0071] In some embodiments, the buffer layer 506 may be carbon-doped gallium nitride. That is, the buffer layer 506 may be gallium nitride doped with carbon. In some embodiments, the buffer layer 506 may be gallium nitride doped with iron.

[0072] Continue reading Figure 5, a channel layer 505 is provided on the buffer layer 506, and a barrier layer 504 is provided on the channel layer 505. The barrier layer 504 and the channel layer 505 can be collectively referred to as an epitaxial structure, which is a key semiconductor layer of the semiconductor device, and plays the role of turning on and off the source and drain. Specifically, the barrier layer 504 and the channel layer 505 can be polarized spontaneously, or polarized under the action of an electric field, thereby generating a two-dimensional electron gas on the side of the channel layer close to the barrier layer 504. Among them, the two-dimensional electron gas can also be called channel electrons, which can move in the horizontal direction in the channel layer 505, thereby turning on the source and drain. In addition, the area where the two-dimensional electron gas is located can be called a channel or a channel region.

[0073] The barrier layer 504 and the channel layer 505 are respectively made of semiconductor materials with different bandgap widths, wherein the bandgap width of the barrier layer 504 is greater than the bandgap width of the channel layer 505, so that when polarization occurs between the channel layer 505 and the barrier layer 504, a two-dimensional electron gas can be generated on the side of the channel layer 505 close to the barrier layer 504.

[0074] In some embodiments, the channel layer 505 can be made of gallium nitride. In one example, the channel layer 505 can be made of unintentionally doped gallium nitride.

[0075] In some embodiments, the barrier layer 504 may be made of aluminum gallium nitride (AlGaN), or made of aluminum indium nitride (InAlN), or made of aluminum indium gallium nitride (InAlGaN), or made of aluminum nitride (AlN), or made of scandium aluminum nitride (ScAlN), or made of scandium aluminum gallium nitride (ScAlGaN).

[0076] Continue reading Figure 5 The semiconductor device further includes a source 501, a gate 502, and a drain 503. The gate 502 can control the on / off state of the source 501 and the drain 503. Specifically, the gate 502 can control the channel layer 505 to generate a two-dimensional electron gas for conducting the source 501 and the drain 503. When the source 501 and the drain 503 have appropriate voltages, the source 501 and the drain 503 can be conducted.

[0077] In one example, when a positive voltage is applied to the gate 502, a low voltage is applied to the drain 503, and the source voltage is 0, the source 501 and the drain 503 are conductive, and the semiconductor device is in the on state. When a negative voltage is applied to the gate 502, a high voltage is applied to the drain 503, and the source voltage is 0, the source 501 and the drain 503 are disconnected, and the semiconductor device is in the off state.

[0078] In some embodiments, as Figure 5As shown, the source 501 , the gate 502 and the drain 503 may be disposed on the barrier layer 504 .

[0079] In some embodiments, the gate 502 may be disposed above the barrier layer 504. A portion of the source 501 and / or drain 503 may be sunken into the barrier layer 504, i.e., in the vertical direction, the distance between the source 501 and / or drain 503 and the channel layer 505 is less than the height of the barrier layer 504. As a result, the source 501 and / or drain 503 is closer to the channel region, which can reduce the on-resistance R between the source 501 and drain 503. on .

[0080] In some embodiments, the gate 502 may be disposed on the barrier layer 504. The source 501 and / or the drain 503 may pass through the barrier layer 504 and contact the channel layer 505, so that the source 501 and / or the drain 503 are closer to the channel region to reduce the on-resistance R between the source 501 and the drain 503. on .

[0081] In some embodiments, the source 501 , the gate 502 , and the drain 503 may be made of a metal material. For example, any one or more of the source 501 , the gate 502 , and the drain 503 may be made of a nickel-gold alloy (NiAu).

[0082] It can be understood that there is an ohmic contact resistance between the metal electrode and the semiconductor material. Ohmic contact resistance refers to the resistance encountered by electrons when flowing from metal to semiconductor, or from semiconductor to metal. Specifically, there is a high potential barrier between the semiconductor and the metal. When the semiconductor doping concentration is very high, electrons can tunnel through the potential barrier, thereby forming an ohmic contact with lower resistance. This lower resistance is the ohmic contact resistance. The ohmic contact resistance is an important component of the resistance between the source and drain of a semiconductor device, and it has an important impact on the performance of the semiconductor device. For the convenience of description, the source 501 and the drain 503 can also be collectively referred to as ohmic contact electrodes.

[0083] In some embodiments, to reduce the ohmic contact resistance between the ohmic contact electrode and the semiconductor material, the ohmic contact electrode may include a metal electrode layer and a contact layer. The contact layer is used to contact the semiconductor material. That is, in the semiconductor device, the contact layer and the semiconductor material form a contact interface. In other words, in the ohmic contact electrode, the metal electrode layer is located on the side away from the substrate 509, and the contact layer is located on the side close to the substrate 509.

[0084] Exemplarily, the contact layer may include a catalytic layer, a barrier layer and a cap layer connected in sequence. The catalytic layer is in contact with the metal electrode layer, the cap layer is located on the side of the contact layer close to the substrate 509, and the barrier layer is located between the catalytic layer and the cap layer. Exemplarily, the catalytic layer may be made of aluminum, which can reduce the ohmic contact resistance between the ohmic contact electrode and the semiconductor material. The barrier layer can improve the adhesion between the ohmic contact electrode and the semiconductor material and reduce the possibility of the ohmic contact electrode detaching from the semiconductor material. Exemplarily, the barrier layer may be made of titanium (Ti), or nickel (Ni), or molybdenum (Mo). The cap layer can avoid or reduce external corrosion of the ohmic contact electrode. Exemplarily, the cap layer may be made of titanium nitride (TiN), or titanium tungsten (TiW), or tungsten, or tantalum nitride (TaN).

[0085] Continue reading Figure 5 , the source electrode 501 is connected to the P-type semiconductor layer 507, so that the P-type semiconductor layer has the potential of the source electrode 501. That is, the potential of the P-type semiconductor layer is approximately 0V. In this way, when the defect states in the buffer layer 506 capture negative charges and have a negative potential, the P-type semiconductor can inject holes into the buffer layer 506. These holes can neutralize the negative charges captured by the defect states, thereby restoring the buffer layer 506 to an electrical equilibrium state, even if the potential of the buffer layer 506 is 0 or close to 0V. This reduces the repulsive effect of the buffer layer 506 on the two-dimensional resistor in the channel layer 505, effectively suppressing the current collapse of the semiconductor device.

[0086] In some embodiments, as Figure 5 As shown, in the horizontal direction, the gate 502 is located between the source 501 and the drain 503. The length of the contact surface between the buffer layer 506 and the P-type semiconductor layer 507 in the horizontal direction can be set to A1. The length A1 is greater than or equal to the distance between the source 501 and the drain 503 in the horizontal direction. As a result, the gate 502, the drain 503, the channel region under the source 501, and the buffer region are all close to the P-type semiconductor layer 507. The holes injected by the P-type semiconductor layer 507 can be neutralized with the negative charges captured by the defect states in the buffer region as quickly as possible, reducing the repulsive effect of the negative charges captured by the defect states in the buffer region on the electrons in the channel region, and effectively suppressing current collapse.

[0087] In some embodiments, as Figure 5As shown, an electrode 511 is further provided on the P-type semiconductor layer 507. Specifically, the area of ​​the upper surface of the P-type semiconductor layer 507 is larger than the area of ​​the contact surface between the P-type semiconductor layer 507 and the buffer layer 505. The electrode 511 is provided on the region of the upper surface of the P-type semiconductor layer 507 that is not in contact with the buffer layer 505. The electrode 511 can be connected to the source 501, thereby connecting the P-type semiconductor layer 507 to the source 501 via the electrode 511. In one example, the electrode 511 can be connected to the source 501 via a thin layer of metal.

[0088] In one example of these embodiments, the electrode 511 may be a metal electrode, wherein the metal electrode may be made of any one or more of Ni, Pt, and Pd.

[0089] In one example of these embodiments, electrode 511 may be a P-type ohmic contact resistor to reduce the ohmic contact resistance between source electrode 501 and P-type semiconductor layer 507. In one example, the P-type ohmic contact resistor may include a metal electrode layer and a contact layer. The contact layer is used to form a contact interface with P-type semiconductor layer 507. That is, the contact layer and P-type semiconductor layer 507 form a contact interface. In other words, in the P-type ohmic contact electrode, the metal electrode layer is located on the side away from substrate 509, and the contact layer is located on the side closer to substrate 509. In one example, the contact layer may include a catalyst layer, a barrier layer, and a cap layer that are sequentially connected. The catalyst layer contacts the metal electrode layer, the cap layer is located on the side of the contact layer closer to substrate 509, and the barrier layer is located between the catalyst layer and the cap layer. For example, the catalyst layer may be made of aluminum to reduce the ohmic contact resistance between the ohmic contact electrode and the semiconductor material. The barrier layer can improve the adhesion between the ohmic contact electrode and the semiconductor material, reducing the possibility of the ohmic contact electrode detaching from the semiconductor material. Exemplarily, the barrier layer can be made of titanium (Ti), nickel (Ni), or molybdenum (Mo). The cap layer can prevent or reduce external corrosion of the ohmic contact electrode. Exemplarily, the cap layer can be made of titanium nitride (TiN), titanium tungsten (TiW), tungsten, or tantalum nitride (TaN).

[0090] In some embodiments, continue to refer to Figure 5 The semiconductor device may further include a passivation layer 510. The passivation layer 510 covers the surface of the barrier layer 504 and is used to protect the epitaxial structure and shield the epitaxial structure from external influences. Exemplarily, the passivation layer 510 may be made of silicon nitride (SiN) or aluminum oxide (Al2O3).

[0091] In the semiconductor device provided in the embodiment of the present application, the buffer layer is in contact with the P-type semiconductor layer in its entirety or for the most part. Thus, the holes injected into the buffer layer by the P-type semiconductor layer are evenly distributed in the buffer layer, which can effectively neutralize the negative charges captured by the defect states of the buffer layer, thereby effectively suppressing current collapse.

[0092] Figure 6 Another semiconductor device is shown. The semiconductor device includes a substrate 509, a plurality of P-type semiconductor layers 507 and a plurality of buffer layers 506, a channel layer 505 disposed on the plurality of buffer layers 506, and a barrier layer 504 disposed on the channel layer 505, as well as a source 501, a gate 502, and a drain 503. Figure 6 As shown, multiple buffer layers 506 and multiple P-type semiconductor layers 507 are stacked alternately. That is, one P-type semiconductor layer 507 is provided with a buffer layer 506, which is then provided with another P-type semiconductor layer, which is then provided with another buffer layer 506, and so on. The buffer layer 506 is located below the bottom surface of the channel layer 505 and directly below the channel layer 505.

[0093] exist Figure 6 In the illustrated embodiment, multiple buffer layers can be provided, with a P-type semiconductor layer located between adjacent buffer layers. In other words, a P-type semiconductor layer is located between a portion of the buffer layer and the channel layer 505. This makes it difficult for defect states in this portion of the buffer layer to affect the two-dimensional electron gas in the channel region, thereby more effectively suppressing current collapse.

[0094] The specific implementation of the substrate 509 , the P-type semiconductor layer 507 , the buffer layer 506 , the channel layer 505 , the barrier layer 504 , the source 501 , the gate 502 , and the drain 503 can be referred to the above description and will not be repeated here.

[0095] Illustratively, a stress release layer 508 is provided between the substrate 509 and the plurality of P-type semiconductor layers 507 . For details, please refer to the above description and will not be repeated here.

[0096] Continue reading Figure 6 , multiple P-type semiconductor layers are connected to the source 501. For example, an electrode 511 may be provided, and the electrode 511 may contact each P-type semiconductor layer. The electrode 511 is connected to the source 501, so that each P-type semiconductor layer can be connected to the source 501 through the electrode 511. Exemplarily, the electrode 511 may be a P-type ohmic contact electrode. In one example, a metal electrode layer and a contact layer. The metal electrode layer is connected to each P-type semiconductor layer through the contact layer. The contact layer can be referred to the above description and will not be repeated here.

[0097] In this semiconductor device, when the defect states in the buffer layer capture and bind electrons, the buffer layer has a relatively high negative potential. The P-type semiconductor layer is connected to the source electrode and has the potential of the source electrode (around 0V), which has a large potential difference with the buffer layer. Under the action of the electric field force, holes in the P-type semiconductor layer can be injected into the buffer layer and neutralize the negative charges in the buffer layer, causing the potential of the buffer layer to approach 0, thereby suppressing the current collapse caused by the defect states in the buffer layer.

[0098] The above examples illustrate the structure of the semiconductor device provided by the embodiments of the present application. Next, an example is given to illustrate a method for manufacturing the semiconductor device.

[0099] See Figure 7 , a P-type semiconductor layer 507, a buffer layer 506, a channel layer 505, and a barrier layer 504 can be sequentially grown or deposited on a substrate 509. For example, a stress relief layer 508 can be first grown on the substrate 509, and then the P-type semiconductor layer 507, a buffer layer 506, a channel layer 505, and a barrier layer 504 can be sequentially grown on the stress relief layer 508.

[0100] In an illustrative example, chemical vapor deposition (CVD) may be used to grow the semiconductor layers.

[0101] A source electrode 501, a gate electrode 502, and a drain electrode 503 may be prepared. Then, the source electrode 501 and the P-type semiconductor layer 507 are connected.

[0102] In some embodiments, an electrode 511 may be grown, and the electrode 511 and the P-type semiconductor layer 507 are connected to the source 501. Thus, the P-type semiconductor layer 507 may be connected to the source 501 through the electrode 511. For example, the electrode 511 may be a P-type ohmic contact electrode.

[0103] The source electrode is connected to the P-type semiconductor layer.

[0104] In some embodiments, see Figure 7 After growing the P-type semiconductor layer 507, buffer layer 506, channel layer 505, and barrier layer 504, etching is performed starting from the barrier layer 504 and proceeding downward toward the P-type semiconductor layer 507. This etching process continues until the P-type semiconductor layer 507 is reached, exposing region B1 of the P-type semiconductor layer and forming a mesa structure. Electrode 511 is then grown on region B1. Afterwards, source 501, gate 502, and drain 503 are fabricated. The source 501 and electrode 511 are then connected.

[0105] In some embodiments, the etching may be performed using an inductively coupled plasma (ICP) etching technique.

[0106] In some embodiments, after etching to the P-type semiconductor layer 507 and exposing the region B1 of the P-type semiconductor layer, the P-type semiconductor layer 507 can be annealed to activate the P-type semiconductor layer 507. Specifically, in a nitrogen or inert gas atmosphere, the P-type semiconductor layer 507 is heated to 600-900°C and kept warm for a preset time T1. Exemplarily, the preset time T1 is 5-15 minutes. In one example, the preset time T1 is 5 minutes. In one example, the preset time T1 is 10 minutes. In one example, the preset time T1 is 15 minutes.

[0107] In some embodiments, after the source electrode 501 and the drain electrode 503 are formed, a passivation layer 510 can be grown on the barrier layer 504. In one example, the passivation layer material can be deposited onto the barrier layer 504 by plasma-enhanced chemical vapor deposition (PECVD) to form the passivation layer 510. The passivation layer 510 can then be etched to form a gate electrode region, and the gate electrode material can be deposited in the gate electrode region to form the gate electrode 502.

[0108] Combined with the above Figure 7 , the example introduces Figure 5 The preparation process of the semiconductor device shown in Figure 2 is as follows. Figure 7 The preparation method shown can also be used to prepare Figure 6 The difference is that in the preparation Figure 6 When forming the semiconductor device shown, multiple P-type semiconductor layers 507 and multiple buffer layers 506 need to be grown. The multiple P-type semiconductor layers 507 and the multiple buffer layers 506 are grown alternately. That is, a P-type semiconductor layer 507 is grown, followed by a buffer layer 506, followed by another P-type semiconductor layer 507, followed by another buffer layer 506, and so on. The channel layer 505 is then grown on the last buffer layer 506.

[0109] Etching can be performed starting from the barrier layer 504 and in a direction toward the P-type semiconductor layer 507, i.e., downward, until the bottommost P-type semiconductor layer 507 is etched to expose the area A1. The bottommost P-type semiconductor layer 507 refers to the P-type semiconductor layer 507 closest to the substrate 509 among the multiple P-type semiconductor layers 507.

[0110] An electrode 511 is grown on region A1, and the grown electrode 511 is in contact with the sidewalls of the other P-type semiconductor layers 507. The other P-type semiconductor layers 507 refer to the P-type semiconductor layers 507 other than the bottommost P-type semiconductor layer 507. The sidewalls of the P-type semiconductor layer 507 herein refer to the regions exposed by etching.

[0111] The P-type semiconductor layer in the semiconductor device provided in the embodiment of the present application is prepared by a single growth process, which can reduce the complexity of the preparation process of the semiconductor device and avoid the production capacity limitation of secondary growth. In addition, the crystal quality of the P-type semiconductor grown in the single growth process is good and the hole concentration is high, so that sufficient holes can be injected into the buffer layer. In addition, the interface quality between the P-type semiconductor layer grown in the single growth process and the buffer layer is good, which can ensure the effective injection of holes.

[0112] The above examples introduce the structure and preparation method of the semiconductor device provided in the embodiments of the present application. Next, the possible application scenarios of the semiconductor device provided in the embodiments of the present application are described with examples.

[0113] This semiconductor device can be used as a microelectronic switching component and can be combined with other microelectronic devices such as capacitors to be used in power conversion circuits, such as inverter circuits, rectifier circuits, freewheeling circuits, etc. Therefore, the embodiments of the present application can provide a power conversion circuit including a capacitor and the semiconductor device described above.

[0114] In some embodiments, the power circuit may specifically be an inverter circuit. An inverter circuit is a circuit that converts direct current into alternating current, and includes multiple bridge arms. The semiconductor device provided in the embodiment of the present application may serve as or participate in constituting a switching element on a bridge arm. By controlling the on and off of the switching elements on different bridge arms of the semiconductor device, direct current can be converted into alternating current. The inverter circuit can be applied to scenarios where the power supply is a direct current power supply and the current required by the load is alternating current. For example, when the battery in an electric vehicle powers an AC motor, it needs to pass through an inverter circuit for current conversion. For another example, before a solar cell is incorporated into an AC power grid, it needs to pass through an inverter circuit for current conversion.

[0115] In some embodiments, the power circuit may specifically be a rectifier circuit. A rectifier circuit is a circuit that converts alternating current (AC) into direct current (DC), and typically includes a main circuit and a filter. The semiconductor device provided in the embodiments of the present application may participate in forming the main circuit. The filter is connected between the main circuit and the load to filter out the AC component in the pulsating DC voltage. The rectifier circuit may be applied to scenarios where AC needs to be converted into DC. For example, when an electric vehicle charges its battery, it may use a charging device including a rectifier circuit to convert AC into the DC required by the electric vehicle.

[0116] It should be noted that the above examples illustrate possible application scenarios of the semiconductor device provided by the embodiments of the present application, and are not exhaustive. The semiconductor device provided by the embodiments of the present application can also be applied to other scenarios, which will not be listed here one by one.

[0117] An embodiment of the present application also provides a power supply system, which may include multiple power generation units and a high-voltage power supply; wherein each power generation unit includes: a low-voltage power supply, and the power conversion circuit described above.

[0118] In some embodiments, the low-voltage power source is a photovoltaic string, which generally has a voltage range of tens of volts, and the high-voltage power source is a DC load, which generally has a voltage of thousands of volts.

[0119] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0120] It is understood that in the description of the embodiments of the present application, words such as "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of the present application should not be interpreted as being more preferred or advantageous over other embodiments or designs. Specifically, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0121] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "plurality" means two or more. For example, "multiple systems" refers to two or more systems, and "multiple terminals" refers to two or more terminals.

[0122] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly identifying the technical features being referred to. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. The terms "include," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0123] It can be understood that the above embodiments are only used to illustrate the technical solutions of the present application and do not limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0124] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a gallium nitride layer doped with magnesium or zinc and located on the substrate; a gallium nitride layer doped with carbon or iron located on the gallium nitride layer doped with magnesium or zinc and in contact with the gallium nitride layer doped with magnesium or zinc; a channel layer located on the carbon- or iron-doped gallium nitride layer; a barrier layer located above the channel layer; and a source electrode, a gate electrode and a drain electrode; wherein the gallium nitride layer doped with magnesium or zinc is connected to the source electrode; The carbon- or iron-doped gallium nitride layer includes a plurality of first carbon- or iron-doped gallium nitride layers, the magnesium- or zinc-doped gallium nitride layer includes a plurality of first magnesium- or zinc-doped gallium nitride layers, the plurality of first carbon- or iron-doped gallium nitride layers and the plurality of first magnesium- or zinc-doped gallium nitride layers are stacked alternately, and the plurality of first magnesium- or zinc-doped gallium nitride layers are all connected to the source.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes: A P-type ohmic contact electrode is in contact with the gallium nitride layer doped with magnesium or zinc, wherein the gallium nitride layer doped with magnesium or zinc is connected to the source electrode through the P-type ohmic contact electrode.

3. The semiconductor device according to claim 2, wherein The P-type ohmic contact electrode is arranged on the gallium nitride layer doped with magnesium or zinc.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The lower surface of the gallium nitride layer doped with carbon or iron is in full contact with the gallium nitride layer doped with magnesium or zinc; wherein the lower surface is a side close to the substrate.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The number of P-type impurity atoms in the gallium nitride layer doped with magnesium or zinc per cubic centimeter is 10 17 -10 19 . The semiconductor device according to claim 1 , wherein: The semiconductor device further includes: A P-type ohmic contact electrode is in contact with the plurality of first gallium nitride layers doped with magnesium or zinc, wherein the plurality of first gallium nitride layers doped with magnesium or zinc are connected to the source electrode through the P-type ohmic contact electrode.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that: A stress release layer is provided between the gallium nitride layer doped with magnesium or zinc and the substrate.

8. The semiconductor device according to any one of claims 1 to 3, wherein: The gallium nitride layer doped with magnesium or zinc is P-type gallium nitride, and the channel layer is unintentionally doped gallium nitride.

9. A power conversion circuit, characterized in that: The circuit comprises a capacitor and a semiconductor device according to any one of claims 1 to 8.

10. A power supply system, characterized in that: The system includes a plurality of power generation units and a high voltage power supply; wherein each power generation unit includes: a low voltage power supply, and the power conversion circuit as claimed in claim 9.

11. The system according to claim 10, wherein: The low-voltage power supply is a photovoltaic string, and the high-voltage power supply is a DC load.

12. A method for preparing a semiconductor device, characterized in that: include: growing a first semiconductor layer on a substrate, wherein the first semiconductor layer comprises a gallium nitride layer doped with magnesium or zinc; growing a gallium nitride layer doped with carbon or iron on the gallium nitride layer doped with magnesium or zinc; growing a channel layer on the gallium nitride layer doped with carbon or iron; growing a barrier layer on the channel layer; Prepare source, gate and drain electrodes; connecting the source electrode and the gallium nitride layer doped with magnesium or zinc; The carbon- or iron-doped gallium nitride layer includes a plurality of first carbon- or iron-doped gallium nitride layers, the magnesium- or zinc-doped gallium nitride layer includes a plurality of first magnesium- or zinc-doped gallium nitride layers, the plurality of first carbon- or iron-doped gallium nitride layers and the plurality of first magnesium- or zinc-doped gallium nitride layers are stacked alternately, and the plurality of first magnesium- or zinc-doped gallium nitride layers are all connected to the source.

13. The method according to claim 12, characterized in that The method further includes: annealing the gallium nitride layer doped with magnesium or zinc; wherein the annealing includes: heating the gallium nitride layer doped with magnesium or zinc to 600-900° C. and keeping the temperature for a preset time.

14. The method according to claim 12 or 13, characterized in that The gallium nitride layer connecting the source electrode and the gallium nitride layer doped with magnesium or zinc includes: Starting from the barrier layer, etching is performed in a direction toward the gallium nitride layer doped with magnesium or zinc, and etching to the gallium nitride layer doped with magnesium or zinc to expose a first region of the gallium nitride layer doped with magnesium or zinc; growing a P-type ohmic contact electrode on the first region; The P-type ohmic contact electrode and the source are connected.

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