High-voltage transistor components and their fabrication methods

Abstract

This invention discloses a high-voltage transistor device and its fabrication method. The high-voltage transistor device includes: a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region, and a drain region. The semiconductor substrate has multiple trenches extending downward from the substrate surface to form a serrated cross-sectional profile. The isolation structure is located outside the multiple trenches and extends downward from the surface into the semiconductor substrate to define a high-voltage region. The gate dielectric layer is located above the high-voltage region and partially fills the multiple trenches. The gate is located above the gate dielectric layer. The source and drain regions are located within the semiconductor substrate and are isolated from each other.

Description

Technical Field

[0001] This invention relates to the structure of a semiconductor device and its manufacturing method, and more particularly to a high-voltage transistor device and its manufacturing method. Background Technology

[0002] Negative-bias temperature instability (NBTI) is a significant factor affecting the reliability of metal-oxide-semiconductor (MOSFETs), such as high-voltage transistors. When high-voltage transistors operate at high temperatures or high current densities, these conditions can cause the Si-H bonds at the gate-dielectric interface to break, leading to dangling bonds and fixed charges in the oxide layer. This causes a shift in the critical voltage of the high-voltage transistor, resulting in failure and impacting its lifespan. Generally, the adverse effects on P-type metal-oxide-semiconductor (MOS) high-voltage transistors are far greater than those on NMOS high-voltage transistors.

[0003] It is known that increasing the thickness of the gate dielectric layer can reduce the impact of negative bias temperature instability. However, the thickness of the gate dielectric layer is inversely proportional to the drive current (Ion) of the high-voltage transistor device, and increasing the thickness of the gate dielectric layer may affect the drive current efficiency of the high-voltage transistor device. How to reduce the negative bias temperature instability of high-voltage transistor devices while taking into account the drive current efficiency of the device has become one of the important issues in this field.

[0004] Therefore, there is a need to provide an advanced high-voltage transistor device and its fabrication method to solve the problems faced by the existing technology. Summary of the Invention

[0005] One embodiment of the present invention discloses a high-voltage transistor device, comprising: a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region, and a drain region. The semiconductor substrate has multiple trenches extending downward from the substrate surface to form a serrated cross-sectional profile. The isolation structure is located outside the multiple trenches and extends downward from the surface into the semiconductor substrate to define a high-voltage region. The gate dielectric layer is located above the high-voltage region and partially fills the multiple trenches. The gate is located above the gate dielectric layer. The source and drain regions are located within the semiconductor substrate and are isolated from each other.

[0006] Another embodiment of the present invention discloses a method for fabricating a high-voltage transistor device. This method includes the following steps: First, a semiconductor substrate is provided; and the semiconductor substrate is etched using a first patterned mask to form multiple trenches extending downward from the substrate surface, giving it a serrated cross-sectional profile. Next, an isolation structure is formed outside the multiple trenches, extending downward from the substrate surface into the semiconductor substrate, to define a high-voltage region. Then, the high-voltage region is etched using a second patterned mask. A gate dielectric layer is then formed above the high-voltage region, partially filling the multiple trenches; a gate electrode is formed above the gate dielectric layer. Source regions are formed in the semiconductor substrate and are isolated from each other.

[0007] According to the above embodiments, the present invention provides a high-voltage transistor device and a method for fabricating the same. Before defining the channel-doped well region of the high-voltage transistor as an isolation structure, a photomask etching process for fabricating other elements (logic elements) is used to etch a semiconductor substrate used as a part of the high-voltage transistor channel with a first patterned photoresist, giving it multiple trenches substantially parallel to the channel length direction (perpendicular to the channel width direction). After forming the channel-doped well region of the high-voltage transistor, another etching process is performed with a second patterned photoresist to remove a portion of the channel-doped well region, giving the interface between the channel-doped well region and the gate dielectric layer a serrated structure substantially parallel to the channel width direction.

[0008] Therefore, without reducing the thickness of the gate dielectric layer, the channel width of the high-voltage transistor can be increased, thereby reducing (or not inducing) the temperature instability of the negative bias voltage of the device and improving the driving current efficiency of the high-voltage transistor. Attached Figure Description

[0009] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:

[0010] Figure 1A A top view schematic diagram illustrating a portion of the semiconductor substrate structure after multiple trenches have been formed in the semiconductor substrate, as shown in an embodiment of the present invention;

[0011] Figure 1B For along Figure 1A A schematic cross-sectional view of the semiconductor substrate structure shown by the tangent S11;

[0012] Figure 1C For along Figure 1A A schematic diagram of a partial structural cross-section drawn with tangent S12;

[0013] Figure 2A This is a top view of a portion of the structure after an isolation structure has been formed in the high-voltage region of a semiconductor substrate.

[0014] Figure 2B For along Figure 2A A schematic diagram of a partial structural cross-section drawn with tangent S21;

[0015] Figure 2C For along Figure 2A A schematic diagram of a partial structural cross-section drawn with tangent S22;

[0016] Figure 3A This is a top view of a portion of the structure after the high-voltage region has been etched using a second photolithography etching process.

[0017] Figure 3B For along Figure 3A A schematic diagram of a partial structural cross-section drawn with tangent S31;

[0018] Figure 3C For along Figure 3A A partial structural cross-section diagram drawn with tangent S32;

[0019] Figure 4A This is a top view schematic diagram illustrating a partial structure of a high-voltage transistor element according to an embodiment of the present invention;

[0020] Figure 4B For along Figure 4A A partial structural cross-sectional diagram drawn with tangent S41; and

[0021] Figure 4C For along Figure 4A A partial structural cross-section diagram drawn with tangent S42.

[0022] Symbol Explanation

[0023] 100: High-voltage transistor components

[0024] 101: Semiconductor substrate

[0025] 101a: Substrate surface

[0026] 101L: Logic Area

[0027] 101H: High-voltage zone

[0028] 102: First photolithography etching process

[0029] 102R: First Patterned Mask

[0030] 102O: Open

[0031] 103: Groove

[0032] 103': Groove

[0033] 104: Isolation Structure

[0034] 105: Doped well region

[0035] 106a: High-voltage field doped region

[0036] 106b: High-voltage field doped region

[0037] 107: Second photolithography etching process

[0038] 107R: Second Patterned Mask

[0039] 108: Concave Chamber

[0040] 109: Gate Dielectric Layer

[0041] 110: Gate

[0042] 111: Interstitial wall

[0043] C: Passage Area

[0044] D1: Channel length direction

[0045] D2: Channel width direction

[0046] h: distance

[0047] P: Serrated profile

[0048] Pt: Top of the serrated profile

[0049] P': Serrated profile

[0050] Pt': Top of the serrated profile

[0051] S11: Tangent

[0052] S12: Tangent

[0053] S21: Tangent

[0054] S22: Tangent

[0055] S31: Tangent

[0056] S32: Tangent

[0057] S41: Tangent

[0058] S42: Tangent Detailed Implementation

[0059] This invention provides a high-voltage transistor device and its manufacturing method, which can reduce the temperature instability of the high-voltage transistor device under negative bias and improve the drive current efficiency of the device. To make the above embodiments and other objects, features, and advantages of this invention more apparent and understandable, several embodiments are described below in conjunction with the accompanying drawings.

[0060] However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The proposed preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the patent application. Those skilled in the art will be able to make equivalent modifications and variations based on the description in the following specification without departing from the spirit and scope of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0061] A method for fabricating a high-voltage transistor element 100 includes the following steps: First, a semiconductor substrate 101 is provided; and a first photolithography etching process 102 is performed to etch the semiconductor substrate 101 with a first patterning mask 102R to form multiple grooves 103 extending downward from the substrate surface 101a, thereby giving it a serrated cross-sectional profile P.

[0062] Please refer to Figures 1A to 1C , Figure 1A This is a top view schematic diagram of a portion of the semiconductor substrate 101 after multiple grooves 103 have been formed in the semiconductor substrate 101 according to an embodiment of the present invention. Figure 1B It is along Figure 1A A schematic cross-sectional view of the semiconductor substrate 101 structure shown by the tangent S11. Figure 1C It is along Figure 1A A schematic diagram of a partial structural cross-section drawn with tangent S12.

[0063] In this embodiment, the semiconductor substrate 101 may include a logic region 101L and a high-voltage region 101H. The first patterned mask 102R may be a patterned photoresist layer, simultaneously covering both the logic region 101L and the high-voltage region 101H of the semiconductor substrate 101, and has multiple photoresist patterns (e.g., openings 102O) located in different regions of the semiconductor substrate 101, exposing at least a portion of the semiconductor substrate 101 located in the logic region 101L and the high-voltage region 101H. Therefore, in addition to forming multiple trenches 103 in the high-voltage region 101H, the first photolithography etching process 102 can also form other etching patterns (not shown) in other regions of the semiconductor substrate 101 (e.g., the logic region 101L).

[0064] Subsequently, a series of intermediate fabrication processes are performed to form other component structures in other areas of the semiconductor substrate 101, such as (but not limited to) forming multiple logic elements (not shown) in the logic region 101L. Then, an isolation structure 104 is formed on the outside of the multiple grooves 103 in the high voltage region 101H, extending downward from the substrate surface 101a into the semiconductor substrate 101 to define the range of the high voltage region 101H.

[0065] Please refer to Figures 2A to 2C , Figure 2A This is a top view schematic diagram showing part of the structure after the isolation structure 104 is formed in the high voltage region 101H of the semiconductor substrate 101. Figure 2B It is along Figure 2A A partial structural cross-section diagram drawn with tangent S21. Figure 2C It is along Figure 2A The diagram shows a partial structural cross-section as illustrated by tangent S22. In this embodiment, the isolation structure 104 can be a shallow trench isolation structure (STI). Furthermore, the isolation structure 104 surrounds the periphery of multiple grooves 103.

[0066] In some embodiments of the present invention, an ion implantation process can be performed on the high-voltage region 101H before forming the isolation structure 104 to form a doped well region 105 (denoted as DNW) with a first electrical dopant (e.g., n-type dopant) in the high-voltage region 101H, extending downward from the substrate surface 101a of the high-voltage region 101H into the semiconductor substrate 101. After forming the isolation structure 104, another ion implantation process can be performed on the high-voltage region 101H to form two isolated high-voltage field (HV field) doped regions 106a and 106b with a second electrical dopant (e.g., p-type dopant) at both ends of the plurality of trenches 103. In some embodiments of the present invention, the high-voltage field doped regions 106a and 106b may partially overlap with both ends of the plurality of trenches 103.

[0067] Then, a second photolithographic etching process 107 is performed on the high-voltage region 101H using a second patterned mask 107R to remove a portion of the doped well region 105 and form a recess 108 in the high-voltage region 101. Please refer to... Figures 3A to 3C , Figure 3A This is a top view of part of the structure after the high-pressure region 101H is etched using the second photolithography etching process 107. Figure 3B It is along Figure 3A A partial structural cross-section diagram drawn with tangent S31. Figure 3C It is along Figure 3A A partial structural cross-section diagram drawn with tangent S32.

[0068] In this embodiment, the second patterned mask 107R is a patterned photoresist layer covering the logic region 101L of the semiconductor substrate 101, exposing the serrated profile P formed by several trenches 103 in the high voltage region 101. Before the second photolithography etching process 107, the top Pt of the serrated profile P is substantially coplanar with the substrate surface 101a (see reference). Figure 2C In the second photolithography etching process 107, as a portion of the doped well region 105 located in the high-voltage region 101 is removed, the serrated profile P also shifts downward along the etching direction, forming another serrated profile P' composed of several grooves 103' (see reference). Figure 3C ).

[0069] The top Pt' of the serrated cross-sectional profile P' is substantially lower than the substrate surface 101a. There is a distance h between the top Pt' of the serrated cross-sectional profile P' and the substrate surface 101a. Each groove 103' forming the serrated cross-sectional profile P' can have a structure that is wider at the top and narrower at the bottom; and the depth-to-width ratio of the groove 103' is substantially 1:10.

[0070] Subsequently, a gate dielectric layer 109 is formed above the high-voltage region 101H, partially filling the multiple trenches 103' and recesses 108. High-voltage field doped regions 106a and 106b, located on either side of the multiple trenches 103', are also formed thereafter. Next, a gate 110 is formed above the gate dielectric layer 109. Subsequently, spacer walls 111 are formed on the sidewalls of the gate dielectric layer 109, and a series of subsequent fabrication processes are performed, such as forming a metal interconnect structure (not shown), to complete the process. Figures 4A to 4C Fabrication of the high-voltage transistor element 100 shown in the figure.

[0071] Please refer to the following: Figure 4A This is a top view schematic diagram of a high-voltage transistor element 100 according to an embodiment of the present invention. Figure 4B It is along Figure 4A A partial structural cross-section diagram drawn with tangent S41. Figure 4C It is along Figure 4A A partial structural cross-section diagram drawn with tangent S42.

[0072] In this embodiment, the high-voltage field doped regions 106a and 106b can serve as the source and drain of the high-voltage transistor element 100, respectively. The interface between the doped well region 105 with a portion of the sawtooth profile P' and the gate dielectric layer 109 can define the channel region C of the high-voltage transistor element 100. The high-voltage field doped regions 106a and 106b (source and drain) are arranged along the channel length direction D1; the sawtooth profile P' extends along the channel width direction D2; and the channel length direction D1 is perpendicular to the channel width direction D2.

[0073] Because the channel region C of the high-voltage transistor element 100 has a sawtooth cross-sectional profile P', compared to existing high-voltage transistor elements of the same size (not shown), the portion of the gate dielectric layer 109 filling the multiple trenches 103' has a larger thickness, which helps to improve the negative bias temperature instability of the high-voltage transistor element 100 and extend its service life. Furthermore, the channel region C with the sawtooth cross-sectional profile P' can substantially increase the channel width of the high-voltage transistor element 100, thereby increasing the drive current of the high-voltage transistor element 100 without increasing its critical dimensions.

[0074] According to the above embodiments, the present invention provides a high-voltage transistor element 100 and a method for fabricating the same. Before the channel-doped well region 105 of the high-voltage transistor 100 is defined by the isolation structure 104, a photomask etching process for fabricating other elements (logic elements) is used to etch a semiconductor substrate 101, which serves as a part of the high-voltage transistor channel, with a first patterned photoresist 102R, to create multiple trenches 103 substantially parallel to the channel length D1 direction (perpendicular to the channel width direction D2). After forming the channel-doped well region 105, another etching process 107 is performed with a second patterned photoresist 107R to remove a portion of the channel-doped well region 105, so that the interface between the channel-doped well region 105 and the gate dielectric layer 109 has a serrated structure P' substantially parallel to the channel width direction D2.

[0075] Therefore, without reducing the thickness of the gate dielectric layer 109, the channel width of the high-voltage transistor element 100 can be lengthened, thereby reducing (or not inducing) the negative bias temperature instability of the high-voltage transistor element and improving the driving current efficiency of the high-voltage transistor.

[0076] While the present invention has been disclosed in conjunction with the above preferred embodiments, it is not intended to limit the invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A high-voltage transistor device, characterized in that, include: The semiconductor substrate has multiple grooves that extend downward from the substrate surface to form a serrated cross-sectional profile. An isolation structure, located on the outside of the multiple grooves and extending downward from the surface into the semiconductor substrate, is used to define the high-voltage region; A gate dielectric layer, located above the high voltage region, partially fills the multiple grooves and completely overlaps with the serrated profile contour, is used to define the channel region; wherein the gate dielectric layer has a top surface that is substantially coplanar with the substrate surface, and there is a distance between the top of the serrated profile contour and the substrate surface. The gate is located above the gate dielectric layer; The source region is located within the semiconductor substrate; as well as The drain region is located within the semiconductor substrate and is isolated from the source region. The serrated profile extends along the width of the channel.

2. The high-voltage transistor device of claim 1, wherein the source region and the drain region are arranged along the channel length direction, and the channel length direction is perpendicular to the channel width direction.

3. The high-voltage transistor device of claim 2, wherein the source region and the drain region are located at opposite ends of one of the plurality of trenches.

4. The high-voltage transistor device of claim 2, wherein the plurality of grooves are parallel to the length direction of the channel and extend into the source region and / or the drain region.

5. The high-voltage transistor element of claim 1, wherein one of the plurality of trenches has a depth-to-width ratio of 1:

10.

6. The high-voltage transistor device of claim 1, wherein one of the plurality of trenches has a structure that is wider at the top and narrower at the bottom.

7. A method for fabricating a high-voltage transistor device, comprising: Provide semiconductor substrates; The semiconductor substrate is etched using a first patterned mask to form multiple grooves that extend downward from the surface of the substrate, giving it a serrated profile. An isolation structure is formed on the outside of the multiple grooves, extending downward from the surface of the substrate into the semiconductor substrate, to define the high voltage region; The high-voltage region is etched using a second patterned mask; A gate dielectric layer is formed above the high-voltage region and partially fills the multiple grooves, completely overlapping the serrated profile to define the channel region; wherein the gate dielectric layer has a top surface substantially coplanar with the substrate surface, and there is a distance between the top of the serrated profile and the substrate surface. A gate is formed above the gate dielectric layer; A source region is formed in the semiconductor substrate; and A drain region is formed in the semiconductor substrate to isolate it from the source region. The serrated profile extends along the width of the channel.

8. The method for fabricating a high-voltage transistor device as claimed in claim 7, further comprising, before etching the high-voltage region with the second patterned mask: A doped well region with a first electrical property is formed in this high-voltage region; and Two high-voltage field doped regions with second electrical properties and isolated from each other are formed in the doped well region.

9. The method of fabricating a high-voltage transistor element as claimed in claim 8, wherein the step of etching the high-voltage region with the second patterned mask removes a portion of the doped well region in the plurality of trenches, thereby creating a distance between the top of the serrated profile and the surface of the substrate.

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