Circuit arrangement and oscillator

Abstract

The present application provides a circuit device and an oscillator capable of improving linearity of a capacitance value of a variable capacitance circuit that controls an oscillation frequency. The circuit device includes a processing circuit that generates capacitance control data and an oscillation circuit. The oscillation circuit has a variable capacitance circuit whose capacitance value is variably controlled according to the capacitance control data, and an oscillation frequency of the oscillation circuit is controlled by the capacitance value of the variable capacitance circuit. The variable capacitance circuit has a capacitor array. The capacitor array has a plurality of capacitors whose capacitance values are weighted in binary, and a plurality of switches that are controlled to be turned on and off according to the capacitance control data. The processing circuit outputs the capacitance control data after dither processing in a manner to time-divisionally switch the capacitance value of the variable capacitance circuit to a first capacitance value and a second capacitance value.

Description

Technical Field

[0001] This invention relates to circuit devices and oscillators, etc. Background Technology

[0002] A temperature-compensated oscillator is known, in which a capacitor array is connected to the oscillation node of the oscillation circuit. The capacitance value of the capacitor array is controlled according to the temperature, thereby compensating for the oscillation frequency due to temperature. Patent Document 1 discloses a digital temperature-compensated oscillator that, in order to achieve precise control using a smaller number of capacitor elements, uses multiple first capacitor elements with the same capacitance value and second capacitor elements with a capacitance value of 1 / (n+1) of the capacitance value of the first capacitor elements. A capacitor array is formed by multiple first and second capacitor elements, and the digital temperature-compensated oscillator controls the capacitance value of the capacitor array according to the temperature, thereby compensating for the oscillation frequency due to temperature.

[0003] Patent Document 1: Japanese Patent Application Publication No. 5-218738

[0004] In temperature compensation using capacitor arrays, the linearity of the capacitor array's capacitance values ​​affects the accuracy of the temperature compensation. Consider using a structure that uses binary weighting for the capacitance values ​​of each capacitor. For example, suppose the capacitance value corresponding to the LSB is C, and the capacitor array has capacitors of C, 2C, 4C, and 8C. In this case, when switching between states where C+2C+4C=7C is selected and 8C is selected, or between states where C+2C=3C is selected and 4C is selected, there is a problem that the linearity of the capacitance values ​​can easily decrease due to parasitic capacitance or manufacturing deviations. Summary of the Invention

[0005] One aspect of the present invention relates to a circuit device comprising: a processing circuit that generates capacitance control data; an oscillation circuit having a variable capacitor circuit whose capacitance value is variably controlled according to the capacitance control data, the oscillation frequency of the oscillation circuit being controlled by the capacitance value of the variable capacitor circuit, the variable capacitor circuit having a capacitor array having: a plurality of capacitors, the capacitance values ​​of each of the plurality of capacitors being binary-weighted; and a plurality of switches connected in series with the plurality of capacitors between an oscillation node and a ground node of the oscillation circuit, and controlled to be turned on and off according to the capacitance control data, the processing circuit outputting the capacitance control data after jitter processing to time-division-switch the capacitance value of the variable capacitor circuit to a first capacitance value and a second capacitance value.

[0006] Furthermore, other aspects of the present invention relate to an oscillator comprising: the circuitry described above; and an oscillator that oscillates by being driven by the oscillation circuitry. Attached Figure Description

[0007] Figure 1 These are examples of the structure of circuit devices and oscillators.

[0008] Figure 2 These are detailed structural examples of oscillator circuits and variable capacitor circuits.

[0009] Figure 3 This is the first detailed structural example of a capacitor array.

[0010] Figure 4 This is a detailed structural example of a capacitor.

[0011] Figure 5 This is a detailed structural example of a capacitor.

[0012] Figure 6 This is a detailed structural example of a capacitor.

[0013] Figure 7 These are examples of the basic capacitor that constitutes a capacitor and the basic switch that constitutes a switch.

[0014] Figure 8 It is the capacitance value of the variable capacitor circuit relative to the capacitor control data, without performing jitter processing based on the jitter processing unit.

[0015] Figure 9 It is a timing diagram illustrating the operation of the processing circuit.

[0016] Figure 10 It is the capacitance value of the variable capacitor circuit relative to the capacitance control data when the jitter processing of this embodiment is applied.

[0017] Figure 11 This is the first detailed structural example of the processing circuit and memory.

[0018] Figure 12 This is the second detailed structural example of a capacitor array.

[0019] Figure 13 This is the second detailed structural example of the processing circuit and memory.

[0020] Figure 14 This is an example of the second table stored in the time-division mode storage section.

[0021] Figure 15 This is a timing diagram illustrating the operation of the processing circuit in the second detailed structural example.

[0022] Figure 16It is the capacitance value of the variable capacitor circuit relative to the capacitor control data, without performing jitter processing based on the jitter processing unit.

[0023] Figure 17 It is the capacitance value of the variable capacitor circuit relative to the capacitor control data when the jitter processing of the second detailed structural example is applied.

[0024] Label Explanation

[0025] 4: Oscillator; 10: Vibrator; 20: Circuit device; 30: Oscillator circuit; 31: Variable capacitor circuit; 32: Drive circuit; 45: Temperature sensor circuit; 60: Processing circuit; 61: Digital filter; 63: Temperature compensation unit; 64: Time-division processing unit; 65: Jitter processing unit; 70: Memory; 71: Capacitor adjustment value storage unit; 72: Time-division mode storage unit; CC1~CC11: Capacitors; CDV: Switching capacitor; CPA1, CPA2: Capacitor array; CTD: Capacitor control data; CTDV: Switching control signal; DTD: Temperature detection data; ICL: Input capacitor control data; ICL': Capacitor control data after jitter processing; LCG: First capacitor bank; SCG: Second capacitor bank; SW1~SW11: Switch; SWDV: Switch for switching; TA1~TA4, TB1: Period; TDP: Time-division mode information; UC1a~UC1d, UC2a, UC2b, UC3a~UC3d, UCa, UCb: Unit capacitors. Detailed Implementation

[0026] The preferred embodiments of the present invention will now be described in detail. Furthermore, the embodiments described below are not intended to unduly limit the scope of the claims, and the structures described in these embodiments are not necessarily all necessary structural elements.

[0027] 1. Circuit device

[0028] Figure 1 This is an example of the structure of the circuit device 20 and the oscillator 4. The oscillator 4 includes the circuit device 20 and the oscillator 10.

[0029] Circuit device 20 is an integrated circuit device called an IC (Integrated Circuit). For example, circuit device 20 is an IC manufactured using semiconductor processes, which is a semiconductor chip on a semiconductor substrate on which circuit elements are formed. Circuit device 20 includes an oscillation circuit 30, a temperature sensor circuit 45, a processing circuit 60, and a memory 70. Alternatively, the temperature sensor circuit may be located externally to circuit device 20. In this case, temperature detection data is input to circuit device 20 from an external source.

[0030] Temperature sensor circuit 45 detects temperature and outputs temperature detection data DTD representing the result. Temperature detection data DTD is data that monotonically increases or decreases relative to temperature. Temperature sensor circuit 45 may include, for example, a temperature sensor and an A / D conversion circuit. The temperature sensor, utilizing the temperature dependence of the forward voltage of the PN junction, outputs a temperature detection voltage whose voltage value changes with temperature. The A / D conversion circuit performs an A / D conversion on the temperature detection voltage, outputting the result as temperature detection data DTD. Alternatively, temperature sensor circuit 45 may include a ring oscillator and a counter. The oscillation frequency of the ring oscillator is temperature-dependent. The counter counts the output pulse signal of the ring oscillator as the oscillation signal during a counting period defined by a clock signal based on the oscillation signal of oscillation circuit 30, and outputs the count value as temperature detection data DTD.

[0031] The oscillation circuit 30 has a variable capacitor circuit 31 composed of a capacitor array and oscillates at an oscillation frequency corresponding to the capacitance value of the variable capacitor circuit 31. Temperature compensation is achieved by controlling the capacitance value of the variable capacitor circuit 31 in a manner that keeps the oscillation frequency constant relative to temperature variations. The oscillation circuit 30 causes the oscillator 10, which is electrically connected to the oscillation circuit 30, to oscillate. Specifically, the circuit device 20 includes a first terminal and a second terminal; one end of the oscillator 10 is connected to the oscillation circuit 30 via the first terminal, and the other end of the oscillator 10 is connected to the oscillation circuit 30 via the second terminal. Various types of oscillation circuits, such as Pierce type, Colpitts type, inverter type, or Hartley type, can be used as the oscillation circuit 30.

[0032] The oscillator 10 is a component that generates mechanical vibration through an electrical signal. The oscillator 10 can be implemented using a vibrating plate such as a quartz resonator. For example, the oscillator 10 is a tuning fork type quartz resonator. Alternatively, the oscillator 10 can be implemented using a quartz resonator with a cut angle of AT or SC, which performs thickness shear vibration. Furthermore, the oscillator 10 of this embodiment can be implemented using various vibrating plates other than tuning fork type or thickness shear vibration type, or piezoelectric resonators made of materials other than quartz. For example, the oscillator 10 can also be a SAW resonator or a MEMS oscillator formed using a silicon substrate as a silicon oscillator. SAW is an abbreviation for Surface Acoustic Wave, and MEMS is an abbreviation for Micro ElectroMechanical Systems.

[0033] The processing circuit 60 performs capacitance control on the variable capacitor circuit 31 based on the temperature detection data DTD. The processing circuit 60 includes a temperature compensation unit 63 and a jitter processing unit 65. The temperature compensation unit 63 performs temperature compensation processing based on the temperature detection data DTD and information stored in the memory 70, and outputs the result as temperature-compensated capacitor control data. The temperature-compensated capacitor control data is input to the jitter processing unit 65 as input capacitor control data. The jitter processing unit 65 performs jitter processing on the input capacitor control data and outputs the result as jitter-processed capacitor control data. The processing circuit 60 can output the jitter-processed capacitor control data as capacitor control data CTD, or it can further process the jitter-processed capacitor control data before outputting it as capacitor control data CTD. The capacitance value of the variable capacitor circuit 31 is set to the capacitance value indicated by the capacitor control data CTD.

[0034] The processing circuit 60 is a logic circuit composed of logic elements such as AND circuits, OR circuits, inverters, and latch circuits. The temperature compensation unit 63 and the jitter processing unit 65 can also be composed of separate logic circuits. Alternatively, the processing of the temperature compensation unit 63 and the jitter processing unit 65 can be executed by a DSP (Digital Signal Processor). In this case, the functions of these units are implemented by executing a program that describes the functions of the temperature compensation unit 63 and the jitter processing unit 65, etc., by the DSP.

[0035] The memory 70 stores information used by the processing circuit 60 when generating the capacitor control data CTD based on the temperature detection data DTD. The information stored in the memory 70 includes a lookup table that maps the temperature detection data DTD to capacitor adjustment values. The processing circuit 60 retrieves the capacitor adjustment value corresponding to the temperature detection data DTD from the lookup table, performs linear interpolation and other processing on the capacitor adjustment value, and outputs the temperature-compensated capacitor control data. The memory 70 is, for example, a non-volatile memory. In this case, the aforementioned information is written to this non-volatile memory during the manufacture of the oscillator 4, etc. The non-volatile memory can be, for example, an EEPROM (Electrically Erasable Programmable Read Only Memory), flash memory, or fuse memory. Alternatively, the memory 70 can also be RAM (Random Access Memory) or a register. In this case, the aforementioned information is written to the RAM or register from an external host device, etc.

[0036] Furthermore, the connection in this embodiment is an electrical connection. An electrical connection refers to a connection that can transmit electrical signals, enabling the transmission of information based on electrical signals. Electrical connections can be made via passive or active components.

[0037] Figure 2 This is a detailed structural example of the oscillation circuit 30 and the variable capacitor circuit 31. The oscillation circuit 30 includes the variable capacitor circuit 31 and the drive circuit 32. Here, the number of bits of the capacitor control data CTD is set to 11, but the number of bits of the capacitor control data CTD can be, for example, 3 or more.

[0038] The driving circuit 32 drives the oscillator 10 to oscillate, and outputs the resulting clock signal CLK to node NQ. Node NQ is the output node of the oscillation circuit 30. The input node N1 of the driving circuit 32 is connected to one end of the oscillator 10, and the output node N2 of the driving circuit 32 is connected to the other end of the oscillator 10.

[0039] The driver circuit 32 includes an inverter INV and resistors R1 and R2. The input node of the inverter INV and one end of resistor R1 are connected to the input node N1 of the driver circuit 32. The output node of the inverter INV and the other end of resistor R1 are connected to node NQ. One end of resistor R2 is connected to node NQ, and the other end of resistor R2 is connected to the output node N2 of the driver circuit 32.

[0040] The variable capacitor circuit 31 is connected to the input node N1 and output node N2 of the drive circuit 32. The capacitance value of the variable capacitor circuit 31 varies according to the capacitance control data CTD[10:0], thereby changing the load of the drive circuit 32 and the oscillation frequency of the oscillation circuit 30. This achieves temperature compensation of the oscillation frequency. The variable capacitor circuit 31 includes: a capacitor array CPA1, which is connected to the input node N1 of the drive circuit 32; and a capacitor array CPA2, which is connected to the output node N2 of the drive circuit 32. The capacitor arrays CPA1 and CPA2 are set to the same capacitance value according to the capacitance control data CTD[10:0]. Alternatively, only one of the capacitor arrays CPA1 and CPA2 may be set.

[0041] Additionally, the nodes connected to the capacitor array within the oscillation loop of the oscillation circuit 30 are also referred to as oscillation nodes. Figure 2 In this context, either input node N1 or output node N2 is an oscillation node.

[0042] Figure 3 This is the first detailed structural example of capacitor array CPA1. Capacitor array CPA2 has the same structure, therefore, capacitor array CPA1 will be used as an example for explanation here.

[0043] The capacitor array CPA1 includes capacitors CC1 to CC11 and switches SW1 to SW11. However, the number of capacitors and switches is not limited to this; the capacitor array CPA1 can include capacitors 1 to n and switches 1 to n. n is an integer greater than 2, for example, the number of bits in the capacitor control data CTD.

[0044] One end of capacitor CC1 is connected to input node N1 of drive circuit 32, and the other end of capacitor CC1 is connected to one end of switch SW1. The other end of switch SW1 is connected to ground node NGN. Similarly, one end of capacitors CC2 to CC11 is connected to input node N1, and the other end of capacitors CC2 to CC11 is connected to one end of switches SW2 to SW11 respectively. The other end of switches SW2 to SW11 is connected to ground node NGN.

[0045] Switches SW1 to SW11 are, for example, transistors. Switch SW1 is controlled to be turned on or off by the first bit of the capacitor control data CTD[10:0], CTD[0]. Similarly, switches SW2 to SW11 are controlled to be turned on or off by the second to eleventh bits of the capacitor control data CTD[10:0], CTD[1] to CTD

[11] , respectively.

[0046] The capacitance values ​​of capacitors CC1 to CC11 are weighted using binary weighting. That is, when s is set to an integer greater than 1 and less than 11, the capacitance value of capacitor CCs is twice the capacitance value of capacitor CC1. s-1 The following describes examples of constructing capacitors CC1 to CC11 by connecting unit capacitors in series and parallel. However, this is not a limitation; capacitor CC1 may consist of one unit capacitor, and capacitor CCs may consist of two unit capacitors. s-1 It consists of individual capacitor units.

[0047] like Figure 3 As shown, capacitors CC4 to CC11 are the first capacitor group (LCG) corresponding to the high-side bits CTD[10:3] of the capacitor control data CTD[10:0]. Capacitors CC1 to CC3 are the second capacitor group (SCG) corresponding to the low-side bits CTD[2:0] of the capacitor control data CTD[10:0]. Each capacitor in the first capacitor group (LCG) consists of multiple unit capacitors connected in parallel, and each capacitor in the second capacitor group (SCG) consists of multiple unit capacitors connected in series. Each unit capacitor is, for example, a MIM capacitor. MIM is an abbreviation for Metal Insulator Metal. Furthermore, the first capacitor group (LCG) only needs to contain one or more capacitors, and the second capacitor group (SCG) only needs to contain one or more capacitors.

[0048] Figure 4 This is a detailed structural example of capacitor CC1. Capacitor CC1 includes unit capacitors UC1a to UC1d connected in series between input node N1 and one end of switch SW1. When the capacitance value of the unit capacitor is set to 4C, the capacitance value of capacitor CC1 is 4C / 4 = C. For example, unit capacitors UC1a and UC1b are two MIM capacitors stacked in the thickness direction of the semiconductor substrate, and unit capacitors UC1c and UC1d are two MIM capacitors stacked in the thickness direction of the semiconductor substrate.

[0049] Figure 5 This is a detailed structural example of capacitor CC2. Capacitor CC2 includes unit capacitors UC2a and UC2b connected in series between input node N1 and one end of switch SW1. The capacitance value of capacitor CC2 is 4C / 2 = 2C. For example, unit capacitors UC2a and UC2b are two MIM capacitors stacked in the thickness direction of the semiconductor substrate.

[0050] Figure 6 This is a detailed structural example of capacitor CC3. Capacitor CC3 includes unit capacitors UC3a and UC3b connected in series between one end of input node N1 and switch SW1, and unit capacitors UC3c and UC3d connected in series between one end of input node N1 and switch SW1. The capacitance value of capacitor CC3 is (4C / 2)×2=4C. For example, unit capacitors UC3a and UC3b are two MIM capacitors stacked in the thickness direction of the semiconductor substrate, and unit capacitors UC3c and UC3d are two MIM capacitors stacked in the thickness direction of the semiconductor substrate.

[0051] Figure 7 This is a structural example of the basic capacitor UC constituting capacitors CC4 to CC11 and the basic switch USW constituting switches SW4 to SW11. The basic capacitor UC includes unit capacitors UCa and UCb connected in parallel between the input node N1 and one end of the basic switch USW. The other end of the basic switch USW is connected to the ground node NGN. The capacitance value of the basic capacitor UC is 4C × 2 = 8C. For example, unit capacitors UCa and UCb are two MIM capacitors stacked in the thickness direction of the semiconductor substrate. The basic switch USW is a transistor.

[0052] Will Figure 7The basic capacitor UC and basic switch USW shown together are called a basic unit. Capacitor CC4 and switch SW4 are composed of one basic unit. Capacitor CC5 and switch SW5 are composed of two basic units connected in parallel. Capacitor CC6 and switch SW6 are composed of four basic units connected in parallel. Thereafter, the number of basic units connected in parallel increases by powers of 2. Furthermore, examples of switches SW4 to SW11 being composed of one or more basic switches have been described here, but switches SW4 to SW11 can also each be composed of one transistor.

[0053] Figure 8 This refers to the capacitance value of the variable capacitor circuit 31 relative to the capacitance control data CTD, without performing jitter processing based on the jitter processing unit 65. The capacitance value of capacitor CC1 is set to 1C, and the capacitance value on the vertical axis is represented in units of 1C. The CTD on the horizontal axis is represented in decimal.

[0054] A1 represents the ideal value when the capacitance value has no error, where capacitance value = CTD. A2 is the capacitance value relative to the capacitance control data CTD, taking into account the capacitance value error. When CTD = 7, capacitors CC1 to CC3 connected in series are used; when CTD = 8, capacitor CC4 is connected in parallel. Because the way parasitic capacitance is added changes between the series and parallel connections of the capacitors, the capacitance value error is significantly different. Therefore, the linearity of the capacitance value decreases drastically when switching between CTD = 7 and CTD = 8. The linearity of the capacitance value in the variable capacitor circuit 31 affects the accuracy of temperature compensation for the oscillation frequency; therefore, when the linearity decreases, the deviation of the oscillation frequency may increase.

[0055] The following describes the jitter processing of this embodiment, which can improve such linearity reduction. Furthermore, the linearity reduction during switching between series and parallel connections is described here as an example, but the jitter processing of this embodiment can also be applied to other linearity reductions. For example, when the CTD is represented as a binary number, such as CTD = 0111 and 1000, the linearity of the capacitance value tends to decrease when bits carry or borrow. The jitter processing of this embodiment is also effective for such linearity reduction.

[0056] Figure 9 This is a timing diagram illustrating the operation of the processing circuit 60. Here, an example is given where the output of the jitter processing unit 65 is the capacitor control data CTD. However, for example, as in the second detailed structural example of the processing circuit 60 described later, the output of the jitter processing unit 65 may be further processed and output as the capacitor control data CTD.

[0057] The temperature compensation unit 63 outputs temperature-compensated capacitor control data ICL at predetermined intervals. This temperature-compensated capacitor control data ICL is input to the jitter processing unit 65 as input capacitor control data. Here, ICL and CTD are 4 bits. TA1 to TA4 represent the period of the predetermined interval. Figure 9 In the example, in TA1, TA2, TA3, and TA4, the temperature compensation unit 63 outputs ICL = 0111, 1000, 1001, and 1010.

[0058] The jitter processing unit 65 jitters the input ICL and alternately outputs CTD = ICL and CTD = ICL + 1. Specifically, when CTD = ICL and CTD = ICL + 1 are set as a group, the jitter processing unit 65 repeats one or more groups in each period TA1 to TA4. Figure 9 An example of repeating two sets in each period is shown. For example, in period TA1, the jitter processing unit 65 outputs CTD = 0111, 1000, 0111, 1000 in time-division format. The time average of the CTD in period TA1 is (7+8) / 2 = 7.5. Similarly, in periods TA2, TA3, and TA4, the jitter processing unit 65 performs jitter processing on the input ICL = 8, 9, and 10, and outputs CTDs with time averages of CTD = 8.5, 9.5, and 10.5.

[0059] In addition, Figure 9 The diagram illustrates examples of different temperature-compensated capacitor control data ICL during periods TA1 to TA4. However, the interval between TA1 and TA4 represents the data sampling period. In reality, the temperature-compensated capacitor control data ICL may differ or be the same in adjacent periods.

[0060] Figure 10 A3 applies the jitter processing of this embodiment to Figure 8 The capacitance value of the variable capacitor circuit 31 relative to the capacitance control data CTD at time A2.

[0061] When ICL=7, the jitter processing unit outputs CTD=7 and 8 in a time-division manner, therefore the capacitance value of the variable capacitor circuit 31 becomes the time average of the capacitance value corresponding to CTD=7 and the capacitance value corresponding to CTD=8. Figure 10In this diagram, the capacitance value of the variable capacitor circuit 31 is represented by a triangular marker corresponding to CTD = 7.5. Similarly, when ICL = 8, the capacitance value of the variable capacitor circuit 31 becomes the time average of the capacitance value corresponding to CTD = 8 and the capacitance value corresponding to CTD = 9. During the switching between CTD = 7 and 8, the capacitance value error is large, but the above-mentioned jittering process disperses the error, thereby improving the linearity of the capacitance value relative to CTD. By improving linearity, the accuracy of temperature compensation for the oscillation frequency is improved, and the deviation of the oscillation frequency can be reduced.

[0062] In this embodiment described above, the circuit device 20 includes a processing circuit 60 for generating capacitance control data CTD and an oscillation circuit 30. The oscillation circuit 30 has a variable capacitor circuit 31 whose capacitance value is variably controlled according to the capacitance control data CTD, and the oscillation frequency is controlled by the capacitance value of the variable capacitor circuit 31. The variable capacitor circuit 31 has a capacitor array CPA1. The capacitor array CPA1 has multiple capacitors CC1 to CC11 whose capacitance values ​​are binary-weighted, and multiple switches SW1 to SW11. The multiple switches SW1 to SW11 are connected in series with the multiple capacitors CC1 to CC11 between the oscillation node and the ground node NGN of the oscillation circuit 30, and are controlled to be turned on and off according to the capacitance control data CTD. The processing circuit 60 outputs the capacitance control data CTD after jitter processing, which switches the capacitance value of the variable capacitor circuit 31 to a first capacitance value and a second capacitance value in a time-division manner.

[0063] exist Figure 9 During period TA1, the capacitance value corresponding to CTD=0111 is the first capacitance value, and the capacitance value corresponding to CTD=1000 is the second capacitance value. Alternatively, in... Figure 15 In the second detailed structural example described later, time-division processing is further performed after the jitter processing, but the capacitance value achieved as the time average of this time-division processing is either the first capacitance value or the second capacitance value. Figure 15 During period TB1, the jitter-processed capacitor control data ICL'[13:0] contains an integer part ICL'[13:3] = CLQ and a fractional part ICL'[2:0]. The fractional part ICL'[2:0] is jitter-processed to become time divisions of 010 and 011. By performing time-division control on the capacitor array for ICL'[2:0] = 010 and 011, the first capacitor value CLQ+2 / 8 and the second capacitor value CLQ+3 / 8 are realized as time averages.

[0064] According to this embodiment, by performing jitter processing by switching the capacitance value of the variable capacitor circuit 31 to a first capacitance value and a second capacitance value in a time-division manner, the capacitance value of the variable capacitor circuit 31 becomes the average of the first capacitance value and the second capacitance value over its time average. This improves the linearity of the capacitance value of the variable capacitor circuit 31 relative to the capacitance control data CTD. The first capacitance value and the second capacitance value differ depending on the temperature detection data DTD input to the processing circuit 60, but are assumed to be as follows: Figure 8 The linearity of the capacitance value decreases when switching between CTD=7 and 8. In this case, dithering is used to distribute the error in the capacitance value, thereby improving the linearity of the capacitance value.

[0065] Furthermore, in this embodiment, the processing circuit 60 samples the input capacitance control data ICL at predetermined intervals during jitter processing. During the first period TA1 of the predetermined interval, the processing circuit 60 time-division switching between the input capacitance control data ICL = 0111 of the first period TA1 and the data 1000 obtained by adding 1 LSB to the input capacitance control data ICL = 0111 of the first period TA1. During the second period TA2 following the first period TA1, the processing circuit 60 time-division switching between the input capacitance control data ICL = 1000 of the second period TA2 and the data 1001 obtained by adding 1 LSB to the input capacitance control data ICL = 1000 of the second period TA2.

[0066] In this embodiment, the temperature-compensated capacitor control data ICL output by the temperature compensation unit 63 is equivalent to the input capacitor control data for jitter processing. Figure 9 In the first period, the input capacitor control data ICL of TA1 is different from that of TA2 in the second period, but the input capacitor control data ICL of TA1 in the first period and the input capacitor control data ICL of TA2 in the second period can also be the same.

[0067] According to this embodiment, since the input capacitor control data ICL is sampled at predetermined intervals, the input capacitor control data ICL does not change during the first period TA1. This input capacitor control data ICL and the data obtained by adding 1 LSB to the input capacitor control data ICL are output in a time-division manner. The same applies during the second period TA2. By performing such dithering, even if the linearity between the capacitor value corresponding to ICL and the capacitor value corresponding to ICL+1 decreases, the dithering process disperses the capacitor value error that causes this decrease in linearity, thus improving linearity.

[0068] Furthermore, in this embodiment, the capacitor array CPA1 has multiple capacitors CC1 to CC11, which have a first capacitor group LCG and a second capacitor group SCG. In the first capacitor group LCG, multiple MIM capacitors are connected in parallel, corresponding to the high-order bits CTD[10:3] of the capacitor control data CTD[10:0]. In the second capacitor group SCG, multiple MIM capacitors are connected in series, corresponding to the low-order bits CTD[2:0] of the capacitor control data CTD[10:0].

[0069] Assuming capacitor CC1 consists of a single unit capacitor, capacitor CC11 consists of 1024 unit capacitors. Since the size of the unit capacitors is constrained by design rules, the layout area of ​​the capacitor array becomes larger. To address this, by using a second capacitor bank SCG formed by connecting multiple MIM capacitors in series, a capacitance value smaller than that of the single unit capacitor can be generated. This allows for a reduction in the layout area of ​​the capacitor array.

[0070] However, although parasitic capacitance is generated between the nodes and ground of the unit capacitors, the capacitance value error differs between the first capacitor bank (LCG) and the second capacitor bank (SCG) due to the different ways in which this parasitic capacitance is added. Therefore, at the boundary between the range of the capacitance control data CTD using the first capacitor bank (LCG) and the range of the capacitance control data CTD using the second capacitor bank (SCG), the linearity of the capacitance value of the variable capacitor circuit 31 may decrease significantly. Regarding this, the linearity at such boundaries is improved by dispersing the capacitance value error through dithering processing.

[0071] Furthermore, in this embodiment, the processing circuit 60 includes a temperature compensation unit 63 and a jitter processing unit 65. The temperature compensation unit 63 performs temperature compensation processing based on the temperature detection data DTD, and outputs the result of the temperature compensation processing as input capacitor control data ICL. The jitter processing unit 65 performs jitter processing on the input capacitor control data ICL and outputs jitter-processed capacitor control data.

[0072] For example, in Figure 9 In the text, the capacitor control data after jitter processing is the capacitor control data CTD. Alternatively, it can be as follows: Figure 15 As described in the second detailed structural example below, the capacitor control data CTD is generated by further processing the jitter-processed capacitor control data ICL'.

[0073] In temperature compensation, when the linearity of the capacitor array decreases, the deviation of the oscillation frequency after temperature compensation may increase. According to this embodiment, the linearity of the capacitor array is improved by dithering, thereby reducing the deviation of the oscillation frequency after temperature compensation.

[0074] 2. Detailed structural example 1

[0075] Figure 11 This is a first detailed structural example of the processing circuit 60 and the memory 70. The processing circuit 60 includes a digital filter 61, a temperature compensation unit 63, and a jitter processing unit 65. The temperature compensation unit 63 is also referred to as a linear interpolation unit. The memory 70 includes a capacitor adjustment value storage unit 71. Furthermore, Figure 11 The number of bits shown for each piece of data is an example; these numbers can be arbitrary.

[0076] Digital filter 61 performs digital filtering on the temperature detection data DTD[9:0] input from temperature sensor circuit 45, and outputs the result as output data FLQ[11:0]. Digital filter 61 is, for example, an IIR filter, and the digital filtering process is, for example, a low-pass filter. IIR is an abbreviation for Infinite Impulse Response.

[0077] The capacitor adjustment value storage unit 71 is a storage area within the address space of the memory 70, specified by a defined address range, storing a first table that maps the high-order 8 bits FLQ[11:4] of the output data FLQ[11:0] to the capacitor adjustment values ​​CL[10:0]. The temperature compensation unit 63 reads the capacitor adjustment value CL[10:0] corresponding to the high-order bits FLQ[11:4] of the output data FLQ[11:0] input from the digital filter 61 from the capacitor adjustment value storage unit 71. The temperature compensation unit 63 performs linear interpolation on the read capacitor adjustment value CL[10:0] and outputs the result as the temperature-compensated capacitor control data ICL[10:0].

[0078] Specifically, when i is an integer greater than or equal to 0 and less than or equal to 255, FLQ[11:4] = i is input to the capacitor adjustment value storage unit 71. The capacitor adjustment value storage unit 71 outputs the capacitor adjustment values ​​CL[10:0] = CLI and CLI+1 corresponding to FLQ[11:4] = i and i+1 in the first table to the temperature compensation unit 63. CLI is referred to as the first capacitor adjustment value, and CLI+1 is referred to as the second capacitor adjustment value. The temperature compensation unit 63 performs interpolation processing between the first capacitor adjustment value CLI and the second capacitor adjustment value CLI+1 based on the lower 4 bits FLQ[3:0] of the output data FLQ[11:0]. The interpolation processing is, for example, linear interpolation, and the temperature compensation unit 63 selects the value corresponding to FLQ[3:0] from the values ​​that divide CLI and CLI+1 into 16 equal parts.

[0079] Temperature-compensated capacitor control data ICL[10:0] is input to the jitter processing unit 65 as input capacitor control data. The jitter processing unit 65 performs jitter processing on the input capacitor control data ICL[10:0], and outputs the jitter-processed capacitor control data as capacitor control data CTD[10:0] to the variable capacitor circuit 31. The operation of the jitter processing unit 65 is as follows: Figure 9 As explained in the text. That is, the jitter processing unit outputs CTD[10:0] = ICL[10:0] and ICL[10:0] + 1 at 65-minute intervals. "+1" means that the LSB of ICL[10:0] is increased by 1.

[0080] In the above embodiment, the processing circuit 60 outputs the jitter-processed capacitor control data as capacitor control data CTD to the variable capacitor circuit 31.

[0081] According to this embodiment, the input capacitor control data and the data obtained by adding 1 LSB to the input capacitor control data are output as capacitor control data CTD to the variable capacitor circuit 31. As a result, the capacitance value of the variable capacitor circuit 31 is switched in a time-division manner to a first capacitance value corresponding to the input capacitor control data and a second capacitance value corresponding to the data obtained by adding 1 LSB to the input capacitor control data. Therefore, by dispersing the error in the capacitance value as described above, the linearity of the capacitance value is improved.

[0082] 3. Detailed structural example 2

[0083] Figure 12 This is the second detailed structural example of capacitor array CPA1. Capacitor array CPA2 has the same structure. Capacitor array CPA1 includes capacitors CC1 to CC11, switches SW1 to SW11, switching capacitor CDV, and switching switch SWDV. For... Figure 3 Explanation of identical parts is omitted.

[0084] One end of the switching capacitor CDV is connected to the input node N1 of the drive circuit 32, and the other end of the switching capacitor CDV is connected to one end of the switching switch SWDV. The other end of the switching switch SWDV is connected to the ground node NGN. The structure of the switching capacitor CDV is similar to... Figure 4 The capacitor CC1 described herein has the same structure. Furthermore, the capacitance value of the switching capacitor CDV is the same as that of capacitor CC1. The switching switch SWDV is, for example, a transistor. The switching switch SWDV is controlled to be turned on and off by the switching control signal CTDV.

[0085] Figure 13This is a second detailed structural example of the processing circuit 60 and the memory 70. The processing circuit 60 includes a digital filter 61, a temperature compensation unit 63, a jitter processing unit 65, and a time-division processing unit 64. The memory 70 includes a capacitor adjustment value storage unit 71 and a time-division mode storage unit 72. Additionally, Figure 13 The number of bits shown for each piece of data is an example; these numbers can be arbitrary. For example, regarding... Figure 11 For structural elements that are identical to those described in the text, the descriptions should be omitted appropriately.

[0086] The capacitor adjustment value storage unit 71 stores a first table that maps the high-order 8 bits of the output data FLQ[11:0] (FLQ[11:4]) to the capacitor adjustment values ​​CL[13:0]. The temperature compensation unit 63 reads the capacitor adjustment value CL[13:0] corresponding to the high-order bits of the output data FLQ[11:0] input from the digital filter 61 from the capacitor adjustment value storage unit 71. The temperature compensation unit 63 performs linear interpolation on the read capacitor adjustment value CL[13:0] and outputs the result as the temperature-compensated capacitor control data ICL[13:0].

[0087] The jitter processing unit 65 jitters the temperature-compensated capacitor control data ICL[13:0] input from the temperature compensation unit 63, and outputs the result as the jitter-processed capacitor control data ICL'[13:0]. The jitter processing unit 65 outputs ICL'[13:0] = ICL[13:0] and ICL[13:0] + 1 in a time-division manner. "+1" means that the LSB of ICL[13:0] is increased by 1.

[0088] The time-division mode storage unit 72 is a storage area within the address space of the memory 70, specified by a defined address range. It stores a second table that maps the lower 3 bits (ICL'[2:0]) of the jitter-processed capacitor control data ICL'[13:0] to the time-division mode information TDP[31:0]. When j is an integer greater than or equal to 0 and less than or equal to 7, ICL'[2:0] = j is input to the time-division mode storage unit 72. The time-division mode storage unit 72 outputs TDP[k] = TDPj, corresponding to ICL'[2:0] = j in the second table, to the time-division processing unit 64. The time-division mode information TDP[31:0] indicates the time sequence in which the first capacitor control data and the second capacitor control data are output.

[0089] When the capacitance value of capacitor CC1, which is the smallest capacitance value in the capacitor array, is set to the integer "1", ICL'[13:3] represents the integer part of the capacitance value, and ICL'[2:0] represents the fractional part of the capacitance value. The fractional part is implemented by time-division processing based on the time-division processing unit 64.

[0090] The time-division processing unit 64 outputs capacitor control data CTD[10:0]=CLQ and switching control signal CTDV=TDP[k] based on the high 11 bits ICL'[13:0]=CLQ and time-division mode information TDPj of the jitter-processed capacitor control data ICL'[13:0]. k is an integer greater than or equal to 0 and less than or equal to 31. The time-division processing unit 64 does not change CTD[10:0]=CLQ, but outputs CTDV=TDP[0], TDP[1], ..., TDP

[31] in a time-division manner, thereby performing time-division control on the capacitance value of the variable capacitor circuit 31. CTD[10:0]=CLQ and CTDV=0 are referred to as the first capacitor control data, and CTD[10:0]=CLQ and CTDV=1 are referred to as the second capacitor control data. The time-division processing unit 64 outputs the first capacitor control data and the second capacitor control data in a time-division manner according to the time-division mode information TDPj, thereby realizing the fractional part of the capacitor value as a time average.

[0091] Figure 14 This is an example of the second table stored in the time-division mode storage unit 72. Figure 14 In this context, ICL'[2:0] is represented by binary numbers. Additionally, in the time-division mode information TDP[31:0], 0 or 1 represents the logic level of each bit.

[0092] When ICL'[2:0] = 000h, the proportion of bits with logic level 1 in TDP[31:0] is 0 / 8, therefore the corresponding decimal is 0.000. When ICL'[2:0] = 001h, the proportion of bits with logic level 1 in TDP[31:0] is 1 / 8, therefore the corresponding decimal is 0.125. Similarly, when ICL'[2:0] = 010h, 011h, 100h, 101h, 110h, 111h, the proportion of bits with logic level 1 in TDP[31:0] is 2 / 8, 3 / 8, 4 / 8, 5 / 8, 6 / 8, 7 / 8, therefore the corresponding decimals are 0.250, 0.375, 0.500, 0.625, 0.750, 0.875.

[0093] By using such time-division mode information TDP[31:0] for time-division control, capacitor control data that essentially includes fractional parts such as CLQ+0, CLQ+0.125, CLQ+0.250, ..., CLQ+0.875 can be achieved.

[0094] Figure 15 This is a timing diagram illustrating the operation of the processing circuit 60 in the second detailed structural example. Figure 15 The figure shows one of several periods, TB1, which are repeated at specified intervals.

[0095] During TB1, the temperature compensation unit 63 outputs ICL[13:3] = CLQ and ICL[2:0] = 010. The jitter processing unit 65 outputs ICL'[13:3] = CLQ, and alternately outputs ICL'[2:0] = 010 and 011 in a time-division manner. The time-division processing unit 64 outputs capacitor control data CTD[10:0] = ICL'[13:3] = CLQ. In addition, when ICL'[2:0] = 010, the time-division processing unit 64 outputs CTDV = TDP[k] = 1, 0, 0, 0, 1, ..., 0 in a time-division manner according to the time-division mode information TDP[31:0] corresponding to ICL'[2:0] = 010. When ICL'[2:0] = 011, the time-division processing unit 64 outputs CTDV = TDP[k] = 1, 0, 1, 0, 1, ..., 0 in a time-division manner according to the time-division mode information TDP[31:0] corresponding to ICL'[2:0] = 011.

[0096] When ICL'[2:0] = 010, the time average of TDP[k] is 2 / 8, therefore the capacitance value of the time-averaged variable capacitor circuit 31 is CLQ + 2 / 8. When ICL'[2:0] = 011, the time average of TDP[k] is 3 / 8, therefore the capacitance value of the time-averaged variable capacitor circuit 31 is CLQ + 3 / 8. Through jittering, they repeat alternately, therefore the time-averaged capacitance value during period TB1 is CLQ + 2.5 / 8.

[0097] Figure 16 This refers to the capacitance value of the variable capacitor circuit 31 relative to the capacitance control data CTD = CLQ, without performing jitter processing based on the jitter processing unit 65. The black circle represents the actual capacitance value existing in the capacitor array, i.e., the integer part represented by CLQ. The white circle represents the fractional part realized through time-division processing based on the time-division processing unit 64.

[0098] If the integer part of the capacitance value is considered, the series and parallel connections of the unit capacitors switch between CLQ=7 and CLQ=8, thus reducing the linearity of the capacitance value corresponding to CLQ=7 and the capacitance value corresponding to CLQ=8. If the fractional part of the capacitance value is included, the linearity of the capacitance value decreases when switching between CLQ=7+7 / 8 and CLQ=8+0 / 8. Furthermore, 7 / 8 and 0 / 8 represent the fractional part achieved through CTDV=TDP[k].

[0099] Figure 17 This refers to the capacitance value of the variable capacitor circuit 31 relative to the capacitor control data CTD = CLQ when applying the jitter processing of the second detailed structural example. Figure 17 In the image, only the area around CLQ=8 is shown in magnification. The black and white circles are... Figure 16Similarly, the triangle represents the capacitance value when the jitter processing of the second detailed structural example is applied.

[0100] When CLQ = 7 + 7 / 8, the outputs of CLQ = 7 + 7 / 8 and CLQ = 8 + 0 / 8 are alternately processed by jittering. Therefore, the capacitance value of the variable capacitor circuit 31 becomes the time average of the capacitance values ​​when CLQ = 7 + 7 / 8 and CLQ = 8 + 0 / 8. Figure 17 In this circuit, the capacitance value of the variable capacitor circuit 31 is represented by a triangular symbol corresponding to CLQ = 7 + 7.5 / 8. During the switching between CLQ = 7 + 7 / 8 and CLQ = 8 + 0 / 8, the capacitance value error is large, but the aforementioned jittering process disperses the error, thereby improving the linearity of the capacitance value relative to CLQ. By improving linearity, the accuracy of temperature compensation for the oscillation frequency is increased, and the deviation of the oscillation frequency can be reduced.

[0101] In this embodiment described above, the processing circuit 60 includes a time-division processing unit 64 that performs time-division processing on the jitter-processed capacitor control data ICL'[13:0]. The jitter processing unit 65 outputs, in time division, the first jitter-processed capacitor control data ICL'[13:3] = CLQ, ICL'[2:0] = 010 corresponding to the first capacitor value CLQ+2 / 8, and the second jitter-processed capacitor control data ICL'[13:3] = CLQ, ICL'[2:0] = 010 corresponding to the second capacitor value CLQ+3 / 8. The time-division processing unit 64 performs time-division processing on the first jitter-processed capacitor control data in such a way that the capacitance value of the variable capacitor circuit 31 becomes the first capacitor value CLQ+2 / 8 on a time average, and outputs capacitor control data CTD[10:0] = CLQ, CTDV = TDP[k]. The time-division processing unit 64 performs time-division processing based on the capacitor control data after the second jitter processing, so that the capacitance value of the variable capacitor circuit 31 becomes the second capacitance value CLQ+3 / 8 on a time average, and outputs capacitor control data CTD[10:0]=CLQ、CTDV=TDP[k].

[0102] According to this embodiment, by further performing time-division processing after jitter processing, a capacitance value smaller than the minimum capacitance value of the capacitor array can be used as the time average for the time-division processing. The minimum capacitance value of the capacitor array is the capacitance value of capacitor CC1. When it is set to the integer "1", CLQ corresponds to the integer part, and 2 / 8 and 3 / 8 correspond to the fractional parts. Therefore, the compensation accuracy of temperature compensation can be improved without increasing the number of capacitors in the capacitor array or the layout area of ​​the capacitor array. By improving the compensation accuracy of temperature compensation, the deviation of the oscillation frequency after temperature compensation becomes smaller.

[0103] Furthermore, in this embodiment, when the capacitor control data ICL'[13:3] = CLQ and ICL'[2:0] = 010 after the first jitter processing is input, the time-division processing unit 64 outputs the capacitor control data corresponding to the third capacitor value and the capacitor control data corresponding to the fourth capacitor value to the variable capacitor circuit 31 in a time-division manner, such that the capacitance value of the variable capacitor circuit 31 on a time average becomes the first capacitance value CLQ+2 / 8. The third capacitance value is less than or equal to the first capacitance value CLQ+2 / 8, and the fourth capacitance value is greater than the first capacitance value CLQ+2 / 8.

[0104] exist Figure 15 In the diagram, the capacitor control data corresponding to the third capacitor value is CTD[10:0] = CLQ, CTDV = 0, and the third capacitor value is the capacitor value corresponding to CLQ. Additionally, the capacitor control data corresponding to the fourth capacitor value is CTD[10:0] = CLQ, CTDV = 1, and the fourth capacitor value is the capacitor value corresponding to CLQ+1. Time division is performed based on CTDV = TDP[k] = 1, 0, 0, 0, 1, ..., 0, and this time averaging achieves the first capacitor value CLQ+2 / 8.

[0105] Furthermore, when the capacitor control data ICL'[13:3] = CLQ and ICL'[2:0] = 011 after the second jitter processing is input, the time-division processing unit 64 outputs the capacitor control data corresponding to the fifth capacitor value and the capacitor control data corresponding to the sixth capacitor value to the variable capacitor circuit 31 in a time-division manner, such that the capacitance value of the variable capacitor circuit 31 on a time average becomes the second capacitor value CLQ+3 / 8. The fifth capacitor value is less than or equal to the second capacitor value CLQ+3 / 8, and the sixth capacitor value is greater than or equal to the second capacitor value CLQ+3 / 8.

[0106] exist Figure 15 In the diagram, the capacitor control data corresponding to the 5th capacitor value is CTD[10:0] = CLQ, CTDV = 0, and the 5th capacitor value is the capacitor value corresponding to CLQ. Additionally, the capacitor control data corresponding to the 6th capacitor value is CTD[10:0] = CLQ, CTDV = 1, and the 6th capacitor value is the capacitor value corresponding to CLQ+1. Time division is performed based on CTDV = TDP[k] = 1, 0, 1, 0, 1, ..., 0, and this time averaging is used to achieve the 2nd capacitor value CLQ+3 / 8.

[0107] According to this embodiment, the capacitance value of the variable capacitor circuit 31 is switched to a first capacitance value CLQ+2 / 8 and a second capacitance value CLQ+3 / 8 through dithering. At this time, the fractional parts 2 / 8 and 3 / 8 of the capacitance value are implemented through time-division processing. Therefore, a capacitance value smaller than the minimum capacitance value of the capacitor array can be used, and the linearity of the capacitance value is improved through dithering.

[0108] Furthermore, in this embodiment, the capacitor array CPA1 includes a switching capacitor CDV and a switching switch SWDV. The switching capacitor CDV has the same capacitance value as the capacitor CC1 with the smallest capacitance value among the binary-weighted capacitors CC1 to CC11. The switching switch SWDV is connected in series with the switching capacitor CDV between the oscillation node and the ground node NGN. The switching switch SWDV is turned off when capacitor control data corresponding to the third capacitance value is input, and turned on when capacitor control data corresponding to the fourth capacitance value is input. Additionally, the switching switch SWDV is turned off when capacitor control data corresponding to the fifth capacitance value is input, and turned on when capacitor control data corresponding to the sixth capacitance value is input.

[0109] According to this embodiment, by switching the switching switch SWDV on or off in a time-division manner, the capacitance value of the variable capacitor circuit 31 changes by an amount corresponding to the capacitance value of the switching capacitor CDV in a time-division manner. Since the capacitance value of the switching capacitor CDV is the same as that of the capacitor CC1 with the smallest capacitance value in the capacitor array, capacitance values ​​smaller than this smallest capacitance value are implemented as time-division averages.

[0110] The circuit arrangement of this embodiment described above includes a processing circuit for generating capacitance control data and an oscillation circuit. The oscillation circuit has a variable capacitor circuit whose capacitance value is variably controlled according to the capacitance control data, and the oscillation frequency of the oscillation circuit is controlled by the capacitance value of the variable capacitor circuit. The variable capacitor circuit has a capacitor array. The capacitor array has: a plurality of capacitors, the capacitance values ​​of which are binary-weighted; and a plurality of switches connected in series with the plurality of capacitors between the oscillation node and the ground node of the oscillation circuit, and controlled to be turned on and off according to the capacitance control data. The processing circuit outputs capacitance control data after jitter processing, in a manner that time-divisionally switches the capacitance value of the variable capacitor circuit to a first capacitance value and a second capacitance value.

[0111] According to this embodiment, by performing jitter processing by switching the capacitance value of the variable capacitor circuit to a first capacitance value and a second capacitance value in a time-division manner, the capacitance value of the variable capacitor circuit becomes the average of the first capacitance value and the second capacitance value over time. As a result, the linearity of the capacitance value of the variable capacitor circuit relative to the capacitance control data is improved. That is, by jitter processing, the errors of the first capacitance value and the second capacitance value are dispersed over time, thus improving the linearity of the capacitance value when observed as a time-averaged capacitance value.

[0112] Furthermore, in this embodiment, the processing circuit may sample the input capacitance control data at predetermined intervals during jitter processing. Alternatively, the processing circuit may, during a first period of the predetermined interval, time-division multiplex the input capacitance control data of the first period and the data obtained by adding 1 LSB to the input capacitance control data of the first period. Or, the processing circuit may, during a second period following the first period, time-division multiplex the input capacitance control data of the second period and the data obtained by adding 1 LSB to the input capacitance control data of the second period.

[0113] According to this embodiment, since the input capacitance control data is sampled at predetermined intervals, the input capacitance control data does not change during the first period, and this input capacitance control data and the data obtained by adding 1 LSB to the input capacitance control data are output in a time-division manner. The same applies during the second period. Even if the linearity between the capacitance value corresponding to the input capacitance control data and the capacitance value corresponding to the data obtained by adding 1 LSB to the input capacitance control data decreases, the linearity is improved by performing the jittering process described above.

[0114] Furthermore, in this embodiment, the capacitor array may have a first capacitor group and a second capacitor group. The first capacitor group may consist of multiple MIM capacitors connected in parallel, corresponding to the high-order bits of the capacitor control data. The second capacitor group may consist of multiple MIM capacitors connected in series, corresponding to the low-order bits of the capacitor control data.

[0115] In the first and second capacitor banks, the parasitic capacitances are added in different ways, resulting in different capacitance value errors. Therefore, at the boundary between the range of capacitance control data using the first capacitor bank and the range of capacitance control data using the second capacitor bank, the linearity of the variable capacitor circuit's capacitance value may decrease significantly. In this embodiment, the capacitance value error is dispersed through dithering, thus improving the linearity at such boundaries.

[0116] Furthermore, in this embodiment, the processing circuit may include a temperature compensation unit and a jitter processing unit. The temperature compensation unit may perform temperature compensation processing based on temperature detection data and output the result of the temperature compensation processing as input capacitor control data. The jitter processing unit may perform jitter processing on the input capacitor control data and output jitter-processed capacitor control data.

[0117] In temperature compensation, when the linearity of the capacitor array decreases, the deviation of the oscillation frequency after temperature compensation may increase. According to this embodiment, the linearity of the capacitor array is improved by dithering, thereby reducing the deviation of the oscillation frequency after temperature compensation.

[0118] In addition, in this embodiment, the processing circuit may output the jitter-processed capacitor control data as capacitor control data to the variable capacitor circuit.

[0119] According to this embodiment, the input capacitor control data and the data obtained by adding 1 LSB to the input capacitor control data are output as capacitor control data to the variable capacitor circuit. As a result, the capacitance value of the variable capacitor circuit is switched in a time-division manner to a first capacitance value corresponding to the input capacitor control data and a second capacitance value corresponding to the data obtained by adding 1 LSB to the input capacitor control data. Therefore, by dispersing the error in the capacitance value as described above, the linearity of the capacitance value is improved.

[0120] Furthermore, in this embodiment, the processing circuit may include a time-division processing unit that performs time-division processing on the jitter-processed capacitor control data. The jitter processing unit may output, in a time-division manner, first jitter-processed capacitor control data corresponding to a first capacitor value and second jitter-processed capacitor control data corresponding to a second capacitor value. Alternatively, the time-division processing unit may perform time-division processing based on the first jitter-processed capacitor control data, such that the capacitance value of the variable capacitor circuit becomes the first capacitor value as a time average, and then output capacitor control data. Finally, the time-division processing unit may perform time-division processing based on the second jitter-processed capacitor control data, such that the capacitance value of the variable capacitor circuit becomes the second capacitor value as a time average, and then output capacitor control data.

[0121] According to this embodiment, by further performing time-division processing after jitter processing, a capacitance value smaller than the minimum capacitance value of the capacitor array is used as the time average of the time-division processing. Therefore, the accuracy of temperature compensation can be improved without increasing the number of capacitors in the capacitor array or the layout area of ​​the capacitor array. By improving the accuracy of temperature compensation, the deviation of the oscillation frequency after temperature compensation becomes smaller.

[0122] Furthermore, in this embodiment, when the time-division processing unit receives the capacitor control data after the first jitter processing, it may output the capacitor control data corresponding to a third capacitor value lower than the first capacitor value and the capacitor control data corresponding to a fourth capacitor value greater than the first capacitor value in a time-division manner, such that the capacitance value of the variable capacitor circuit on a time-averaged basis becomes the first capacitor value. Alternatively, when the time-division processing unit receives the capacitor control data after the second jitter processing, it may output the capacitor control data corresponding to a fifth capacitor value lower than the second capacitor value and the capacitor control data corresponding to a sixth capacitor value greater than the second capacitor value in a time-division manner, such that the capacitance value of the variable capacitor circuit on a time-averaged basis becomes the second capacitor value.

[0123] According to this embodiment, the capacitance value of the variable capacitor circuit is switched between a first capacitance value and a second capacitance value through dithering. At this time, the fractional parts of the first capacitance value and the second capacitance value are implemented separately through time-division processing. This achieves a capacitance value smaller than the minimum capacitance value of the capacitor array, and improves the linearity of the capacitance value through dithering.

[0124] Furthermore, in this embodiment, the capacitor array may include: a switching capacitor whose capacitance value is the same as the capacitor with the smallest capacitance value among a plurality of binary-weighted capacitors; and a switching switch connected in series with the switching capacitor between the oscillation node and the ground node. Alternatively, the switching switch may be open when capacitor control data corresponding to a third capacitance value is input, and open when capacitor control data corresponding to a fourth capacitance value is input. Or, the switching switch may be open when capacitor control data corresponding to a fifth capacitance value is input, and open when capacitor control data corresponding to a sixth capacitance value is input.

[0125] According to this embodiment, by switching the switch on or off in a time-division manner, the capacitance value of the variable capacitor circuit changes by an amount corresponding to the capacitance value of the switching capacitor in a time-division manner. The capacitance value of the switching capacitor is the same as that of the capacitor with the smallest capacitance value in the capacitor array; therefore, a capacitance value smaller than this smallest capacitance value is implemented as a time-division average.

[0126] Furthermore, the oscillator of this embodiment includes: a circuit arrangement of any one of the above; and an oscillator that oscillates by being driven by an oscillation circuit.

[0127] Furthermore, while this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the invention's novel aspects and effects. Therefore, all such modifications are included within the scope of this invention. For example, in the specification or drawings, a term described at least once with a broader or synonymous term can be replaced with that different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of this invention. Furthermore, the structure and operation of circuit devices, oscillators, and other components are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit arrangement, characterized by The circuit device includes: The processing circuit generates capacitor control data; An oscillating circuit having a variable capacitor circuit whose capacitance value is variably controlled according to said capacitance control data, the oscillation frequency of the oscillating circuit being controlled by the capacitance value of said variable capacitor circuit. The variable capacitor circuit has a capacitor array. The capacitor array has: Multiple capacitors, wherein the capacitance values ​​of each capacitor are weighted in binary order; as well as Multiple switches are connected in series with the multiple capacitors between the oscillation node and the ground node of the oscillation circuit, and are controlled to turn on and off according to the capacitor control data. The processing circuit outputs the capacitor control data after jittering, which involves switching the capacitance value of the variable capacitor circuit to a first capacitance value and a second capacitance value in a time-division manner. The processing circuit has: The temperature compensation unit performs temperature compensation processing based on temperature detection data and outputs the result of the temperature compensation processing as input capacitor control data. A jitter processing unit performs jitter processing on the input capacitor control data and outputs jitter-processed capacitor control data. as well as The time-division processing unit performs time-division processing on the jitter-processed capacitor control data. The jitter processing unit samples the input capacitance control data at predetermined intervals during the jitter processing. During the first period of the specified interval, the input capacitor control data of the first period, which is the capacitor control data after the first jitter processing corresponding to the first capacitor value, is switched in a time-division manner, and the data obtained by adding 1 LSB to the input capacitor control data of the first period, which is the capacitor control data after the second jitter processing corresponding to the second capacitor value. In the second period following the first period, the input capacitor control data of the second period, which serves as the capacitor control data after the first jitter processing, is time-division switched with the data obtained by adding 1 LSB to the input capacitor control data of the second period, which serves as the capacitor control data after the second jitter processing. The time-division processing unit performs time-division processing and outputs the capacitor control data based on the capacitor control data after the first jitter processing, such that the capacitance value of the variable capacitor circuit becomes the first capacitance value over time. Based on the capacitor control data after the second jitter processing, the time-division processing unit performs time-division processing and outputs the capacitor control data based on the capacitance value of the variable capacitor circuit becoming the second capacitance value over time.

2. The circuit device according to claim 1, characterized in that, The plurality of capacitors in the capacitor array have: The first capacitor bank, which consists of multiple MIM capacitors connected in parallel, corresponds to the high-order bits of the capacitor control data; and The second capacitor bank consists of multiple MIM capacitors connected in series, and corresponds to the low-order bits of the capacitor control data.

3. The circuit device according to claim 1, characterized in that, The time-division processing unit When the capacitor control data after the first jitter processing is input, the capacitor control data corresponding to the third capacitor value below the first capacitor value and the capacitor control data corresponding to the fourth capacitor value above the first capacitor value are output to the variable capacitor circuit in a time-division manner, such that the capacitance value of the variable capacitor circuit on a time average becomes the first capacitor value. When the capacitor control data after the second jitter processing is input, the capacitor control data corresponding to the fifth capacitor value below the second capacitor value and the capacitor control data corresponding to the sixth capacitor value above the second capacitor value are output to the variable capacitor circuit in a time-division manner, such that the capacitance value of the variable capacitor circuit on a time average becomes the second capacitor value.

4. The circuit device according to claim 3, characterized in that, The capacitor array has: A switching capacitor whose capacitance value is the same as the capacitor with the smallest capacitance value among the binary-weighted plurality of capacitors; and A switching switch is connected in series with the switching capacitor between the oscillation node and the ground node. The switching switch is turned off when the capacitor control data corresponding to the third capacitor value is input, turned on when the capacitor control data corresponding to the fourth capacitor value is input, turned off when the capacitor control data corresponding to the fifth capacitor value is input, and turned on when the capacitor control data corresponding to the sixth capacitor value is input.

5. A circuit arrangement, characterized by The circuit device includes: The processing circuit generates capacitor control data; An oscillating circuit having a variable capacitor circuit whose capacitance value is variably controlled according to said capacitance control data, the oscillation frequency of the oscillating circuit being controlled by the capacitance value of said variable capacitor circuit. The variable capacitor circuit has a capacitor array. The capacitor array has: Multiple capacitors, wherein the capacitance values ​​of each capacitor are weighted in binary order; as well as Multiple switches are connected in series with the multiple capacitors between the oscillation node and the ground node of the oscillation circuit, and are controlled to turn on and off according to the capacitor control data. The processing circuit outputs the capacitor control data after jittering, which involves switching the capacitance value of the variable capacitor circuit to a first capacitance value and a second capacitance value in a time-division manner. The processing circuit samples the input capacitor control data at predetermined intervals during the jitter processing. In each period divided by the predetermined interval, it switches between the input capacitor control data sampled corresponding to each period and the data obtained by adding 1 LSB to the input capacitor control data sampled corresponding to each period at a time interval shorter than the predetermined interval.

6. The circuit device according to claim 5, characterized in that, The processing circuit has: The temperature compensation unit performs temperature compensation processing based on temperature detection data and outputs the result of the temperature compensation processing as the input capacitor control data. as well as The jitter processing unit performs jitter processing on the input capacitor control data and outputs jitter-processed capacitor control data.

7. The circuit device according to claim 6, characterized in that, The processing circuit outputs the jitter-processed capacitor control data as the capacitor control data to the variable capacitor circuit.

8. The circuit device according to claim 6, characterized in that, The processing circuit includes a time-division processing unit that performs time-division processing on the jitter-processed capacitor control data. The jitter processing unit outputs, in a time-division manner, first jitter-processed capacitor control data corresponding to the first capacitor value and second jitter-processed capacitor control data corresponding to the second capacitor value. The time-division processing unit performs time-division processing and outputs the capacitor control data based on the capacitor control data after the first jitter processing, such that the capacitance value of the variable capacitor circuit becomes the first capacitance value over time. Based on the capacitor control data after the second jitter processing, the time-division processing unit performs time-division processing and outputs the capacitor control data based on the capacitance value of the variable capacitor circuit becoming the second capacitance value over time.

9. An oscillator characterized by The oscillator contains: The circuit device according to any one of claims 1 to 8; and An oscillator that oscillates by being driven by the oscillation circuit.

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