An RC oscillator circuit based on laser trimming

Abstract

This invention belongs to the field of RC oscillator technology, specifically providing a laser-tuned RC oscillator circuit, including: a bias voltage generation circuit for generating a standard voltage VREF, an RC charging and discharging circuit, a comparator circuit, and a clock jitter circuit for reducing clock jitter. The input terminal of the clock jitter circuit is connected to a power supply, and the output terminal of the clock jitter circuit is connected to one end of the RC charging and discharging circuit, and then together connected to the first input terminal of the comparator. The other end of the RC charging and discharging circuit is grounded. The second input terminal of the comparator is connected to the standard voltage VREF, and the output terminal of the comparator outputs an oscillation signal. This circuit uses a current-based capacitor charging and discharging structure plus a comparator, which saves chip area compared to the traditional capacitor charging and discharging structure plus two comparators. Furthermore, the calibration accuracy is within 0.5%, and this circuit can be applied to any circuit requiring a clock. On the other hand, the clock jitter output by this circuit is relatively small.

Description

Technical Field

[0001] This invention relates to the field of RC oscillator technology, and more specifically, to a laser-tuned RC oscillator circuit. Background Technology

[0002] In electronic products, some application systems, besides the main CPU, also have interface chips that require internal clocks. Some of these require high precision and stability in clock frequency. Two solutions are available: one is to use an external crystal oscillator for the interface chip, achieving high precision, but this requires two more pins and increases the overall system cost. The other approach is to use a built-in RC oscillator in the interface chip. This solution is low-cost and doesn't increase the number of pins, but the RC oscillator's precision and stability are lower. Traditionally, improving RC oscillation precision involves mid-cycle testing before packaging during chip manufacturing, using laser lithography to fine-tune the R or C oscillators on the die. This method requires mid-cycle testing during chip manufacturing and adjustments to each chip based on the test results, resulting in high testing costs. This solution is unacceptable for low-value chips. Regardless of the method used, an oscillator is essential.

[0003] Traditional RC oscillators either have relatively low absolute accuracy in oscillation frequency because the resistance and capacitance within the chip vary by about 20% with the process; or they require clock frequency calibration during wafer CP (wafer testing) and then writing the calibrated Trim value (voltage adjustment value) into memory cells such as FLASH, EEPROM, or OTP. This requires special process support or additional masks, which increases costs and lengthens the manufacturing cycle. Summary of the Invention

[0004] This invention addresses the technical problem of low absolute accuracy of the oscillation frequency in traditional RC oscillators in the prior art.

[0005] This invention provides a laser-tuned RC oscillator circuit, comprising:

[0006] The circuit includes a bias voltage generation circuit, an RC charging and discharging circuit, a comparator circuit, and a clock jitter circuit to reduce clock jitter.

[0007] The input terminal of the clock jitter circuit is connected to the power supply. The output terminal of the clock jitter circuit is connected to one end of the RC charging and discharging circuit, and then connected together to the first input terminal of the comparator. The other end of the RC charging and discharging circuit is grounded.

[0008] The second input terminal of the comparator is connected to the standard voltage VREF, and the output terminal of the comparator outputs an oscillation signal.

[0009] Preferably, the RC oscillator circuit further includes a first inverter and a second inverter connected in series, and the output terminal of the comparator circuit is connected to the first inverter and the second inverter in sequence;

[0010] The clock jitter circuit includes MOS transistors Mp0 and Mp1;

[0011] The drain terminals of Mp0 and Mp1 are connected to the same power supply. The gate terminal of Mp0 is connected to the output terminal of the second inverter, and the gate terminal of Mp1 is connected to the output terminal of the first inverter. The source terminal of Mp0 is grounded, and the source terminal of Mp1 is connected to the first input terminal of the comparator.

[0012] Preferably, the RC charging and discharging circuit includes a MOS transistor Mp2, the source terminal of Mp1 is connected to the drain terminal of Mp2, the gate terminal of Mp2 is connected to the output terminal of the first inverter, and the source terminal of Mp2 is grounded.

[0013] Preferably, the output of the first inverter is connected in series with another inverter before outputting.

[0014] Preferably, the RC oscillator circuit further includes a buffer circuit, and the output of the comparator is connected in series with the buffer circuit to output an oscillation signal.

[0015] Preferably, the RC charging and discharging circuit further includes a capacitor adjustment circuit, which includes a fuse and a voltage-regulating MOSFET. One end of the capacitor is connected to the output terminal of the clock jitter circuit, and the other end is connected to the drain terminal of the voltage-regulating MOSFET. The gate terminal of the voltage-regulating MOSFET is connected to the power supply through the fuse, and the source terminal of the voltage-regulating MOSFET is grounded.

[0016] Preferably, one end of the capacitors of the plurality of capacitor adjustment circuits is connected in parallel and then connected to the output terminal of the clock jitter circuit.

[0017] Preferably, the RC charging and discharging circuit further includes a capacitor adjustment circuit, which is implemented by adding a current mirror to the gate terminal of the MOS transistor that controls the capacitor by laser adjustment and fuse.

[0018] Beneficial Effects: This invention provides a laser-tuned RC oscillator circuit, comprising: a bias voltage generation circuit for generating a standard voltage VREF, an RC charging and discharging circuit, a comparator circuit, and a clock jitter circuit for reducing clock jitter. The input terminal of the clock jitter circuit is connected to a power supply, and the output terminal of the clock jitter circuit is connected to one end of the RC charging and discharging circuit, and then together connected to the first input terminal of the comparator. The other end of the RC charging and discharging circuit is grounded. The second input terminal of the comparator is connected to the standard voltage VREF, and the output terminal of the comparator outputs an oscillation signal. This circuit uses a current-driven capacitor charging and discharging plus a comparator structure, which saves chip area compared to the traditional capacitor charging and discharging plus two comparators structure. Furthermore, the calibration accuracy is 0.5%, and this circuit can be applied to any circuit requiring a clock. Compared to traditional high-precision clock circuits, it does not require special manufacturing processes, only the most basic CMOS process. This circuit has higher absolute frequency accuracy than traditional laser-tuned RC oscillator circuits, and the clock jitter output by this circuit is smaller. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a traditional RC oscillator circuit.

[0020] Figure 2 A schematic diagram of a laser-adjustable RC oscillator circuit provided for this invention;

[0021] Figure 3 This is a traditional laser trimming fuse circuit diagram;

[0022] Figure 4 The circuit diagram of the laser trimming fuse provided for this invention. Detailed Implementation

[0023] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0024] Figure 1This invention provides a laser-tuned RC oscillator circuit, comprising: a bias voltage generation circuit for generating a standard voltage VREF, an RC charging and discharging circuit, a comparator circuit, and a clock jitter circuit for reducing clock jitter. The input terminal of the clock jitter circuit is connected to a power supply. The output terminal of the clock jitter circuit is connected to one end of the RC charging and discharging circuit, and then both are connected to the first input terminal of the comparator. The other end of the RC charging and discharging circuit is grounded. The second input terminal of the comparator is connected to the standard voltage VREF, and the output terminal of the comparator outputs an oscillation signal. This circuit uses a current-driven capacitor charging and discharging structure plus a comparator, saving chip area compared to the traditional capacitor charging and discharging structure plus two comparators. Furthermore, the calibration accuracy is 0.5%, and this circuit can be applied to any circuit requiring a clock. Compared to traditional high-precision clock circuits, it does not require special manufacturing processes, only basic CMOS technology. This circuit has higher absolute frequency accuracy than traditional laser-tuned RC oscillator circuits, and the clock jitter output by this circuit is smaller.

[0025] This invention uses a laser-tuned fuse to break the gate of the MOS transistor controlling the capacitor, plus a weak pull-down current mirror, instead of the traditional method of directly breaking the metal line of the socket terminal of the lower plate switch of the capacitor. This solution corrects the loss of absolute clock accuracy caused by the clock frequency being controlled by the register's Trim bit during CP testing and then adjusted by laser.

[0026] like Figure 1 and Figure 3 As shown, a traditional RC oscillator requires two comparators to fix the voltage across the capacitor between approximately VREFL (standard low voltage) and VREFH (standard high voltage). When the voltage VC across the capacitor is lower than VREFL, the s=0 PMOS switch turns on the Ipbias current source to charge the capacitor; when the voltage VC across the capacitor is higher than VREFH, the s=1 NMOS switch turns on the Inbias current source to discharge the capacitor. In this way, the circuit outputs a periodic clock.

[0027] Traditional RC oscillator circuits require two comparators to control the high and low levels of capacitor charging and discharging. This RC oscillator circuit only requires one comparator to control the high level of charging, saving chip area. This RC oscillator circuit can be used in any chip that requires a clock; it does not require special manufacturing processes, only basic CMOS technology; and compared to traditional laser-tuned RC oscillator circuits, it has higher absolute accuracy and lower jitter.

[0028] like Figure 2As shown, the RC oscillation circuit used in this embodiment of the invention only requires one comparator. This design fixes the voltage across the capacitor between approximately 0 and VREF, and the capacitor is charged and discharged by the same current. When the voltage across C is lower than VREF (standard voltage), a = 0, the PMOS switch Mp1 turns on the Ipbias current source to charge the capacitor; when the voltage across the capacitor is higher than VREF, a = 1, the NMOS switch turns on to discharge the capacitor, thus the circuit outputs a periodic clock; and when a = 1, b = 0, the PMOS switch Mp0 turns on the Ipbias current source to output current to ground, thus ensuring that the Ipbias current source always operates in the saturation region, avoiding the transition of the current source from the saturation region to the linear region and back to the saturation region in traditional oscillation circuits, reducing the nonlinearity of the circuit, and also reducing clock jitter.

[0029] Therefore, by connecting a PMOS switch Mp0 in parallel at the current source switch Mp1 that controls capacitor charging, the current source that charges the capacitor always operates in the saturation region, avoiding the switching process of the current source from the linear region to the saturation region, reducing the nonlinearity of the circuit, and reducing clock jitter.

[0030] To achieve a high-precision output clock frequency, the capacitor in the RC charging and discharging circuit needs to be trimmed (voltage adjusted). The capacitor here is... Figure 2 Trim in the process. The voltage regulation process is usually completed during the CP (wafer testing) stage. Traditional Trim solutions, such as... Figure 3 As shown, Trim<7:0> is initially controlled by a register. The register's power-on reset value is 8'b1111,1111, with all capacitors selected, outputting the slowest clock frequency. During Trim, a binary search (Div2) filtering method is used. That is, the first step sets the highest bit to 1 and the other bits to 0. At this time, the register value is 8'b1000,0000. It checks whether the frequency meets the requirements. If the test frequency is greater than the target frequency, the highest bit remains unchanged at 1, and the second highest bit is set to 1; if the frequency is less than the target frequency, the highest bit is set to 0, and the second highest bit is set to 1, and this continues until the lowest bit.

[0031] The process continues until a register value that meets the frequency accuracy requirements is found. Once a register value that meets the frequency requirements is found (for example, if this register is 8'b0111, 1111), the Fuse with register 1 remains unchanged, and the Fuse with register 0 is melted by laser.

[0032] Traditional Trim testing methods introduce no error when the register is 1, as the fuse remains stationary. However, when the register is 0, the source terminal of the switch below the fuse introduces capacitance error, resulting in frequency accuracy error. Taking register 8'b0111,1111 obtained during CP (wafer testing) as an example, the highest bit register value is 0. In this case, the capacitance in the highest bit is the series connection of the MOS parasitic capacitance Cgs and C7. This value is close to the MOS parasitic capacitance Cgs but not zero. The fuse then blows the Trim... <7> After the control switch source terminal is connected, the capacitance value of the highest bit is 0. This means that the actual total capacitance after fuse is not equal to the total capacitance of the register used during CP testing, which introduces capacitance error and thus introduces accuracy error.

[0033] To address the accuracy error introduced by the discrepancy between the actual total capacitance after fuse testing and the total capacitance used in the register during CP testing in traditional solutions, the Trim circuit (i.e., voltage regulation circuit) in this embodiment of the invention employs the following... Figure 4 The method is the same as the traditional Trim method during CP. After finding a suitable Trim value using a binary search, the position of register 1 remains unchanged, and the fuse is blown at the position of register 0. After the fuse blows, due to the pull-down current of the current mirror, the gate of the MOS transistor with a Trim value of 0 will be pulled low. This keeps the total capacitance after laser fuse and the total capacitance during CP test consistent, without introducing capacitance error. Therefore, the RC oscillation circuit implemented in this invention has high frequency accuracy.

[0034] This solution provides an RC oscillator circuit that uses laser trimming to calibrate the frequency, requiring no special process support, and has higher absolute accuracy than traditional RC oscillator circuits that use laser trimming.

[0035] In this embodiment of the invention, a weak pull-down current mirror is added to the gate terminal of the MOS transistor that controls the laser trimming fuse, instead of the traditional method of directly melting the metal line of the socket terminal of the lower plate switch of the capacitor. This solution corrects the loss of absolute clock accuracy caused by the clock frequency being controlled by the register Trim bit during CP testing and then by laser trimming.

[0036] Preferred solutions, such as Figure 2 As shown, the RC oscillator circuit also includes a first inverter and a second inverter connected in series, and the output of the comparator circuit is connected to the first inverter and the second inverter in sequence.

[0037] The clock jitter circuit includes MOS transistors Mp0 and Mp1;

[0038] The drain terminals of Mp0 and Mp1 are connected to the same power supply. The gate terminal of Mp0 is connected to the output terminal of the second inverter, and the gate terminal of Mp1 is connected to the output terminal of the first inverter. The source terminal of Mp0 is grounded, and the source terminal of Mp1 is connected to the first input terminal of the comparator.

[0039] Specifically, the RC charging and discharging circuit includes a MOSFET Mp2. The source terminal of Mp1 is connected to the drain terminal of Mp2, the gate terminal of Mp2 is connected to the output terminal of the first inverter, and the source terminal of Mp2 is grounded. The output terminal of the first inverter is then connected in series with another inverter for output.

[0040] By connecting a PMOS switch Mp0 in parallel with the current source switch Mp1 that controls capacitor charging, the current source that charges the capacitor always operates in the saturation region, avoiding the switching process of the current source from the linear region to the saturation region, reducing the nonlinearity of the circuit, and reducing clock jitter.

[0041] In a preferred embodiment, the RC charging and discharging circuit further includes a capacitor adjustment circuit, which includes a fuse and a voltage-regulating MOSFET. One end of the capacitor is connected to the output terminal of the clock jitter circuit, and the other end is connected to the drain terminal of the voltage-regulating MOSFET. The gate terminal of the voltage-regulating MOSFET is connected to the power supply through the fuse, and the source terminal of the voltage-regulating MOSFET is grounded.

[0042] In this circuit, one end of each capacitor in the multiple capacitor adjustment circuits is connected in parallel and then connected to the output of the clock jitter circuit.

[0043] A further solution is the capacitor Trim (voltage adjustment) circuit, which uses a laser-tuned fuse to blow the gate of the MOSFET controlling the capacitor and adds a weak pull-down with a current mirror, instead of the traditional method of directly blowing the metal line of the socket terminal of the lower plate switch of the capacitor. This solution corrects the loss of absolute clock accuracy caused by the clock frequency being controlled by the register Trim bit and then by laser tuning during CP testing.

[0044] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0045] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A laser-tuned RC oscillator circuit, characterized in that, include: The circuit includes a bias voltage generation circuit, an RC charging and discharging circuit, a comparator circuit, and a clock jitter circuit to reduce clock jitter. The input terminal of the clock jitter circuit is connected to the power supply. The output terminal of the clock jitter circuit is connected to one end of the RC charging and discharging circuit, and then connected together to the first input terminal of the comparator. The other end of the RC charging and discharging circuit is grounded. The second input terminal of the comparator is connected to the standard voltage VREF, and the output terminal of the comparator outputs an oscillation signal. The RC charging and discharging circuit also includes a capacitor adjustment circuit, which includes a fuse and a voltage-regulating MOSFET. One end of the capacitor is connected to the output terminal of the clock jitter circuit, and the other end is connected to the drain terminal of the voltage-regulating MOSFET. The gate terminal of the voltage-regulating MOSFET is connected to the power supply through the fuse, and the source terminal of the voltage-regulating MOSFET is grounded. One end of each capacitor in the multiple capacitor adjustment circuits is connected in parallel and then connected to the output terminal of the clock jitter circuit. The capacitor adjustment circuit is implemented by adding a weak pull-down current mirror to the gate terminal of the MOS transistor that controls the laser-adjusted fuse capacitor.

2. The laser-adjustable RC oscillator circuit according to claim 1, characterized in that, The RC oscillator circuit also includes a first inverter and a second inverter connected in series, and the output of the comparator circuit is connected to the first inverter and the second inverter in sequence. The clock jitter circuit includes MOS transistors Mp0 and Mp1; The drain terminals of Mp0 and Mp1 are connected to the same power supply. The gate terminal of Mp0 is connected to the output terminal of the second inverter, and the gate terminal of Mp1 is connected to the output terminal of the first inverter. The source terminal of Mp0 is grounded, and the source terminal of Mp1 is connected to the first input terminal of the comparator.

3. The laser-adjustable RC oscillator circuit according to claim 2, characterized in that, The RC charging and discharging circuit includes a MOS transistor Mp2. The source terminal of Mp1 is connected to the drain terminal of Mp2, the gate terminal of Mp2 is connected to the output terminal of the first inverter, and the source terminal of Mp2 is grounded.

4. The laser-adjustable RC oscillator circuit according to claim 2, characterized in that, The output of the first inverter is then connected in series with another inverter to produce the output.

5. The laser-adjustable RC oscillator circuit according to claim 1, characterized in that, The RC oscillator circuit also includes a buffer circuit, and the output of the comparator is connected in series with the buffer circuit to output an oscillation signal.

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