A frame-type device and clock synchronization method thereof

Abstract

The present application provides a frame-type device and a clock synchronization method thereof. The method comprises: an output mode switch chip located on each multi-switch chip service board receives a clock synchronization protocol message through a service board main interface connected to an upstream device of the board, thereby synchronizing the chip time of the chip; each multi-switch chip service board is bound to a different precision time protocol instance and the clock node type is a boundary clock or a transparent clock; the output mode switch chip located on each multi-switch chip service board synchronizes the synchronized chip time of the chip to each input mode switch chip on the board; and the service board located on each multi-switch chip service board sends a clock synchronization protocol message carrying the chip time of the chip from the output mode switch chip or the input mode switch chip where the interface is located to the downstream device of the board.

Description

Technical Field

[0001] The present application relates to communication technology, and in particular to a frame-type device and a clock synchronization method thereof. Background Art

[0002] PTP (Precision Time Protocol) is a time synchronization protocol designed for high-precision time synchronization between devices, but it can also be used for frequency synchronization between devices. Nodes in a PTP domain are called clock nodes, and the interfaces running PTP on clock nodes are called PTP interfaces. PTP defines three basic clock nodes: Ordinary Clock (OC), Boundary Clock (BC), and Transparent Clock (TC).

[0003] When a network contains multiple types of service traffic with different clock synchronization requirements, the network needs to be divided into multiple PTP domains. Devices that pass through the same clock signal are added to the same PTP domain. A PTP instance is bound to a PTP domain, and the instances are isolated from each other.

[0004] like Figure 1 As shown, in the existing clock synchronization method of the frame-type device, the main control board is provided with a slave port and a master port, and the slave interface and the master interface can be flexibly located on the same business board or different business boards. The switching chip where the slave interface is located receives an announce message from the upstream device, synchronizes the chip time of this chip and other switching chips on this board according to the clock synchronization information, and then synchronizes the chip time to the switching chip of the main control board through the backplane. After the switching chip of the main control board synchronizes the system time according to the chip time, it synchronizes the system time to the switching chips of other business boards through the backplane. After the switching chip where the master interface is located synchronizes the chip time, it sends an announce message to the downstream device connected to the master interface for clock synchronization. The problem caused by this clock synchronization method is that although the frame-type device has multiple business boards and can support multiple PTP instances, the frame-type device can only serve as a basic clock node and cannot flexibly support BC and OC clock nodes at the same time according to the requirements of the network topology. Summary of the Invention

[0005] The purpose of this application is to provide a frame-type device and a clock synchronization method thereof to provide BC and OC nodes that support multiple PTP instances.

[0006] To achieve the above-mentioned objectives, the present application provides a clock synchronization method for a frame-type device, the method comprising: an output mode switch chip located on each multi-switch chip service board receives a clock synchronization protocol message through a service board main interface connected to an upstream device of the board, and synchronizes the chip time of the chip; each multi-switch chip service board is bound to a different Precision Time Protocol (PTP) instance, and the clock node type is a boundary clock or a transparent clock;

[0007] The output mode switch chip located on each multi-switch chip service board synchronizes the synchronized chip time of the chip to each input mode switch chip on the board;

[0008] The service board located on each multi-switch chip service board sends a clock synchronization protocol message carrying the chip time of the chip from the output mode switch chip or the input mode switch chip where the interface is located to the downstream device of the board.

[0009] To achieve the above objectives, the present application also provides a frame device, wherein the main control board of the frame device is connected to multiple service boards via a backplane, and the multiple service boards include service boards with multiple multi-switch chips bound to different PTP instances and whose clock node types are boundary clocks or transparent clocks;

[0010] The output mode switch chip of each multi-switch chip service board is used to receive clock synchronization protocol messages through the service board main interface connected to the upstream device of the board to synchronize the chip time of the chip; and synchronize the synchronized chip time of the chip to each input mode switch chip of the board;

[0011] The service board of each multi-switch chip service board sends a clock synchronization protocol message carrying the chip time of the chip from the output mode switch chip or the input mode switch chip where the interface is located to the downstream device of the board.

[0012] The beneficial effect of the present application is that each service board can perform clock synchronization processing with its own clock node type in its own bound PTP instance, thereby providing BC and OC nodes that support multiple PTP instances on the frame device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of clock synchronization for existing modular devices;

[0014] Figure 2 A flowchart of an embodiment of a method for clock synchronization of a frame-type device provided in this application;

[0015] Figure 3 Schematic diagram of clock synchronization of the frame device provided in this application. DETAILED DESCRIPTION

[0016] The present invention will be described in detail with reference to a plurality of examples shown in the accompanying drawings. In the following detailed description, a number of specific details are provided to provide a comprehensive understanding of the present invention. Known methods, steps, components, and circuits are not described in detail in the examples to avoid obscuring the understanding of the examples.

[0017] Among the terms used, the term "including" means including but not limited to; the term "containing" means including but not limited to; the terms "above," "within," and "below" are inclusive; the terms "greater than" and "less than" are exclusive. The term "based on" means based on at least a portion.

[0018] Figure 2 The flowchart of the clock synchronization method embodiment of the frame-type device provided in the present application includes:

[0019] Step 101: The output mode switch chip located in each multi-switch chip service board receives a clock synchronization protocol message through the service board main interface connected to the upstream device of the board to synchronize the chip time of the chip;

[0020] Each multi-switch chip service board is bound to a different Precision Time Protocol (PTP) instance, and the clock node type is a boundary clock or a transparent clock.

[0021] Step 102: The output mode switch chip located on each multi-switch chip service board synchronizes the synchronized chip time of the chip to each input mode switch chip on the board;

[0022] Step 103: The service board located on each multi-switch chip service board sends a clock synchronization protocol message carrying the chip time of the chip from the output mode switch chip or the input mode switch chip where the interface is located to the downstream device of the board.

[0023] Figure 1 The beneficial effect of the illustrated embodiment is that each service board can perform clock synchronization processing with its own clock node type in its own bound PTP instance, thereby providing BC and OC nodes that support multiple PTP instances on the frame device.

[0024] Figure 3 Schematic diagram of clock synchronization of the frame device provided in this application. Figure 3 In the example, the main control board is connected to the service boards 1-3 via a backplane (not shown). Service boards 1 and 3 are multi-switch chip service boards, while service board 2 is a single-switch chip service board.

[0025] The main control board assigns a PTP instance to each of the service boards 1-3, and each PTP instance is different, that is, in a different PTP domain.

[0026] Assuming that the upstream and downstream devices connected to business boards 1 and 3 are both network devices (not shown in the figure), the main control board sets the clock node type of business boards 1 and 3 to BC boundary clock; since the upstream device connected to business board 2 is a network device and the downstream device is a terminal (not shown in the figure), the clock node type of business board 2 is set to ordinary clock OC.

[0027] The main control board sets port P1 of business board 1 connected to the upstream device as the slave interface of business board 1; sets port P2 of business board connected to the downstream device as the master interface of business board 1; sets switching chip 12 where the master interface on business board 1 is located to output mode, and sets switching chip 11 to input mode.

[0028] In this application, the chip on each switching chip that connects to the upstream device from the interface needs to be set to OUTPUT mode to synchronize time with other chips on the same board. Other chips on the same board are set to INPUT mode to receive time synchronization from the OUTPUT mode chip. For a single-chip board, the entire chip can be set to OUTPUT mode.

[0029] The main control board sets port P3 of service board 2 connected to the upstream device as the slave interface of service board 3; sets port P5 of service board connected to the downstream device as the master interface of service board 3; and sets switching chip 21 to output mode.

[0030] The main control board sets port P4 of business board 3 connected to the upstream device as the slave interface of business board 3; sets port P5 on the business board connected to the downstream device as the master interface of business board 3; sets the switching chip 31 where the main interface on business board 3 is located to output mode, and sets other switching chips 32-3n to input mode. Figure 3 Although only one single-chip service board is shown as an example, the PT instances bound to each single-chip service board in this application are also different, and different clock node types can also be supported by the single-chip service board.

[0031] The main control board selects a single optimal service board and synchronizes the system time based on its chip time. Events and logs recorded by subsequent chassis devices are based on the system time after the switch chip on the main control board synchronizes. The main control board can select service board 1, which has the smallest service board ID, service board 3, which has the highest processing performance, or service board 2, which has a lighter service load. However, within the entire chassis, the main control board only needs to synchronize based on the chip time of one service board. In this embodiment, the main control board selects service board 1 as the optimal service board.

[0032] Figure 3In the example, switch chip 12 in output mode on service board 1 receives an announce message from the upstream device of service board 1 through interface P1. It updates its chip time based on the received announce message and synchronizes it with switch chip 11 in input mode on the same board. Switch chip 11 also synchronizes the synchronized chip time with switch chips m1 and m2 connected to the main control board for system time synchronization.

[0033] After the input mode switching chip 11 of the service board 1 synchronizes its chip time, it generates an announce message and sends it to the downstream device connected to the service board 1 through the main interface P1 on the chip.

[0034] The switching chip 21 in output mode of service board 2 receives the announce message sent by the upstream device of service board 2 from interface P3, updates the chip time of this chip according to the received announce message, generates an announce message, and sends it to the downstream device connected to service board 2 through the main interface P4 on this chip.

[0035] Switch chip 31 in output mode on service board 3 receives announce messages from its upstream device via interface P5. Based on these messages, it updates its own chip time and synchronizes it with switch chips 32-3n in input mode on the board. After synchronizing its own chip time, switch chip 31 in output mode on service board 3 generates an announce message and sends it via its primary interface P6 to the downstream device connected to service board 3.

[0036] The input mode switching chips 32 - 3 n of the service board 3 are based on the chip time from the output mode switching chip 31 .

[0037] The beneficial effect of the embodiments of the present application is that each business board in the frame device is set to a different clock node type and bound to a different PTP domain, so that time synchronization is performed only on one business board in each PTP domain, the time of each business board does not interfere with each other, and the events of each business board will be synchronized in each PTP domain, and other PTP terminal devices can be connected, enriching the PTP networking and the types of PTP services that can be provided.

[0038] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A clock synchronization method for a frame-type device, characterized in that: The method comprises: The output mode switch chip located on each multi-switch chip service board receives clock synchronization protocol messages through the service board main interface connected to the upstream device of the board to synchronize the chip time of the chip; each multi-switch chip service board is bound to a different Precision Time Protocol (PTP) instance and the clock node type is boundary clock or transparent clock; The output mode switch chip located on each multi-switch chip service board synchronizes the synchronized chip time of the chip to each input mode switch chip on the board; The service board located on each multi-switch chip service board sends a clock synchronization protocol message carrying the chip time of the chip from the output mode switch chip or the input mode switch chip where the interface is located to the downstream device of the board.

2. The method according to claim 1, characterized in that The method further comprises: The output mode switching chip on the single-switch chip service board receives clock synchronization protocol messages through the service board master interface connected to the upstream device of the board to synchronize the chip time of the chip; and sends clock synchronization protocol messages with the chip time of the chip to the downstream device of the board through the service slave interface of the chip; Each single-switch chip service board is bound to a different PTP instance, and the clock node type is boundary clock or transparent clock.

3. The method according to claim 1 or 2, characterized in that The method further comprises: The output mode switch chip of the designated optimal multi-switch chip service board synchronizes the chip time of the synchronized chip to each switch chip of the main control board through the backplane; or the output mode switch chip of the designated optimal single-switch chip service board synchronizes the chip time of the synchronized chip to each switch chip of the main control board through the backplane; The switching chip of the main control board updates the system time of the frame device according to the synchronized chip time.

4. The method according to claim 3, characterized in that The main control board sets the clock node type of each multi-switch chip business board based on the upstream and downstream devices connected to each multi-switch chip business board; The main control board sets each multi-switch chip business board to be bound to a PTP instance and is different from the PTP instance bound to other multi-switch chip business boards or single-switch chip business boards; The main control board sets the two ports on each multi-switch chip service board connected to its upstream device and downstream device as the service board slave interface and the service board master interface respectively; The main control board sets the switching chip where the service board slave interface on each multi-switch chip service board is located to output mode, and sets other switching chips to input mode.

5. The method according to claim 1, wherein The main control board sets the clock node type of each single-switch chip service board based on the upstream and downstream devices connected to each single-switch chip service board; The main control board sets each single-switch chip business board to be bound to a PTP instance and is different from the PTP instance bound to other multi-switch chip business boards or each single-switch chip business board; The main control board sets the two ports on each single-switch chip service board connected to its upstream device and downstream device as the service board slave interface and the service board master interface respectively; The main control board sets the switching chip of each single-switch chip service board to output mode.

6. A frame-type device, wherein a main control board of the frame-type device is connected to multiple service boards via a backplane, characterized in that: The multiple service boards include service boards with multiple multi-switch chips that are bound to different PTP instances and whose clock node types are boundary clocks or transparent clocks; The output mode switch chip of each multi-switch chip service board is used to receive clock synchronization protocol messages through the service board main interface connected to the upstream device of the board to synchronize the chip time of the chip; and synchronize the synchronized chip time of the chip to each input mode switch chip of the board; The service board of each multi-switch chip service board sends a clock synchronization protocol message carrying the chip time of the chip from the output mode switch chip or the input mode switch chip where the interface is located to the downstream device of the board.

7. The device according to claim 6, characterized in that The device also includes a plurality of single-switch chip service boards bound to different Precision Time Protocol PTP instances and having a clock node type of a boundary clock or a transparent clock; The output mode switching chip located on the single switching chip business board receives the clock synchronization protocol message through the business board main interface connected to the upstream device of the board to synchronize the chip time of the chip; and sends the clock synchronization protocol message with the chip time of the chip to the downstream device of the board through the business slave interface of the chip.

8. The device according to claim 6 or 7, characterized in that The output mode switch chip of the designated optimal multi-switch chip service board synchronizes the chip time of the synchronized chip to each switch chip of the main control board through the backplane; or the output mode switch chip of the designated optimal single-switch chip service board synchronizes the chip time of the synchronized chip to each switch chip of the main control board through the backplane; The switching chip of the main control board updates the system time of the frame device according to the synchronized chip time.

9. The device according to claim 8, characterized in that The main control board sets the clock node type of each multi-switch chip business board based on the upstream and downstream devices connected to each multi-switch chip business board; The main control board sets each multi-switch chip business board to be bound to a PTP instance and is different from the PTP instance bound to other multi-switch chip business boards or single-switch chip business boards; The main control board sets the two ports on each multi-switch chip service board connected to its upstream device and downstream device as the service board slave interface and the service board master interface respectively; The main control board sets the switching chip where the service board slave interface on each multi-switch chip service board is located to output mode, and sets other switching chips to input mode.

10. The device according to claim 8, characterized in that The main control board sets the clock node type of each single switch chip business board based on the upstream and downstream devices connected to each single switch chip business board; The main control board sets each single-switch chip business board to be bound to a PTP instance and is different from the PTP instance bound to other multi-switch chip business boards or each single-switch chip business board; The main control board sets the two ports on each single-switch chip service board connected to its upstream device and downstream device as the service board slave interface and the service board master interface respectively; The main control board sets the switching chip of each single-switch chip service board to output mode.

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