Memory Operations Considering Wear Leveling

Abstract

As described herein, an apparatus may include a memory including a first portion, a second portion, and a third portion. The apparatus may also include a memory controller including a first logical-to-physical table stored in a buffer memory. The memory controller may determine that the first portion and the second portion are accessed sequentially, and may adjust the first logical-to-physical table so that a memory transaction performed by the memory controller accesses the third portion instead of the first portion.

Description

Background Art

[0001] This section is intended to introduce the reader to various aspects of the technology that may be related to various aspects of the technology described and / or claimed below. It is believed that this discussion helps to provide the reader with background information to promote a better understanding of various aspects of the present disclosure. Therefore, it should be understood that these statements should be read in this light, rather than as an admission of the prior art.

[0002] In general, a computing system includes a processing circuit system, such as one or more processors or other suitable components; and a memory device, such as a chip or an integrated circuit. One or more memory devices may be used on a memory module, such as a dual in-line memory module (DIMM), to store data accessible to the processing circuit system. For example, based on user input to the computing system, the processing circuit system may request the memory module to retrieve data corresponding to the user input from its memory device. In some cases, the retrieved data may include firmware, or instructions that can be executed by the processing circuit system to perform an operation, and / or may include data to be used as input for the operation. In addition, in some cases, data output from the operation may be stored in the memory, for example, to enable subsequent retrieval. In the case of retrieving firmware from non-volatile memory (e.g., media, storage device), the mode of retrieval of information stored in the memory may be inefficient. Each memory chip is composed of subunits sometimes referred to as memory banks. Memory banks may share input / output circuit systems, but may operate independently of each other in other ways. In this way, the computing system can refer to a portion of one memory bank without referring to a portion of another memory bank. The memory unit may be a single memory chip or a collection of memory chips. Memory cells can be thought of as being made up of memory "groups". Because memory groups can operate independently, a read or write instruction to one memory group can continue to execute while another memory group is busy processing a previous read / write instruction. This means that the memory chip can operate simultaneous operations in multiple groups. However, if an operation is issued to the same group, the memory chip can wait to process the next operation until any previous operation is completed. Therefore, the read / write speed of a given memory system (e.g., one or more memory cells) can depend on how the data transferred to / from the memory is distributed across different groups. For example, if all data is stored in the same group, the total duration for performing a memory operation is expected to be longer relative to the total duration for performing a memory operation when the data is stored and / or distributed across multiple groups.

[0003] In a storage system, an address comparison table may be used to map memory addresses from logical to physical addresses. For example, a logical to physical (L2P) translation table may be used to map data (e.g., information stored in a memory) from logical to physical addresses of the memory. Over time, some physical addresses of the memory may be accessed more frequently than other physical addresses of the memory in response to a memory access pattern, which may age portions of the memory corresponding to more accessed physical addresses at a relatively faster rate than other portions of the memory. Unequal aging of memory is generally undesirable. More efficient memory access operations may be required to improve memory management operations (e.g., improve performance, reduce the amount of time used to perform memory operations) and improve wear leveling (e.g., reduce unequal access patterns, equalize access patterns to promote equal aging of memory). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Various aspects of the present disclosure may be better understood after reading the following detailed description and referring to the accompanying drawings, in which:

[0005] Figure 1 is a block diagram of a computing system including a client device and one or more computing devices according to an embodiment;

[0006] Figure 2 According to the embodiment, it can be used for Figure 1 A block diagram of a memory module of a computing device;

[0007] Figure 3 According to the embodiment Figure 2 a block diagram of a memory module after a duration such that the memory module is subject to relatively unequal access patterns;

[0008] Figure 4 According to the embodiment Figure 2 an illustration of a controller of a memory module of the invention, the controller operating to adjust a current logical-to-physical table (L2P table) to proactively compensate for unequal access patterns; and

[0009] Figure 5 For operation according to an embodiment Figure 4 Flowchart of a process by which a controller preemptively compensates for unequal access patterns. DETAILED DESCRIPTION

[0010] When introducing the elements of various embodiments of the present disclosure, the articles "a", "an", "the", and "said" are intended to indicate the presence of one or more of these elements. The terms "comprise", "include", and "have" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. One or more specific embodiments of the present embodiment described herein will be described below. In an effort to provide a concise description of these embodiments, all features of the actual implementation may not be described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the specific goals of the developer, such as consistency with system-related and enterprise-related constraints, which may vary from one implementation to another. In addition, it should be understood that such development work may be complex and time-consuming, but for the general technician who benefits from the present disclosure, these are routine tasks in design, construction, and manufacturing.

[0011] In general, the hardware of a computer system includes processing circuitry and memory implemented using one or more processors and / or one or more memory devices (e.g., such as chips, such as integrated circuits). During operation of the computing system, the processing circuitry may perform various operations (e.g., tasks) by executing corresponding instructions, for example, based on user input to determine output data by operating on input data. To facilitate the operation of the computing system, data accessible to the processing circuitry may be stored in the memory device, such that the memory device stores input data, output data, data indicating executable instructions, or any combination thereof.

[0012] Additionally, in some cases, the memory device may be implemented using different memory types. For example, the memory device may be implemented as a volatile memory, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). Alternatively, the memory device may be implemented as a non-volatile memory, such as a flash memory (e.g., NAND, NOR) memory, a phase change memory (e.g., 3D XPoint TM ) or ferroelectric random access memory (FeRAM). In any case, the memory device typically includes at least one memory die (e.g., an array of memory cells configured on a portion or "die" of a semiconductor wafer) to store data bits (e.g., a "0" bit or a "1" bit) transmitted to the memory device through a channel (e.g., a data channel, a communication coupling, a bus interface), and can be functionally similar from the perspective of processing circuitry, even when the memory device includes different memory types.

[0013] During the operation of the host device, the application or programming of the host device or other components of the host device may generate or access information stored in the memory. Information stored as data in the memory may be stored at a physical location. These physical locations in the memory may be accessed by components of the host device via referenceable logical addresses. The memory controller may control the operation of the memory and / or act as an intermediate device between the memory and the host device. In this way, when the memory receives a command from the host device, the command may include an instruction (e.g., a read instruction, a write instruction) and an indication of a logical address (e.g., a bit string indicating a location in the memory that the component of the host device wishes to access). After receiving the command, the memory controller may refer to a logical to physical conversion table (L2P table) to determine the physical address corresponding to the logical address of the command, wherein the physical address is the physical location in the memory that the host device wishes to access with the command.

[0014] Over time, some physical addresses of memory may be accessed more frequently than other physical addresses of memory. Unequal access distributions and / or unequal access patterns to memory may age some portions of memory at a relatively faster rate than other portions of memory. Unequal aging of memory is generally undesirable because it may shorten the life of the device, and the operation of equalizing aging of memory (e.g., equalizing accesses to memory) may be referred to as a "wear leveling" operation.

[0015] As described herein, in order to compensate for memory access patterns, such as reducing unequal wear from unequal memory accesses and / or improving the total duration for processing memory commands, a memory controller may adjust an L2P table based on commands issued by a host device. For example, the memory controller may adjust the L2P table taking into account physical addresses that are accessed relatively more frequently than other physical addresses and / or taking into account logical addresses that are typically accessed sequentially or after each other for a duration such that processing of a first command is still in progress in order to delay the initiation of processing of a subsequent command. By adjusting the L2P table based on address access patterns (e.g., traffic patterns), the memory controller may preemptively reduce or eliminate unequal wear and facilitate wear leveling and / or may improve the speed at which memory operations are performed (e.g., by increasing the number of memory accesses that can be performed in parallel). In some embodiments, the memory controller may also consider performance when adjusting the L2P table to improve (e.g., make more equal) the distribution of physical address accesses and improve wear leveling (e.g., make the number of accesses more equal).

[0016] In this way, L2P translations can be used to improve the performance of a memory system (e.g., reduce the time spent performing memory operations). Because L2P tables provide the ability to store data in any physical location in memory while the data can still be in a contiguous logical address space, L2P tables can be utilized to optimize and / or improve memory access patterns. In some cases, the optimal data storage pattern is memory access dependent, so each software application of a computing system (e.g., each software application that has or uses access to a memory system) can have its own optimal pattern. Therefore, in some embodiments, a memory system and / or a computing system can analyze software application accesses to a memory system to determine traffic patterns. Through the deployment of deep learning algorithms, traffic patterns can be used to generate L2P translation tables designed to improve access to a memory system based on actual access trends of software applications.

[0017] In some cases, L2P tables may be generated that represent optimal behavior or relatively improved performance for multiple software applications. L2P tables generated based on traffic patterns for two or more software applications may be used and / or accessed as default L2P tables for a memory system. By using L2P tables that are adjusted based on the traffic patterns of the software applications, the performance of the memory system may be improved because logical addresses that are accessed relatively frequently after each other may define reference physical addresses in different groups. These L2P tables may also be used to manage wear leveling, such as by distributing memory accesses across one or more memory groups. Furthermore, it should be noted that because these wear leveling algorithms modify the L2P tables during operation of the memory system to optimize wear leveling and / or expected sequences of memory accesses, memory operations do not need to be delayed while these determinations are being made.

[0018] To help explain, Figure 1 An example of a computing system 10 is depicted that includes one or more remote computing devices 12. As in the depicted embodiment, the remote computing device 12 may be communicatively coupled to one or more client devices 14 via a communication network 16. It should be appreciated that the depicted embodiment is intended to be illustrative only and not limiting. For example, in other embodiments, the remote computing device 12 may be communicatively coupled to a single client device 14 or more than two client devices 14. Additionally, depending on the computing system 10, the memory controller 34 may not only be on the memory module 26. In this manner, depicted is a general use of the described technology, where the memory controller 34 is entirely on the memory module 26. However, other examples may include a memory controller without a memory module and / or may use a processing circuit 24 as the memory controller 34.

[0019] In any case, communication network 16 may enable data communication between client device 14 and remote computing device 12. In some embodiments, client device 14 may be physically remote (e.g., separate) from remote computing device 12, such as such that remote computing device 12 is located at a centralized data center. Thus, in some embodiments, communication network 16 may be a wide area network (WAN), such as the Internet. To facilitate communication via communication network 16, remote computing device 12 and client device 14 may each include a network interface 18.

[0020] In addition to the network interface 18, the client device 14 may include an input device 20 and / or an electronic display 22 to enable a user to interact with the client device 14. For example, the input device 20 may receive user input and, thus, may include buttons, a keyboard, a mouse, a track pad, and / or the like. Additionally or alternatively, the electronic display 22 may include a touch sensing component that receives user input by detecting the presence and / or location of an object touching its screen (e.g., the surface of the electronic display 22). In addition to enabling user input, the electronic display 22 may facilitate providing a visual representation of information by displaying a graphical user interface (GUI) of an operating system, an application program interface, text, static images, video content, or the like.

[0021] As described above, communication network 16 may enable data communication between remote computing device 12 and one or more client devices 14. In other words, communication network 16 may enable user input to be transmitted from client device 14 to remote computing device 12. Additionally or alternatively, communication network 16 may enable the results of operations performed by remote computing device 12 based on the user input to be transmitted back to client device 14, for example, as image data to be displayed on its electronic display 22.

[0022] Indeed, in some embodiments, data communications provided by the communications network 16 may be utilized to make centralized hardware available to multiple users, such that the hardware at the client devices 14 may be reduced. For example, the remote computing device 12 may provide data storage for multiple different client devices 14, thereby enabling a reduction in data storage (e.g., memory) provided locally at the client devices 14. Additionally or alternatively, the remote computing device 12 may provide processing for multiple different client devices 14, thereby enabling a reduction in processing power provided locally at the client devices 14.

[0023] Thus, in addition to the network interface 18, the remote computing device 12 may also include a processing circuit system 24 and one or more memory modules 26 (e.g., subsystems) communicatively coupled via a data bus 28. In some embodiments, the processing circuit system 24 and / or the memory module 26 may be implemented across multiple remote computing devices 12, such as such that a first remote computing device 12 includes a portion of the processing circuit system 24 and the first memory module 26A, while an Mth remote computing device 12 includes another portion of the processing circuit system 24 and the Mth memory module 26M. Additionally or alternatively, the processing circuit system 24 and the memory module 26 may be implemented in a single remote computing device 12.

[0024] In any case, processing circuitry 24 may generally execute instructions to perform operations indicated, for example, by user input received from client device 14. Thus, processing circuitry 24 may include one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more processor cores, or any combination thereof. In some embodiments, processing circuitry 24 may additionally operate based on circuit connections formed (e.g., programmed) in processing circuitry 24. Thus, in such embodiments, processing circuitry 24 may additionally include one or more application specific integrated circuits (ASICs), one or more field programmable logic arrays (FPGAs), or any combination of suitable processing devices.

[0025] In addition, memory module 26 may provide data storage accessible to processing circuit system 24. For example, memory module 26 may store data received from client device 14, data generated by operations performed by processing circuit system 24, data to be input to operations performed by processing circuit system 24, instructions executable by processing circuit system 24 to perform operations, or any combination thereof. To facilitate providing data storage, memory module 26 may include one or more memory devices 30 (e.g., chips or integrated circuits). In other words, memory devices 30 may each include a tangible, non-transitory computer-readable medium that stores data accessible to processing circuit system 24.

[0026] Because the hardware of the remote computing device 12 may be utilized by multiple client devices 14, at least in some cases, the memory module 26 may store data corresponding to different client devices 14. In some embodiments, the data may be grouped and stored as data blocks 32. Indeed, in some embodiments, the data corresponding to each client device 14 may be stored as a separate data block 32. For example, the memory device 30 in the first memory module 26A may store a first data block 32A corresponding to the first client device 14A and an Nth data block 32N corresponding to the Nth client device 14N. One or more data blocks 32 may be stored within a memory die of the memory device 30.

[0027] Additionally or alternatively, in some embodiments, data block 32 may correspond to a virtual machine (VM) provided to client device 14. In other words, as an illustrative example, remote computing device 12 may provide first client device 14A to a first virtual machine via first data block 32A and provide Nth client device 14N to an Nth virtual machine via Nth data block 32N. Thus, when first client device 14A receives user input intended for the first virtual machine, first client device 14A may transmit the user input to remote computing device 12 via communication network 16. Based at least in part on the user input, remote computing device 12 may retrieve first data block 32A, execute the instructions to perform a corresponding operation, and transmit the result of the operation back to first client device 14A via communication network 16.

[0028] Similarly, when the Nth client device 14N receives user input intended for the Nth virtual machine, the Nth client device 14N may transmit the user input to the remote computing device 12 via the communication network 16. Based at least in part on the user input, the remote computing device 12 may retrieve the Nth data block 32N, execute the instructions to perform the corresponding operation, and transmit the result of the operation back to the Nth client device 14N via the communication network 16. Thus, the remote computing device 12 may access (e.g., read and / or write) the various data blocks 32 stored in the memory module 26.

[0029] To facilitate improved access to the storage data blocks 32, the memory module 26 may include a memory controller 34 that controls the storage of data in its memory devices 30. In some embodiments, the memory controller 34 may operate based on circuit connections formed (e.g., programmed) in the memory controller 34. Thus, in such embodiments, the memory controller 34 may include any combination of one or more application specific integrated circuits (ASICs), one or more field programmable gate arrays (FPGAs), or suitable processing devices. In any case, as described above, the memory module 26 may include memory devices 30 that use different memory types, such as the memory devices 30 that provide varying tradeoffs between data access speed and data storage density. Thus, in such embodiments, the memory controller 34 may control data storage across multiple memory devices 30 to facilitate exploiting various tradeoffs, such as enabling the memory module 26 to provide fast data access speeds as well as higher data storage capacity.

[0030] To help explain, Figure 2An example of a memory module 26 including different types of memory devices 30 is depicted. Specifically, the memory module 26 may include one or more non-volatile memory devices 30 and one or more volatile memory devices 30. In some embodiments, the volatile memory devices 30 may be dynamic random access memory (DRAM) and / or static random access memory (SRAM). In other words, in such embodiments, the memory module 26 may include one or more DRAM devices (e.g., chips or integrated circuits), one or more SRAM devices (e.g., chips or integrated circuits), or any combination of suitable memory devices.

[0031] In addition, in some embodiments, the non-volatile memory device 30 may be a flash memory (eg, NAND) memory, a phase change (eg, 3D XPoint TM ) memory and / or FeRAM. In other words, in such embodiments, the memory module 26 may include one or more NAND memory devices, one or more 3D XPoint TM In some embodiments, non-volatile memory device 30 may provide a storage class memory (SCM) that may, at least in some cases, facilitate reducing implementation associated costs by avoiding other non-volatile data storage devices in computing system 10.

[0032] In any case, in some embodiments, the memory module 26 may include a memory device 30 on a flat (e.g., front and / or back) surface of a printed circuit board (PCB). To facilitate data communication via the data bus 28, the memory module 26 may include a bus interface 44 (bus I / F). For example, the bus interface 44 may include data pins (e.g., contacts) formed along the (e.g., bottom) edge of the printed circuit board. Thus, in some embodiments, the memory module 26 may be a single in-line memory module (SIMM), a dual in-line memory module (DIMM), or the like.

[0033] Additionally, in some embodiments, the bus interface 44 may include logic that enables the memory module 26 to communicate via the communication protocol of the data bus 28. For example, the bus interface 44 may control the timing of data output from the memory module 26 to the data bus 28 and / or interpret data input from the data bus 28 to the memory module 26 according to the communication protocol. Thus, in some embodiments, the bus interface 44 may be a double data rate fourth generation (DDR4) interface, a double data rate fifth generation (DDR5) interface, a peripheral component interconnect express (PCIe) interface, a non-volatile dual in-line memory module (e.g., NVDIMM-P) interface, a cache coherent interconnect for accelerators (CCIX) interface, or the like.

[0034] In any case, as described above, the memory controller 34 can control the storage of data within the memory module 26, such as to facilitate improved data access speed and / or data storage efficiency by taking advantage of the various trade-offs provided by the memory type of the memory module 26. Thus, as in the depicted example, the memory controller 34 can be coupled between the bus interface 44 and the memory device 30 via one or more internal buses 37, such as provided as conductive traces formed on a printed circuit board. For example, the memory controller 34 can control whether a data block 32 is stored in the memory device 30. In other words, the memory controller 34 can transfer a data block 32 from a first memory device 30 to a second memory device 30, or vice versa.

[0035] To facilitate data transfer, the memory controller 34 may include a buffer memory 46, for example, to provide temporary data storage. In some embodiments, the buffer memory 46 may include a static random access memory (SRAM), and thus may provide faster data access speeds than the volatile memory device 30 and the non-volatile memory device 30. In some cases, the buffer memory 46 may be a DRAM or FeRAM. In addition, to facilitate access to the stored data blocks 32, the memory module 26 may include a logical to physical address mapping table (L2P table) and / or other parameters stored in the buffer memory 46, a non-volatile memory device (e.g., a portion of the memory device 30), a volatile memory device (e.g., a portion of the memory device 30), a dedicated address mapping memory device (e.g., a portion of the memory device 30), or any combination thereof. The other parameters may include a physical experience table that stores parameters and / or data related to the operation of the memory module 26 and / or one or more components of the computing system 10.

[0036] Additionally, the remote computing device 12 may communicate with a service processor and / or service bus included in or separate from the processing circuitry 24 and / or data bus 28. The service processor, processing circuitry 24, and / or memory controller 34 may perform error detection operations and / or error correction operations (ECC), and may be disposed external to the remote computing device 12 so that error detection and error correction operations may continue if power to the remote computing device 12 is lost. For simplicity of description, the operation of the service processor is described as being included in and performed by the memory controller 34, but it should be noted that in some embodiments, error correction operations or data recovery operations may be employed as functions performed by the service processor, processing circuitry 24, or additional processing circuitry located within or external to the remote computing device 12 or client device 14.

[0037] The memory module 26 is Figure 2 26 as a single device that includes various components or sub-modules. In some examples, remote computing device 12 may include one or several discrete components equivalent to the various devices, modules, and components that make up memory module 26. For example, remote computing device 12 may include non-volatile memory, volatile memory, and a controller located on one or several different chips or substrates. In other words, the features and functions of memory module 26 do not have to be employed in a single module to achieve the benefits described herein.

[0038] As described above, the memory module 26 may store information as data in a data block 32. The die 48 of the memory module 26 may store the data block 32. The data block 32 may be stored in a portion 50 of the die 48 or across multiple portions 50. The portion 50 may store any amount of bits and thus be designed for a particular application of the memory module 26. As an example, the portion 50 of memory may store 512 megabits (MB). In this manner, the portion 50 of memory may be considered a unit of memory, a bank of memory, a partition of memory, a portion of the memory module 26, an entire memory module 26, or the like. However, as depicted, for ease of discussion, the portion 50 may be a portion of memory that is considered smaller than the portion of memory allocated as the die 30.

[0039] When processing circuitry 24 requests access to data stored in memory module 26, processing circuitry 24 may issue commands. The commands may include instructions to perform a read operation to operate memory controller 34 to facilitate retrieval of information stored in one of portions 50. Sometimes, the commands include instructions to perform a write operation to operate memory controller 34 to facilitate storage of information in one of portions 50. Other commands may be used to instruct memory controller 34 to perform other operations.

[0040] Over time, some physical addresses of memory may be accessed more frequently than other physical addresses of memory, which may age some portions of memory at a relatively faster rate than other portions of memory. To elaborate, Figure 3 for Figure 2 Block diagram of the memory module after the duration. Figure 3 Memory modules 26 may be affected by relatively unequal aging and / or unequal memory access, which is illustrated by using different shading to emphasize relatively more or relatively less access to portions 50. For example, memory device 30B is accessed relatively more times than memory device 30D, and thus portion 50 of memory device 30B may experience component aging at a faster rate than portion 50 of memory device 30D.

[0041] To compensate for under-optimized memory accesses, the memory controller 34 may adjust the L2P table based on commands issued by the host device (e.g., a historical data set indicating traffic patterns associated with accesses of the memory controller 34). For example, the memory controller 34 may adjust the L2P table to take into account physical addresses that are relatively more frequently accessed than other physical addresses and / or to take into account physical addresses that are relatively more frequently accessed after other physical addresses. By adjusting the L2P table based on the most frequently accessed physical addresses, the memory controller 34 may preemptively reduce or eliminate uneven aging and / or uneven memory accesses because the adjusted L2P table may make traffic patterns between portions of the memory relatively more equal or equal. Additionally or alternatively, by adjusting the L2P table based on frequently subsequently accessed physical addresses, addresses that are expected to be accessed after each other may be used to address physical locations of memory that are independent of each other, such as different memory banks and / or different portions of memory.

[0042] Figure 4 An example of a controller 34 operating to compensate for a suboptimal memory access pattern is shown in FIG. Figure 4 1 is an illustration of a memory controller 34 operating to adjust an original logical-to-physical table (L2P table) to preemptively compensate for frequently sequentially accessed addresses (e.g., memory accesses). The memory controller 34 may receive as input various traffic data sets 60 (60A, 60B, 60C) and a current L2P table 62. The current L2P table 62 may be an original L2P table or may be a previously adjusted L2P table that the memory controller 34 currently references for memory operations (e.g., read operations, write operations).

[0043] The memory controller 34 may use the traffic data sets 60 to dynamically change the current L2P table 62 to a new L2P table 64. To do so, the memory controller 34 may analyze one or more of the traffic data sets 60. From the analysis, the memory controller 34 may learn which portions of the memory module 26 are frequently accessed sequentially with respect to each other. For example, the memory controller 34 may analyze one of the traffic data sets 60 to determine that a first portion 50 is frequently accessed (e.g., sequentially accessed a threshold number of times) just before a second portion 50 is accessed. In response to the memory controller 34 identifying portions of the memory module 26 that are accessed more frequently by a threshold amount of accesses and / or are accessed sequentially by a threshold amount of accesses, the memory controller 34 may generate a new L2P table 64 to compensate for these access patterns.

[0044] The memory controller 34 may alter the L2P mapping of the memory modules 26 to compensate for any undesirable access patterns. For example, the memory controller 34 may change the physical location addressed by a subsequently accessed logical address to a reference location on an independent operating portion of memory (e.g., a portion of memory on a different memory bank, a different memory die 50). The memory controller 34 may interchange memory addresses such that one or more frequently accessed addresses are replaced by less frequently accessed addresses, e.g., the most frequently accessed address may be replaced by the least frequently accessed address, the second most frequently accessed address may be replaced by the second least frequently accessed address, and so on.

[0045] In some cases, portions 50 may be interchangeable, but it should be understood that undesirable memory access patterns may be compensated for at any suitable granularity of memory access, such as at the level of memory die 48. In some cases, memory controller 34 may not be the controller that adjusts memory access patterns in response to traffic data set 60. When the controller that adjusts memory access patterns is processing circuitry 24 or some other system-level controller (e.g., as opposed to memory module-level memory controller 34), current L2P table 62 may be adjusted to compensate for undesirable access patterns between memory modules 26.

[0046] Each of the traffic data sets 60 may include real-time traffic data, test traffic data, historical traffic data, or the like. In this manner, each of the traffic data sets 60 may be a representative traffic sample for a given workload. Real-time traffic data may be information associated with memory read and write operations that are stored and analyzed by the memory controller 34 in real time or while the memory read and write operations are in progress. Memory transactions (e.g., individual read or write operations occur) may be recorded by the memory controller 34 over time until a certain amount of memory transaction data is recorded to form the traffic data set 60 (e.g., 60A, 60B, 60C). The certain amount of memory transaction data may be defined by a threshold value, such that the memory controller 34 monitors and records memory transactions until the number of memory transactions is greater than or equal to the threshold amount of memory transactions. In response to the number of memory transactions being greater than or equal to the threshold amount, the memory controller 34 may associate the memory transactions as part of the traffic data set 60. In this manner, the traffic data set 60 may indicate real memory operations. When test traffic data is used, the memory transactions may simulate or be a collection of sample data based on real memory transactions, or generally expected memory traffic patterns may be used. Furthermore, in some cases, data values ​​that may or may not simulate or represent real memory traffic patterns may be used as test traffic data, or as generally expected memory traffic patterns. Furthermore, in some cases, the memory controller 34 may store memory transaction data over time, and later (e.g., several days or months later) use the stored memory transaction data as the traffic data set 60.

[0047] In some embodiments, the memory controller 34 may also consider performance when adjusting the L2P table to improve the physical address access distribution (e.g., reduce the amount of sequential accesses to the same portion 50 of memory). For example, the memory controller 34 may use a deep learning operation that uses the read or write operation time as a cost (e.g., input) and uses the new L2P table 64 as a knob (e.g., variable) to adjust to optimize the cost. An example of a deep learning operation may include using a long short-term memory (LSTM) artificial recurrent neural network. In this way, the memory controller 34 may test various qualifying address allocations before selecting a final address allocation combination that will be output as the final L2P table 64. The memory controller 34 may determine an arrangement of address allocations that minimizes cost while maximizing the reallocation of some addresses (specifically, addresses that are accessed relatively more frequently sequentially one after another or for a duration such that processing of a second command waits until processing of a first command ends). In this manner, when reallocating physical addresses to logical addresses, the memory controller 34 may consider memory access latency (e.g., defined as the cost of a read or write operation time) and reallocation percentage (e.g., the percentage of overused or relatively more sequentially accessed portions of memory reallocated to relatively less sequentially accessed portions of memory). For example, the memory controller 34 may consider a comparison between the total duration of one or more read and / or write operations for the first L2P table adjustment option and the second L2P table adjustment option to determine which resulting L2P table corresponds to a more appropriate adjustment and / or optimization.

[0048] When the memory controller 34 uses deep learning operations, the memory controller 34 may train a final L2P table 64 on one or more traffic data sets 60. A subset of the traffic data of the traffic data set 60 may be reserved for testing of the trained L2P table 64 in order to verify the performance of the adjusted logical-to-physical address allocation. The performance of the trained L2P table 64 may be tested to see how the access speed or access distribution changes after training or adjustment. For example, the memory controller 34 may verify the performance of the new L2P table 64 (e.g., the trained L2P table 64) by comparing the performance results of the new L2P table 64 with the previous performance results of the current L2P table 62 or with the default settings of the logical-to-physical allocation (e.g., the original L2P table for the memory controller 34).

[0049] Changes may be applied to the new L2P table 64 over time and / or as part of an iterative process, such as by adjusting a subset of logical addresses from a set of logical addresses to be adjusted. In this manner, the memory controller 34 may perform one or more rounds of improvements to the current L2P table 62 such that the new L2P table 64 becomes incrementally improved over time. For example, a first current L2P table 62 may be adjusted and output as a new L2P table 64, which is used as a second current L2P table 62 at the next iteration, adjusted and output as a subsequent new L2P table 64. Any number of iterations may be performed by the memory controller 34 to adjust the current L2P table 62 to compensate for sequential access patterns. In some cases, a threshold number of iterations may be defined and used to control the maximum number of iterations to be performed by the memory controller 34.

[0050] Because the memory controller 34 is monitoring accesses and access patterns, the memory controller 34 can preemptively compensate for memory access patterns before they affect components of the computing system 10. For example, when the memory controller 34 adjusts the L2P table before an undesired access pattern affects the memory module 26, sequential accesses can be preemptively (e.g., actively) prevented due to actively compensating for accesses to portions of memory. Preemptive adjustment of the L2P table can occur in response to the memory controller 34 determining that the queued command corresponds to a dependent portion of memory and determining to adjust the L2P table to change, for example, the location in memory where data is written so as to be able to proceed synchronously with another memory access.

[0051] To detail example operations of memory controller 34, Figure 5 Flowchart of process 76 for preemptively compensating for memory access patterns. Memory controller 34 is described below as performing process 76, but it should be understood that any suitable processing circuitry may additionally or alternatively perform process 76. Furthermore, while process 76 is described below as being performed in a particular order, it should be understood that any suitable order may be used to perform the individual operations of process 76.

[0052] At block 78, the memory controller 34 may receive a training data set. The training data set may include one or more traffic data sets 60 and / or one or more portions of one or more traffic data sets 60. As described above, the traffic data set 60 may include real-time traffic data, test traffic data, historical traffic data, or the like. In some cases, the memory controller 34 may divide the traffic data set 60 and / or the data portion of the traffic data set 60 into a training data set and a test data set.

[0053] At block 80, the memory controller 34 may use the training data set and / or the traffic data set 60 to determine one or more sequentially accessed logical addresses. The memory controller 34 may use a threshold value to identify an expected trend of sequentially accessed logical addresses. For example, the memory controller 34 may use a threshold amount of memory accesses to determine when a sequential access pattern occurs a sufficient number of times to correspond to an expected (e.g., preemptively anticipated) sequential access pattern, because a relatively small number (e.g., less than the threshold amount of occurrence) of sequential accesses of two or more logical addresses may not necessarily benefit from reallocation or adjustment of the L2P table. The threshold value may define a threshold number of memory accesses relative to other amounts of memory accesses. In this way, the memory controller 34 may identify a portion of the memory module 26 that is accessed a greater than the threshold amount of times relative to a different portion of the memory, and thus determine that accesses to a first portion of the memory (e.g., a first portion 50 on the same die 48) and a second portion of the memory (e.g., a second portion 50 on the same die 48) are accessed sequentially.

[0054] At block 82, the memory controller 34 may generate a new L2P table 64 to compensate for the sequentially accessed logical addresses. In this manner, the memory controller 34 may adjust the logical addresses to the physical address assignments so that the sequentially referenced logical addresses are translated to physical addresses associated with separate portions of memory (e.g., different memory banks, different dies 48, different portions 50). As discussed above, the memory controller 34 may interchange the physical addresses assigned to the logical addresses via the L2P table so that the portions 50, dies 48, and / or memory devices 30 are accessed in different modes according to the same logical addressing. The memory controller 34 may adjust the current L2P table 62 to generate the new L2P table 64 and / or generate the new L2P table 64 independent of the existing data structure storing the current L2P table 62. In some cases, the memory controller 34 may generate a set of eligible new L2P tables 64 and use the operations of block 84 to evaluate the set of eligible new L2P tables 64 for selection at block 86. To generate each of the set of eligible new L2P tables 64, the memory controller 34 may systematically vary one or more aspects (e.g., variables) of the first new L2P table 64 to test different options for the new L2P table 64. In this manner, the memory controller 34 may determine an appropriate arrangement of L2P tables that minimizes read or write latency while improving the distribution of relatively more frequently accessed logical addresses of the memory (e.g., reallocating physical addresses corresponding to independent portions of the memory). Thus, the memory controller 34 may adjust the current L2P table 62 to test various eligible address allocations (e.g., a set of eligible new L2P tables 64) before selecting a final address allocation combination to be output as the final L2P table 64. For example, in response to determining that a first portion 50 of the memory is accessed sequentially with accessing a second portion 50 of the memory, the memory controller 34 may generate a plurality of logical-to-physical tables that each include allocating logical addresses that originally corresponded to physical addresses of the first portion 50 of the memory to physical addresses that now correspond to a third portion 50 of the memory (e.g., a portion of the memory that is independent of the second portion 50 of the memory).

[0055] At block 84, the memory controller 34 may evaluate the performance of the set of qualified new L2P tables 64. The memory controller 34 may test each of the set of qualified new L2P tables 64 using a test data set (e.g., one or more portions of the traffic data set 60) to obtain performance indicators. Each performance indicator of each of the set of qualified new L2P tables 64 may be compared to a corresponding performance indicator of the current L2P table 62 or a default setting of the memory controller 34. The comparison between the performance indicators may produce a performance improvement indicator that indicates whether the performance is improved or not improved (e.g., resulting in faster memory access, resulting in equal memory access speed with relatively more equal access distribution, resulting in reduced read or write latency). The performance improvement indicator may indicate an improvement in the performance of a particular L2P table in the set of qualified new L2P tables 64. In this manner, the memory controller 34 may evaluate the performance of the set of qualified new L2P tables 64 based at least in part on the performance improvement indicator to determine a suitable combination of changes to the current L2P table 62 that results in desired or maximized performance. In some cases, the memory controller 34 may use a deep learning operation (e.g., LSTM) that uses the read or write operation time (e.g., read or write latency) as a cost and uses the new L2P table 64 as a knob (e.g., variable) to adjust to optimize the cost.

[0056] At block 86, the memory controller 34 may select a final new L2P table 64 from the set of qualified new L2P tables 64, and may use the final new L2P table 64 in the buffer memory 46. Thus, the L2P table may be selected from the plurality of L2P tables generated and tested at block 84 to evaluate the memory access latency of each of the plurality of L2P tables. In some cases, the current L2P table 62 may be retained in memory as a backup L2P table and / or for future reference. The new L2P table 64 may be written to the buffer memory 46 to overwrite the current L2P table 62. In this manner, the memory controller 34 replaces the current L2P table 62 and uses the new L2P table 64 for future memory accesses (e.g., the new L2P table 64 used by the memory controller 34). For example, the memory controller 34 may store a first L2P table (e.g., the current L2P table 62) as an original logical-to-physical table in the buffer memory 46, generate a second L2P table (e.g., the new L2P table 64) using the first L2P table after adjusting the first L2P table, such as at box 82, and may overwrite the first L2P table in the buffer memory 46 with the second L2P table so that the memory controller 34 uses the second L2P table when performing logical-to-physical address translation.

[0057] It should be noted that although Figure 1, client device 14 is depicted as being communicatively coupled to remote computing device 12, and in some embodiments, the systems and methods described above may be used for memory controller 34 of client device 14. The techniques described herein may be used in combination with various memory types and computing structures to achieve the benefits described herein.

[0058] In some cases, the memory controller 34 may use a traffic data set 60 that includes an indication of the workload type. In this way, the resulting new L2P table 64 may be selected based at least in part on the workload type operating the memory controller 34. For example, some memories (e.g., memory chips) have several memory banks that can be operated in parallel, such as sixteen memory banks that are sometimes operated in parallel. The current L2P table 62 for different workloads may be optimized or designed to increase the probability that consecutive commands to different memory banks can be executed in parallel, thereby resulting in performance improvements for the memory (e.g., faster speed to complete memory transactions). An example of a workflow may include different software applications used by the same computing device and accessing the memory module 26 during the execution of the software application. When designing the L2P table for a particular workload, the logical address may initially reference a physical address of a portion 50 of memory disposed or located within the same memory die 48 or the same memory device 30. During the example workflow, the memory controller 34 may sequentially access logical addresses of the reference portion 50 of memory (e.g., the same portion of memory, the same memory die 48, the same memory device 30) that are not capable of being processed in parallel. These sequential access patterns involving logical addresses may be identified, and the logical addresses may be reassigned physical addresses corresponding to portions 50 disposed on or within different memory dies 48 or different memory devices 30 such that the logical addresses are assigned physical addresses that reference independent portions of memory. In this manner, workloads that sequentially access logical addresses may cause the memory controller 34 to access different portions 50 of memory in parallel because the physical address reference portions 50 of memory can be processed in parallel (e.g., because the physical address reference portions 50 of memory are operated independently). In some embodiments, the workload type may be identified to the memory controller 34, which may be able to pre-populate a new L2P table 64 selected for load in response to the type of workload. For example, the L2P table 64 may be stored and loaded by a computing device (e.g., a memory controller 34 of the computing device) in response to a corresponding software application being executed on the computing device.

[0059] In some embodiments, refinement of current L2P table 62 (e.g., to generate new L2P table 64) may be performed after manufacturing time during operation of computing system 10. In this manner, current L2P table 62 may be updated over time and over the device life of computing system 10. In some cases, refinement of the L2P table may be performed while computing system 10 is in a reduced power mode, idle, offline, or otherwise not accessing memory modules 26, so that new L2P table 64 may be available to memory controller 34 without interrupting ongoing memory processes. For example, Figure 5 The operation may be performed by the memory controller 34 when the memory controller 34 is not in the middle of another memory operation (eg, a read operation, a write operation, a refresh operation) in progress.

[0060] In some embodiments, determining the relatively more accessed portion of the memory module 26 and / or determining the final adjustment to the L2P table may include the memory controller 34 performing a difference analysis to identify a difference in the amount of accesses that is greater than an access threshold amount. For example, the first portion 50 may have been accessed 10 times, the second portion 50 may have been accessed 50 times, and the access threshold amount may be a difference equal to 15 accesses. Because the difference between the accesses of the first portion 50 and the second portion 50 is 40 and the access threshold amount corresponds to a difference equal to 15 accesses, the memory controller 34 may identify the second portion 50 as being relatively more overused. In this manner, the memory controller 34 may sometimes adjust the logical address to physical address allocation to make the less accessed portion of the memory module 26 relatively more frequently accessed.

[0061] Additionally or alternatively, in some embodiments, Figure 5Identifying overused portions of the memory module 26 at block 80 of the present invention may include identifying overused portions of the memory module 26 and / or relatively underused portions of the physical addresses. For example, the memory controller 34 may determine that the first portion 50 is accessed more frequently than the second portion 50 by analyzing, at least in part, a first number of memory transactions (e.g., memory read operations, memory write operations, memory refresh operations) involving the first portion 50 during a time period, analyzing a second number of memory transactions involving the second portion 50 during the same time period, and determining that the first number is greater than the second number. The time periods may be of the same duration, such that the time periods share a start and end time, and / or the time periods may be of the same duration relative to a start time (e.g., equal duration segments that do not necessarily start at the same start time). The time period may be a monitoring period used in comparing accesses to portions of the memory and / or analyzing traffic patterns associated with memory accesses. It should be noted that in some embodiments, a counter may be used to count physical address accesses. The counter may count up to an access threshold or may count down from an access threshold in response to a particular physical address being accessed. Any suitable type and number of counters may be used, for example, each address may correspond to a counter and / or a set of addresses may correspond to a counter.

[0062] The technical effects of the present disclosure may include improving memory operations by compensating for memory access patterns (e.g., unequal access patterns, sequential logical address access patterns) of the memory. The memory controller may identify logical addresses that are frequently accessed sequentially with each other and reallocate logical addresses corresponding to the identified logical addresses that are accessed sequentially to different physical addresses. This may enable the reallocation of logical addresses to physical addresses corresponding to portions of memory that are less used and / or corresponding to independent portions of memory, thereby allowing parallel memory access operations of independent portions of memory. The reallocation of logical addresses to new or adjusted physical addresses may be stored in a new and / or updated L2P table. A memory controller that manages access to memory according to a new and / or updated L2P table may improve the performance of a memory system.

[0063] In view of these technical effects, multiple memory devices may be included on a memory module, thereby enabling the memory devices to be communicatively coupled to a processing circuit as a unit. For example, a dual in-line memory module (DIMM) may include a printed circuit board (PCB) and multiple memory devices. The memory module is communicatively coupled to a client device or a host device via a communication network in response to a command from a memory controller. Or in some cases, a memory controller may be used on the host side of a memory host interface; for example, a processor, a microcontroller, an FPGA, an ASIC, or the like may each include a memory controller. This communication network may enable data communication therebetween, and therefore, the client device utilizes hardware resources accessible through the memory controller. Based at least in part on user input to the client device, the processing circuit system of the memory controller may perform one or more operations to facilitate retrieval or transmission of data between the client device and the memory device. The data transmitted between the client device and the memory device may be used for various purposes, including but not limited to presenting visualization, processing operations, calculations, or the like to a user through a graphical user interface (GUI) at the client device. Therefore, in this regard, the above-mentioned improvements to memory controller operations and memory write operations may manifest as improvements in visualization quality (eg, drawing speed, drawing quality), improvements in processing operations, improvements in calculations, or the like.

[0064] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments are susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the specific forms disclosed, but are intended to cover all modifications, equivalents and alternatives within the spirit and scope of the present disclosure.

[0065] The technology presented and claimed herein refers to and applies to substantial objects and specific examples of practical nature, which improve the technical field of the present invention in a demonstrable manner and are therefore not abstract, intangible or purely theoretical. In addition, if any claim item attached to the end of this specification contains one or more elements expressed as "a means for [performing] [a function] ..." or "a step for [performing] [a function] ...", it is expected that such elements will be interpreted in accordance with 35 U.S.C. 112 (f). However, for any claim containing elements specified in any other manner, it is expected that such elements will not be interpreted according to 35 U.S.C. 112 (f).

Claims

1. A device comprising: a memory including a first portion, a second portion, and a third portion; and A memory controller comprising a buffer memory configured to store a first logical-to-physical table, wherein the memory controller is configured to: determining that the first portion and the second portion are accessed sequentially to obtain an address access pattern; In response to obtaining the address access pattern, determining a memory access latency associated with the address access pattern; and In response to determining the memory access latency, the first logical-to-physical table is adjusted so that memory transactions addressing the first portion access the third portion independently of the second portion.

2. The apparatus of claim 1 , wherein the memory controller is configured to: storing the first logical-to-physical table as an original logical-to-physical table in the buffer memory; generating a second logical-to-physical table using said first logical-to-physical table after said adjustment of said first logical-to-physical table; and The first logical-to-physical table is overwritten in the buffer memory with the second logical-to-physical table, wherein the memory controller is configured to access the memory using the second logical-to-physical table.

3. The device of claim 1, wherein the memory comprises a flash memory, a NAND memory, a phase change memory, a 3D XPoint TM At least one of a memory or a ferroelectric random access memory or any combination thereof. 4 . The apparatus of claim 1 , wherein the memory controller is configured to adjust the first logical-to-physical table in response to determining that the first portion and the second portion are accessed sequentially a number of times greater than a threshold.

5. The apparatus of claim 4, wherein the first portion is accessed as part of one or more of: Memory read operations; Memory write operations; and Memory refresh operation. 6 . The apparatus of claim 1 , wherein the memory comprises a first die comprising the second portion and a second die comprising the third portion.

7. The apparatus of claim 1 , wherein the memory controller is configured to adjust the first logical-to-physical table at least in part by changing a first logical address from addressing the first portion to addressing the third portion so that the memory transaction performed by the memory controller accesses the third portion instead of the first portion.

8. The apparatus of claim 7, wherein the memory controller is configured to change the first logical address from addressing the first portion to addressing the third portion at least in part by: identifying in the first logical-to-physical table that the first logical address corresponds to a first physical address of the first portion; identifying in the first logical-to-physical table that a second logical address corresponds to a second physical address of the third portion; and A second logical-to-physical table is generated at least in part by reallocating the first logical address to correspond to the second physical address and by reallocating the second logical address to correspond to the first physical address.

9. The apparatus of claim 1 , wherein the memory controller is configured to: Receive a training dataset; determining, based at least in part on the training data set, that the first portion is accessed more frequently than the second portion; generating a plurality of logical-to-physical tables, the plurality of logical-to-physical tables each compensating for the first portion being accessed more frequently than the second portion; and One of the plurality of logical-to-physical tables is selected to be used in adjusting the first logical-to-physical table.

10. The apparatus of claim 9, wherein the memory controller is configured to select one of the plurality of logical-to-physical tables based at least in part on a comparison of the memory access latency, the comparison of the memory access latency comprising a comparison of a read latency, a write latency, or both, for each of the plurality of logical-to-physical tables.

11. The apparatus of claim 1, wherein the memory controller is configured to determine that the first portion and the second portion are accessed sequentially after completing a memory write operation, a memory read operation, a memory refresh operation, or any combination thereof.

12. A method for operating a memory controller, comprising: receiving a traffic data set including a plurality of data indicating access frequencies of a plurality of portions of memory communicatively accessed by the memory controller, wherein the traffic data set is generated when the memory controller uses a first assignment such that a first logical address corresponds to a first physical address in a first portion of the plurality of portions; determining that the first portion and a second portion of the plurality of portions are accessed sequentially to obtain an address access pattern; In response to obtaining the address access pattern, determining a memory access latency associated with the address access pattern; responsive to determining the memory access latency, generating a second allocation such that the first logical address corresponds to a third physical address of a third portion; and The second allocation is stored in a buffer memory configured to store the first allocation to overwrite the first allocation in the buffer memory.

13. The method of claim 12, wherein determining that the first portion and the second portion are accessed sequentially comprises determining that the first portion and the second portion are accessed sequentially a greater amount during the duration than the first portion and the third portion are accessed sequentially during the duration.

14. The method of claim 12, comprising generating the second allocation based at least in part on an evaluation of a plurality of allocations.

15. The method of claim 14, wherein the second allocation is selected from the plurality of allocations in response to the second allocation producing a relatively lowest read or write latency from a plurality of read or write latencies respectively produced by the plurality of allocations.

16. A semiconductor device comprising: a memory comprising a first portion, a second portion, and a third portion, wherein the first portion and the third portion are configured to be accessed at least partially in parallel; and A memory controller comprising a buffer memory, wherein the memory controller is configured to: Determining that the first part and the second part are accessed in sequence; responsive to determining that the accesses of the first portion and the second portion are accessed sequentially, generating a plurality of logical-to-physical tables, the plurality of logical-to-physical tables each comprising an assignment of a logical address to be used to access the third portion, wherein the logical address was used to access the first portion at a previous time; selecting a first logical-to-physical table from the plurality of logical-to-physical tables based at least in part on an evaluation of a memory access latency of each of the plurality of logical-to-physical tables; and The first logical-to-physical table is stored in the buffer memory to overwrite the second logical-to-physical table.

17. The semiconductor device of claim 16 , wherein the memory controller is configured to repeat the generation of the plurality of the logical-to-physical tables and the selection of corresponding logical-to-physical tables until a number of iterations corresponding to a number of repetitions is greater than or equal to a threshold number of iterations. 18 . The semiconductor device of claim 16 , wherein the memory controller is configured to adjust the second logical-to-physical table when generating the plurality of logical-to-physical tables so that a memory transaction performed by the memory controller accesses the third portion instead of the first portion.

19. The semiconductor device according to claim 16, wherein the memory controller is configured to: identifying a set of first portions that are accessed more frequently than a set of second portions, wherein the set of first portions includes the first portion, and wherein the set of second portions includes the second portion; and The plurality of logical-to-physical tables are generated to correspond to a plurality of allocation options that reallocate at least some of the set of the first portions to physical addresses corresponding to at least some of the set of the second portions.

20. The semiconductor device of claim 19, wherein the memory controller is configured to select the first logical-to-physical table from the plurality of logical-to-physical tables based at least in part on a determination that takes into account the memory access latency and a reallocation percentage of a set of the first portions.

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