Identifying Multi-Scale Features Using Neural Networks

Abstract

Apparatus, system, and technique for identifying features within one or more images. Features within one or more images are identified using one or more neural networks that include a convolutional layer having a plurality of filters executable by one or more parallel processing units.

Description

Technical Field

[0001] At least one embodiment relates to an improved convolutional layer in a convolutional neural network for facilitating and performing artificial intelligence. For example, at least one embodiment relates to processors and computing systems for identifying features in parallel in a convolutional layer according to various novel techniques described herein. Background Art

[0002] Performing convolutional layer steps to generate a feature map in a convolutional neural network increases complexity based on the features identified in one or more input data items. The amount of memory, time, and computational resources required to identify a particular feature in the data increases with each feature to be identified. Typically, the resources and computational complexity increase due to each filter required to identify each individual feature in the convolutional layer. These resources and computational complexity further increase when the input data includes multiple individual information layers. In particular, for each information layer in the set of input data items, for each feature to be identified, the convolutional layer in the convolutional neural network will need to apply an individual filter of a particular size to each layer in the set of input data items. Since the operation of applying a filter to each layer in the set of input data items produces an individual output for each filter applied (e.g., in a separable convolutional layer), pointwise operations must be performed to aggregate the different filter information into the output feature map for each input data item. As more and more complex features are identified in the dataset, the filter count and associated resource requirements increase significantly. Brief Description of the Drawings

[0003] Figure 1 Shows an example convolutional neural network according to at least one embodiment;

[0004] Figure 2A Shows a vertical line feature in an input data item according to at least one embodiment;

[0005] Figure 2B Shows a horizontal line feature in an input data item according to at least one embodiment;

[0006] Figure 2C Shows a multi-scale feature in an input data item according to at least one embodiment;

[0007] Figure 3 Shows depthwise convolution in a convolutional layer of a convolutional neural network according to at least one embodiment;

[0008] Figure 4 Shows pointwise convolution in a convolutional layer of a convolutional neural network according to at least one embodiment;

[0009] Figure 5Shows a separable convolutional layer in a convolutional neural network according to at least one embodiment;

[0010] Figure 6 Shows an architecture for performing depthwise convolution in a spatially adaptive separable convolutional layer of a convolutional neural network according to at least one embodiment;

[0011] Figure 7 Shows a spatially adaptive separable convolutional layer in a convolutional neural network according to at least one embodiment;

[0012] Figure 8 Shows a process for generating a feature map in a spatially adaptive separable convolutional layer according to at least one embodiment;

[0013] Figure 9A Shows an inference and / or training logic according to at least one embodiment;

[0014] Figure 9B Shows an inference and / or training logic according to at least one embodiment;

[0015] Figure 10 Shows the training and deployment of a neural network according to at least one embodiment;

[0016] Figure 11 Shows an example data center system according to at least one embodiment;

[0017] Figure 12A Shows an example of an autonomous vehicle according to at least one embodiment;

[0018] Figure 12B Shows according to at least one embodiment Figure 12A an example of the camera positions and fields of view of an autonomous vehicle;

[0019] Figure 12C Is a block diagram showing an example system architecture of an autonomous vehicle according to at least one embodiment Figure 12A of;

[0020] Figure 12D Is a diagram showing a system for communication between one or more cloud-based servers and an autonomous vehicle according to at least one embodiment Figure 12A of;

[0021] Figure 13 Is a block diagram showing a computer system according to at least one embodiment;

[0022] Figure 14 Is a block diagram showing a computer system according to at least one embodiment;

[0023] Figure 15Shows a computer system according to at least one embodiment;

[0024] Figure 16 Shows a computer system according to at least one embodiment;

[0025] Figure 17A Shows a computer system according to at least one embodiment;

[0026] Figure 17B Shows a computer system according to at least one embodiment;

[0027] Figure 17C Shows a computer system according to at least one embodiment;

[0028] Figure 17D Shows a computer system according to at least one embodiment;

[0029] Figure 17E and Figure 17F Shows a shared programming model according to at least one embodiment;

[0030] Figure 18 Shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0031] Figure 19A - Figure 19B Shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0032] Figure 20A - Figure 20B Shows additional exemplary graphics processor logic according to at least one embodiment;

[0033] Figure 21 Shows a computer system according to at least one embodiment;

[0034] Figure 22A Shows a parallel processor according to at least one embodiment;

[0035] Figure 22B Shows a partitioning unit according to at least one embodiment;

[0036] Figure 22C Shows a processing cluster according to at least one embodiment;

[0037] Figure 22D Shows a graphics multiprocessor according to at least one embodiment;

[0038] Figure 23 Shows a multi-graphics processing unit (GPU) system according to at least one embodiment;

[0039] Figure 24 Shows a graphics processor according to at least one embodiment;

[0040] Figure 25 is a block diagram showing a processor micro - architecture for a processor according to at least one embodiment;

[0041] Figure 26 shows a deep - learning application processor according to at least one embodiment;

[0042] Figure 27 is a block diagram showing an example neuromorphic processor according to at least one embodiment;

[0043] Figure 28 shows at least a portion of a graphics processor according to one or more embodiments;

[0044] Figure 29 shows at least a portion of a graphics processor according to one or more embodiments;

[0045] Figure 30 shows at least a portion of a graphics processor according to one or more embodiments;

[0046] Figure 31 is a block diagram of a graphics processing engine 3110 of a graphics processor according to at least one embodiment;

[0047] Figure 32 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0048] Figure 33A - Figure 33B shows thread execution logic 3300 according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0049] Figure 34 shows a parallel processing unit (“PPU”) according to at least one embodiment;

[0050] Figure 35 shows a general - purpose processing cluster (“GPC”) according to at least one embodiment;

[0051] Figure 36 shows a memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment; and

[0052] Figure 37 shows a streaming multiprocessor according to at least one embodiment. DETAILED DESCRIPTION

[0053] Figure 1A convolutional neural network according to at least one embodiment is shown, which includes several convolutional layers 104, 112. The convolutional layers 104, 112 are responsible for identifying features included or shown in one or more input data items 102. In at least one embodiment, the convolutional neural network uses one or more input data items 102 to assist computer vision applications. The input data items include, for example, an input image containing multiple layers representing color channels, and other information when available.

[0054] In at least one embodiment, the convolutional neural network includes multiple layers, including those for feature learning 104, 106, 108, 110, 112, 114, 116, 118, and those for classification 120, 122. In at least one embodiment, the convolutional neural network will obtain an input image containing multiple layers and assign importance to aspects, features, or objects in each input image during the feature learning stages 104, 106, 108, 110, 112, 114, 116, 118. In at least one embodiment, the classification stage will obtain information about aspects, features, or objects in one or more input images and use the trained neural network to classify those aspects, features, or objects in the one or more input images.

[0055] In at least one embodiment, the system trains the convolutional neural network to generate feature maps 106, 110, 114, 118 containing information about aspects, features, or objects in the input image during the feature learning stages 104, 106, 108, 110, 112, 114, 116, 118. In at least one embodiment, the feature learning stages 104, 106, 108, 110, 112, 114, 116, 118 include multiple steps, in which the convolutional layers 104, 112 are applied to a two-dimensional data matrix, such as a feature map.

[0056] In at least one embodiment, one or more convolutional layers form feature learning stages 104, 106, 108, 110, 112, 114, 116, 118. In at least one embodiment, one or more convolutional layers will include a set of filters (also referred to as kernels, feature extractors, and matrices), where each filter is applied to data in an image to obtain the width and height of the image for each layer in the image. In at least one embodiment, convolutional layers 104, 112 will take as input multiple feature maps 106, 114 representing data layers, such as the red layer, green layer, and blue layer in an RGB image. In at least one embodiment, feature maps 106, 114 are two-dimensional matrices of values associated with the image, where each value can represent one or more aspects of the input image(s) 102. In at least one embodiment, one or more aspects of the input image(s) 102 represented in the feature map can be probabilities associated with the likelihood of aspects or positions present in the image 102 or in the layers of the image.

[0057] In at least one embodiment, a filter is a small matrix. In at least one embodiment, a filter can be used to identify features of an image, as well as perform blurring, sharpening, embossing, edge detection, or other image-related filtering operations. In at least one embodiment, a filter or kernel will be applied to an image through a convolution operation, which can include performing a dot product operation across all dimensions of the input image. In at least one embodiment, convolutional layers 104, 112 can include one or more filters.

[0058] In at least one embodiment, convolutional layers 104, 112 can include a depthwise convolution stage and a pointwise convolution stage. In at least one embodiment, depthwise convolution will apply one or more filters across the width and height of the input image 102 or feature maps 106, 114. In at least one embodiment, depthwise convolution will apply one or more filters or kernels across a subset of the width and height of the input image 102 or feature maps 106, 114. In at least one embodiment, the application of one or more filters or kernels can be used to identify features in the image 102 or feature maps 106, 114. In at least one embodiment, a set of feature maps output from depthwise convolution will contain information about aspects, features, or objects in the input set of the image 102 or feature maps 106, 114. In at least one embodiment, the pointwise convolution operation in a convolutional layer will apply the convolution operation on a per-pixel basis to each feature map generated by depthwise convolution. In at least one embodiment, pointwise convolution will combine the information contained in each feature map generated by depthwise convolution, as further described below.

[0059] In at least one embodiment, the convolutional layers 104, 112 will generate one or more feature maps 106, 114. In at least one embodiment, one or more pooling layers 108, 116 will reduce the size of the feature maps 106, 114 after the convolutional layers 104, 112. In at least one embodiment, one or more pooling layers 108, 116 reduce the feature map size in order to reduce the computational power requirements in subsequent convolutional layers 104, 112 or other operations 120 in the convolutional neural network.

[0060] In at least one embodiment, one or more pooling layers 108, 116 can be max pooling layers or average pooling layers. In at least one embodiment, a max pooling layer returns the maximum value from a portion of the input image or feature map that has been processed by the kernels in the convolutional layers 104, 112. In at least one embodiment, an average pooling layer returns the average of all values from a portion of the input image or feature map that has been processed by the kernels in the convolutional layers 104, 112.

[0061] In at least one embodiment, after a predetermined number of convolutional layers 104, 112 and subsequent pooling layers 108, 116 have extracted aspects, features, or objects from the input image or feature map, a classification stage 120 is performed to generate an output 122 that includes the corresponding probabilities for each classification. In at least one embodiment, fully connected layers 120 can be used to learn the non - linear combination of high - level features identified by the feature learning stage 104, 106, 108, 110, 112, 114, 116, 118. At least in one embodiment, the fully connected layers 120 can include several steps. In at least one embodiment, the fully connected layers 120 can flatten the input set of feature maps into a one - dimensional vector. In at least one embodiment, additional steps can be performed at 120. In at least one embodiment, the flattened representation of the data is fed into a feed - forward neural network as described below, and backpropagation is used to train the neural network through iterative training. In at least one embodiment, after a predetermined number of iterations or epochs, the feed - forward neural network is able to distinguish the features initially specified in the filters or kernels during the earlier convolutional layers 104, 112. In at least one embodiment, the output is classified using Softmax classification technique.

[0062] Figure 2AShows a vertical line feature @102@02 in an input data item (e.g., an image). In at least one embodiment, a convolutional layer may take one or more images as input. In at least one embodiment, one or more images may contain aspects, features, or objects @102@02 to be recognized by the convolutional layer. In at least one embodiment, the vertical line @102@02 may be an aspect, feature, or object that can be recognized by a filter or kernel in the convolutional layer. In at least one embodiment, one or more filters in the convolutional layer may be responsible for recognizing a single feature, such as a vertical line @102@02 in the input image.

[0063] Figure 2B Shows a horizontal line feature @102@04 in an input data item (e.g., an image). In at least one embodiment, a convolutional layer may take one or more images as input, and one or more images may contain aspects, features, or objects @102@04 to be recognized or emphasized by the convolutional layer in a feature map. In at least one embodiment, the horizontal line @102@04 may be an aspect, feature, or object that can be recognized, extracted, or emphasized by a filter or kernel in the convolutional layer in the feature map. In at least one embodiment, one or more filters in the convolutional layer may be responsible for recognizing a single feature, such as a horizontal line @102@04 in the input image.

[0064] Figure 2C Shows multi-scale features @102@06 in an input data item, such as an object of variable size. In at least one embodiment, a convolutional layer may take one or more images as input, and one or more images may contain one or more variable-size aspects, features, or objects @102@06 to be recognized or emphasized by the convolutional layer containing one or more filters or kernels in a feature map. In at least one embodiment, the multi-scale features @102@06 may include one or more aspects, features, or objects that can be recognized, extracted, or emphasized by a filter or kernel in the convolutional layer in the feature map. In at least one embodiment, one or more filters in the convolutional layer may be responsible for recognizing single features at multiple scales @102@06 in the input image. In at least one embodiment, multiple filters may be aligned for each position of each multi-scale feature @102@06 in the feature map or other input data item. In at least one embodiment, the filters may be aligned by padding or linearly scaling filters of various sizes.

[0065] Figure 3Shows depthwise convolution in the convolutional layer of a convolutional neural network. In at least one embodiment, the input data item 302 (e.g., an image) can include multiple layers. In at least one embodiment, the layers in the input data image 302 can include color information, such as the red layer, green layer, and blue layer in an RGB input image 302. In at least one embodiment, depthwise convolution in the convolutional layer of a convolutional neural network can first separate each layer 304 into individual layers 306, 308, 310, which are represented as two-dimensional matrices or feature maps as described above. In at least one embodiment, each separated layer or feature map 306, 308, 310 can represent a subset of the information about the input data item or image 302.

[0066] In at least one embodiment, each separated layer or feature map 306, 308, 310 will then have a filter or kernel applied by convolution. In at least one embodiment, the separated layer or feature map 306, 308, 310 can be a two-dimensional matrix of dimension K×K. In at least one embodiment, the input data item or image 302 can have C in layers or feature maps 306, 308, 310. In at least one embodiment, depthwise convolution in the convolutional layer of a convolutional neural network can output C out layers or feature maps 322.

[0067] In at least one embodiment, a traditional convolutional layer or separable convolutional layer will share a single K×K filter across all layers or feature maps 306, 308, 310 during the convolution step 312. In at least one embodiment, a spatially adaptive separable convolutional layer can apply multiple filters or kernels of different sizes, not limited to K×K, to different layers or feature maps 306, 308, 310 during the convolution step 312, as described below. In at least one embodiment, a spatially adaptive separable convolutional layer can apply multiple filters or kernels of size K×K to different layers or feature maps 306, 308, 310 during the convolution step 312, where each filter corresponds to a different feature, as described below.

[0068] In at least one embodiment, each K×K filter or each filter of a smaller dimension is applied to each input layer or feature map 306, 308, 310 in the convolution step 312. In at least one embodiment, the convolution step 312 may include computing the dot product between the input matrix and the filter. In at least one embodiment, the output feature maps 314, 316, 318 may be two-dimensional matrices of dimension K×K, which represent the dot product between the filter or kernel and the input layer or feature maps 306, 308, 310. In at least one embodiment, the output feature maps 314, 316, 318 may be two-dimensional matrices of variable dimension, which represent the dot product between a filter of size less than K×K and a subset of the values in the two-dimensional matrix, which represent the input layer or feature maps 306, 308, 310. In at least one embodiment, the output feature maps 314, 316, 318 may be combined 320 into a multi-layer output 322, so that pointwise convolution can be applied, as described below.

[0069] Figure 4 Pointwise convolution in the convolutional layer of a convolutional neural network is shown. In at least one embodiment, the input feature map 402 may be generated as the output from the depthwise convolution operation in the convolutional layer, as described above. In at least one embodiment, for each layer, the input feature map 402 may be a two-dimensional matrix that contains information about the layer in the image after the filter or kernel has been applied during the depthwise convolution operation in the convolutional layer. In at least one embodiment, the input feature map 402 may have a K×K dimension in a separable convolutional layer. In at least one embodiment, the input feature map 402 may be of variable dimension in a spatially adaptive separable convolutional layer.

[0070] In at least one embodiment, the pointwise convolution operation 404 in the convolutional layer applies a convolution operation on the input feature map 402 generated by the depthwise convolution on a per-pixel or per-matrix-element basis. In at least one embodiment, the pointwise convolution 404 combines the spatial information contained within the input feature map 402 generated by the depthwise convolution and produces an output feature map 406.

[0071] Figure 5 A separable convolutional layer in a convolutional neural network is shown. In at least one embodiment, the separable convolutional layer is a form of a decomposed convolutional layer, which consists of a depthwise convolution 508 as described above and a 1×1 pointwise convolution 522 also as described above. In at least one embodiment, the decomposed convolutional layer performs convolution across the input channels 502, 504, 506 simultaneously.

[0072] In at least one embodiment, the depthwise convolution 508 applies one or more K×K filters or kernels to each input feature map to obtain the spatial information of the K×K feature map U p,q where p,q ∈ [1,...,Cin 510, 512, 514, 516, 518, 520. In at least one embodiment, the 1×1 pointwise convolution 522 combines the p,q spatial information in 510, 512, 514, 516, 518, 520 to generate output feature maps 524, 526, 528. In at least one embodiment, multiple filters may be applied to each input image layer or feature map 502, 504, 506 during the depthwise convolution 508. Figure 5 The depthwise convolution 508 is illustrated, where the K×K filter or kernel (where the number M of filters or kernels to be applied is equal to 2).

[0073] In at least one embodiment, as Figure 5 shown, the separable convolution layer receives the input image layer or feature maps 502, 504, 506 as input C in , where each input image layer or feature map 502, 504, 506 has a width W and a height H. In at least one embodiment, the activation size may describe the large amount of computations to be performed in the separable convolution layer. In at least one embodiment, the activation size or computation of the separable convolution layer is:

[0074] W×H×K×K×C in +W×H×C in ×C out

[0075] In at least one embodiment, a convolutional neural network as described herein may attempt to use backpropagation to learn the values of the filters or kernels applied to the input data 502, 504, 506 in the convolutional layer. In at least one embodiment, each layer or convolutional layer in a convolutional neural network that contains a matrix (such as a feature map) describing the weights 510, 512, 514, 516, 518, 520, 524, 526, 528 may be considered a learnable layer, or a layer containing learnable elements. In at least one embodiment, the element count of the filters or kernels in a learnable layer is considered the parameters of the filters or kernels in the layer. In at least one embodiment, for a separable convolution layer, the parameter count or the elements that can be learned are:

[0076] K×K×C in +C in ×C out

[0077] In at least one embodiment, the separable convolution layer may contain more than one K×K filter or kernel to be applied to each input feature map or image layer 502, 504, 506. In at least one embodiment, the total number of filters applied to each input layer or feature map 502, 504, 506 is M. Figure 5Shows a separable convolutional layer with M = 2 according to at least one embodiment. In at least one embodiment, the activation size of a separable convolutional layer that includes more than one K×K filter or kernel is:

[0078] W×H×K×K×M×C in +W×H×C in ×M×C out

[0079] In at least one embodiment, the activation size of a separable convolutional layer that includes more than one K×K filter or kernel is:

[0080] K×K×M×C in +C in ×M×C out

[0081] Figure 6 Shows an architecture for performing depthwise convolution in a spatially adaptive separable convolutional layer of a convolutional neural network. In at least one embodiment, as described herein, the spatially adaptive separable convolutional layer enables neurons in the convolutional neural network to adaptively adjust at different positions in the input data item or image 602. In at least one embodiment, the input value 602 can be an image layer or a feature map, as described above in connection with the exemplary convolutional neural network.

[0082] In at least one embodiment, the "split" operation generates multiple paths or matrices 604, 606 from the input image layer or feature map 602, where the different spatial filters used to create the intermediate feature maps or matrices 604, 606 can have variable kernel sizes, or can have a uniform kernel size but are constructed to identify different features. In at least one embodiment, the total number of filters to be applied is M. In at least one embodiment, the depthwise convolutional layer will apply multiple filters or spatial transforms 604, 606 to each input image layer or feature map 602. In at least one embodiment, the multiple filters or spatial transforms 604, 606 can be of variable size or uniform size. In at least one embodiment, M different spatial transforms F mc :X c →U mc ∈R W×H 604, 606, where c ∈ [1,…,C in are applied to the input feature Figure X ∈R W×H×Cin 602. In at least one embodiment, F mc 604, 606 is the mth filter applied to the cth input feature Figure X c .

[0083] In at least one embodiment, the "compete" operation will generate a compact feature descriptor 624 that is encoded with more information about the multi-scale features in the input 602. In at least one embodiment, the "compete" operation will apply soft attention across different branches or filter channels 604, 606 at each spatial location identified by the respective filters F mc In at least one embodiment, a Softmax operation 608 is applied to the feature maps specific to each filter channel at each pixel to obtain selection weight maps S m ∈R W×H×Cin 610, 612, where m = 1, …, M. In at least one embodiment, a dot product is performed between each selection weight map S m 610, 612 and the feature maps U mc 604, 606 to generate the selected information D mc 618, 620.

[0084] In at least one embodiment, an element-wise addition operation aggregates the selected information D mc across the filter channels F mc to generate a compact feature descriptor V c ∈R W×H 624, where c ∈ [1, …, C in . In at least one embodiment, the selection weight map values S ij mc 610, 612 can be computed from the pixel values U ij mc 604, 606 (where i is a specific row, j is a specific column, c is a specific input 602, and m is a specific filter channel). In at least one embodiment, Softmax can be used to determine the selection weight map values 610, 612, which can be computed as:

[0085]

[0086] In at least one embodiment, the compact feature descriptor or the final spatially adaptive feature map V c ∈R W×H 624, where c ∈ [1, …, C in , can be computed as:

[0087]

[0088] Or

[0089]

[0090] Figure 7Shows a spatially adaptive separable convolutional layer in a convolutional neural network. In at least one embodiment, on each input image layer or feature Figure X c 702, 704, 706, where c ∈ [1, …, C in , the depthwise convolution 728 is performed as described Figure 6 above. In at least one embodiment, the filter or kernel F mc : X c →U mc ∈R W×H is applied to the input feature Figure X c ∈R W×H 702, 704, 706, where c ∈ [1, …, C in . In at least one embodiment, F mc is the m-th filter applied to the c-th input feature Figure X c in order to generate U mc 708, 710, 712, 714, 716, 718.

[0091] In at least one embodiment, for each filter channel U mc 708, 710, 712, 714, 716, 718, the softmax function 720 is applied after the depthwise convolution, as described above. In at least one embodiment, soft information is collected from the dot products 722, 724 between each softmax 720 output and each filter channel U mc 708, 710, 712, 714, 716, 718. In at least one embodiment, the soft information outputs from the dot products 722, 724 are aggregated 726 for each filter channel, as described above, in order to generate a compact feature descriptor or the final spatially adaptive feature map V c ∈R W×H 730, 732, 734, where c ∈ [1, …, C in .

[0092] In at least one embodiment, as described above, the pointwise convolution 736 is performed on each compact feature descriptor V cPerformed on 730, 732, 734 to generate output feature maps 738, 740, 742. In at least one embodiment, when the number of "splits" or the number of filters applied during the depthwise convolution 728 increases, the pointwise convolution 736 input values or the compact feature descriptors 730, 732, 734 do not change. In at least one embodiment, because each pixel in each "split" and "compete" operation performed in the depthwise convolution 728 is independent of every other pixel, each depthwise convolution 728 of each input feature map 702, 704, 706 can be performed in parallel. In at least one embodiment, each parallel depthwise convolution operation 728 of each input feature map 702, 704, 706 can be performed on a graphics processing unit (GPU) or any other parallel processing unit (PPU) as described herein.

[0093] In at least one embodiment, as Figure 7 shown, the spatially adaptive separable convolution layer receives the image layer or feature maps 702, 704, 706 as input C in , where each input image layer or feature map 702, 704, 706 has a width W and a height H. In at least one embodiment, the activation size can describe the number of computations to be performed in the separable convolution layer. In at least one embodiment, the activation size or computation of the spatially adaptive separable convolution layer is:

[0094]

[0095] In at least one embodiment, as described herein, a convolutional neural network can attempt to learn the values of the filters or kernels applied to the input data 702, 704, 706 in the spatially adaptive separable convolution layer using backpropagation. In at least one embodiment, each layer or convolutional layer in a convolutional neural network that contains a matrix (e.g., a feature map) describing weights 702, 704, 706 can be considered a learnable layer or a layer containing learnable elements. In at least one embodiment, the number of elements of the filters or kernels in a learnable layer is considered a parameter of the filters or kernels in the layer. In at least one embodiment, for the spatially adaptive separable convolution layer described herein, the parameter count or learnable elements are described as follows, where

[0096]

[0097] Figure 8Illustrates the process of generating an output feature map by a spatially adaptive separable convolutional layer in a convolutional neural network. In at least one embodiment, the spatially adaptive separable convolutional layer begins 802 by performing a depthwise convolution 816. In at least one embodiment, the steps in the depthwise convolution 816 can be performed in parallel on a graphics processing unit (GPU) or any other parallel processing unit (PPU), as described herein.

[0098] In at least one embodiment, the spatial filter as described above is applied 804 to the input feature map. In at least one embodiment, the Softmax function is applied 806 to the spatial information generated by applying the spatial filter to the input feature map 804. In at least one embodiment, the selected information is generated 808 across filter channels based on the output from the Softmax function 806 and the spatial information generated by applying the spatial filter to the input feature map 804. In at least one embodiment, the selected information generated 808 across filter channels is aggregated 810 into a compact feature descriptor. In at least one embodiment, the compact feature information aggregated 810 from the selected information generated 808 across filter channels is combined by a pointwise convolution 812 to generate an output feature map, thereby completing 814 the process of generating an output feature map by the spatially adaptive separable convolutional layer.

[0099] Inference and Training Logic

[0100] Figure 9A Illustrates inference and / or training logic 915 for performing inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are provided below in conjunction with Figure 9A and / or Figure 9B provide details regarding the inference and / or training logic 915.

[0101] In at least one embodiment, the inference and / or training logic 915 can include, but is not limited to, code and / or data storage 901 for storing forward and / or output weights and / or input / output data, and / or other parameters that configure neurons or layers of a neural network trained to and / or for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 915 can include or be coupled to code and / or data storage 901 for storing graph code or other software to control timing and / or sequencing, where the weights and / or other parameter information is loaded to configure the logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads the weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 901 stores the weight parameters and / or input / output data of each layer of the neural network used or trained in conjunction with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 901 can be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0102] In at least one embodiment, any portion of the code and / or data storage 901 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 901 can be cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 901 is internal or external to the processor, e.g., or consists of DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage space on or off the chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0103] In at least one embodiment, the inference and / or training logic 915 can include, but is not limited to, code and / or data storage 905 to store the backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained as and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 905 stores the weight parameters and / or input / output data of each layer of the neural network that is trained or used in conjunction with one or more embodiments during the backpropagation of the input / output data and / or weight parameters. In at least one embodiment, the training logic 915 can include or be coupled to code and / or data storage 905 for storing graph code or other software to control timing and / or sequencing, where the weights and / or other parameter information is loaded to configure the logic that includes integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads the weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any part of the code and / or data storage 905 can be included with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory. In at least one embodiment, any part of the code and / or data storage 905 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 905 can be cache memory, DRAM, SRAM, non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 905 is internal or external to the processor, e.g., whether it consists of DRAM, SRAM, flash memory, or some other storage type, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0104] In at least one embodiment, the code and / or data storage 901 and the code and / or data storage 905 can be separate storage structures. In at least one embodiment, the code and / or data storage 901 and the code and / or data storage 905 can be the same storage structure. In at least one embodiment, the code and / or data storage 901 and the code and / or data storage 905 can be partially the same storage structure and partially different storage structures. In at least one embodiment, any part of the code and / or data storage 901 and the code and / or data storage 905 can be included together with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory.

[0105] In at least one embodiment, the inference and / or training logic 915 can include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910 (including integer and / or floating point units) for performing logical and / or mathematical operations at least in part based on and / or indicated by training and / or inference code (e.g., graph code), the result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in the activation store 920, which are a function of input / output and / or weight parameter data stored in the code and / or data store 901 and / or the code and / or data store 905. In at least one embodiment, the activations are generated by linear algebra and / or matrix-based mathematics performed by the ALU 910 in response to executing instructions or other code, where the weight values stored in the code and / or data store 905 and / or the code and / or data store 901 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in the code and / or data store 905 or the code and / or data store 901 or other on-chip or off-chip storage.

[0106] In at least one embodiment, one or more ALUs 910 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 910 can be outside of the processors or other hardware logic devices or circuits using them (e.g., coprocessors). In at least one embodiment, one or more ALUs 910 can be included within the execution units of a processor or otherwise included in a group of ALUs accessible by the execution units of a processor, which execution units of the processor can be within the same processor or distributed between different types of different processors (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, the data store 901, the code and / or data store 905, and the activation store 920 can be on the same processor or other hardware logic device or circuit, while in another embodiment, they can be on different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of the activation store 920 can be included with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory. Additionally, the inference and / or training code can be stored with other code accessible by the processor or other hardware logic or circuits and can be fetched and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuits of the processor.

[0107] In at least one embodiment, the activation store 920 can be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the activation store 920 can be wholly or partially inside or outside one or more processors or other logic circuits. In at least one embodiment, whether the activation store 920 is internal or external to the processor can be selected depending on on-chip or off-chip available storage, the latency requirements for training and / or inference functions, the batch size of data used in inferring and / or training a neural network, or some combination of these factors, e.g., or include DRAM, SRAM, flash memory, or other storage types. In at least one embodiment, Figure 9A the inference and / or training logic 915 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the TM processing unit from Google, the inference processing unit (IPU) from Graphcore, or the Figure 9A processor (e.g., “Lake Crest”) from Intel Corporation. In at least one embodiment,

[0108] Figure 9B The inference and / or training logic 915 is shown in accordance with at least one embodiment. In at least one embodiment, the inference and / or training logic 915 can include, but is not limited to, hardware logic where computing resources are dedicated or otherwise uniquely used along with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 9B the inference and / or training logic 915 shown in can be used in conjunction with an application specific integrated circuit (ASIC), such as the TM processing unit from Google, the inference processing unit (IPU) from Graphcore, or the Figure 9BThe inference and / or training logic 915 shown in [Figure X] can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (such as field programmable gate arrays (FPGAs)). In at least one embodiment, the inference and / or training logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 9B In at least one embodiment shown in [Figure X], each of code and / or data storage 901 and code and / or data storage 905 is respectively associated with dedicated computing resources (such as computing hardware 902 and computing hardware 906). In at least one embodiment, each of computing hardware 902 and computing hardware 906 includes one or more ALUs that respectively perform mathematical functions (such as linear algebra functions) only on the information stored in code and / or data storage 901 and code and / or data storage 905, and the result of the executed function is stored in activation storage 920.

[0109] In at least one embodiment, each of code and / or data storage 901 and 905 and the corresponding computing hardware 902 and 906 respectively corresponds to different layers of a neural network, such that the activation obtained from one "storage / computation pair 901 / 902" of code and / or data storage 901 and computing hardware 902 is provided as the input to the next "storage / computation pair 905 / 906" of code and / or data storage 905 and computing hardware 906, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 901 / 902 and 905 / 906 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the inference and / or training logic 915 after or in parallel with the storage computation pairs 901 / 902 and 905 / 906.

[0110] Neural Network Training and Deployment

[0111] Figure 10 It should be noted that the reference to "[Figure X]" in the translation is a placeholder as the original text seems to be missing the specific figure reference. You may need to replace it with the actual figure number if available.Illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, a training dataset 1002 is used to train an untrained neural network 1006. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j or other training frameworks. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights can be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised or unsupervised manner.

[0112] In at least one embodiment, supervised learning is used to train the untrained neural network 1006, where the training dataset 1002 includes inputs paired with desired outputs for the input, or where the training dataset 1002 includes inputs with known outputs and the output of the neural network 1006 is a manual hierarchy. In at least one embodiment, the untrained neural network 1006 is trained in a supervised manner, and the inputs from the training dataset 1002 are processed and the resulting output is compared with a set of expected or desired outputs. In at least one embodiment, the error is then propagated back through the untrained neural network 1006. In at least one embodiment, the training framework 1004 adjusts the weights that control the untrained neural network 1006. In at least one embodiment, the training framework 1004 includes tools for monitoring the degree to which the untrained neural network 1006 converges to a model (e.g., the trained neural network 1008), a model suitable for generating correct answers (e.g., results 1014) based on known input data (e.g., new data 1012). In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to improve the output of the untrained neural network 1006 using a loss function and an adjustment algorithm (e.g., stochastic gradient descent). In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 reaches the desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to perform any number of machine learning operations.

[0113] In at least one embodiment, unsupervised learning is used to train an untrained neural network 1006, where the untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1002 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 1006 can learn groupings within the training dataset 1002 and can determine how individual inputs relate to the untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 1008 that can perform operations useful for reducing the dimensionality of new data 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the new dataset 1012 that deviate from the normal pattern of the new dataset 1012.

[0114] In at least one embodiment, semi-supervised learning can be used, which is a technique where a mixture of labeled and unlabeled data is included in the training dataset 1002. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1008 to adapt to new data 1012 without forgetting the knowledge injected into the network during initial training.

[0115] Data Center

[0116] Figure 11 An example data center 1100 in which at least one embodiment can be used is shown. In at least one embodiment, the data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0117] In at least one embodiment, as Figure 11As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources ("node C.R.") 1116(1)-1116(N), where "N" represents any whole positive integer. In at least one embodiment, the node C.R. 1116(1)-1116(N) may include, but is not limited to, any number of central processing units ("CPU") or other processors (including accelerators, field programmable gate arrays (FPGA), graphics processors, etc.), memory devices (such as dynamic read-only memory), storage devices (such as solid-state or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VM"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 1116(1)-1116(N) may be servers having one or more of the above computing resources.

[0118] In at least one embodiment, the grouped computing resources 1114 may include separate groupings (not shown) of node C.R. housed within one or more racks, or many racks (also not shown) within data centers located in various geographical locations. Separate groupings of node C.R. within the grouped computing resources 1114 may include grouped computing, network, memory, or storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0119] In at least one embodiment, the resource coordinator 1112 may configure or otherwise control one or more of the node C.R. 1116(1)-1116(N) and / or the grouped computing resources 1114. In at least one embodiment, the resource coordinator 1112 may include a software design infrastructure ("SDI") management entity for the data center 1100. In at least one embodiment, the resource coordinator may include hardware, software, or some combination thereof.

[0120] In at least one embodiment, as Figure 11As shown, the framework layer 1120 includes a job scheduler 1132, a configuration manager 1134, a resource manager 1136, and a distributed file system 1138. In at least one embodiment, the framework layer 1120 may include a framework that supports software 1132 of the software layer 1130 and / or one or more applications 1142 of the application layer 1140. In at least one embodiment, the software 1132 or the application 1142 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1120 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark that can utilize the distributed file system 1138 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1132 may include a Spark driver to facilitate scheduling of the workloads supported by the various layers of the data center 1100. In at least one embodiment, the configuration manager 1134 may be able to configure different layers, such as the software layer 1130 and the framework layer 1120 including Spark and the distributed file system 1138 for supporting large-scale data processing. In at least one embodiment, the resource manager 1136 is capable of managing the cluster or grouped computing resources mapped to or allocated for supporting the distributed file system 1138 and the job scheduler 1132. In at least one embodiment, the cluster or grouped computing resources may include grouped computing resources 1114 on the data center infrastructure layer 1110. In at least one embodiment, the resource manager 1136 may coordinate with the resource coordinator 1112 to manage these mapped or allocated computing resources.

[0121] In at least one embodiment, the software 1132 included in the software layer 1130 may include software used by at least a portion of the nodes C.R. 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1138 of the framework layer 1120. One or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0122] In at least one embodiment, one or more applications 1142 included in the application layer 1140 may include one or more types of applications used by at least a portion of nodes C.R. 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1138 of the framework layer 1120. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (such as PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0123] In at least one embodiment, any one of the configuration manager 1134, the resource manager 1136, and the resource coordinator 1112 may implement any number and type of self-modifying actions based on any quantity and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions may relieve the data center operator of the data center 1100 from making potentially poor configuration decisions and may avoid underutilization and / or poorly performing portions of the data center.

[0124] In at least one embodiment, the data center 1100 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture by using the software and computing resources described above with respect to the data center 1100. In at least one embodiment, by using the weight parameters calculated by one or more of the training techniques described herein, the resources described above with respect to the data center 1100 may be used to infer or predict information using the trained machine learning model corresponding to one or more neural networks.

[0125] In at least one embodiment, the data center may use a CPU, an application specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or inference using the above resources. In addition, one or more of the above software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0126] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 9A and / or Figure 9BProvide details regarding inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 can be used in a system Figure 11 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0127] In at least one embodiment, the spatially adaptive separable convolution layer 7 can be used with a system Figure 11 to perform inference and prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0128] Autonomous Vehicle

[0129] Figure 12A FIG. shows an example of a self-driving vehicle 1200 according to at least one embodiment. In at least one embodiment, the self-driving vehicle 1200 (alternatively referred to herein as "vehicle 1200") can be, but is not limited to, a passenger vehicle such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 1200 can be a semi-trailer truck for hauling cargo. In at least one embodiment, vehicle 1200 can be an airplane, robotic vehicle, or other type of vehicle.

[0130] Autonomous vehicles can be described according to automation levels defined by the National Highway Traffic Safety Administration ("NHTSA") under the United States Department of Transportation and the Society of Automotive Engineers ("SAE") in "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806 released on June 15, 2018, Standard No. J3016-201609 released on September 30, 2016, and previous and future versions of this standard). In one or more embodiments, vehicle 1200 may be capable of functioning according to one or more of automation levels 1 through 5. For example, in at least one embodiment, according to the embodiment, vehicle 1200 may be capable of conditional automation (level 3), highly automated (level 4), and / or fully automated (level 5).

[0131] In at least one embodiment, vehicle 1200 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 1200 may include, but is not limited to, a propulsion system 1250, such as an internal combustion engine, a hybrid device, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1250 may be connected to the driveline of vehicle 1200, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1200. In at least one embodiment, a signal may be received from throttle / accelerator 1252 to control propulsion system 1250.

[0132] In at least one embodiment, when propulsion system 1250 is operating (e.g., when the vehicle is moving), a steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, steering system 1254 may receive a signal from a steering actuator 1256. The steering wheel may be optional for fully automated (level 5) functions. In at least one embodiment, a brake sensor system 1246 may be used to operate vehicle brakes in response to signals received from a brake actuator 1248 and / or a brake sensor.

[0133] In at least one embodiment, controller 1236 may include, but is not limited to, one or more system-on-chips (“SoC”) ( Figure 12A(not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1200. For example, in at least one embodiment, the controller 1236 may send signals to operate the vehicle brakes via the brake actuator 1248, operate the steering system 1254 via one or more steering actuators 1256, and operate the propulsion system 1250 via one or more throttles / accelerators 1252. One or more controllers 1236 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operation commands (e.g., signals representative of commands) to effect autonomous driving and / or assist a driver in driving the vehicle 1200. In at least one embodiment, one or more controllers 1236 may include a first controller 1236 for autonomous driving functions, a second controller 1236 for functional safety functions, a third controller 1236 for artificial intelligence functions (e.g., computer vision), a fourth controller 1236 for infotainment functions, a fifth controller 1236 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1236 may handle two or more of the above functions, and two or more controllers 1236 may handle a single function and / or any combination thereof.

[0134] In at least one embodiment, one or more controllers 1236 provide signals for controlling one or more components and / or systems of the vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from sensors of sensor types such as but not limited to one or more global navigation satellite system (“GNSS”) sensors 1258 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more inertial measurement unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide-angle cameras 1270 (e.g., fish-eye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360-degree cameras), remote cameras ( Figure 12A (not shown), mid-range cameras ( Figure 12A(not shown in the figure), one or more speed sensors 1244 (e.g., for measuring the speed of vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more braking sensors (e.g., as part of a braking sensor system 1246), and / or other sensor types receive.

[0135] In at least one embodiment, one or more controllers 1236 may receive inputs (e.g., represented by input data) from the instrument panel 1232 of vehicle 1200 and provide outputs (e.g., represented by output data, display data, etc.) through a human-machine interface (“HMI”) display 1234, a sound signaler, a speaker, and / or other components of vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., high-definition map ( Figure 12A (not shown in the figure), location data (e.g., the location of vehicle 1200, e.g., on a map), direction, the locations of other vehicles (e.g., occupancy grids), information about objects, and the status of objects sensed by one or more controllers 1236, etc. For example, in at least one embodiment, the HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic signal changes, etc.) and / or information about driving operations the vehicle has made, is making, or will make (e.g., changing lanes now, exiting at Exit 34B in two miles, etc.).

[0136] In at least one embodiment, vehicle 1200 further includes a network interface 1224, which may communicate through one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, network interface 1224 may be capable of communicating through Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”), etc. In at least one embodiment, one or more wireless antennas 1226 may also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter referred to as “LPWAN”) (e.g., LoRaWAN, SigFox, etc.) to enable communication between objects in the environment (e.g., vehicles, mobile devices).

[0137] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This article is combined with Figure 9A and / orFigure 9B Provide details regarding inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in a system Figure 12A to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0138] In at least one embodiment, the spatially adaptive separable convolutional layer 7 may be used with the system Figure 12A to infer and predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0139] Figure 12B illustrates an example of the camera positions and fields of view of an Figure 12A autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1200.

[0140] In at least one embodiment, the camera types for the cameras may include, but are not limited to, digital cameras that may be adapted to work with components and / or systems of the vehicle 1200. One or more cameras may operate at an automotive safety integrity level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate according to the embodiment, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the cameras may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer (RGGB) sensor color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, transparent pixel cameras, such as cameras having RCCC, RCCB, and / or RBGC color filter arrays, may be used to attempt to improve photosensitivity.

[0141] In at least one embodiment, one or more cameras can be used to perform Advanced Driver Assistance System (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-functional monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and smart headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can record and provide image data (e.g., video) simultaneously.

[0142] In at least one embodiment, one or more of the cameras can be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D”) printed) assembly, in order to cut out stray light and reflections from within the vehicle (e.g., reflections from the dashboard reflected in the windshield mirror), which may interfere with the camera's image data capture ability. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side cameras, one or more cameras can also be integrated within the four pillars at each corner of the cabin.

[0143] In at least one embodiment, a camera having a field of view including a portion of the environment in front of vehicle 1200 (e.g., a forward camera) can be used for surround view, and to help identify a forward path and obstacles with the help of one or more controllers 1236 and / or a control SoC, thus providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0144] In at least one embodiment, various cameras can be used in a forward configuration, including for example a monocular camera platform including a CMOS (“Complementary Metal Oxide Semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects entering from the periphery (e.g., pedestrians, crossing the road, or bicycles). Although in Figure 12BOnly one wide - angle camera 1270 is shown, but in other embodiments, any number (including zero) of wide - angle cameras 1270 can be on the vehicle 1200. In at least one embodiment, any number of long - range cameras 1298 (e.g., long - range stereo camera pairs) can be used for depth - based object detection, especially for objects for which the neural network has not been trained. In at least one embodiment, the long - range cameras 1298 can also be used for object detection and classification and basic object tracking.

[0145] In at least one embodiment, any number of stereo cameras 1268 can also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1268 can include an integrated control unit that includes a scalable processing unit that can provide programmable logic (“FPGA”) and a multi - core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit can be used to generate a 3D map of the environment of the vehicle 1200, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 can include, but are not limited to, compact stereo vision sensors, which can include, but are not limited to, two camera samples (one on the left and one on the right) and an image - processing chip, which can measure the distance from the vehicle 1200 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane - departure warning functions. In at least one embodiment, other types of stereo cameras 1268 can be used in addition to those described herein.

[0146] In at least one embodiment, a camera with a field of view that includes a portion of the environment on the side of the vehicle 1200 (e.g., a side - view camera) can be used for surround viewing, thus providing information for creating and updating an occupancy grid, and generating side - collision warnings. For example, in at least one embodiment, surround cameras 1274 (e.g., four surround cameras 1274 as Figure 12B shown) can be positioned on the vehicle 1200. One or more surround cameras 1274 can include, but are not limited to, any number and combination of wide - angle cameras 1270, one or more fisheye samples, one or more 360 - degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye - sample cameras can be located at the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 can use three surround cameras 1274 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward camera) as the fourth surround - view camera.

[0147] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1200 (e.g., a rear view camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0148] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B , details about the reasoning and / or training logic 915 are provided herein. In at least one embodiment, the reasoning and / or training logic 915 may be Figure 12B for use in a system for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0149] In at least one embodiment, the spatially adaptive separable convolutional layer 7 can be used with the system Figure 12B Together, they are used to perform inference and prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0150] Figure 12C According to at least one embodiment, Figure 12A A block diagram of an example system architecture of an autonomous vehicle 1200. In at least one embodiment, Figure 12C Each of one or more components, one or more features, and one or more systems of the vehicle 1200 in FIG. 1 is shown as being connected via a bus 1202. In at least one embodiment, the bus 1202 may include, but is not limited to, a CAN data interface (referred to herein alternatively as a "CAN bus"). In at least one embodiment, the CAN may be a network inside the vehicle 1200 that helps control various features and functions of the vehicle 1200, such as actuation of brakes, acceleration, braking, steering, wipers, etc. In one embodiment, the bus 1202 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1202 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, the bus 1202 may be a CAN bus that complies with ASIL B.

[0151] In at least one embodiment, in addition to or instead of CAN, FlexRay and / or Ethernet can be selected for use. In at least one embodiment, there can be any number of buses 1202, which can include but are not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1202 can be used to perform different functions and / or can be used for redundancy. For example, the first bus 1202 can be used for collision avoidance functions, and the second bus 1202 can be used for actuation control. In at least one embodiment, each bus 1202 can communicate with any component of the vehicle 1200, and two or more buses 1202 can communicate with the same component. In at least one embodiment, each of any number of system-on-chips (“SoC”) 1204, each of one or more controllers 1236, and / or each computer in the vehicle can access the same input data (e.g., input from sensors of the vehicle 1200) and can be connected to a common bus, such as a CAN bus.

[0152] In at least one embodiment, the vehicle 1200 can include one or more controllers 1236, such as those described herein with respect to Figure 12A The controller 1236 can be used for a variety of functions. In at least one embodiment, the controller 1236 can be coupled to any one of various other components and systems of the vehicle 1200 and can be used to control the vehicle 1200, the artificial intelligence of the vehicle 1200, the infotainment of the vehicle 1200, and / or similar functions.

[0153] In at least one embodiment, the vehicle 1200 can include any number of SoC 1204. Each of the SoC 1204 can include but is not limited to a central processing unit (“one or more CPUs”) 1206, a graphics processing unit (“one or more GPUs”) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data stores 1216, and / or other components and features not shown. In at least one embodiment, one or more SoC 1204 can be used to control the vehicle 1200 in various platforms and systems. For example, in at least one embodiment, one or more SoC 1204 can be combined with a high-definition (“HD”) map 1222 in a system (e.g., the system of the vehicle 1200), and the high-definition map 1222 can be obtained from one or more servers via a network interface 1224 ( Figure 12CMap refresh and / or update is obtained (not shown in the figure).

[0154] In at least one embodiment, one or more CPUs 1206 may include a CPU cluster or CPU complex (alternatively referred to herein as "CCPLEX"). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or secondary ("L2") caches. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in a multi-processor configuration coupled to each other. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 1206 can be active at any given time.

[0155] In at least one embodiment, one or more CPUs 1206 may implement power management functions, which include but are not limited to one or more of the following features: individual hardware modules can be automatically clock-gated when idle to save dynamic power; each core clock can be gated when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core can be independently powered; each core cluster can be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster can be independently power-gated when all cores are power-gated. In at least one embodiment, one or more CPUs 1206 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for core, cluster, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, where the work is shared with the microcode.

[0156] In at least one embodiment, one or more GPUs 1208 may include an integrated GPU (referred to herein as an “iGPU”). In at least one embodiment, one or more GPUs 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may use an enhanced tensor instruction set in at least one embodiment. In one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, where each streaming microprocessor may include a level one (“L1”) cache (e.g., an L1 cache having a storage capacity of at least 96 KB), and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache having a 512 KB storage capacity). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may use a compute application programming interface (API). In at least one embodiment, one or more GPUs 1208 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0157] In at least one embodiment, one or more GPUs 1208 may be power optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1208 may be fabricated on fin field effect transistors (“FinFETs”). In at least one embodiment, each streaming microprocessor may contain multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computational and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0158] In at least one embodiment, one or more GPUs 1208 may include high bandwidth memory (“HBM”) and / or 16GB HBM2 memory subsystems to provide peak memory bandwidth of approximately 900GB / second in some examples. In at least one embodiment, synchronous graphics random access memory (“SGRAM”), such as graphics double data rate type five synchronous random access memory (“GDDR5”), may be used in addition to or in place of HBM memory.

[0159] In at least one embodiment, one or more GPUs 1208 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1208 to directly access the page tables of one or more CPUs 1206. In at least one embodiment, when the memory management unit (“MMU”) of one or more GPUs 1208 experiences a miss, an address translation request may be sent to one or more CPUs 1206. In response, in at least one embodiment, one or more CPUs 1206 may look up the virtual-physical mapping of the address in their page tables and transmit the translation back to one or more GPUs 1208. In at least one embodiment, unified memory technology may allow a single unified virtual address space for the memory of both one or more CPUs 1206 and one or more GPUs 1208, thus simplifying the programming of one or more GPUs 1208 and porting applications to one or more GPUs 1208.

[0160] In at least one embodiment, one or more GPUs 1208 may include any number of access counters that may track the frequency of access by one or more GPUs 1208 to the memory of other processors. In at least one embodiment, one or more access counters may help ensure that memory pages are moved into the physical memory of the processor that most frequently accesses the pages, thereby increasing the efficiency of the memory range shared among processors.

[0161] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a level three (“L3”) cache that may be available to one or more CPUs 1206 and one or more GPUs 1208 (e.g., connected to both the CPU 1206 and the GPU 1208). In at least one embodiment, one or more caches 1212 may include a write-back cache that may track the state of lines, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although smaller cache sizes may be used, according to an embodiment, the L3 cache may include 4MB or more.

[0162] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memories. In at least one embodiment, a large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and offload some tasks of one or more GPUs 1208 (e.g., free up more cycles of one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for target workloads that are stable enough to withstand acceleration testing (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, a CNN may include a region-based or region convolutional neural network (“RCNN”) and Fast RCNN (e.g., as used for object detection) or other types of CNNs.

[0163] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLA”). One or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPU”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). The one or more DLAs may be further optimized for a particular set of neural network types and floating-point operations as well as inference. In at least one embodiment, the design of the one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU and generally far exceed the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including supporting, for example, INT8, INT16, and FP16 data types for single-instance convolution functions of features and weights as well as post-processor functions. In at least one embodiment, the one or more DLAs may execute a neural network, especially a CNN, quickly and efficiently on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and identification and detection using data from a microphone 1296; a CNN for face recognition and vehicle owner identification using data from a camera sensor; and / or a CNN for security and / or safety-related events.

[0164] In at least one embodiment, the DLA may perform any function of one or more GPUs 1208, and by using an inference accelerator, for example, a designer may target one or more DLAs or one or more GPUs 1208 for any function. For example, in at least one embodiment, a designer may concentrate the processing and floating-point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 1208 and / or other one or more accelerators 1214.

[0165] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1238, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. One or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0166] In at least one embodiment, the RISC cores may interact with an image sensor (e.g., the image sensor of any of the cameras described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, according to an embodiment, the RISC cores may use any one of a variety of protocols. In at least one embodiment, the RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or storage devices may be used to implement the RISC cores. For example, in at least one embodiment, the RISC cores may include an instruction cache and / or tightly coupled RAM.

[0167] In at least one embodiment, the DMA may enable components of one or more PVAs to access system memory independently of one or more CPUs 1206. In at least one embodiment, the DMA may support any number of features for optimizing the delivery to the PVA, including but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more dimensions of addressing, which may include but are not limited to block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0168] In at least one embodiment, a vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core can include a digital signal processor, e.g., a single instruction multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0169] In at least one embodiment, each vector processor can include an instruction cache and can be coupled to a dedicated memory. As a result, in at least one embodiment, each vector processor can be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA can be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA can execute the same computer vision algorithm, except on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA can execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on sequence images or partial images. In at least one embodiment, among other things, any number of PVAs can be included in a hardware acceleration cluster, and any number of vector processors can be included in each PVA. In at least one embodiment, the PVA can include additional error correction code (“ECC”) memory to enhance overall system security.

[0170] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, which includes, for example but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using the APB).

[0171] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and the DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communication for continuous data transfer. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0172] In at least one embodiment, one or more SoCs 1204 may include a real-time line-of-sight tracking hardware accelerator. In at least one embodiment, the real-time line-of-sight tracking hardware accelerator may be used to quickly and efficiently determine the position and extent of an object (e.g., within a world model) to generate a real-time visualization simulation for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0173] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator that can be used in key processing stages for ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well matched to algorithm domains that require predictable processing. In other words, the PVA excels in semi-dense or dense general computing, even on small data sets that require predictable runtimes with low latency and low power. In at least one embodiment, for autonomous vehicles, such as vehicle 1200, the PVA is designed to run classical computer vision algorithms because they are effective in object detection and integer math operations.

[0174] For example, according to at least one embodiment of the technology, the PVA is used to perform computer stereo vision. In at least one embodiment, an algorithm based on semi-global matching can be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for level 3 - 5 autonomous driving use dynamic estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, the PVA can perform computer stereo vision functions on inputs from two monocular cameras.

[0175] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, for example, the PVA is used for time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0176] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including for example but not limited to neural networks, the output of which is a confidence level for each object detection. In at least one embodiment, the confidence level can be represented or interpreted as a probability, or represented as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence level enables the system to make further decisions, namely regarding which detections should be considered true positive detections rather than false positive detections. For example, in at least one embodiment, the system can set a threshold for the confidence level and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, false positive detections would cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network can take at least some subset of parameters as its input, such as bounding box dimensions, a obtained ground plane estimate (e.g., from another subsystem), and the outputs of one or more IMU sensors 1266 related to the vehicle 1200 direction, distance, 3D position estimate of an object obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1264 or one or more RADAR sensors 1260).

[0177] In at least one embodiment, one or more SoCs 1204 can include one or more data storage devices 1216 (e.g., memory). In at least one embodiment, one or more data storages 1216 can be on-chip memories of one or more SoCs 1204, which can store neural networks to be executed on one or more GPUs 1208 and / or DLA. In at least one embodiment, one or more data storages 1216 can have a large enough capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, one or more data storages 1212 can include L2 or L3 caches.

[0178] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). One or more processors 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions as well as associated security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1204 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoC 1204 thermal and temperature sensors, and / or manage one or more SoC 1204 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1204 may use the ring oscillator to detect the temperature of one or more CPUs 1206, one or more GPUs 1208, and / or one or more accelerators 1214. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1204 in a lower power state and / or place the vehicle 1200 in a driver's safe parking pattern (e.g., safely park the vehicle 1200).

[0179] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors, which may be used as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem that can provide full hardware support for multi-channel audio to the hardware through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0180] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine, which may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, processor cores, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0181] In at least one embodiment, one or more processors 1210 may further include a security cluster engine, which includes but is not limited to dedicated processor subsystems for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In a security mode, in at least one embodiment, two or more cores may operate in a lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine, which may include but is not limited to dedicated processor subsystems for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine as part of a camera processing pipeline.

[0182] In at least one embodiment, one or more processors 1210 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required for a video playback application to produce a final video for generating a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 1204, the neural network being configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform but is not limited to lip reading to activate cellular services and make calls, indicate emails, change the destination of the vehicle, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are otherwise disabled.

[0183] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, in the case where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of the information provided by adjacent frames. In at least one embodiment, in the case where an image or a part of the image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from a previous image to reduce the noise in the current image.

[0184] In at least one embodiment, the video image synthesizer may also be configured to perform stereoscopic correction on the input stereoscopic lens frames. In at least one embodiment, when using an operating system desktop, the video image synthesizer may also be used for user interface synthesis and does not require one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when powering one or more GPUs 1208 and making them actively perform 3D rendering, the video image synthesizer may be used to offload one or more GPUs 1208 to improve performance and responsiveness.

[0185] In at least one embodiment, one or more SoCs 1204 may further include a Mobile Industry Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block for receiving video and inputs from cameras, which can be used for camera and related pixel input functions. In at least one embodiment, one or more SoCs 1204 may further include an input / output controller, which can be controlled by software and can be used to receive I / O signals not committed to a specific role.

[0186] In at least one embodiment, one or more SoCs 1204 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoder / decoders (“codecs”), power management, and / or other devices. One or more SoCs 1204 can be used to process data from cameras (e.g., via Gigabit Multimedia Serial Link and Ethernet connections), sensors (e.g., one or more LIDAR sensors 1264, one or more RADAR sensors 1260, etc., which can be connected via Ethernet), data from bus 1202 (e.g., the speed, steering wheel position, etc. of vehicle 1200), data from one or more GNSS sensors 1258 (e.g., via Ethernet or CAN bus connection), etc. In at least one embodiment, one or more SoCs 1204 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and can be used to relieve one or more CPUs 1206 from conventional data management tasks.

[0187] In at least one embodiment, one or more SoCs 1204 can be an end-to-end platform with a flexible architecture that spans automation levels 3 - 5, thus providing an integrated functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, which provides a platform that can offer a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1204 can be faster and more reliable than conventional systems, and even more energy-efficient and space-efficient. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data storage devices 1216, can provide a fast and efficient platform for level 3 - 5 autonomous vehicles.

[0188] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (such as the C programming language) to execute multiple processing algorithms on various visual data. However, in at least one embodiment, a CPU generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual level 3 - 5 autonomous vehicles.

[0189] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve level 3 - 5 autonomous driving functions. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1220) can include text and word recognition, thus allowing a supercomputer to read and understand traffic signs, including signs that the neural network has not been specifically trained for. In at least one embodiment, the DLA can also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing that semantic understanding to a path planning module running on the CPU Complex.

[0190] In at least one embodiment, for a level 3, 4, or 5 drive, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: flashing lights indicate icy conditions" and an electric light can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executed on the CPU Complex) that when flashing lights are detected, there is an icy condition. In at least one embodiment, a third deployed neural network operating on multiple frames can be used to identify the flashing lights and notify the vehicle's path planning software of the presence (or absence) of the flashing lights. In at least one embodiment, all three neural networks can run simultaneously, e.g., within the DLA and / or on one or more GPUs 1208.

[0191] In at least one embodiment, a CNN for facial recognition and vehicle owner recognition can use data from a camera sensor to identify the presence of an authorized driver and / or the owner of the vehicle 1200. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in a security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0192] In at least one embodiment, the CNN for emergency vehicle detection and recognition can use data from microphone 1296 to detect and recognize emergency vehicle sirens. In at least one embodiment, one or more SoCs 1204 use the CNN to classify ambient and urban sounds, as well as to classify visual data. In at least one embodiment, the CNN running on the DLA is trained to recognize the relative approach speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to recognize emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in the United States, the CNN will seek to recognize only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1262 to execute emergency vehicle safety routines, slow down the vehicle, pull the vehicle over to the side of the road, park, and / or idle the vehicle until the emergency vehicle has passed.

[0193] In at least one embodiment, vehicle 1200 can include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs), which can be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, one or more CPUs 1218 can include X86 processors, e.g., one or more CPUs 1218 can be used to perform any of a variety of functions, such as including potentially arbitrating inconsistent results between ADAS sensors and one or more SoCs 1204, and / or monitoring the status and health of one or more monitoring controllers 1236 and / or on-chip information system (“Info SoC”) 1230.

[0194] In at least one embodiment, vehicle 1200 can include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs), which can be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, one or more GPUs 1220 can provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and can be used for training and / or updating neural networks at least in part based on inputs from the sensors of vehicle 1200 (e.g., sensor data).

[0195] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, but is not limited to, one or more wireless antennas 1226 (e.g., one or more wireless antennas 1226 for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1224 may be used to enable a wireless connection to other vehicles and / or computing devices (e.g., a passenger's client device) via the cloud over the Internet (e.g., using a server and / or other network devices). In at least one embodiment, to communicate with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 1200 and the other vehicles. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. The vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles in the vicinity of vehicle 1200 (e.g., vehicles in front of, to the side of, and / or behind vehicle 1200). In at least one embodiment, the foregoing functionality may be part of the cooperative adaptive cruise control function of vehicle 1200.

[0196] In at least one embodiment, network interface 1224 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1236 to communicate over a wireless network. In at least one embodiment, network interface 1224 may include a radio frequency front end for upconverting from baseband to radio frequency and downconverting from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by known processes and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0197] In at least one embodiment, vehicle 1200 may further include one or more data stores 1228, which may include, but are not limited to, off-chip (e.g., one or more SoCs 1204) storage. In at least one embodiment, one or more data stores 1228 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard drives, and / or other components and / or devices that can store at least one bit of data.

[0198] In at least one embodiment, vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including for example but not limited to a GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0199] In at least one embodiment, vehicle 1200 may further include one or more RADAR sensors 1260. The one or more RADAR sensors 1260 may be used by vehicle 1200 for remote vehicle detection, even in dark and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. The one or more RADAR sensors 1260 may use CAN and / or bus 1202 (e.g., to transmit data generated by the one or more RADAR sensors 1260) for control and access to object tracking data and in some examples may access Ethernet to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example but not limited to, one or more of the RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, the one or more RADAR sensors 1260 are pulsed Doppler RADAR sensors.

[0200] In at least one embodiment, one or more RADAR sensors 1260 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, a long-range RADAR system may provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 m). In at least one embodiment, one or more RADAR sensors 1260 may assist in differentiating between static and moving objects and may be used by the ADAS system 1238 for emergency braking assistance and forward collision warning. One or more sensors 1260 included in the long-range RADAR system may include, but are not limited to, monostatic multimode RADARs having multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas may create a focused beam pattern designed to record the vehicle 1200's surroundings at a higher speed with minimal traffic interference from adjacent lanes. In at least one embodiment, the other two antennas may widen the field of view so that it is possible to quickly detect vehicles entering or leaving the lane of the vehicle 1200.

[0201] In at least one embodiment, by way of example, a mid-range RADAR system may include a range of, for example, up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the blind spots behind and near the vehicle. In at least one embodiment, the short-range RADAR system may be used in the ADAS system 1238 for blind spot detection and / or lane change assistance.

[0202] In at least one embodiment, the vehicle 1200 may further include one or more ultrasonic sensors 1262. One or more ultrasonic sensors 1262 that may be positioned at the front, rear, and / or sides of the vehicle 1200 may be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1262 may operate at a functional safety level of ASIL B.

[0203] In at least one embodiment, vehicle 1200 may include one or more LIDAR sensors 1264. The one or more LIDAR sensors 1264 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1264 may be of functional safety level ASIL B. In at least one embodiment, vehicle 1200 may include multiple (e.g., two, four, six, etc.) LIDAR sensors 1264 (e.g., providing data to a gigabit Ethernet switch) that may use Ethernet.

[0204] In at least one embodiment, the one or more LIDAR sensors 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1264 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm - 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors 1264 may be used. In such an embodiment, the one or more LIDAR sensors 1264 may be implemented as small devices that can be embedded in the front, rear, sides, and / or corner positions of vehicle 1200. In at least one embodiment, the one or more LIDAR sensors 1264, in such an embodiment, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, and have a range of 200 m, even for low-reflectivity objects. In at least one embodiment, the forward one or more LIDAR sensors 1264 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0205] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) can also be used. 3D flash LIDAR uses a laser flash as the transmission source to illuminate approximately 200m around the vehicle 1200. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1200 to the object. In at least one embodiment, flash LIDAR can allow the use of each laser flash to generate a highly accurate and distortion-free image of the surrounding environment. In at least one embodiment, four flash LIDAR sensors can be deployed, with one sensor on each side of the vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera that has no moving parts other than a fan (such as a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use Class I (eye-safe) laser pulses of 5 nanoseconds per frame and can capture the reflected laser in the form of 3D range point clouds and co-registered intensity data.

[0206] In at least one embodiment, the vehicle 1200 may further include one or more IMU sensors 1266. In at least one embodiment, one or more IMU sensors 1266 may be located at the center of the rear axle of the vehicle 1200, in at least one embodiment. In at least one embodiment, one or more IMU sensors 1266 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, one or more IMU sensors 1266 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, one or more IMU sensors 1266 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0207] In at least one embodiment, one or more IMU sensors 1266 can be implemented as a miniature high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, one or more IMU sensors 1266 can enable the vehicle 1200 to estimate its heading without input from a magnetic sensor by directly observing and correlating the speed changes from the GPS to one or more IMU sensors 1266. In at least one embodiment, one or more IMU sensors 1266 and one or more GNSS sensors 1258 can be combined in a single integrated unit.

[0208] In at least one embodiment, vehicle 1200 may include one or more microphones 1296 placed inside and / or around vehicle 1200. In at least one embodiment, in addition, one or more microphones 1296 may be used for emergency vehicle detection and identification.

[0209] In at least one embodiment, vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide-angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long-range cameras 1298, one or more mid-range cameras 1276, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire perimeter of vehicle 1200. In at least one embodiment, the type of camera used depends on vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around vehicle 1200. In at least one embodiment, the number of cameras may vary according to the embodiment. For example, in at least one embodiment, vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. The cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each camera may be described in more detail previously herein with reference to Figure 12A and Figure 12B may be described in more detail.

[0210] In at least one embodiment, vehicle 1200 may further include one or more vibration sensors 1242. One or more vibration sensors 1242 may measure the vibration of components of vehicle 1200 (e.g., an axle). For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1242 are used, the difference between the vibrations may be used to determine the friction or slippage of the road surface (e.g., when there is a vibration difference between a powered drive axle and a freely rotating axle).

[0211] In at least one embodiment, vehicle 1200 may include an ADAS system 1238. The ADAS system 1238 may include, but is not limited to, a SoC. In at least one embodiment, the ADAS system 1238 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions and combinations thereof.

[0212] In at least one embodiment, the ACC system may use one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle adjacent to vehicle 1200 and automatically adjusts the speed of vehicle 1200 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that vehicle 1200 change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0213] In at least one embodiment, the CACC system uses information from other vehicles, which may be received via a wireless link from other vehicles via a network interface 1224 and / or one or more wireless antennas 1226 or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Generally, the V2V communication concept provides information about the vehicle immediately ahead (e.g., the vehicle immediately in front of and in the same lane as vehicle 1200), while the I2V communication concept provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, in the case of information about the vehicle ahead of a given vehicle 1200, the CACC system may be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0214] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward camera and / or one or more RADAR sensors 1260, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid braking pulses.

[0215] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system can use one or more forward cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or braking for an impending collision.

[0216] In at least one embodiment, when the vehicle 1200 crosses a lane marking, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn the driver. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure by activating the turn signal. In at least one embodiment, the LDW system can use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variant of the LDW system. If the vehicle 1200 starts to leave the lane, the LKA system provides steering input or braking to correct the vehicle 1200.

[0217] In at least one embodiment, the BSW system detects and warns a vehicle driver in a vehicle's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0218] In at least one embodiment, when an object is detected outside the rear camera range while the vehicle 1200 is in reverse, the RCTW system can provide visual, audible, and / or haptic notifications. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1260, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0219] In at least one embodiment, conventional ADAS systems may be prone to producing false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to decide whether a safety condition truly exists and take appropriate action. In at least one embodiment, in the case of conflicting results, the vehicle 1200 itself decides whether to heed the results of the primary computer or the secondary computer (e.g., the first controller 1236 or the second controller 1236 of the controller 1236). For example, in at least one embodiment, the ADAS system 1238 can be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run various software redundantly on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1238 can be provided to the monitoring MCU. In at least one embodiment, if the outputs of the primary computer and the auxiliary computer conflict, the supervisory MCU decides how to reconcile the conflict to ensure safe operation.

[0220] In at least one embodiment, the host computer may be configured to provide a confidence score to the supervisory MCU to indicate the host computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the host computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, in the case where the confidence score does not meet the threshold and where the host computer and the secondary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine an appropriate result.

[0221] In at least one embodiment, the supervisory MCU may be configured to run a neural network that is trained and configured to determine, at least in part based on the outputs from the host computer and the secondary computer, the conditions under which the secondary computer provides a false alarm. In at least one embodiment, the neural network in the supervisory MCU may learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system identifies a metallic object that is not actually dangerous, such as a drainage grate or manhole cover that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when there is a bicyclist or pedestrian present and when lane departure is actually the safest course of action. In at least one embodiment, the supervisory MCU may include at least one of a DLA or a GPU suitable for running a neural network with an associated memory. In at least one embodiment, the supervisory MCU may be included as and / or be a component of one or more SoCs 1204.

[0222] In at least one embodiment, the ADAS system 1238 may include a secondary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the secondary computer may use classical computer vision rules (if-then), and the presence of the neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the overall system more fault-tolerant, especially for faults caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the host computer and the different software code running on the secondary computer provides the same overall result, the supervisory MCU may be more confident that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not cause a significant error.

[0223] In at least one embodiment, the output of the ADAS system 1238 can be input into the perception module of the host computer and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the auxiliary computer can have its own neural network, which is trained to reduce the risk of false positives.

[0224] In at least one embodiment, the vehicle 1200 can further include an infotainment SoC 1230 (e.g., in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system 1230 can not be an SoC and can include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1230 can include, but is not limited to, a combination of hardware and software, which can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assistance, radio data system, vehicle-related information such as fuel level, total covered distance, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle. For example, the infotainment SoC 1230 can include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, car, in-vehicle entertainment system, WiFi, steering wheel audio control, hands-free voice control, head-up display (“HUD”), HMI display 1234, telematics device, control panel (e.g., for controlling various components, features, and / or systems and / or interacting therewith) and / or other components. In at least one embodiment, the infotainment SoC 1230 can further be used to provide information (e.g., visual and / or auditory) to the user of the vehicle, such as information from the ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0225] In at least one embodiment, the infotainment SoC 1230 may include any number and type of GPU capabilities. In at least one embodiment, the infotainment SoC 1230 may communicate with other devices, systems, and / or components of the vehicle 1200 via a bus 1202 (such as a CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 1230 may be coupled to a monitoring MCU such that the GPU of the infotainment system can perform some autonomous driving functions in the event of a failure of the main controller 1236 (e.g., the main computer and / or standby computer of the vehicle 1200). In at least one embodiment, the infotainment SoC 1230 may cause the vehicle 1200 to enter a driver-to-safe stop mode as described herein.

[0226] In at least one embodiment, the vehicle 1200 may further include a dashboard 1232 (e.g., a digital dashboard, an electronic dashboard, a digital instrument cluster, etc.). The dashboard 1232 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, the dashboard 1232 may include, but is not limited to, any number and combination of a set of gauges, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine fault lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1230 and the dashboard 1232. In at least one embodiment, the dashboard 1232 may be included as part of the infotainment SoC 1230, and vice versa.

[0227] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, the inference and / or training logic 915 may be used in a system Figure 12C to infer or predict operations at least in part based on weight parameters calculated using neural network training operations \ neural network functions and / or architectures or neural network use cases described herein.

[0228] In at least one embodiment, the spatially adaptive separable convolutional layer 7 may be used with a system Figure 12C to infer and predict operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0229] Figure 12D A diagram of a system 1276 for communicating between a cloud-based server and an Figure 12A autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, the system 1276 may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. The one or more servers 1278 may include, but are not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(H) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). The GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected by high-speed connection lines, such as, but not limited to, the NVLink interface 1288 and / or the PCIe connection 1286 developed by NVIDIA. In at least one embodiment, the GPUs 1284 are connected via NVLink and / or an NVSwitchSoC, and the GPUs 1284 and the PCIe switches 1282 are connected via a PCIe interconnect. In at least one embodiment, although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1278 may include, but is not limited to, any combination of any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282. For example, in at least one embodiment, each of the one or more servers 1278 may include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0230] In at least one embodiment, one or more servers 1278 may receive, via one or more networks 1290, image data representing an image from a vehicle that depicts an unexpected or changed road condition, such as a recently started roadwork. In at least one embodiment, one or more servers 1278 may transmit, via one or more networks 1290, an updated neural network 1292, and / or map information 1294, including but not limited to information regarding traffic and road conditions, to the vehicle. In at least one embodiment, an update to the map information 1294 may include but not limited to an update to the HD map 1222, such as information regarding construction sites, potholes, detours, floods, and / or other obstacles. In at least one embodiment, the neural network 1292, the updated neural network 1292, and / or the map information 1294 may be generated by new training and / or experiences represented in data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 1278 and / or other servers).

[0231] In at least one embodiment, one or more servers 1278 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. The training data may be generated by vehicles, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., in cases where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., in cases where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1290, and / or the machine learning model may be used by one or more servers 1278 to remotely monitor the vehicle).

[0232] In at least one embodiment, one or more servers 1278 may receive data from a vehicle and apply the data to a most recent real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1278 may include a deep learning supercomputer powered by one or more GPUs 1284 and / or a dedicated AI computer, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 may include a deep learning infrastructure of a data center powered by CPUs.

[0233] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of performing fast, real-time inference and may use that ability to evaluate and verify the health of the processors, software, and / or associated hardware in vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1200, such as an image sequence and / or objects that vehicle 1200 has located within that image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to the objects identified by vehicle 1200, and if the results do not match and the deep learning infrastructure determines that the AI in vehicle 1200 is malfunctioning, one or more servers 1278 may send a signal to vehicle 1200 to instruct the fail-safe computer in vehicle 1200 to take control, notify the passengers, and complete a safe parking operation.

[0234] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration may enable real-time response. In at least one embodiment, for example, in cases where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, the hardware architecture 915 is used to execute one or more embodiments. This is described in conjunction with Figure 9A and / or Figure 9B Provide details regarding the hardware architecture 915.

[0235] Computer System

[0236] Figure 13 is a block diagram showing an exemplary computer system according to at least one embodiment, which exemplary computer system may be a system with interconnected devices and components, a system-on-chip (SOC), or some combination thereof formed with a processor 1300, which processor may include execution units to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, computer system 1300 may include, but is not limited to, components such as a processor 1302, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 1300 may include a processor, such as available from Intel Corporation of Santa Clara, California processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM a microprocessor, although other systems can also be used, including PCs with other microprocessors, engineering workstations, set-top boxes, etc. In at least one embodiment, the computer system 1300 can execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0237] Embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), systems on a chip, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0238] In at least one embodiment, the computer system 1300 can include, but is not limited to, a processor 1302, which can include, but is not limited to, one or more execution units 1308 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the system 13 is a single-processor desktop or server system, but in another embodiment, the system 13 can be a multi-processor system. In at least one embodiment, the processor 1302 can include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1302 can be coupled to a processor bus 1310, which can transfer data signals between the processor 1302 and other components in the computer system 1300.

[0239] In at least one embodiment, the processor 1302 may include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 1304. In at least one embodiment, the processor 1302 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to the processor 1302. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and requirements. In at least one embodiment, the register file 1306 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and instruction pointer registers.

[0240] In at least one embodiment, the execution unit 1308, which includes logic for performing integer and floating point operations, among other things, is also located within the processor 1302. The processor 1302 may also include a microcode (“ucode”) read only memory (“ROM”) for storing the microcode for certain macroinstructions. In at least one embodiment, the execution unit 1308 may include logic for processing the packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309 in the instruction set of the general purpose processor 1302, along with the associated circuitry for the instructions to be executed, operations used by many multimedia applications may be performed using the packed data in the general purpose processor 1302. In one or more embodiments, operations may be performed on the packed data by using the full width of the processor's data bus, which may obviate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time, to accelerate and more efficiently execute many multimedia applications.

[0241] In at least one embodiment, the execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, the computer system 1300 may include, but is not limited to, a memory 1320. In at least one embodiment, the memory 1320 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. The memory 1320 may store instructions 1319 and / or data 1321 represented by data signals that may be executed by the processor 1302.

[0242] In at least one embodiment, the system logic chip may be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip may include, but is not limited to, a Memory Controller Hub (“MCH”) 1316, and the processor 1302 may communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 may provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 may initiate data signals among the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals among the processor bus 1310, the memory 1320, and the system I / O 1322. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 may be coupled to the memory 1320 via the high-bandwidth memory path 1318, and the graphics / video card 1312 may be coupled to the MCH 1316 via an Accelerated Graphics Port (“AGP”) interconnect 1314.

[0243] In at least one embodiment, the computer system 1300 may use the system I / O 1322, which is a proprietary hub interface bus, to couple the MCH 1316 to an I / O Controller Hub (“ICH”) 1330. In at least one embodiment, the ICH 1330 may provide direct connections to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1320, the chipset, and the processor 1302. Examples may include, but are not limited to, an audio controller 1329, a Firmware Hub (“Flash BIOS”) 1328, a wireless transceiver 1326, a data storage 1324, a legacy I / O controller 1323 that includes a user input and a keyboard interface, a serial expansion port 1327 (such as a Universal Serial Bus (USB)), and a network controller 1334. The data storage 1324 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash device, or other mass storage devices.

[0244] In at least one embodiment, Figure 13 a system is shown that includes interconnected hardware devices or “chips”, and in other embodiments, Figure 13An exemplary system-on-chip (SoC) can be shown. In at least one embodiment, the device shown in FIG. cc can be interconnected with a dedicated interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1300 are interconnected using a Compute Express Link (CXL) interconnect.

[0245] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 915 are provided herein in conjunction with Figure 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 can be used in a system Figure 13 to infer or predict operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures or neural network usages described herein.

[0246] In at least one embodiment, the spatially adaptive separable convolutional layer 7 can be used with the system Figure 13 to infer and predict operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0247] Figure 14 is a block diagram showing an electronic device 1400 for utilizing a processor 1410 according to at least one embodiment. In at least one embodiment, the electronic device 1400 can be, for example but not limited to, a notebook, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0248] In at least one embodiment, system 1400 can include, but is not limited to, a processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1410 is coupled using a bus or interface, such as an I 2 C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advanced Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 14 shows a system including interconnected hardware devices or “chips,” while in other embodiments, Figure 14 an exemplary system-on-chip (SoC) can be shown. In at least one embodiment, Figure 14The devices shown in the figure can be interconnected with dedicated interconnections, standardized interconnections (e.g., PCIe), or some combination thereof. In at least one embodiment, a Compute Express Link (CXL) interconnect is used to interconnect Figure 14 one or more components of.

[0249] In at least one embodiment, Figure 14 may include a display 1424, a touch screen 1425, a touchpad 1430, a Near Field Communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, an Embedded Controller (“EC”) 1435, a Trusted Platform Module (“TPM”) 1438, a BIOS / Firmware / Flash (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 “SSD or HDD” (such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”)), a Wireless Local Area Network unit (“WLAN”) 1450, a Bluetooth unit 1452, a Wireless Wide Area Network unit (“WWAN”) 1456, a Global Positioning System (GPS) 1455, a camera (“USB 3.0 camera”) 1454 (such as a USB 3.0 camera), or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented, for example, to the LPDDR3 standard. These components can each be implemented in any suitable manner.

[0250] In at least one embodiment, other components can be communicatively coupled to the processor 1410 through the components discussed above. In at least one embodiment, an accelerometer 1441, an Ambient Light Sensor (“ALS”) 1442, a compass 1443, and a gyroscope 1444 can be communicatively coupled to the sensor hub 1440. In at least one embodiment, a thermal sensor 1439, a fan 1437, a keyboard 1446, and a touchpad 1430 can be communicatively coupled to the EC 1435. In at least one embodiment, a speaker 1463, headphones 1464, and a microphone (“mic”) 1465 can be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 1464, which in turn can be communicatively coupled to the DSP 1460. In at least one embodiment, the audio unit 1464 can include, for example but not limited to, an audio encoder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a Subscriber Identity Module (“SIM”) 1457 can be communicatively coupled to the WWAN unit 1456. In at least one embodiment, components such as the WLAN unit 1450, the Bluetooth unit 1452, and the WWAN unit 1456 can be implemented in a Next Generation Form Factor (“NGFF”).

[0251] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are provided herein in connection with Figure 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be in a Figure 14 system for inferring or predicting operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network usage described herein.

[0252] In at least one embodiment, the spatially adaptive separable convolutional layer 7 may be used with the system Figure 14 for inferring and predicting operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0253] Figure 15 FIG. 13 illustrates a computer system 1500 in accordance with at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0254] In at least one embodiment, the computer system 1500 includes, but is not limited to, at least one central processing unit (“CPU”) 1502 that is connected to a communication bus 1510 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), PCI-Express (“Peripheral Component Interconnect Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1500 includes, but is not limited to, a main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in the main memory 1504, which may take the form of random access memory (“RAM”). In at least one embodiment, the network interface subsystem (“network interface”) 1522 provides an interface to other computing devices and networks for receiving data from other systems and transmitting data to other systems having the computer system 1500.

[0255] In at least one embodiment, computer system 1500 includes, but is not limited to, input device 1508, parallel processing system 1512, and a display device 1506 that may be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”), plasma display, or other suitable display technology. In at least one embodiment, user input is received from input devices 1508 such as a keyboard, mouse, touchpad, microphone, or more. In at least one embodiment, each of the foregoing modules may be located on a single semiconductor platform to form a processing system.

[0256] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 915 are provided herein in conjunction with Figure 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in a system Figure 15 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures or neural network usage described herein.

[0257] In at least one embodiment, spatial adaptive separable convolutional layer 7 may be used with a system Figure 15 to infer and predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0258] Figure 16 FIG. shows a computer system 1600 according to at least one embodiment. In at least one embodiment, computer system 1600 includes, but is not limited to, computer 1610 and USB stick 1620. In at least one embodiment, computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, computer 1610 includes, but is not limited to, servers, cloud instances, laptop computers, and desktop computers.

[0259] In at least one embodiment, the USB stick 1620 includes, but is not limited to, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing core 1630 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1630 includes an application specific integrated circuit (“ASIC”) optimized to perform any amount and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1630 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1630 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0260] In at least one embodiment, the USB interface 1640 can be any type of USB connector or USB socket. For example, in at least one embodiment, the USB interface 1640 is a USB Type-C socket for data and power. In at least one embodiment, the USB interface 1640 is a USB Type-A connector. In at least one embodiment, the USB interface logic 1650 can include any amount and type of logic that enables the processing unit 1630 to engage with a device (e.g., computer 1610) via the USB connector 1640.

[0261] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, inference and / or training logic 915 can be used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network usage described herein.

[0262] In at least one embodiment, the spatially adaptive separable convolution layer 7 can be used with the system Figure 16 to infer and predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0263] Figure 17AAn exemplary architecture is shown, in which multiple GPUs 1710-1713 are communicatively coupled to multiple multi-core processors 1705-1706 via high-speed links 1740-1743 (e.g., bus / point-to-point interconnect, etc.). In one embodiment, the high-speed links 1740-1743 support a communication throughput of 4GB / s, 30GB / s, 80GB / s or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0264] In addition, in one embodiment, two or more of the GPUs 1710-1713 are interconnected via high-speed links 1729-1730, which can be implemented using the same or different protocols / links as those used for the high-speed links 1740-1743. Similarly, two or more of the multi-core processors 1705-1706 can be connected via a high-speed link 1728, which can be a symmetric multi-processor (SMP) bus operating at a speed of 20GB / s, 30GB / s, 120GB / s or higher. Alternatively, the same protocol / link (e.g., via a common interconnect structure) can be used to complete Figure 17A all communications between the various system components shown in

[0265] In at least one embodiment, each of the multi-core processors 1705-1706 is communicatively coupled to a processor memory 1701-1702 via a memory interconnect 1726-1727, and each of the GPUs 1710-1713 is communicatively coupled to a GPU memory 1720-1723 via a GPU memory interconnect 1750-1753. The memory interconnects 1726-1727 and 1750-1753 can utilize the same or different memory access technologies. By way of example and not limitation, the processor memories 1701-1702 and the GPU memories 1720-1723 can be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, some portions of the processor memories 1701-1702 can be volatile memories while other portions can be non-volatile memories (e.g., using a two-level memory (2LM) hierarchy).

[0266] As described herein, although the various core processors 1705-1706 and GPUs 1710-1713 may be physically coupled to specific memories 1701-1702, 1720-1723 respectively, a unified memory architecture may be implemented where the same virtual system address space (also referred to as the "effective address" space) is distributed among the various physical memories. For example, the processor memories 1701-1702 may each contain 64GB of the system memory address space, and the GPU memories 1720-1723 may each contain 32GB of the system memory address space (in this example, resulting in a total addressable memory size of 256GB).

[0267] Figure 17B Additional details for the interconnection between the multi-core processor 1707 and the graphics acceleration module 1746 according to one exemplary embodiment are shown. The graphics acceleration module 1746 may include one or more GPU chips integrated on a line card that is coupled to the processor 1707 via a high-speed link 1740. Alternatively, the graphics acceleration module 1746 may be integrated on the same package or chip as the processor 1707.

[0268] In at least one embodiment, the illustrated processor 1707 includes multiple cores 1760A-1760D, each core having a translation lookaside buffer 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, the cores 1760A-1760D may include various other components (not shown) for executing instructions and processing data. The caches 1762A-1762D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1756 may be included within the caches 1762A-1762D and shared by groups of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 1707 and the graphics acceleration module 1746 are connected to the system memory 1714, which may include Figure 17A the processor memories 1701-1702 therein.

[0269] Maintain coherence for data and instructions stored in respective caches 1762A - 1762D, 1756, and system memory 1714 via coherence bus 1764 through inter-core communication. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via coherence bus 1764 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is executed via coherence bus 1764 to snoop cache accesses.

[0270] In one embodiment, proxy circuit 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764, thereby allowing graphics acceleration module 1746 to participate in the cache coherence protocol as a peer of cores 1760A - 1760D. In particular, interface 1735 provides a connection to proxy circuit 1725 via high-speed link 1740 (e.g., PCIe bus, NVLink, etc.), and interface 1737 connects graphics acceleration module 1746 to link 1740.

[0271] In one implementation, accelerator integrated circuit 1736 provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines 1731, 1732, N of the graphics acceleration module. Graphics processing engines 1731, 1732, N may each include a separate graphics processing unit (GPU). Alternatively, graphics processing engines 1731, 1732, N may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1746 may be a GPU having multiple graphics processing engines 1731 - 1732, N, or graphics processing engines 1731 - 1732, N may be individual GPUs integrated on a common package, line card, or chip.

[0272] In one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and also includes a memory access protocol for accessing system memory 1714. The MMU 1739 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, the cache 1738 stores commands and data for efficient access by the graphics processing engines 1731-1732,N. In at least one embodiment, the data stored in the cache 1738 and the graphics memories 1733-1734,M is kept consistent with the core caches 1762A-1762D, 1756, and the system memory 1714. As previously described, this task can be accomplished via the proxy circuit 1725 on behalf of the cache 1738 and the graphics memories 1731-1732,M (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 1762A-1762D, 1756 to the cache 1738 and receiving updates from the cache 1738).

[0273] A set of registers 1745 stores context data for the threads executed by the graphics processing engines 1731-1732,N, and the context management circuit 1748 manages the thread contexts. For example, the context management circuit 1748 may perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, the context management circuit 1748 may store the current register values into a specified area in memory (e.g., identified by a context pointer) during a context switch. Then, the register values can be restored when the context is returned. In one embodiment, the interrupt management circuit 1747 receives and processes interrupts received from system devices.

[0274] In one implementation, the MMU 1739 converts virtual / valid addresses from the graphics processing engine 1731 into real / physical addresses in the system memory 1714. One embodiment of the accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. The graphics accelerator modules 1746 may be dedicated to a single application executing on the processor 1707 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1731 - 1732, N are shared among multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into "slices" based on processing requirements and priorities associated with the VMs and / or applications, and these slices are allocated to different VMs and / or applications.

[0275] In at least one embodiment, the accelerator integrated circuit 1736 acts as a bridge for the system of the graphics accelerator modules 1746 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 1736 may provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1731 - 1732.

[0276] Since the hardware resources of the graphics processing engines 1731 - 1732, N are explicitly mapped to the real address space seen by the host processor 1707, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 1736 is to physically isolate the graphics processing engines 1731 - 1732, N such that they appear as independent units to the system.

[0277] In at least one embodiment, one or more graphics memories 1733 - 1734, M are coupled to each of the graphics processing engines 1731 - 1732, N respectively. The graphics memories 1733 - 1734, M store instructions and data that are processed by each of the graphics processing engines 1731 - 1732, N. The graphics memories 1733 - 1734, M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6) or HBM, and / or may be non - volatile memories such as 3D XPoint or Nano - Ram.

[0278] In one embodiment, to reduce data traffic on link 1740, a biasing technique is used to ensure that the data stored in graphics memories 1733 - 1734, M is the data most frequently used by graphics processing engines 1731 - 1732, N, and preferably data not used (or at least not frequently used) by cores 1760A - 1760D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not by graphics processing engines 1731 - 1732, N) in caches 1762A - 1762D, 1756 of the cores and system memory 1714.

[0279] Figure 17C Another exemplary embodiment is shown where accelerator integrated circuit 1736 is integrated within processor 1707. In this embodiment, graphics processing engines 1731 - 1732, N communicate directly with accelerator integrated circuit 1736 via interface 1737 and interface 1735 (which can also utilize any form of bus or interface protocol) over high - speed link 1740. Accelerator integrated circuit 1736 can perform the same operations as described with respect to Figure 17B the operations described. However, due to its close proximity to coherence bus 1764 and caches 1762A - 1762D, 1756, it may have higher throughput. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include programming models controlled by accelerator integrated circuit 1736 and programming models controlled by graphics acceleration module 1746.

[0280] In at least one embodiment, graphics processing engines 1731 - 1732, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1731 - 1732, N, thereby providing virtualization within a VM / partition.

[0281] In at least one embodiment, graphics processing engines 1731 - 1732, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1731 - 1732, N to allow each operating system to access them. For a single - partition system without a hypervisor, the operating system owns graphics processing engines 1731 - 1732, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1731 - 1732, N to provide access to each process or application.

[0282] In at least one embodiment, the graphics acceleration module 1746 or individual graphics processing engines 1731-1732, N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 1714 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process (i.e., the calling system software to add the process element to the process element linked list) when registering its context with the graphics processing engines 1731-1732, N. In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0283] Figure 17D An exemplary accelerator integration slice 1790 is shown. As used herein, "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1736. An application is an effective address space 1782 in the system memory 1714 that stores a process element 1783. In one embodiment, in response to a GPU call 1781 from an application 1780 executing on the processor 1707, the process element 1783 is stored. The process element 1783 contains the process state of the corresponding application 1780. The work descriptor (WD) 1784 contained in the process element 1783 can be a single job requested by the application or can contain a pointer to a job queue. In at least one embodiment, the WD 1784 is a pointer to a job request queue in the address space 1782 of the application.

[0284] The graphics acceleration module 1746 and / or the individual graphics processing engines 1731-1732, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure can be included for setting the process state and sending the WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment.

[0285] In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 1746 or an individual graphics processing engine 1731. Since the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0286] In operation, the WD fetch unit 1791 in the accelerator integrated slice 1790 fetches the next WD 1784, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1746. Data from the WD 1784 can be stored in the register 1745 and used by the MMU 1739, the interrupt management circuit 1747, and / or the context management circuit 1748, as shown. For example, one embodiment of the MMU 1739 includes a segment / page walk circuit for accessing segment / page tables 1786 within the OS virtual address space 1785. The interrupt management circuit 1747 can process interrupt events 1792 received from the graphics acceleration module 1746. When performing a graphics operation, the virtual address 1793 generated by the graphics processing engines 1731 - 1732, N is translated to a physical address by the MMU 1739.

[0287] In one embodiment, the same set of registers 1745 is replicated for each of the graphics processing engines 1731 - 1732, N and / or the graphics acceleration module 1746, and the registers 1745 can be initialized by a hypervisor or an operating system. Each of these replicated registers can be included in the accelerator integrated slice 1790. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0288] Table 1 – Hypervisor Initialized Registers

[0289]

[0290] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0291] Table 2 – Operating System Initialized Registers

[0292]

[0293]

[0294] In one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731 - 1732, N. It contains all the information required for the graphics processing engines 1731 - 1732, N to complete the work, or it can be a pointer to a memory location where the application has set up a command queue of work to be done.

[0295] Figure 17EAdditional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1798 in which a list of process elements 1799 is stored. The hypervisor real address space 1798 can be accessed via a hypervisor 1796 that virtualizes a graphics acceleration module engine for an operating system 1795.

[0296] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1746. There are two programming models in which the graphics acceleration module 1746 is shared by multiple processes and partitions, time slice sharing and graphics directed sharing.

[0297] In this model, the system hypervisor 1796 owns the graphics acceleration module 1746 and makes its functionality available to all operating systems 1795. For the graphics acceleration module 1746 to support virtualization through the system hypervisor 1796, the graphics acceleration module 1746 can comply with the following conditions: 1) The job requests of the application must be autonomous (i.e., do not need to maintain state between jobs), or the graphics acceleration module 1746 must provide a context save and restore mechanism. 2) The graphics acceleration module 1746 guarantees that the job requests of the application are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1746 provides the ability to preempt job processing. 3) When operating in the directed sharing programming model, fairness must be ensured between the processes of the graphics acceleration module 1746.

[0298] In at least one embodiment, the application 1780 is required to use the type of the graphics acceleration module 1746, the work descriptor (WD), the authority mask register (AMR) value, and the context save / restore area pointer (CSRP) for system calls of the operating system 1795. In at least one embodiment, the type of the graphics acceleration module 1746 describes the target acceleration function for system calls. In at least one embodiment, the type of the graphics acceleration module 1746 can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and can take the form of a graphics acceleration module 1746 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing the work to be done by the graphics acceleration module 1746. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 1736 and the graphics acceleration module 1746 does not support the user authority mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 1796 can selectively apply the current authority mask override register (AMOR) value before placing the AMR in the process element 1783. In at least one embodiment, the CSRP is one of the registers 1745 that contains the valid address of a region in the address space 1782 of the application for the graphics acceleration module 1746 to save and restore the context state. If it is not necessary to save the state between jobs or when the job is preempted, this pointer is optional. In at least one embodiment, the context save / restore area can be fixed system memory.

[0299] Upon receiving a system call, the operating system 1795 can verify that the application 1780 has been registered and is granted the permission to use the graphics acceleration module 1746. Then, the operating system 1795 uses the information shown in Table 3 to call the hypervisor 1796.

[0300] Table 3 – Call Parameters from Operating System to Hypervisor

[0301] 1 Work Descriptor (WD) 2 Access Mask Register (AMR) Value (May be Masked) 3 Effective Address (EA) Context Save / Restore Area Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0302] Upon receiving a hypervisor call, the hypervisor 1796 verifies that the operating system 1795 has been registered and is granted the permission to use the graphics acceleration module 1746. Then, the hypervisor 1796 places the process element 1783 into the process element linked list of the corresponding type of the graphics acceleration module 1746. The process element can include the information shown in Table 4.

[0303] Table 4 – Process Element Information

[0304]

[0305]

[0306] In at least one embodiment, the hypervisor initializes a plurality of accelerator integrated slice 1790 registers 1745.

[0307] As Figure 17F shown, in at least one embodiment, a unified memory is used, and the unified memory can be addressed via a common virtual memory address space for accessing the physical processor memories 1701 - 1702 and the GPU memories 1720 - 1723. In this implementation, operations executed on the GPUs 1710 - 1713 utilize the same virtual / effective memory address space to access the processor memories 1701 - 1702, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 1701, a second portion is allocated to the second processor memory 1702, a third portion is allocated to the GPU memory 1720, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memories 1701 - 1702 and the GPU memories 1720 - 1723, thereby allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0308] In one embodiment, the bias / coherency management circuits 1794A - 1794E within one or more MMUs 1739A - 1739E ensure cache coherency between one or more host processors (e.g., 1705) and the caches of the GPUs 1710 - 1713, and implement a bias technique for the physical memory indicating where certain types of data should be stored. Although Figure 17F multiple instances of the bias / coherency management circuits 1794A - 1794E are shown, the bias / coherency circuits can be implemented within the MMUs of one or more host processors 1705 and / or within the accelerator integrated circuit 1736.

[0309] One embodiment allows mapping the GPU-attached memories 1720-1723 as part of the system memory and accessing them using shared virtual memory (SVM) technology, without suffering performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access the GPU-attached memories 1720-1723 as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 1705 software to set operands and access compute results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU-attached memories 1720-1723 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 1710-1713. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0310] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page-granularity structure (e.g., controlled at the granularity of memory pages), and this page-granularity structure includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, with or without a bias cache in the GPUs 1710-1713 (e.g., for caching frequently / most recently used entries of the bias table), the bias table may be implemented in the stolen memory ranges of one or more of the GPU-attached memories 1720-1723. Alternatively, the entire bias table may be maintained within the GPU.

[0311] In at least one embodiment, before actually accessing the GPU memory, the bias table entries associated with each access to the GPU attached memories 1720 - 1723 are accessed, thereby causing the following operations. First, local requests from the GPUs 1710 - 1713 that find their pages in the GPU bias are directly forwarded to the corresponding GPU memories 1720 - 1723. Local requests from the GPUs that find their pages in the host bias are forwarded to the processor 1705 (e.g., via the high - speed link discussed above). In one embodiment, requests from the processor 1705 that find the requested page in the host - processor bias complete requests similar to normal memory reads. Alternatively, requests that point to GPU - bias pages can be forwarded to the GPUs 1710 - 1713. In at least one embodiment, if the GPU is not currently using a page, the GPU can subsequently migrate the page to the host - processor bias. In at least one embodiment, the bias state of a page can be changed by a software - based mechanism, a software - assisted - by - hardware mechanism, or, in limited cases, by a purely hardware - based mechanism.

[0312] A mechanism for changing the bias state employs an API call (e.g., OpenCL), which then calls the device driver of the GPU. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and perform a cache flush operation in the host in some migrations. In at least one embodiment, the cache flush operation is used for migrations from the host - processor 1705 bias to the GPU bias, but not for the reverse migration.

[0313] In one embodiment, cache coherence is maintained by temporarily rendering GPU - bias pages that cannot be cached by the host - processor 1705. To access these pages, the processor 1705 can request access from the GPU 1710, and the GPU 1710 may or may not immediately grant access. Thus, to reduce communication between the processor 1705 and the GPU 1710, it is beneficial to ensure that GPU - bias pages are pages required by the GPU rather than the host - processor 1705, and vice versa.

[0314] One or more hardware structures 915 are used to execute one or more embodiments. Details regarding one or more of the said hardware structures 915 are provided herein in conjunction with Figure 9A and / or Figure 9B

[0315] Figure 18Shows an exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein, which may be fabricated using one or more IP cores. In addition to the illustration, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0316] Figure 18 Is a block diagram showing an exemplary system on a chip integrated circuit 1800 that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1800 includes peripheral or bus logic, which includes a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and a sup.2S / I.sup.2C controller 1840. In at least one embodiment, integrated circuit 1800 may include a display device 1845 coupled to one or more of a high definition multimedia interface (HDMI) controller 1850 and a mobile industry processor interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1870.

[0317] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 9A and / or Figure 9B to provide details regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be in integrated circuit 1800 for inferring or predicting operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0318] In at least one embodiment, a spatially adaptive separable convolutional layer 7 may be used in integrated circuit diagram 1800 for inferring or predicting operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0319] Figure 19A - 19BIllustrates an exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein, which may be fabricated using one or more IP cores. In addition to the illustration, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0320] Figure 19A - 19B Is a block diagram illustrating an exemplary graphics processor used within a SoC in accordance with an embodiment described herein. Figure 19A Illustrates an exemplary graphics processor 1910 of a system-on-chip integrated circuit in accordance with at least one embodiment, which may be fabricated using one or more IP cores. Figure 19B Illustrates an additional exemplary graphics processor 1940 of a system-on-chip integrated circuit in accordance with at least one embodiment, which may be fabricated using one or more IP cores. In at least one embodiment, Figure 19A The graphics processor 1910 is a low-power graphics processor core. In at least one embodiment, Figure 19B The graphics processor 1940 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1910, 1940 may be Figure 18 A variant of the graphics processor 1810.

[0321] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A - 1915N (e.g., 1915A, 1915B, 1915C, 1915D through 1915N - 1, and 1915N). In at least one embodiment, the graphics processor 1910 may execute different shader programs via separate logic such that the vertex processor 1905 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 1915A - 1915N perform fragment (e.g., pixel) shading operations for fragment or pixel or shader programs. In at least one embodiment, the vertex processor 1905 executes the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1915A - 1915N use the primitives and vertex data generated by the vertex processor 1905 to generate a frame buffer to be displayed on a display device. In at least one embodiment, the one or more fragment processors 1915A - 1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0322] In at least one embodiment, the graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A - 1920B, one or more caches 1925A - 1925B, and one or more circuit interconnects 1930A - 1930B. In at least one embodiment, one or more MMUs 1920A - 1920B provide virtual - to - physical address mapping for the graphics processor 1910, including for the vertex processor 1905 and / or fragment processors 1915A - 1915N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1925A - 1925B. In at least one embodiment, one or more MMUs 1920A - 1920B may be synchronized with other MMUs within the system, including one or more MMUs associated with Figure 18 one or more application processors 1805, image processors 1815, and / or video processors 1820 such that each processor 1805 - 1820 may participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A - 1930B enable the graphics processor 1910 to connect to other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0323] In at least one embodiment, the graphics processor 1940 includes one or more MMU1920A - 1920B, caches 1925A - 1925B, and Figure 19A the circuit interconnects 1930A - 1930B of the graphics processor 1910. In at least one embodiment, the graphics processor 1940 includes one or more shader cores 1955A - 1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F to 1955N - 1, and 1955N), which provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of multiple shader cores may vary. In at least one embodiment, the graphics processor 1940 includes an inter - core task manager 1945, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1955A - 1955N and a tiling unit 1958 to accelerate tiling operations for tile - based rendering, where the rendering operation of a scene is subdivided in the image space, e.g., to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0324] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is combined herein with Figure 9A and / or Figure 9B to provide details regarding inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be in an integrated circuit Figure 19A and / or Figure 19B for performing inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions or architectures, or neural network use cases described herein.

[0325] In at least one embodiment, the spatially adaptive separable convolutional layer 7 may be used in integrated circuits 19A and / or 19B for performing inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0326] Figure 20A - 20B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 20A is shown that may be included in Figure 18 the graphics core 2000 within the graphics processor 1810, and in at least one embodiment, it may be the unified shader core 1955A - 1955N as Figure 19B shown. Figure 20B A highly parallel general - purpose graphics processing unit 2030 suitable for deployment on a multi - chip module is shown in at least one embodiment.

[0327] In at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, texture units 2018, and cache / shared memory 2020, which are common to the execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 may include multiple slices 2001A - 2001N or partitions per core, and the graphics processor may include multiple instances of the graphics core 2000. The slices 2001A - 2001N may include support logic, which includes local instruction caches 2004A - 2004N, thread schedulers 2006A - 2006N, thread dispatchers 2008A - 2008N, and a set of registers 2010A - 2010N. In at least one embodiment, the slices 2001A - 2001N may include a set of additional functional units (AFU 2012A - 2012N), floating - point units (FPU 2014A - 2014N), integer arithmetic logic units (ALU 2016A - 2016N), address calculation units (ACU 2013A - 2013N), double - precision floating - point units (DPFPU 2015A - 2015N), and matrix processing units (MPU 2017A - 2017N).

[0328] In at least one embodiment, the FPU 2014A - 2014N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while the DPFPU 2015A - 2015N performs double - precision (64 - bit) floating - point operations. In at least one embodiment, the ALU 2016A - 2016N can perform variable - precision integer operations with 8 - bit, 16 - bit, and 32 - bit precision and can be configured for mixed - precision operations. In at least one embodiment, the MPU 2017A - 2017N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, the MPU 2017A - 2017N can perform various matrix operations to accelerate machine - learning application frameworks, including enabling accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, the AFU 2012A - 2012N can perform additional logic operations not supported by the floating - point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0329] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Herein, in connection with Figure 9A and / or Figure 9BProvide details regarding inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 can be used in the graphics core 2000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0330] In at least one embodiment, the spatially adaptive separable convolutional layer 7 can be used in the graphics core 2000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0331] Figure 20B A general-purpose processing unit (GPGPU) 2030 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, the GPGPU 2030 can be directly linked to other instances of the GPGPU 2030 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, the GPGPU 2030 includes a host interface 2032 to enable connection to a host processor. In at least one embodiment, the host interface 2032 is a PCI Express interface. In at least one embodiment, the host interface 2032 can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 2030 receives commands from the host processor and uses a global scheduler 2034 to allocate execution threads associated with those commands to a group of compute clusters 2036A - 2036H. In at least one embodiment, the compute clusters 2036A - 2036H share a cache memory 2038. In at least one embodiment, the cache memory 2038 can serve as a higher-level cache for the cache memories within the compute clusters 2036A - 2036H.

[0332] In at least one embodiment, the GPGPU 2030 includes memories 2044A - 2044B, which are coupled to the compute clusters 2036A - 2036H via a set of memory controllers 2042A - 2042B. In at least one embodiment, the memories 2044A - 2044B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0333] In at least one embodiment, each of the compute clusters 2036A - 2036H includes a set of graphics cores, such asFigure 20A The graphics core 2000, which may include various types of integer and floating-point logic units that can perform computational operations across various precision ranges of a computer, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least one subset of the floating-point units in each of the compute clusters 2036A - 2036H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0334] In at least one embodiment, multiple instances of the GPGPU 2030 may be configured to function as compute clusters. In at least one embodiment, the communication for synchronization and data exchange among the compute clusters 2036A - 2036H varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 2030 communicate via the host interface 2032. In at least one embodiment, the GPGPU 2030 includes an I / O hub 2039 that couples the GPGPU 2030 to the GPU link 2040, enabling direct connection to other instances of the GPGPU 2030. In at least one embodiment, the GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization among multiple instances of the GPGP 2030. In at least one embodiment, the GPU link 2040 is coupled to a high-speed interconnect to send and receive data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 2030 are located in separate data processing systems and communicate via network devices accessible through the host interface 2032. In at least one embodiment, the GPU link 2040 may be configured to enable connection to a processor other than or in place of the host interface 2032.

[0335] In at least one embodiment, the GPGPU 2030 may be configured to train a neural network. In at least one embodiment, the GPGPU 2030 may be used within an inference platform. In at least one embodiment, in cases where the GPGPU 2030 is used for inference, the GPGPU may include fewer compute clusters 2036A - 2036H compared to when using the GPGPU to train a neural network. In at least one embodiment, the memory technology associated with the memories 2044A - 2044B may differ between inference and training configurations, with higher-bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2030 may support inference-specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during the inference operations of a deployed neural network.

[0336] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 9A and / or Figure 9B provide details regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in the GPGPU 2030 to infer or predict operations at least in part based on weight parameters computed using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0337] In at least one embodiment, the spatially adaptive separable convolutional layer 7 may be used in the GPGPU 2030 to infer or predict operations at least in part based on weight parameters computed using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0338] Figure 21 FIG. shows a block diagram of a computer system 2100 according to at least one embodiment. In at least one embodiment, the computer system 2100 includes a processing subsystem 2101 having one or more processors 2102 and a system memory 2104 communicating via an interconnect path that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset component or may be integrated within one or more of the processors 2102. In at least one embodiment, the memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In one embodiment, the I / O subsystem 2111 includes an I / O hub 2107 that may enable the computer system 2100 to receive input from one or more input devices 2108. In at least one embodiment, the I / O hub 2107 may enable a display controller to provide output to one or more display devices 2110A, and the display controller may be included within one or more of the processors 2102. In at least one embodiment, one or more display devices 2110A coupled to the I / O hub 2107 may include a local, internal, or embedded display device.

[0339] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 coupled to a memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 can be any of a number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the one or more parallel processors 2112 form a parallel or vector processing system for computing concentration, which can include a large number of processing cores and / or processing clusters, such as a Many Integrated Core (MIC) processor. In at least one embodiment, the one or more parallel processors 2112 form a graphics processing subsystem that can output pixels to one of one or more display devices 2110A coupled via an I / O hub 2107. In at least one embodiment, the one or more parallel processors 2112 can also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2110B.

[0340] In at least one embodiment, the system storage unit 2114 can be connected to the I / O hub 2107 to provide a storage mechanism for the computer system 2100. In at least one embodiment, an I / O switch 2116 can be used to provide an interface mechanism to enable connections between the I / O hub 2107 and other components, such as a network adapter 2118 and / or a wireless network adapter 2119 that can be integrated into the platform, as well as various other devices that can be added via one or more additional devices 2120. In at least one embodiment, the network adapter 2118 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2119 can include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0341] In at least one embodiment, the computer system 2100 can include other components not explicitly shown, including USB or other port connections, an optical storage drive, a video capture device, etc., which can also be connected to the I / O hub 2107. In at least one embodiment, any suitable protocol (such as a PCI (Peripheral Component Interconnect)-based protocol (such as PCI-Express) or other bus or point-to-point communication interface and / or protocol) can be used to implement the communication paths between the various components, such as an NV-Link high-speed interconnect or interconnect protocol. Figure 21 among the various components, such as an NV-Link high-speed interconnect or interconnect protocol.

[0342] In at least one embodiment, one or more parallel processors 2112 include circuitry optimized for graphics and video processing, the circuitry including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2112 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computer system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2112, memory hub 2105, processor 2102, and I / O hub 2107 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, the components of computer system 2100 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 2100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computer system.

[0343] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 9A and / or Figure 9B to provide details regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in Figure 21 system 2100 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0344] In at least one embodiment, a spatially adaptive separable convolutional layer 7 may be used in system 2100 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0345] Processor

[0346] Figure 22A A parallel processor 2200 is shown in accordance with at least one embodiment. In at least one embodiment, the various components of parallel processor 2200 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2200 is a Figure 21 variant of one or more of the parallel processors 2112 shown in accordance with an exemplary embodiment.

[0347] In at least one embodiment, the parallel processor 2200 includes a parallel processing unit 2202. In at least one embodiment, the parallel processing unit 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of the parallel processing unit 2202. In at least one embodiment, the I / O unit 2204 can be directly connected to other devices. In at least one embodiment, the I / O unit 2204 is connected to other devices by using a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between the memory hub 2105 and the I / O unit 2204 forms a communication link 2113. In at least one embodiment, the I / O unit 2204 is connected to a host interface 2206 and a memory crossbar 2216, where the host interface 2206 receives commands for performing processing operations and the memory crossbar 2216 receives commands for performing memory operations.

[0348] In at least one embodiment, when the host interface 2206 receives a command buffer via the I / O unit 2204, the host interface 2206 can direct the work operations to execute those commands to the front end 2208. In at least one embodiment, the front end 2208 is coupled to a scheduler 2210 that is configured to allocate commands or other work items to a processing cluster array 2212. In at least one embodiment, the scheduler 2210 ensures that the processing cluster array 2212 is properly configured and in an active state before tasks are assigned to the processing cluster array 2212 within the processing cluster array 2212. In at least one embodiment, the scheduler 2210 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 can be configured to perform complex scheduling and work distribution operations at both coarse-grained and fine-grained levels, enabling fast preemption and context switching of threads executing on the processing array 2212. In at least one embodiment, the host software can demonstrate the workload for scheduling on the processing array 2212 through one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically allocated on the processing array 2212 by the scheduler 2210 logic within the microcontroller including the scheduler 2210.

[0349] In at least one embodiment, the processing cluster array 2212 may include up to "N" processing clusters (e.g., cluster 2214A, cluster 2214B to cluster 2214N). In at least one embodiment, each of the clusters 2214A - 2214N of the processing cluster array 2212 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2210 may use various scheduling and / or work assignment algorithms to assign work to the clusters 2214A - 2214N of the processing cluster array 2212, which may vary according to the workload generated by each type of program or computation. In at least one embodiment, the scheduling may be handled dynamically by the scheduler 2210, or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the processing cluster array 2212. In at least one embodiment, different clusters 2214A - 2214N of the processing cluster array 2212 may be assigned to process different types of programs or to perform different types of computations.

[0350] In at least one embodiment, the processing cluster array 2212 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2212 is configured to perform general - purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2212 may include logic for performing processing tasks that include filtering of video and / or audio data, performing modeling operations, including physical operations, and performing data transformation.

[0351] In at least one embodiment, the processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2212 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 may transfer data from the system memory via the I / O unit 2204 for processing. In at least one embodiment, during processing, the transferred data may be stored in on - chip memory (e.g., parallel processor memory 2222) during processing and then written back to the system memory.

[0352] In at least one embodiment, when the parallel processing unit 2202 is used to perform graphics processing, the scheduler 2210 can be configured to divide the processing workload into tasks of approximately equal size to better distribute the graphics processing operations to the multiple clusters 2214A - 2214N of the processing cluster array 2212. In at least one embodiment, portions of the processing cluster array 2212 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2214A - 2214N can be stored in a buffer to allow the transfer of the intermediate data between the clusters 2214A - 2214N for further processing.

[0353] In at least one embodiment, the processing cluster array 2212 can receive processing tasks to be executed via the scheduler 2210, which receives commands defining the processing tasks from the front end 2208. In at least one embodiment, the processing tasks can include indices of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as status parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2210 can be configured to obtain the indices corresponding to the tasks, or can receive the indices from the front end 2208. In at least one embodiment, the front end 2208 can be configured to ensure that the processing cluster array 2212 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch - buffer, push buffer, etc.).

[0354] In at least one embodiment, each of one or more instances of parallel processing unit 2202 may be coupled to parallel processor memory 2222. In at least one embodiment, parallel processor memory 2222 may be accessed via memory crossbar 2216, which may receive memory requests from processing cluster array 2212 as well as I / O unit 2204. In at least one embodiment, memory crossbar 2216 may access parallel processor memory 2222 via memory interface 2218. In at least one embodiment, memory interface 2218 may include a plurality of partitioning units (e.g., partitioning unit 2220A, partitioning unit 2220B through partitioning unit 2220N), each of which may be coupled to a portion (e.g., a memory unit) of parallel processor memory 2222. In at least one embodiment, the plurality of partitioning units 2220A - 2220N are configured to be equal to the number of memory units such that first partitioning unit 2220A has a corresponding first memory unit 2224A, second partitioning unit 2220B has a corresponding memory unit 2224B, and Nth partitioning unit 2220N has a corresponding Nth memory unit 2224N. In at least one embodiment, the number of partitioning units 2220A - 2220N may not be equal to the number of memory devices.

[0355] In at least one embodiment, memory units 2224A - 2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2224A - 2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory units 2224A - 2224N, allowing partitioning units 2220A - 2220N to write portions of each rendering target in parallel to effectively utilize the available bandwidth of parallel processor memory 2222. In at least one embodiment, local instances of parallel processor memory 2222 may be excluded in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0356] In at least one embodiment, any one of clusters 2214A - 2214N in the processing cluster array 2212 can process data to be written into any of the memory cells 2224A - 2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar 2216 can be configured to transfer the output of each of clusters 2214A - 2214N to any of the partition units 2220A - 2220N or to another one of clusters 2214A - 2214N, where clusters 2214A - 2214N can perform additional processing operations on the output. In at least one embodiment, each of clusters 2214A - 2214N can communicate with the memory interface 2218 through the memory crossbar 2216 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar 2216 has connections to the memory interface 2218 to communicate with the I / O unit 2204 and connections to local instances of the parallel processor memory 2222, enabling processing units within different processing clusters 2214A - 2214N to communicate with system memory or other memories that are not local to the parallel processing units 2202. In at least one embodiment, the memory crossbar 2216 can use virtual channels to separate the traffic flow between clusters 2214A - 2214N and partition units 2220A - 2220N.

[0357] In at least one embodiment, multiple instances of the parallel processing unit 2202 can be provided on a single insertion card, or multiple insertion cards can be interconnected. In at least one embodiment, different instances of the parallel processing unit 2202 can be configured to operate interoperably, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2202 can include floating - point units with higher precision relative to other instances. In at least one embodiment, systems incorporating one or more instances of the parallel processing unit 2202 or parallel processor 2200 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, gaming consoles, and / or embedded systems.

[0358] Figure 22B is a block diagram of a partition unit 2220 according to at least one embodiment. In at least one embodiment, the partition unit 2220 is Figure 22AAn example of one of the partition units 2220A - 2220N. In at least one embodiment, the partition unit 2220 includes an L2 cache 2221, a frame buffer interface 2225, and a ROP 2226 (raster operation unit). The L2 cache 2221 is a read / write cache configured to perform load and store operations received from the memory crossbar 2216 and the ROP 2226. In at least one embodiment, the L2 cache 2221 outputs read misses and urgent write-back requests to the frame buffer interface 2225 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2225 for processing. In at least one embodiment, the frame buffer interface 2225 interacts with one of the memory units (such as Figure 22A the memory units 2224A - 2224N (e.g., within the parallel processor memory 2222)).

[0359] In at least one embodiment, the ROP 2226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, the ROP 2226 then outputs the processed graphic data stored in the graphics memory. In at least one embodiment, the ROP 2226 includes compression logic to compress depth or color data written to the memory and decompress depth or color data read from the memory. The compression logic can be lossless compression logic utilizing one or more of a variety of compression algorithms. The type of compression performed by the ROP 2226 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, delta color compression is performed based on depth and color data on a per-tile basis.

[0360] In at least one embodiment, the ROP 2226 is included within each processing cluster (e.g., clusters 2214A - 2214N of FIG. 22), rather than within the partition unit 2220. In at least one embodiment, read and write requests for pixel data are made through the memory crossbar 2216 rather than pixel fragment data transfer. In at least one embodiment, the processed graphic data can be displayed on a display device (such as Figure 21 one of the one or more display devices 2110), routed by the processor 2102 for further processing, or routed by Figure 22A one of the processing entities within the parallel processor 2200 for further processing.

[0361] Figure 22CIt is a block diagram of a processing cluster 2214 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of the processing clusters 2214A - 2214N of FIG. 22. In at least one embodiment, the processing cluster 2214 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0362] In at least one embodiment, the operation of the processing cluster 2214 can be controlled by assigning processing tasks to the pipeline manager 2232 of the SIMT parallel processor. In at least one embodiment, the pipeline manager 2232 receives instructions from the scheduler 2210 of FIG. 22 and manages the execution of these instructions through the graphics multiprocessor 2234 and / or the texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures can be included within the processing cluster 2214. In at least one embodiment, one or more instances of the graphics multiprocessor 2234 can be included within the processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 can process data, and the data crossbar 2240 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2232 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2240.

[0363] In at least one embodiment, each graphics multiprocessor 2234 within the processing cluster 2214 can include the same set of functional execution logic (e.g., arithmetic logic unit, load store unit, etc.). In at least one embodiment, the functional execution logic can be configured in a pipeline manner, where new instructions can be issued before the completion of previous instructions. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating - point arithmetic, comparison operations, boolean operations, shifts, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can exist.

[0364] In at least one embodiment, the instructions transmitted to processing cluster 2214 constitute a thread. In at least one embodiment, a set of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a program on different input data. In at least one embodiment, each thread within the thread group can be assigned to a different processing engine within graphics multiprocessor 2234. In at least one embodiment, the thread group can include fewer threads than the multiple processing engines within graphics multiprocessor 2234. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle of processing the thread group. In at least one embodiment, the thread group can also include more threads than the multiple processing engines within graphics multiprocessor 2234. In at least one embodiment, when the thread group includes more threads than the number of processing engines within graphics multiprocessor 2234, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 2234.

[0365] In at least one embodiment, graphics multiprocessor 2234 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 2234 can relinquish the internal cache and use the cache memory (e.g., L1 cache 2248) within processing cluster 2214. In at least one embodiment, each graphics multiprocessor 2234 can also access the L2 cache within the partition units (e.g., Figure 22A partition units 2220A - 2220N) of, which are shared among all processing clusters 2214 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2202 can be used as global memory. In at least one embodiment, processing cluster 2214 includes multiple instances of graphics multiprocessor 2234, which can share common instructions and data that can be stored in L1 cache 2248.

[0366] In at least one embodiment, each processing cluster 2214 may include a memory management unit (“MMU”) 2245 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2245 may reside within the memory interface 2218 of FIG. 22. In at least one embodiment, the MMU 2245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more discussion on tiling) and optionally to cache line indices. In at least one embodiment, the MMU 2245 may include a translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2234 or the L1 cache or the processing cluster 2214. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request to a cache line is a hit or a miss.

[0367] In at least one embodiment, the processing cluster 2214 may be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from the L1 cache within the graphics multiprocessor 2234 as needed and texture data is fetched from the L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2234 outputs the processed task to the data crossbar 2240 to provide the processed task to another processing cluster 2214 for further processing or store the processed task in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 2216. In at least one embodiment, the preROP 2242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2234 and direct the data to a ROP unit that may be located with the partition units described herein (e.g., partition units 2220A - 2220N of FIG. 22). In at least one embodiment, the PreROP 2242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0368] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 9A and / or Figure 9BProvide details regarding inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 can be used in the graphics processing cluster 2214 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0369] In at least one embodiment, the spatially adaptive separable convolutional layer 7 can be used in the graphics processing cluster 2214 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0370] Figure 22D A graphics multiprocessor 2234 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2234 is coupled to a pipeline manager 2232 of the processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 has an execution pipeline that includes, but is not limited to, an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more general-purpose graphics processing unit (GPGPU) cores 2262, and one or more load / store units 2266. The GPGPU cores 2262 and the load / store units 2266 are coupled to a cache memory 2272 and a shared memory 2270 via a memory and cache interconnect 2268.

[0371] In at least one embodiment, the instruction cache 2252 receives a stream of instructions to be executed from the pipeline manager 2232. In at least one embodiment, the instructions are cached in the instruction cache 2252 and dispatched for execution by the instruction unit 2254. In one embodiment, the instruction unit 2254 can dispatch instructions as a thread group (e.g., a warp), with each thread of the thread group assigned to a different execution unit within the GPGPU core 2262. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, the address mapping unit 2256 can be used to translate an address in the unified address space into a different memory address that can be accessed by the load / store unit 2266.

[0372] In at least one embodiment, the register file 2258 provides a set of registers for the functional units of the graphics multiprocessor 2234. In at least one embodiment, the register file 2258 provides temporary storage for the operands of the data paths of the functional units (e.g., GPGPU cores 2262, load / store units 2266) connected to the graphics multiprocessor 2234. In at least one embodiment, the register file 2258 is partitioned among each of the functional units such that a dedicated portion of the register file 2258 is allocated to each functional unit. In at least one embodiment, the register file 2258 is partitioned among different warps being executed by the graphics multiprocessor 2234.

[0373] In at least one embodiment, the GPGPU cores 2262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of the graphics multiprocessor 2234. The GPGPU cores 2262 may be architecturally similar or may have different architectures. In at least one embodiment, a first portion of the GPGPU core 2262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2234 may additionally include one or more fixed-function or special-function units to perform specific functions such as copy rectangle or pixel blend operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0374] In at least one embodiment, the GPGPU cores 2262 include SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU cores 2262 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU cores may be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel by a single SIMD8 logic unit.

[0375] In at least one embodiment, the memory and cache interconnect 2268 is an interconnect network that connects each functional unit of the graphics multiprocessor 2234 to the register file 2258 and the shared memory 2270. In at least one embodiment, the memory and cache interconnect 2268 is a crossbar interconnect that allows the load / store unit 2266 to perform load and store operations between the shared memory 2270 and the register file 2258. In at least one embodiment, the register file 2258 can operate at the same frequency as the GPGPU core 2262, resulting in very low latency for data transfer between the GPGPU core 2262 and the register file 2258. In at least one embodiment, the shared memory 2270 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2234. In at least one embodiment, the cache memory 2272 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 2236. In at least one embodiment, the shared memory 2270 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in the cache memory 2272, threads executing on the GPGPU core 2262 can also programmatically store data in the shared memory.

[0376] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0377] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are provided herein in connection with Figure 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 can be used in the graphics multiprocessor 2234 to infer or predict operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures or neural network usage described herein.

[0378] In at least one embodiment, the spatially adaptive separable convolutional layer 7 can be used in the graphics multiprocessor 2234 for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0379] Figure 23 A multi-GPU computing system 2300 is shown in accordance with at least one embodiment. In at least one embodiment, the multi-GPU computing system 2300 can include a processor 2302 coupled to a plurality of general purpose graphics processing units (GPGPUs) 2306A-D via a host interface switch 2304. In at least one embodiment, the host interface switch 2304 is a fast PCI switch device that couples the processor 2302 to a fast PCI bus through which the processor 2302 can communicate with the GPGPUs 2306A-D. The GPGPUs 2306A-D can be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2316. In at least one embodiment, the GPU-to-GPU links 2316 are connected to each of the GPGPUs 2306A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2316 enable direct communication between each of the GPGPUs 2306A-D without the need for communication on the host interface bus 2304 to which the processor 2302 is connected. In at least one embodiment, through the GPU-to-GPU traffic directed to the P2P GPU links 2316, the host interface bus 2304 remains available for system memory access or communication with other instances of the multi-GPU computing system 2300, e.g., via one or more network devices. Although in at least one embodiment the GPGPUs 2306A-D are connected to the processor 2302 via the host interface switch 2304, in at least one embodiment the processor 2302 includes direct support for the P2P GPU links 2316 and can be directly connected to the GPGPUs 2306A-D.

[0380] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are provided herein in conjunction with Figure 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 can be used in the multi-GPU computing system 2300 for inferencing or predicting operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0381] In at least one embodiment, a spatially adaptive separable convolutional layer 7 is available in a multi-GPU computing system 2300 for inferencing or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0382] Figure 24 is a block diagram of a graphics processing unit 2400 according to at least one embodiment. In at least one embodiment, the graphics processing unit 2400 includes a ring interconnect 2402, a pipeline front end 2404, a media engine 2437, and graphics cores 2480A - 2480N. In at least one embodiment, the ring interconnect 2402 couples the graphics processing unit 2400 to other processing units, including other graphics processing units or one or more general processor cores. In at least one embodiment, the graphics processing unit 2400 is one of many processors integrated within a multi-core processing system.

[0383] In at least one embodiment, the graphics processing unit 2400 receives multiple batches of commands via the ring interconnect 2402. In at least one embodiment, incoming commands are interpreted by a command stream converter 2403 in the pipeline front end 2404. In at least one embodiment, the graphics processing unit 2400 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 2480A - 2480N. In at least one embodiment, for 3D geometry processing commands, the command stream converter 2403 provides commands to a geometry pipeline 2436. In at least one embodiment, for at least some media processing commands, the command stream converter 2403 provides commands to a video front end 2434 coupled to the media engine 2437. In at least one embodiment, the media engine 2437 includes a video quality engine (VQE) 2430 for video and image post-processing and a multi-format encode / decode (MFX) 2433 engine for providing hardware-accelerated encoding and decoding of media data. In at least one embodiment, both the geometry pipeline 2436 and the media engine 2437 generate execution threads for thread execution resources provided by at least one graphics core 2480A.

[0384] In at least one embodiment, the graphics processor 2400 includes scalable thread execution resources characterized by modular cores 2480A - 2480N (sometimes referred to as core slices), with each graphics core having multiple sub - cores 2450A - 2450N, 2460A - 2460N (sometimes referred to as core sub - slices). In at least one embodiment, the graphics processor 2400 can have any number of graphics cores 2480A through 2480N. In at least one embodiment, the graphics processor 2400 includes a graphics core 2480A having at least a first sub - core 2450A and a second sub - core 2460A. In at least one embodiment, the graphics processor 2400 is a low - power processor having a single sub - core (e.g., 2450A). In at least one embodiment, the graphics processor 2400 includes multiple graphics cores 2480A - 2480N, each graphics core including a set of first sub - cores 2450A - 2450N and a set of second sub - cores 2460A - 2460N. In at least one embodiment, each of the first sub - cores 2450A - 2450N includes at least a first set of execution units 2452A - 2452N and media / texture samplers 2454A - 2454N. In at least one embodiment, each of the second sub - cores 2460A - 2460N includes at least a second set of execution units 2462A - 2462N and samplers 2464A - 2464N. In at least one embodiment, each sub - core 2450A - 2450N, 2460A - 2460N shares a set of shared resources 2470A - 2470N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0385] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, the inference and / or training logic 915 can be in the graphics processor 2400 for inferring or predicting operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network usage described herein.

[0386] In at least one embodiment, the spatially adaptive separable convolution layer 7 can be used in the graphics processor 2400 for inferring or predicting operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0387] Figure 25FIG. is a block diagram showing a microarchitecture of a processor 2500 that may include logic circuitry for executing instructions. In at least one embodiment, the processor 2500 may execute instructions, including x86 instructions, ARM instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2510 may include registers for storing packed data, such as the 64-bit wide MMX TM registers in a microprocessor enabled with MMX technology by Intel Corporation in Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating-point forms may operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or later versions (generally referred to as “SSEx” technology) may hold such packed data operands. In at least one embodiment, the processor 2510 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0388] In at least one embodiment, the processor 2500 includes an in-order front end (“front end”) 2501 to fetch instructions to be executed and prepare the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2501 may include several units. In at least one embodiment, the instruction prefetcher 2526 fetches instructions from memory and provides the instructions to the instruction decoder 2528, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2528 decodes the received instructions into one or more operations of so-called “microinstructions” or “micro-operations” (also referred to as “micro-ops” or “microinstructions”) that are machine-executable. In at least one embodiment, the instruction decoder 2528 parses the instructions into an opcode and corresponding data and control fields, which may be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 2530 may assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2534 for execution. In at least one embodiment, when the trace cache 2530 encounters a complex instruction, the microcode ROM 2532 provides the microinstructions required to complete the operation.

[0389] In at least one embodiment, some instructions can be converted into a single micro-operation, while other instructions require several micro-operations to complete the entire operation. In at least one embodiment, if more than four microinstructions are required to complete an instruction, the instruction decoder 2528 can access the microcode ROM 2532 to execute the instruction. In at least one embodiment, an instruction can be decoded into a small number of microinstructions for processing at the instruction decoder 2528. In at least one embodiment, if multiple microinstructions are required to complete an operation, the instruction can be stored in the microcode ROM 2532. In at least one embodiment, the trace cache 2530 refers to an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer for reading a microcode sequence from the microcode ROM 2532 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2532 finishes sorting the micro-operations of an instruction, the front end 2501 of the machine can resume fetching micro-operations from the trace cache 2530.

[0390] In at least one embodiment, an out-of-order execution engine (“out-of-order engine”) 2503 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance as the instructions descend along the pipeline and are scheduled for execution. The out-of-order execution engine 2503 includes, but is not limited to, an allocator / register renamer 2540, a memory micro-instruction queue 2542, an integer / floating-point micro-instruction queue 2544, a memory scheduler 2546, a fast scheduler 2502, a slow / general floating-point scheduler (“slow / general FP scheduler”) 2504, and a simple floating-point scheduler (“simple FP scheduler”) 2506. In at least one embodiment, the fast scheduler 2502, the slow / general floating-point scheduler 2504, and the simple floating-point scheduler 2506 are also collectively referred to as “micro-instruction schedulers 2502, 2504, 2506”. The allocator / register renamer 2540 allocates the machine buffers and resources required for each micro-instruction to be executed in sequence. In at least one embodiment, the allocator / register renamer 2540 renames logical registers to entries in the register file. In at least one embodiment, the allocator / register renamer 2540 also allocates entries for each micro-instruction in one of the two micro-instruction queues, the memory micro-instruction queue 2542 for memory operations and the integer / floating-point micro-instruction queue 2544 for non-memory operations, in front of the memory scheduler 2546 and the micro-instruction schedulers 2502, 2504, 2506. In at least one embodiment, the micro-instruction schedulers 2502, 2504, 2506 determine when a micro-instruction is ready for execution based on the readiness of their dependent input register operand sources and the availability of the execution resources micro-instructions that need to be completed. In at least one embodiment, the fast scheduler 2502 of at least one embodiment may be scheduled every half main clock cycle, while the slow / general floating-point scheduler 2504 and the simple floating-point scheduler 2506 may be scheduled once per main processor clock cycle. In at least one embodiment, the micro-instruction schedulers 2502, 2504, 2506 arbitrate the scheduling ports to schedule micro-instructions for execution.

[0391] In at least one embodiment, execution block 2511 includes, but is not limited to, integer register file / branch network 2508, floating-point register file / branch network (“FP register file / branch network”) 2510, address generation units (“AGUs”) 2512 and 2514, fast arithmetic logic units (“fast ALUs”) 2516 and 2518, slow arithmetic logic unit (“slow ALU”) 2520, floating-point ALU (“FP”) 2522, and floating-point move unit (“FP move”) 2524. In at least one embodiment, integer register file / branch network 2508 and floating-point register file / bypass network 2510 are also referred to herein as “register files 2508, 2510”. In at least one embodiment, AGUs 2512 and 2514, fast ALUs 2516 and 2518, slow ALU 2520, floating-point ALU 2522, and floating-point move unit 2524 are also referred to herein as “execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524”. In at least one embodiment, execution block 2511 can include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0392] In at least one embodiment, register files 2508, 2510 can be arranged between microinstruction schedulers 2502, 2504, 2506 and execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, integer register file / branch network 2508 performs integer operations. In at least one embodiment, floating-point register file / branch network 2510 performs floating-point operations. In at least one embodiment, each of register files 2508, 2510 can include, but is not limited to, a branch network that can bypass or forward a just-completed result that has not yet been written to the register file to a new dependent. In at least one embodiment, register files 2508, 2510 can communicate data with each other. In at least one embodiment, integer register file / branch network 2508 can include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating-point register file / branch network 2510 can include, but is not limited to, 128-bit wide entries, since floating-point instructions typically have operands with widths of 64 to 128 bits.

[0393] In at least one embodiment, execution units 2512, 2514, 2516, 2518, 2520, 2522, 2524 may execute instructions. In at least one embodiment, register files 2508, 2510 store integer and floating-point data operand values that the microinstructions need to execute. In at least one embodiment, the processor 2500 may include, but is not limited to, any number of execution units 2512, 2514, 2516, 2518, 2520, 2522, 2524 and their combinations. In at least one embodiment, the floating-point ALU 2522 and the floating-point move unit 2524 may execute floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating-point ALU 2522 may include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, instructions involving floating-point values may be processed with floating-point hardware. In at least one embodiment, ALU operations may be passed to the fast ALUs 2516, 2518. In at least one embodiment, the fast ALUs 2516, 2518 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations enter the slow ALU 2520 because the slow ALU 2520 may include, but is not limited to, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by the AGUs 2512, 2514. In at least one embodiment, the fast ALU 2516, the fast ALU 2518, and the slow ALU 2520 may perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2516, the fast ALU 2518, and the slow ALU 2520 may be implemented to support various data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2522 and the floating-point move unit 2524 may be implemented to support a certain range of operands with bits of various widths. In at least one embodiment, the floating-point ALU 2522 and the floating-point move unit 2524 may operate on 128-bit wide packed data operands that may combine SIMD and multimedia instructions.

[0394] In at least one embodiment, the microinstruction schedulers 2502, 2504, 2506 schedule dependent operations before the completion of the execution of the parent load. In at least one embodiment, since microinstructions can be speculatively scheduled and executed in the processor 2500, the processor 2500 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be dependent operations running in the pipeline that leave the scheduler temporarily without the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that used incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and independent operations may be allowed to complete. In at least one embodiment, the scheduler and the replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0395] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be part of an instruction that identifies an operand. In at least one embodiment, the registers can be those that can be used from outside the processor (from the programmer's perspective). In at least one embodiment, the registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, the registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques by circuits within the processor, such as dedicated physical registers, physical registers dynamically allocated using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also contains eight multimedia SIMD registers for packing data.

[0396] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 915 are provided in conjunction with Figure 9A and / or Figure 9B In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into execution block 2511 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2511. Additionally, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2511 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0397] Figure 26The deep learning application processor 2600 according to at least one embodiment is shown. In at least one embodiment, the deep learning application processor 2600 uses instructions which, if executed by the deep learning application processor 2600, cause the deep learning application processor 2600 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2600 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2600 performs matrix multiplication operations or is “hardwired” into the hardware as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2600 includes, but is not limited to, processing clusters 2610(1)-2610(12), inter-chip links (“ICL”) 2620(1)-2620(12), inter-chip controllers (“ICC”) 2630(1)-2630(2), second generation high bandwidth memories (“HBM2”) 2640(1)-2640(4), memory controllers (“Mem Ctrlr”) 2642(1)-2642(4), high bandwidth memory physical layers (“HBM PHY”) 2644(1)-2644(4), management controller central processing units (“management controller CPU”) 2650, serial peripheral interface, internal integrated circuit and general purpose input / output blocks (“SPI, I2C, GPIO”) 2660, peripheral component interconnect express controllers and direct memory access blocks (“PCIe controllers and DMA”) 2670, and sixteen-channel peripheral component interconnect express ports (“PCI Express x16”) 2680.

[0398] In at least one embodiment, the processing clusters 2610 may perform deep learning operations, including inference or prediction operations based on weight parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2610 may include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2600 may include any number and type of processing clusters 2600. In at least one embodiment, the inter-chip link 2620 is bidirectional. In at least one embodiment, the inter-chip link 2620 and the inter-chip controller 2630 enable multiple deep learning application processors 2600 to exchange information, including activation information resulting from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2600 may include any number (including zero) and type of ICL 2620 and ICC 2630.

[0399] In at least one embodiment, the HBM2 2640 provides a total of 32 GB of memory. The HBM2 2640(i) is associated with both a memory controller 2642(i) and an HBM PHY 2644(i). In at least one embodiment, any number of HBM2 2640s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2642 and HBM PHYs 2644. In at least one embodiment, any number and type of blocks can replace the SPI, I2C, GPIO 3360, PCIe controller 2660, and DMA 2670 and / or PCIe 2680 to implement any number and type of communication standards in any technically feasible manner.

[0400] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 9A and / or Figure 9B provide details regarding the inference and / or training logic 915. In at least one embodiment, a deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2600. In at least one embodiment, the deep learning application processor 2600 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2600. In at least one embodiment, the processor 2600 can be used to perform one or more of the neural network use cases described herein.

[0401] In at least one embodiment, the spatially adaptive separable convolutional layer 7 can be used in a deep learning application processor 2600 for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0402] Figure 27is a block diagram of a neuromorphic processor 2700 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2700 may receive one or more inputs from a source external to the neuromorphic processor 2700. In at least one embodiment, these inputs may be transmitted to one or more neurons 2702 within the neuromorphic processor 2700. In at least one embodiment, the neurons 2702 and their components may be implemented using circuitry or logic that includes one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2700 may include, but is not limited to, thousands of instances of neurons 2702, but any suitable number of neurons 2702 may be used. In at least one embodiment, each instance of a neuron 2702 may include a neuron input 2704 and a neuron output 2706. In at least one embodiment, the neurons 2702 may generate outputs that may be transmitted as inputs to other instances of neurons 2702. In at least one embodiment, the neuron inputs 2704 and the neuron outputs 2706 may be interconnected via synapses 2708.

[0403] In at least one embodiment, neurons 2702 and synapses 2708 may be interconnected such that the neuromorphic processor 2700 operates to process or analyze information received by the neuromorphic processor 2700. In at least one embodiment, when the input received through neuron input 2704 exceeds a threshold, neuron 2702 may send an output pulse (or "fire" or "spike"). In at least one embodiment, neuron 2702 may sum or integrate the signals received at neuron input 2704. For example, in at least one embodiment, neuron 2702 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, neuron 2702 may use a transfer function such as a sigmoid or threshold function to produce an output (or "fire"). In at least one embodiment, the leaky integrate-and-fire neuron may sum the signals received at neuron input 2704 into a membrane potential and may apply an exponential decay factor (or leak) to reduce the membrane potential. In at least one embodiment, if multiple input signals are received at neuron input 2704 fast enough to exceed the threshold (i.e., before the membrane potential decays too low to fire), the leaky integrate-and-fire neuron may fire. In at least one embodiment, neuron 2702 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Additionally, in at least one embodiment, neuron 2702 may include, but is not limited to, comparator circuitry or logic that produces an output spike at neuron output 2706 when the result of applying a transfer function to neuron input 2704 exceeds a threshold. In at least one embodiment, once neuron 2702 fires, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2702 may resume normal operation after a suitable period of time (or refractory period).

[0404] In at least one embodiment, neurons 2702 may be interconnected by synapses 2708. In at least one embodiment, synapses 2708 may operate to transmit a signal from the output of a first neuron 2702 to the input of a second neuron 2702. In at least one embodiment, a neuron 2702 may transmit information over more than one instance of a synapse 2708. In at least one embodiment, one or more instances of a neuron output 2706 may be connected, via an instance of a synapse 2708, to an instance of a neuron input 2704 within the same neuron 2702. In at least one embodiment, an instance of a neuron 2702 that produces an output to be transmitted over an instance of a synapse 2708 may be referred to as a "presynaptic neuron" relative to that instance of the synapse 2708. In at least one embodiment, an instance of a neuron 2702 that receives an input transmitted over an instance of a synapse 2708 may be referred to as a "postsynaptic neuron" relative to that instance of the synapse 2708. In at least one embodiment, with respect to the various instances of synapses 2708, since an instance of a neuron 2702 may receive inputs from one or more instances of synapses 2708 and may also transmit outputs over one or more instances of synapses 2708, a single instance of a neuron 2702 may be both a "presynaptic neuron" and a "postsynaptic neuron".

[0405] In at least one embodiment, the neurons 2702 may be organized into one or more layers. Each instance of the neurons 2702 may have a neuron output 2706 that may fan out to one or more neuron inputs 2704 through one or more synapses 2708. In at least one embodiment, the neuron outputs 2706 of the neurons 2702 in the first layer 2710 may be connected to the neuron inputs 2704 of the neurons 2702 in the second layer 2712. In at least one embodiment, the layer 2710 may be referred to as a "feedforward layer". In at least one embodiment, each instance of the neurons 2702 in an instance of the first layer 2710 may fan out to each instance of the neurons 2702 in the second layer 2712. In at least one embodiment, the first layer 2710 may be referred to as a "fully connected feedforward layer". In at least one embodiment, each instance of the neurons 2702 in each instance of the second layer 2712 fans out to fewer than all instances of the neurons 2702 in the third layer 2714. In at least one embodiment, the second layer 2712 may be referred to as a "sparsely connected feedforward layer". In at least one embodiment, the neurons 2702 in the second layer 2712 may fan out to the neurons 2702 in multiple other layers, including fanning out to the neurons 2702 in the (same) second layer 2712. In at least one embodiment, the second layer 2712 may be referred to as a "recurrent layer". The neuromorphic processor 2700 may include any suitable combination of, but is not limited to, recurrent layers and feedforward layers, including but not limited to sparsely connected feedforward layers and fully connected feedforward layers.

[0406] In at least one embodiment, the neuromorphic processor 2700 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnections to connect the synapses 2708 to the neurons 2702. In at least one embodiment, the neuromorphic processor 2700 may include, but is not limited to, circuitry or logic that allows the assignment of synapses to different neurons 2702 as needed, based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, the synapses 2708 may be connected to the neurons 2702 using an interconnect structure (such as a network-on-chip) or through dedicated connections. In at least one embodiment, circuitry or logic may be used to implement the synapse interconnections and their components.

[0407] Figure 28A processing system according to at least one embodiment is shown. In at least one embodiment, system 2800 includes one or more processors 2802 and one or more graphics processors 2808, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2802 or processor cores 2807. In at least one embodiment, system 2800 is a processing platform integrated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0408] In at least one embodiment, system 2800 can be included in or incorporated into a server-based gaming platform, a gaming console including a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, system 2800 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 2800 can also be coupled to or integrated within a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2800 is a television or a set-top box device having one or more processors 2802 and a graphical interface generated by one or more graphics processors 2808.

[0409] In at least one embodiment, each of the one or more processors 2802 includes one or more processor cores 2807 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2807 is configured to process a particular instruction set 2809. In at least one embodiment, the instruction set 2809 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, the processor cores 2807 can each process a different instruction set 2809, which can include instructions that help to emulate other instruction sets. In at least one embodiment, the processor cores 2807 can also include other processing devices, such as a digital signal processor (DSP).

[0410] In at least one embodiment, the processor 2802 includes a cache memory 2804. In at least one embodiment, the processor 2802 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among the various components of the processor 2802. In at least one embodiment, the processor 2802 also uses an external cache (e.g., a level three (L3) cache or a last level cache (LLC)) (not shown), and the external cache can be shared among the processor cores 2807 using known cache coherence techniques. In at least one embodiment, the processor 2802 further includes a register file 2806, and the processor may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). In at least one embodiment, the register file 2806 may include general-purpose registers or other registers.

[0411] In at least one embodiment, one or more processors 2802 are coupled to one or more interface buses 2810 to transfer communication signals, such as address, data, or control signals, between the processor 2802 and other components in the system 2800. In at least one embodiment, the interface bus 2810 may be a processor bus, such as a version of the direct media interface (DMI) bus, in one embodiment. In at least one embodiment, the interface 2810 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2802 includes an integrated memory controller 2816 and a platform controller hub 2830. In at least one embodiment, the memory controller 2816 facilitates communication between the memory device and other components of the processing system 2800, while the platform controller hub (PCH) 2830 provides a connection to input / output (I / O) devices via a local I / O bus.

[0412] In at least one embodiment, the memory device 2820 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or have suitable performance to be used as a processor memory. In at least one embodiment, the storage device 2820 can be used as the system memory of the processing system 2800 to store data 2822 and instructions 2821 for use when one or more processors 2802 execute an application or process. In at least one embodiment, the memory controller 2816 is also coupled to an optional external graphics processor 2812, which can communicate with one or more graphics processors 2808 in the processor 2802 to perform graphics and media operations. In at least one embodiment, the display device 2811 can be connected to the processor 2802. In at least one embodiment, the display device 2811 can include one or more of internal display devices, such as in a mobile electronic device or a laptop device or an external display device connected through a display interface (such as DisplayPort, etc.). In at least one embodiment, the display device 2811 can include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) applications or augmented reality (AR) applications.

[0413] In at least one embodiment, the platform controller hub 2830 enables peripheral devices to be connected to the storage device 2820 and the processor 2802 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2846, a network controller 2834, a firmware interface 2828, a wireless transceiver 2826, a touch sensor 2825, and a data storage device 2824 (e.g., a hard disk drive, a flash memory, etc.). In at least one embodiment, the data storage device 2824 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2825 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2826 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2828 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 2834 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2810. In at least one embodiment, the audio controller 2846 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2800 includes an optional legacy I / O controller 2840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, the platform controller hub 2830 can also be connected to one or more Universal Serial Bus (USB) controllers 2842, which connect input devices, such as a keyboard and mouse 2843 combination, a camera 2844, or other USB input devices.

[0414] In at least one embodiment, instances of the memory controller 2816 and the platform controller hub 2830 can be integrated into a discrete external graphics processor, such as the external graphics processor 2812. In at least one embodiment, the platform controller hub 2830 and / or the memory controller 2816 can be external to one or more processors 2802. For example, in at least one embodiment, the system 2800 can include an external memory controller 2816 and a platform controller hub 2830, which can be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2802.

[0415] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 9A and / or Figure 9BProvide details regarding inference and / or training logic 915. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into a graphics processor 2800. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in a 3D pipeline 2812. Additionally, in at least one embodiment, the inference and / or training operations described herein may be completed using logic other than Figure 9A or Figure 9B the logic shown. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the graphics processor 2800 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0416] Figure 29 is a block diagram of a processor 2900 having one or more processor cores 2902A - 2902N, an integrated memory controller 2914, and an integrated graphics processor 2908, according to at least one embodiment. In at least one embodiment, the processor 2900 may include additional cores, up to and including the additional core 2902N shown in dashed boxes. In at least one embodiment, each processor core 2902A - 2902N includes one or more internal cache units 2904A - 2904N. In at least one embodiment, each processor core may also access one or more shared cache units 2906.

[0417] In at least one embodiment, the internal cache units 2904A - 2904N and the shared cache units 2906 represent a cache memory hierarchy within the processor 2900. In at least one embodiment, the cache memory units 2904A - 2904N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared mid - level cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level of cache, where the highest level of cache before external memory is classified as the LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2906 and 2904A - 2904N.

[0418] In at least one embodiment, the processor 2900 may further include a set of one or more bus controller units 2916 and a system agent core 2910. In at least one embodiment, one or more bus controller units 2916 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2910 provides management functions for various processor components. In at least one embodiment, the system agent core 2910 includes one or more integrated memory controllers 2914 to manage access to various external memory devices (not shown).

[0419] In at least one embodiment, one or more processor cores 2902A-2902N include support for simultaneous multi-threading. In at least one embodiment, the system agent core 2910 includes components for coordinating and operating cores 2902A-2902N during multi-threaded processing. In at least one embodiment, the system agent core 2910 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of the processor cores 2902A-2902N and the graphics processor 2908.

[0420] In at least one embodiment, the processor 2900 further includes a graphics processor 2908 for performing graphics processing operations. In at least one embodiment, the graphics processor 2908 is coupled to a shared cache unit 2906 and a system agent core 2910 that includes one or more integrated memory controllers 2914. In at least one embodiment, the system agent core 2910 further includes a display controller 2911 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2911 may also be a separate module coupled to the graphics processor 2908 via at least one interconnect, or may be integrated within the graphics processor 2908.

[0421] In at least one embodiment, a ring-based interconnect unit 2912 is used to couple the internal components of the processor 2900. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2908 is coupled to the ring interconnect 2912 via an I / O link 2913.

[0422] In at least one embodiment, the I / O link 2913 represents at least one of a variety of I / O interconnects, including a package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2918 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 2902A - 2902N and the graphics processor 2908 uses the embedded memory module 2918 as a shared last-level cache.

[0423] In at least one embodiment, the processor cores 2902A - 2902N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2902A - 2902N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 2902A - 2902N execute a common instruction set, while one or more other processor cores 2902A - 2902N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, in terms of microarchitecture, the processor cores 2902A - 2902N are heterogeneous, where one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2900 can be implemented on one or more chips or as a SoC integrated circuit.

[0424] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, part or all of the inference and / or training logic 915 can be incorporated into the graphics processor 2908. For example, in at least one embodiment, the training and / or inference techniques described herein can use one or more ALUs embodied in Figure 29 the 3D pipeline 2812, the graphics core 2915A, the shared functional logic 2916, the graphics core 2915B, the shared functional logic 2920, or other logic in. Additionally, in at least one embodiment, the inference and / or training operations described herein can be accomplished using logic other than Figure 9A or Figure 9B the logic shown. In at least one embodiment, the weight parameters can be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the graphics processor 2910 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0425] Figure 30is a block diagram of a graphics processor 3000, which can be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 3000 communicates with registers on the graphics processor 3000 and co...

Claims

1. A processor, comprising: one or more circuits for using one or more neural networks to identify one or more features in the image based at least in part on the positions of the one or more features within the image, wherein the one or more circuits are for calculating a feature map based at least in part on combining values of two or more filters applied to the image from different positions.

2. The processor according to claim 1, wherein the one or more circuits are for identifying the one or more features in the image at least by: calculating a first value of a first filter for the position; calculating a second value of a second filter for the position; and calculating a third value of the feature map based at least in part on the first value and the second value.

3. The processor according to claim 2, wherein the third value is calculated at least in part by aggregating the first value and the second value.

4. The processor according to claim 2, wherein the first value and the second value indicate the probabilities that the first filter and the second filter detect the one or more features at the position.

5. The processor according to claim 1, wherein the one or more neural networks are convolutional neural networks.

6. The processor according to claim 1, wherein the one or more neural networks identify one or more features in a convolutional layer of the convolutional neural network among the one or more neural networks.

7. The processor according to claim 6, wherein the convolutional layer includes depthwise convolution and pointwise convolution.

8. A machine-readable medium having a set of instructions stored thereon, which if executed by one or more processors, cause the one or more processors to at least: use one or more neural networks to identify one or more features in the image based at least in part on the positions of the one or more features within the image, the instructions, when executed, cause the one or more processors to calculate a feature map based at least in part on combining values of two or more filters applied to the image from different positions.

9. The machine-readable medium according to claim 8, wherein the instructions, when executed, cause the one or more processors to identify the one or more features within the image at least by: calculating a first value of a first filter for the position; calculating a second value of a second filter for the position; and calculating a third value of the feature map based at least in part on the first value and the second value.

10. The machine-readable medium according to claim 9, wherein the instructions, when executed, further cause the one or more processors to calculate the third value at least in part by aggregating the first value and the second value.

11. The machine-readable medium according to claim 9, wherein the first value and the second value indicate the weights of the first filter or the second filter detecting the one or more features at the position.

12. The machine-readable medium according to claim 11, wherein when the instructions are executed, the one or more processors calculate the weights using a softmax function.

13. The machine-readable medium according to claim 8, wherein the one or more neural networks are convolutional neural networks.

14. The machine-readable medium according to claim 8, wherein when the instructions are executed, the one or more processors identify one or more features in a convolutional layer of a convolutional neural network among the one or more neural networks, the convolutional layer including depthwise convolution and pointwise convolution.

15. A processor, comprising: one or more circuits for assisting in training one or more neural networks to identify the one or more features in the image based at least in part on the positions of the one or more features within the image, wherein the one or more circuits are for calculating a feature map based at least in part on combining values of two or more filters applied to the image from different positions.

16. The processor according to claim 15, wherein the one or more circuits identify the one or more features at least by: calculating a first value of a first filter for the position; calculating a second value of a second filter for the position; and calculating a third value of the feature map based at least in part on the first value and the second value.

17. The processor according to claim 16, wherein the third value is calculated at least by applying a softmax function to the first value and the second value and aggregating the results of applying the softmax function to the first value and the second value.

18. The processor according to claim 16, wherein the first value and the second value indicate the probabilities that the first filter or the second filter detect the one or more features at the position.

19. The processor according to claim 15, wherein the one or more neural networks to be trained are convolutional neural networks.

20. The processor according to claim 15, wherein the one or more neural networks identify one or more features in a convolutional layer of a convolutional neural network among the one or more neural networks.

21. The processor according to claim 20, wherein the convolutional layer includes depthwise convolution and pointwise convolution.

22. A method of identifying multi-scale features using a neural network, comprising: training one or more neural networks to identify the one or more features in the image based at least in part on the positions of the one or more features within the image, wherein the one or more circuits are for calculating a feature map based at least in part on combining values of two or more filters applied to the image from different positions.

23. The method according to claim 22, wherein the one or more neural networks include at least one convolutional layer that: applies one or more filters to the image; calculates weights associated with the outputs of the one or more filters; and Aggregate the weights into one or more feature maps of the image.

24. The method according to claim 23, wherein weights at different positions in the image are calculated.

25. The method according to claim 23, wherein each of the one or more filters identifies each of the one or more features in the image.

26. The method according to claim 22, wherein the one or more neural networks to be trained are convolutional neural networks.

27. The method according to claim 22, wherein the one or more feature maps include values corresponding to the one or more features, wherein each of the one or more features is at a different position in the image.

28. The method according to claim 23, wherein the convolutional layer includes depthwise convolution and pointwise convolution.

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