Display module and its driving method

Abstract

A display module includes a display panel and a driver. Among them, the display panel includes a plurality of pixels, each pixel includes a plurality of sub-pixels, and the pixels are disposed on a plurality of row lines of the display panel. The driver is configured to: apply a pulse width modulation (PWM) data voltage to the sub-pixels in the order of the row lines; and drive the display panel such that the sub-pixels included in a plurality of consecutive row lines among the plurality of row lines emit light for a time corresponding to the applied PWM data voltage in the order of the row lines.

Description

Technical Field

[0001] The present disclosure relates to a display module and a driving method thereof, and more particularly, to a display module including self-luminous elements as sub-pixels and a driving method thereof. Background Art

[0002] In a display panel driving inorganic light-emitting elements (such as red light-emitting diodes (LEDs), green LEDs, and blue LEDs (hereinafter, LED refers to an inorganic light-emitting element)) as sub-pixels according to related art, the gray scale of the sub-pixels can be expressed by a pulse amplitude modulation (PAM) driving method.

[0003] In this case, according to the amplitude of the driving current, the gray scale of the emitted light and the wavelength of the emitted light change together, so the color reproducibility of the image is reduced. Figure 1 Shows the wavelength change according to the amplitude of the driving current flowing through the blue LED, green LED, and red LED. Summary of the Invention

[0004] Technical Problem

[0005] Provided are a display module and a driving method thereof that provide improved color reproducibility for an input image signal.

[0006] Provided are a display module and a driving method thereof including a sub-pixel circuit capable of driving inorganic light-emitting elements constituting sub-pixels more effectively and stably.

[0007] Provided are a display module and a driving method thereof including a driving circuit suitable for high-density integration by optimizing the design of various driving circuits for driving inorganic light-emitting elements.

[0008] Problem Solution

[0009] According to an aspect of the present disclosure, a display module may include: a display panel including a plurality of pixels, wherein each pixel includes a plurality of sub-pixels, and the pixels are disposed on a plurality of row lines of the display panel. The display panel may further include: a driver configured to apply a pulse width modulation (PWM) data voltage to the sub-pixels in the order of the row lines; and drive the display panel such that the sub-pixels included in a plurality of consecutive row lines among the plurality of row lines emit light for a time corresponding to the applied PWM data voltage in the order of the row lines.

[0010] The driver may also be configured to: during a data setting period for each of the row lines, apply a PWM data voltage to the sub-pixels included in each of the row lines included in the row lines; and drive the display panel such that the sub-pixels included in each of the row lines included in the plurality of consecutive row lines emit light for a time corresponding to the applied PWM data voltage during a plurality of light emission periods for each of the row lines.

[0011] A first light emission period among the plurality of light emission periods may be temporally consecutive with the data setting period, and each of the plurality of light emission periods may have a predetermined time interval.

[0012] The plurality of row lines may be divided into a plurality of groups, each group including consecutive row lines. The driver may also be configured to: during a second image frame period, apply a second PWM data voltage to the sub-pixels included in each of the row lines included in the row lines in the order of the row lines from the first row line to the last row line among the plurality of row lines; and drive the display panel such that during the second image frame period, the sub-pixels included in the first group among the plurality of groups emit light in the order of the row lines, and then the sub-pixels included in each of the plurality of consecutive groups emit light based on the applied second PWM data voltage in the order of the row lines. The plurality of consecutive groups may include the first group.

[0013] The driver may also be configured to: during a first image frame period before the second image frame period, apply a first PWM data voltage to the sub-pixels included in each of the row lines included in the row lines in the order of the row lines from the first row line to the last row line among the plurality of row lines; and drive the display panel such that during the second image frame period, the sub-pixels included in each of the groups other than at least one group driven based on the second PWM data voltage among the plurality of groups emit light based on the first PWM data voltage in the order of the row lines.

[0014] The driver may also be configured to: drive the display panel such that during the second image frame period, the sub-pixels included in each of the row lines included in each of the groups among the plurality of groups emit light multiple times during the plurality of light emission periods for each of the row lines based on one or more of the first PWM data voltage and the second PWM data voltage.

[0015] Each of the plurality of sub-pixels may include: an inorganic light-emitting element; and a sub-pixel circuit configured to control a light-emitting time of the inorganic light-emitting element during each of the plurality of light-emitting periods according to a drive of the driver. The sub-pixel circuit may include: a constant current generator circuit configured to provide a constant current to the inorganic light-emitting element based on an applied constant current generator voltage; and a PWM circuit configured to provide the constant current to the inorganic light-emitting element for a time corresponding to an applied PWM data voltage.

[0016] The constant current generator circuit may include a first driving transistor, and based on the constant current generator voltage being applied, the constant current generator circuit is configured to: apply a first voltage based on the applied constant current generator voltage and a threshold voltage of the first driving transistor to a gate terminal of the first driving transistor. The PWM circuit may include a second driving transistor, and based on the PWM data voltage being applied, the PWM circuit is configured to: apply a second voltage based on the applied PWM data voltage and a threshold voltage of the second driving transistor to a gate terminal of the second driving transistor.

[0017] The constant current generator circuit may further include: a first transistor connected between a drain terminal and a gate terminal of the first driving transistor; and a second transistor having a drain terminal connected to a source terminal of the first driving transistor and a gate terminal connected to a gate terminal of the first transistor. In a state where the constant current generator voltage is applied through a source terminal of the second transistor when the first transistor and the second transistor are turned on, the first voltage may be applied to the gate terminal of the first driving transistor through the turned-on first driving transistor.

[0018] The PWM circuit may further include: a third transistor connected between a drain terminal and a gate terminal of the second driving transistor; and a fourth transistor having a drain terminal connected to a source terminal of the second driving transistor and a gate terminal connected to a gate terminal of the third transistor. In a state where the PWM data voltage is applied through a source terminal of the fourth transistor when the third transistor and the fourth transistor are turned on, the second voltage may be applied to the gate terminal of the second driving transistor through the turned-on second driving transistor.

[0019] The constant current generator circuit may further be configured to: provide a constant current to the inorganic light-emitting element, the constant current having an amplitude based on a first driving voltage applied to a source terminal of the first driving transistor and the first voltage applied to the gate terminal of the first driving transistor.

[0020] The sub-pixel circuit may include: a first switching transistor having a gate terminal connected to the drain terminal of a second driving transistor and a source terminal connected to the drain terminal of a first driving transistor. The constant current generator circuit may also be configured to: in a state where a first driving voltage is applied to the source terminal of the first switching transistor through the first driving transistor, supply a constant current to the inorganic light-emitting element through the turned-on first switching transistor. The PWM circuit may also be configured to: in a state where the second driving transistor is turned on based on a second voltage applied to the gate terminal of the second driving transistor and a second driving voltage applied to the source terminal of the second driving transistor, apply the second driving voltage to the gate terminal of the first switching transistor to turn off the first switching transistor.

[0021] Based on that the second voltage applied to the gate terminal of the second driving transistor changes according to the sweep voltage applied to the PWM circuit, and the voltage between the gate terminal and the source terminal of the second driving transistor becomes the threshold voltage of the second driving transistor, the second driving transistor may be turned on.

[0022] The sub-pixel circuit may further include: a second switching transistor having a source terminal connected to the drain terminal of the first switching transistor and a drain terminal connected to the anode terminal of the inorganic light-emitting element. The second switching transistor may be turned on after a predetermined time has elapsed since the time when the second driving voltage is applied to the source terminal of the second driving transistor.

[0023] The PWM circuit may further include: a resetter configured to turn on the first switching transistor before the first driving voltage is applied to the source terminal of the first switching transistor through the first driving transistor.

[0024] The voltage of the gate terminal of the second driving transistor that linearly changes according to the sweep voltage in the first light-emitting period among the plurality of light-emitting periods may be restored to the second voltage through the sweep voltage before the second light-emitting period after the first light-emitting period among the plurality of light-emitting periods. The resetter may also be configured to: based on the start of the second light-emitting period, turn on the first switching transistor that is turned off in the first light-emitting period.

[0025] The constant current generator circuit may be driven based on the second driving voltage during the data setting period and driven based on the first driving voltage during the plurality of light-emitting periods.

[0026] According to another aspect of the present disclosure, a driving method of a display module, wherein the display module includes a display panel having a plurality of pixels, each pixel including a plurality of sub-pixels, the pixels being disposed on a plurality of row lines of the display panel, the driving method may include: applying a pulse-width modulation (PWM) data voltage to the sub-pixels in the order of the row lines; and driving the display panel such that the sub-pixels included in a plurality of consecutive row lines among the plurality of row lines emit light for a time corresponding to the applied PWM data voltage in the order of the row lines.

[0027] Advantages of the present invention

[0028] According to various embodiments, it is possible to prevent the wavelength of light emitted by the inorganic light-emitting element from changing according to the gray scale.

[0029] In addition, it is possible to easily correct spots or colors that may appear in an image displayed on the display panel due to deviations between sub-pixel circuits. Specifically, even when a modular display panel is combined to form a large-area display panel, it is possible to more easily correct the brightness or color difference between display panel modules.

[0030] In addition, a more optimized driving circuit can be designed, and the inorganic light-emitting element can be stably and effectively driven. Specifically, the power consumption of the display panel for displaying an image can be reduced.

[0031] In addition, it can contribute to the miniaturization and weight reduction of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a graph showing the wavelength change according to the magnitude of the driving current flowing through a blue light-emitting diode (LED), a green LED, and a red LED;

[0034] Figure 2 is a diagram showing the pixel structure of a display module according to an embodiment;

[0035] Figure 3A is a conceptual diagram showing a driving method of a display panel according to the prior art;

[0036] Figure 3B is a conceptual diagram showing a driving method of a display panel according to an embodiment;

[0037] Figure 3C is a conceptual diagram showing a driving method of a display panel according to an embodiment;

[0038] Figure 3DIt is a conceptual diagram showing a driving method of a display panel according to an embodiment;

[0039] Figure 4 It is a block diagram showing a configuration of a display module according to an embodiment;

[0040] Figure 5 It is a diagram showing a driving method of a display panel for multiple image frames according to an embodiment;

[0041] Figure 6 It shows in more detail Figure 5 a diagram of the second frame shown;

[0042] Figure 7 It is a diagram showing a light-emitting operation of a display panel according to an embodiment;

[0043] Figure 8 It is a diagram showing a light-emitting operation of a display panel according to an embodiment;

[0044] Figure 9 It is a diagram showing a light-emitting operation of a display panel according to an embodiment;

[0045] Figure 10 It is a block diagram of a display module according to an embodiment;

[0046] Figure 11 It is a configuration diagram of a sub-pixel circuit according to an embodiment;

[0047] Figure 12 It is a detailed circuit diagram of a sub-pixel circuit according to an embodiment;

[0048] Figure 13 It is a timing diagram of a gate signal according to an embodiment;

[0049] Figure 14 It is a timing diagram of various signals for driving a display panel according to an embodiment;

[0050] Figure 15 It is a diagram showing an operation of a sub-pixel circuit for a gate signal according to an embodiment;

[0051] Figure 16 It is a diagram showing an operation of a sub-pixel circuit for a gate signal according to an embodiment;

[0052] Figure 17 It is a diagram showing an operation of a sub-pixel circuit for a gate signal according to an embodiment;

[0053] Figure 18 It is a diagram showing an operation of a sub-pixel circuit for a gate signal according to an embodiment;

[0054] Figure 19is a diagram showing the operation of a sub-pixel circuit for each gray level according to an embodiment;

[0055] Figure 20 is a diagram showing the operation of a sub-pixel circuit for a gate signal according to an embodiment;

[0056] Figure 21 is a diagram showing the gate signals applied during one frame time according to an embodiment;

[0057] Figure 22 is a diagram showing the operation of a sub-pixel circuit related to the implementation of a black gray level according to an embodiment;

[0058] Figure 23 is a diagram showing the operation of a sub-pixel circuit related to the implementation of a black gray level according to an embodiment;

[0059] Figure 24A is a diagram showing a method of driving a display panel according to an embodiment of the present disclosure;

[0060] Figure 24B is a block diagram of a sub-pixel circuit according to an embodiment;

[0061] Figure 24C is for driving Figure 24B a timing diagram of various control signals for the sub-pixel circuit shown;

[0062] Figure 24D is a diagram showing the light-emitting operation of a display panel according to an embodiment;

[0063] Figure 25A shows a driving method of a display panel according to an embodiment;

[0064] Figure 25B is a block diagram of a sub-pixel circuit according to an embodiment;

[0065] Figure 25C is for driving Figure 25B a timing diagram of various control signals for the sub-pixel circuit shown;

[0066] Figure 25D is a diagram showing the light-emitting operation of a display panel according to an embodiment;

[0067] Figure 26 is a diagram showing a sweep-gate operation according to an embodiment;

[0068] Figure 27A is a detailed circuit diagram of a sub-pixel circuit according to an embodiment;

[0069] Figure 27B is a detailed circuit diagram of a sub-pixel circuit according to an embodiment;

[0070] Figure 28A It is a diagram showing image distortion occurring at the boundary portion of a display module according to an embodiment and a method for solving the same;

[0071] Figure 28B It is a diagram showing image distortion occurring at the boundary portion of a display module according to an embodiment and a method for solving the same;

[0072] Figure 29 It is a diagram showing a method of driving a display panel using multiple sweep signals according to an embodiment;

[0073] Figure 30A It is a cross-sectional view of a display module according to an embodiment;

[0074] Figure 30B It is a cross-sectional view of a display module according to an embodiment;

[0075] Figure 30C It is a plan view of a TFT layer according to an embodiment of the present invention;

[0076] Figure 31A It is a diagram showing an example of forming a gate driver in a TFT layer according to an embodiment;

[0077] Figure 31B It is a diagram showing an example of forming a gate driver in a TFT layer according to an embodiment;

[0078] Figure 31C It is a diagram showing an example of forming a gate driver in a TFT layer according to an embodiment;

[0079] Figure 32 It is a structural diagram of a display device according to an embodiment; and

[0080] Figure 33 It is a flowchart of a driving method of a display module according to an embodiment. Detailed Description of the Invention

[0081] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0082] In the description of the present disclosure, if it is determined that the gist of the present disclosure may be unnecessarily obscured, a detailed description of known related technologies will be omitted. In addition, redundant descriptions of the same configuration will be omitted.

[0083] The suffix “unit” of the constituent elements used in the following description is given or mixed only for ease of drafting the specification, and does not distinguish the meanings or functions of themselves from each other.

[0084] The terms used in this disclosure are used to describe embodiments and are not intended to limit and / or restrict this disclosure. Unless otherwise clearly specified in the context, the singular form includes the plural expression.

[0085] In this specification, terms such as "comprising" or "having" are used to specify the presence of the described features, integers, steps, operations, components, parts, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0086] Expressions such as "first", "second", "the first", "the second", etc. used in this disclosure may be used to express various components regardless of order and / or importance, but are used to distinguish one component from other components and do not limit the components.

[0087] When referring to a component (e.g., the first component) being "(operatively or communicatively) coupled / coupled to" or "connected to" another component (e.g., the second component), it should be understood that one component can be directly coupled / coupled to another component or can be coupled / coupled to another component via yet another component (e.g., the third component).

[0088] When referring to a component (e.g., the first component) being "directly coupled / directly coupled to" or "directly connected to" another component (e.g., the second component), it should be understood that there are no other components (e.g., the third component) between one component and another component.

[0089] Unless otherwise defined, the terms used in the embodiments of this disclosure can be interpreted as having the meanings commonly known to those of ordinary skill in the art.

[0090] Various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0091] Figure 2 is a diagram showing the pixel structure of a display panel according to an embodiment.

[0092] Referring to Figure 2 , the display panel 100 may include a plurality of pixels 10 arranged (or disposed) in a matrix form. In this regard, the matrix form includes a plurality of row lines or a plurality of column lines.

[0093] In some cases, the row lines may be referred to as horizontal lines, scan lines, or gate lines, and the column lines may be referred to as vertical lines or data lines.

[0094] Each pixel 10 included in the display panel 100 may include three types of sub-pixels (such as a red (R) sub-pixel 20-1, a green (G) sub-pixel 20-2, and a blue (B) sub-pixel 20-3).

[0095] Each of the sub-pixels 20-1 to 20-3 may include an inorganic light-emitting element corresponding to the type of the sub-pixel and a sub-pixel circuit for controlling the light-emitting time of the inorganic light-emitting element.

[0096] That is, the R sub-pixel 20-1 may include an R inorganic light-emitting element and a sub-pixel circuit for controlling the light-emitting time of the R inorganic light-emitting element, the G sub-pixel 20-2 may include a G inorganic light-emitting element and a sub-pixel circuit for controlling the light-emitting time of the G inorganic light-emitting element, and the B sub-pixel 20-3 may include a B inorganic light-emitting element and a sub-pixel circuit for controlling the light-emitting time of the B inorganic light-emitting element.

[0097] Each sub-pixel circuit may represent the gray level of each sub-pixel by controlling the emission time of the corresponding inorganic light-emitting element based on the applied pulse-width modulation (PWM) data voltage, which will be described in detail later.

[0098] The sub-pixels included in each row line of the display panel 100 may be driven in the order of setting (or programming) the PWM data voltage and emitting light based on the set PWM data voltage. In this regard, according to an embodiment, the sub-pixels included in each row line of the display panel 100 may be driven in the order of the row lines.

[0099] That is, for example, the setting of the PWM data voltage and the light-emitting operation of the sub-pixels included in one row line (e.g., the first row line) and the setting of the PWM data voltage and the light-emitting operation of the sub-pixels included in the next row line (e.g., the second row line) may be sequentially performed.

[0100] Here, sequentially performing does not mean that the operations related to the next row line need to start after all the operations related to one row line are completed. That is, in the above example, after setting the PWM data voltage to the sub-pixels included in the first row line, the PWM data voltage may be set to the sub-pixels included in the second row line, and it is not necessary to set the PWM data voltage to the sub-pixels included in the second row line after completing the light-emitting operation of the sub-pixels included in the first row line.

[0101] Figure 3A is a conceptual diagram showing a driving method of a display panel according to the prior art, and Figures 3B to 3D is a conceptual diagram showing a driving method of a display panel according to various embodiments.

[0102] Figures 3A to 3D shows various methods of driving the display panel during one image frame time. In Figures 3A to 3DIn this case, the vertical axis represents the row lines, and the horizontal axis represents time. Additionally, the data setting period indicates the driving period of the display panel 100 set by applying the PWM data voltage to the sub-pixels included in each row line, and the light emission period indicates the driving period of the display panel 100, where the sub-pixels emit light during the time corresponding to the PWM data voltage within this driving period.

[0103] According to Figure 3A , in the prior art, it can be seen that after the PWM data voltage is completely set to all the row lines of the display panel first, the light emission periods are carried out jointly.

[0104] In this case, since all the row lines of the display panel emit light simultaneously during the light emission period, a high peak current is required, and thus there is a problem of an increase in the peak power consumption required for the product. When the peak power consumption increases, the capacity of the power supply device (such as a switch-mode power supply (SMPS)) installed in the product increases, resulting in an increase in cost and volume, which leads to design limitations.

[0105] In Figures 3B to 3D 's embodiments, there may be the following differences: whether the PWM data voltage setting for all the row lines is completed only during one image frame time (in the case of Figure 3B ), whether the light emission periods for all the row lines are completely carried out during one image frame time (in the case of Figure 3C ), or whether there are multiple light emission periods during one image frame time (in the case of Figure 3D ). It can be seen that the PWM data voltage setting period and the light emission period of each row line are carried out sequentially in the order of the row lines.

[0106] As described above, when the light emission periods for each row line are driven sequentially in the order of the row lines according to various embodiments, since the number of row lines that emit light simultaneously decreases, the required peak current amount is reduced compared to the prior art, and thus the peak power consumption can be reduced.

[0107] As described above, according to various embodiments, in the active matrix (AM) method, the occurrence of the change in the wavelength of the light emitted by the inorganic light-emitting element according to the gray scale can be prevented by PWM driving the inorganic light-emitting element. Additionally, the instantaneous peak power consumption can be reduced by driving the display panel 100 such that the sub-pixels emit light sequentially in the order of the row lines.

[0108] Figure 2 An example is shown in which the sub-pixels 20-1 to 20-3 are arranged in a left-right reversed L shape in one pixel region. However, the embodiments are not limited thereto, and the R sub-pixel 20-1, the G sub-pixel 20-2, and the B sub-pixel 20-3 can be arranged in a line within the pixel region, or can be arranged in various shapes according to the embodiments.

[0109] In addition, in Figure 2 it is described by way of example that three types of sub-pixels form one pixel. However, according to an embodiment, four types of sub-pixels (such as R, G, B, and W (white)) may form one pixel, or any number of different sub-pixels may form one pixel.

[0110] Figure 4 is a block diagram showing the configuration of a display module according to an embodiment. Referring to Figure 4 , the display module 300 may include a display panel 100 and a driver 200.

[0111] The driver 200 may drive the display panel 100. Specifically, the driver 200 may provide various control signals, data signals, and power signals to the display panel 100 to drive the display panel 100.

[0112] To this end, the driver 200 may include at least one gate driver circuit (or scan driver circuit) for providing control signals for driving the pixels of the display panel 100 arranged in a matrix form in units of row lines.

[0113] In addition, the driver 200 may include a source driver circuit (or data driver circuit) for providing a PWM data voltage to each pixel (or each sub-pixel) of the display panel 100 arranged in a matrix form.

[0114] In addition, the driver 200 may include a MUX circuit for selecting each of the plurality of sub-pixels 20-1 to sub-pixel 20-3 that make up the pixel 10.

[0115] In addition, the driver 200 may include a drive voltage providing circuit for providing various drive voltages (for example, a first drive voltage, a second drive voltage, a ground voltage, a test voltage, a Vset voltage, etc., described later) or a constant current generator voltage described later to each sub-pixel circuit included in the display panel 100.

[0116] In addition, the driver 200 may include a clock signal providing circuit for providing various clock signals for driving the gate driver or the data driver circuit, and may include a sweep voltage providing circuit for providing a sweep voltage described later.

[0117] According to an embodiment, at least some of the various circuits of the driver 200 described above may be implemented in the form of separate chips and installed on an external printed circuit board (PCB) together with a timing controller (TCON), and may be connected to the sub-pixel circuits formed in the TFT layer of the display panel 100 through film on glass (FOG) wiring.

[0118] According to an embodiment, at least some of the various circuits of the above-described driver 200 may be implemented in the form of separate chips and disposed on a film in the form of chip-on-film (COF), and may be connected to sub-pixel circuits formed in the TFT layer of the display panel 100 through FOG wiring.

[0119] According to an embodiment, at least some of the various circuits of the above-described driver 200 may be implemented in the form of separate chips and disposed in the form of COG (i.e., disposed on the rear surface of the glass substrate of the display panel 100 (on the opposite surface of the surface on which the TFT layer is formed with respect to the glass substrate (described later))), and may be connected to sub-pixel circuits formed in the TFT layer of the display panel 100 through connection wiring.

[0120] According to an embodiment, at least some of the various circuits of the above-described driver 200 may be formed in the TFT layer together with sub-pixel circuits formed in the TFT layer in the display panel 100 and connected to the sub-pixel circuits.

[0121] For example, among the various circuits of the above-described driver 200, a gate driver circuit, a sweep voltage providing circuit, and a MUX circuit may be formed in the TFT layer of the display panel 100, a data driver circuit may be disposed on the rear surface of the glass substrate of the display panel 100, and a driving voltage providing circuit, a clock signal providing circuit, and a timing controller (TCON) may be disposed on an external printed circuit board (PCB), but are not limited thereto.

[0122] Specifically, according to an embodiment, the driver 200 may apply a PWM data voltage to sub-pixels included in each row line of the display panel 100 in the order of the row lines, and drive the display panel 100 such that the sub-pixels included in at least some consecutive row lines among the multiple row lines emit light for a time corresponding to the applied PWM data voltage in the order of the row lines.

[0123] Here, the at least some consecutive row lines may refer to all row lines of the display panel 100, or when all row lines of the display panel 100 are divided into multiple groups including some consecutive row lines, the at least some consecutive row lines may refer to consecutive row lines of each group.

[0124] Therefore, the driver 200 may drive the display panel 100 such that the sub-pixels included in all row lines of the display panel 100 emit light in the order of the row lines, as Figure 3B and Figure 3C shown.

[0125] In addition, as Figure 3DAs shown, the driver 200 can drive the display panel 100 such that the sub-pixels included in the row lines belonging to each group emit light in the order of the row lines of each group of row lines including consecutive row lines.

[0126] Hereinafter, reference will be made to Figures 5 to 9 for a detailed description of Figure 3D the driving method of the display panel 100 as shown.

[0127] Figure 5 shows the driving method of the display panel 100 for multiple image frames. In Figure 5 each frame, the vertical axis indicates the row lines, and the horizontal axis indicates time. Additionally, the blanking time indicates the time period between frames to which no valid image data is applied.

[0128] VST and SP represent control signals applied by the driver 200 to the sub-pixels included in each row line for data setting operations, and SET, Emi_PWM, Sweep, and Emi_PAM represent control signals applied by the driver 200 to the sub-pixels included in each row line for light emission operations. Such various control signals of the driver 200 will be described in detail later.

[0129] Referring to Figure 5 , it can be seen that during one image frame time, for each row line, the data setting period (i.e., the time period during which the control signals VST and SP are applied) occurs once, and the light emission period (i.e., the time period during which the control signals SET, Emi_PWM, Sweep, and Emi_PAM are applied) occurs multiple times.

[0130] That is, according to the embodiment, the driver 200 can apply a PWM data voltage to the sub-pixels included in each row line during the data setting period for each row line, and drive the display panel 100 such that in the multiple light emission periods of each row line, the sub-pixels included in each row line emit light for a time corresponding to the applied PWM data voltage.

[0131] Figure 6 is a diagram showing more details of Figure 5 the second frame as shown. In Figure 6 , the vertical axis represents the row lines and the horizontal axis represents time. In Figure 6 , for ease of description, as an example, the display panel 100 includes 40 row lines.

[0132] Referring to Figure 6, during the data setting period 61 of the first row line, for example, the driver 200 applies the control signals VST and SP to the sub-pixels included in the first row line. Accordingly, the PWM data voltages provided from the data driver are respectively set (or programmed) to the sub-pixels included in the first row line.

[0133] Thereafter, during the first light emission period 62 of the first row line, the driver 200 applies control signals (SET, Emi_PWM, Sweep, and Emi_PAM) to the sub-pixels included in the first row line. Accordingly, in the first light emission period 62, the sub-pixels included in the first row line emit light for a time corresponding to the PWM data voltage set in the data setting period 61.

[0134] Thereafter, even during the second light emission period 63 of the first row line, as in the first light emission period 62, the driver 200 also applies control signals (SET, Emi_PWM, Sweep, and Emi_PAM) to the sub-pixels included in the first row line. Accordingly, even in the second light emission period 63, the sub-pixels included in the first row line emit light for a time corresponding to the PWM data voltage set in the data setting period 61.

[0135] This is the same in the third light emission period 64 and the fourth light emission period 65 of the first row line.

[0136] As Figure 6 shown, the driver 200 can sequentially perform the above operations of the first row line on the sub-pixels included in the remaining row lines (the second row line to the 40th row line) in the order of the row lines.

[0137] In Figure 6 , since only one frame period (i.e., the second frame period) is shown, it is shown that after the data setting period progresses from the 11th row line to the 20th row line, the light emission period only occurs three times, after the data setting period progresses from the 21st row line to the 30th row line, the light emission period only occurs twice, and after the data setting period progresses from the 31st row line to the 40th row line, the light emission period only occurs once. However, it can be seen that in Figure 5 the second frame period and the third frame period shown, after the data setting period also progresses from the 11th row line to the 40th row line, the light emission periods occur four times respectively.

[0138] According to Figure 6 the example shown, it can be seen that the first light emission period 62 among the multiple light emission periods of the first row line is continuous in time with the data setting period 61 of the first row line, and each of the multiple light emission periods 62 to 65 has a predetermined time interval. This is the same for the remaining row lines.

[0139] In this regard, according to an embodiment, the number of light emission cycles performed in each row line and the predetermined time interval between the light emission cycles during one image frame period may be set based on the size of the display panel 100 and / or the shutter speed of the camera, etc. However, the embodiment is not limited thereto.

[0140] Generally, since the shutter speed of the camera is several times faster than one image frame time, as Figure 3B or Figure 3C shown, when the display panel 100 is driven such that the light emission cycles are performed once in the order of the row lines within one image frame time, the image displayed on the display panel 100 captured by the camera may be distorted.

[0141] Therefore, as Figure 3D shown, when the display panel 100 is driven such that a plurality of light emission cycles are performed at a predetermined time interval during one image frame time, the predetermined time interval is set based on the speed of the camera. Thus, even when the display panel 100 is captured at any moment, the image displayed on the display panel 100 captured by the camera will not be distorted.

[0142] Figure 6 The data setting period and the light emission period shown in [] are only shown to conceptually explain the data setting operation and the light emission operation performed in the order of the row lines over time, and the specific driving timings of the control signal VST and SP for data setting or the control signals SET, Emi_PWM, Sweep, and Emi_PAM for the light emission operation are not limited to those shown in []. The specific driving timings of the control signals will be described in detail later after []. Figure 6 After Figure 13 The specific driving timings of the control signals will be described in detail later.

[0143] Hereinafter, with reference to Figures 7 to 9 and Figure 6 the image displayed on the display panel 100 during one image frame period will be described. It is shown Figures 7 to 9 , assuming that the PWM data voltage corresponding to the full white gray level is set to each sub-pixel of the display panel 100 for ease of explanation.

[0144] Figure 7 It is shown that when the display panel 100 is driven as shown in [] during one image frame period, the light emission operations of the first row line to the 10th row line of the display panel 100 during the time ① shown in [] are performed. Figure 6 during Figure 6 shown.

[0145] Specifically, when the first light emission cycle 62 of the first row line starts, as Figure 7 indicated by the reference numeral 71 in [], the first row line of the display panel 100 starts to emit light (specifically, including the sub-pixels in the row line emitting light, but hereinafter, for ease of description, it will be abbreviated as the row line emitting light).

[0146] Thereafter, when the first light emission period of the second row line starts, since the light emission period of the first row line has not ended yet, as shown by the reference numeral 72 in Figure 7 the first row line and the second row line emit light together.

[0147] Thereafter, when the first light emission period of the third row line starts, since the light emission periods of the first row line and the second row line have not ended yet, as shown by the reference numeral 73 in Figure 7 the first row line to the third row line emit light together.

[0148] Thereafter, when the first light emission period of the fourth row line starts, because the first light emission period 62 of the first row line ends, as shown by the reference numeral 74 in Figure 7 the first row line stops emitting light, and the second row line to the fourth row line emit light together.

[0149] In this way, the light emission of the three row lines proceeds sequentially to the 10th row line. Figure 7 The reference numeral 75 in

[0150] indicates that the first light emission period of the 10th row line starts, and the 8th row line to the 10th row line emit light. Figure 7 Thereafter, when the second light emission period 63 of the first row line starts, because the first light emission period of the 8th row line ends, as shown by the reference numeral 76 in

[0151] the first row line emits light again together with the 9th row line and the 10th row line. Figure 7 Thereafter, when the second light emission period of the second row line starts, since the first light emission period of the 9th row line ends, as shown by the reference numeral 77 in

[0152] the 10th row line, the first row line and the second row line emit light together. Figure 7 Finally, when the second light emission period of the third row line starts, the first light emission period of the 10th row line ends, and as shown by the reference numeral 78 in

[0153] the first row line to the third row line emit light again.

[0154] In the above, although the light emission operations of the first row line to the 10th row line are described, it can be seen that regarding Figure 6 the progress of the light emission period over time as shown, even in the cases of the 11th row line to the 20th row line, the 21st row line to the 30th row line, and the 31st row line to the 40th row line, each row line can emit light in the same manner as described for the first row line to the 10th row line.

[0155] However, it can be seen that in the case of the 11th row line to the 20th row line, the 21st row line to the 30th row line, and the 31st row line to the 40th row line, the PWM data voltage serving as the basis for light emission is different from the case of the first row line to the 10th row line.

[0156] Hereinafter, the light emission operations of all row lines of the display panel 100 will be described through Figure 8 and Figure 9 the light emission operations of all row lines of the display panel 100 will be described.

[0157] Figure 8 Shown is the light emission operation of the row lines based on the PWM data voltage (hereinafter referred to as the second PWM data voltage) applied during the image frame period shown in Figure 6 (i.e., the second frame period of Figure 5 ). The order of the light emission periods used in the descriptions of Figure 8 and Figure 9 represents the order of the light emission periods based on the second PWM data voltage.

[0158] Figure 5 The light emission operation of the row lines based on the PWM data voltage (hereinafter referred to as the first PWM data voltage) applied during the first frame period is not shown in Figure 8 ).

[0159] As described above in Figure 7 , during the first light emission period, the first row line to the 10th row line emit light in sequence based on the second PWM data voltage applied to each row line. Figure 8 The reference numeral 81 in

[0160] indicates this point. Figure 8 Thereafter, when the first light emission period of the 11th row line to the 20th row line is carried out together with the second light emission period of the first row line to the 10th row line, as shown by the reference numeral 82 in

[0161] the first row line to the 10th row line and the 11th row line to the 20th row line emit light in sequence based on the second PWM data voltage. Figure 8 Thereafter, when the third light emission period of the first row line to the 10th row line, the second light emission period of the 11th row line to the 20th row line, and the first light emission period of the 21st row line to the 30th row line are carried out together, as shown by the reference numeral 83 in

[0162] the first row line to the 10th row line, the 11th row line to the 20th row line, and the 21st row line to the 30th row line emit light in sequence based on the second PWM data voltage. Figure 8As shown by reference numeral 84 in the drawings, the first row line to the 10th row line, the 11th row line to the 20th row line, the 21st row line to the 30th row line, and the 31st row line to the 40th row line emit light in sequence based on the second PWM data voltage.

[0163] Specifically, according to an embodiment, a plurality of row lines included in the display panel 100 may be divided into a plurality of groups each including consecutive row lines.

[0164] In the above example, the first row line to the 10th row line may be divided into a first group, the 11th row line to the 20th row line may be divided into a second group, the 21st row line to the 30th row line may be divided into a third group, and the 31st row line to the 40th row line may be divided into a fourth group.

[0165] The driver 200 may apply the PWM data voltage to the sub-pixels included in each row line in order from the first row line to the last row line among the plurality of row lines during one image frame period.

[0166] That is, as Figure 6 shown, it can be seen that during one image frame period (i.e., Figure 5 the second frame period of

[0167] ), the driver 200 may apply the PWM data voltage to the sub-pixels included in each row line in order from the first row line to the 40th row line.

[0168] In addition, the driver 200 may drive the display panel 100 such that during one image frame period, based on the applied second PWM data voltage, the sub-pixels included in one group among the plurality of groups emit light in order of row lines, and then the sub-pixels included in each of at least two consecutive groups emit light in order of row lines. The at least two consecutive groups may include the one group.

[0168] That is, the driver 200 may drive the display panel 100 such that during one image frame period (i.e., Figure 5 the second frame period of Figure 8 ), as shown by reference numeral 81 in the drawings, the sub-pixels included in the first group emit light in order of row lines based on the second PWM data voltage, and then, as Figure 8 shown by reference numeral 82 in the drawings, the sub-pixels included in each of the first group and the second group emit light in order of row lines based on the second PWM data voltage.

[0169] That is, the driver 200 may drive the display panel 100 such that during one image frame period (i.e., Figure 5 the second frame period of Figure 8 ), as shown by reference numeral 82 in the drawings, the sub-pixels included in each of the first group and the second group emit light in order of row lines based on the second PWM data voltage, and then, as Figure 8As shown by reference numeral 83, the sub-pixels included in each of the first to third groups emit light in the order of the row lines based on the second PWM data voltage.

[0170] That is, the driver 200 can drive the display panel 100 such that during one image frame period (i.e., Figure 5 the second frame period), as Figure 8 shown by reference numeral 83, the sub-pixels included in each of the first to third groups emit light in the order of the row lines based on the second PWM data voltage, and then, as Figure 8 shown by reference numeral 84, the sub-pixels included in each of the first to fourth groups emit light in the order of the row lines based on the second PWM data voltage.

[0171] Figure 9 shows the light-emitting operations of all the row lines of the display panel 100 based on the first PWM data voltage and the second PWM data voltage.

[0172] Referring to Figure 6 , it can be seen that for each group, the first light-emitting period of the first to 10th row lines is carried out in the order of the row lines, and the light-emitting periods of the 11th to 20th row lines, the 21st to 30th row lines, and the 31st to 40th row lines are also carried out together in the order of the row lines. At this time, the first to 10th row lines emit light based on the second PWM data voltage, and the remaining row lines emit light based on the first PWM data voltage, and Figure 9 reference numeral 91 shows this point.

[0173] Referring back to Figure 6 , for each group, the second light-emitting period of the first to 10th row lines and the first light-emitting period of the 11th to 20th row lines are carried out in the order of the row lines, and the light-emitting periods of the 21st to 30th row lines and the 31st to 40th row lines are also carried out together in the order of the row lines. At this time, the first to 20th row lines emit light based on the second PWM data voltage, and the remaining row lines emit light based on the first PWM data voltage, and Figure 9 reference numeral 92 shows this point.

[0174] Referring back to Figure 6 , when the third light-emitting period of the first to 10th row lines, the second light-emitting period of the 11th to 20th row lines, and the first light-emitting period of the 21st to 30th row lines are carried out in the order of the row lines, the light-emitting period of the 31st to 40th row lines is also carried out together in the order of the row lines. At this time, the first to 30th row lines emit light based on the second PWM data voltage, and the 31st to 40th row lines emit light based on the first PWM data voltage, and Figure 9 reference numeral 93 shows this point.

[0175] Reference cycle Figure 6 In the fourth light-emitting cycle of the first row line to the 10th row line, the third light-emitting cycle of the 11th row line to the 20th row line, the second light-emitting cycle of the 21st row line to the 30th row line, and the first light-emitting cycle of the 31st row line to the 40th row line are performed together in the order of the row lines. In this case, all of the first row line to the 40th row line emit light based on the second PWM data voltage, and Figure 9 Reference numeral 94 in Figure 9 Reference numeral 94 in Figure 8 may be the same as reference numeral 84 in

[0176] Specifically, as described above in Figure 8 , the driver 200 may drive the display panel 100 such that during one image frame cycle (e.g., the second frame cycle in Figure 5 ), sub-pixels included in one group among a plurality of groups emit light in the order of the row lines based on the second PWM data voltage, and then, sub-pixels included in each of at least two consecutive groups emit light in the order of the row lines.

[0177] Meanwhile, the driver 200 may drive the display panel 100 such that during one image frame cycle (e.g., the second frame cycle in Figure 5 ), sub-pixels included in each of the remaining groups other than at least one group driven based on the second PWM data voltage among the plurality of groups emit light in the order of the row lines based on the first PWM data voltage.

[0178] In this way, it can be seen that the driver 200 may drive the display panel 100 such that during one image frame cycle (e.g., the second frame cycle in Figure 5 ), sub-pixels included in each row line of each group among the plurality of groups emit light multiple times during a plurality of light-emitting cycles of each row line based on at least one of the first PWM data voltage and the second PWM data voltage, thereby driving the display panel 100 as described above with reference to Figure 9 .

[0179] In Figure 3D and Figures 5 to 9 , for ease of description, a case where the display panel 100 includes 40 row lines and the light-emitting cycle is performed four times for each row line is described by way of example, but the embodiments are not limited thereto, and various embodiments may exist according to the size or implementation example of the display panel 100.

[0180] For example, the driver 200 may drive the display panel 100 including 270 row lines, where 480 pixels are arranged in each row line, such that the light-emitting cycle is performed 9 times for each row line.

[0181] Hereinafter, reference will be made to Figures 10 to 22Describe in detail the specific structure and operation of the display panel 100 according to the embodiment.

[0182] Figure 10 is a block diagram showing the structure of the display module 300 according to the embodiment. In Figure 10 the description of, descriptions redundant with those above in Figure 4 will be omitted.

[0183] Referring to Figure 10 , the display module 300 includes a display panel 100 and a driver 200, and the display panel 100 includes a sub-pixel circuit 110 and an inorganic light-emitting element 120.

[0184] As will be described later, the display panel 100 may have a structure in which the sub-pixel circuit 110 is formed on glass and the inorganic light-emitting element 120 is disposed on the sub-pixel circuit 110. In Figure 10 , for ease of description, only one sub-pixel related structure included in the display panel 100 is shown, but the sub-pixel circuit 110 and the inorganic light-emitting element 120 are provided for each sub-pixel of the above display panel 100.

[0185] The inorganic light-emitting element 120 may be mounted on the sub-pixel circuit 110 to be electrically connected to the sub-pixel circuit 110, and emit light based on the driving current provided from the sub-pixel circuit 110.

[0186] The inorganic light-emitting element 120 may include sub-pixels 20-1 to 20-3 of the display panel 100, and may include multiple types according to the color of the emitted light. For example, the inorganic light-emitting element 120 may include a red (R) inorganic light-emitting element that emits red light, a green (G) inorganic light-emitting element that emits green light, and a blue (B) inorganic light-emitting element that emits blue light.

[0187] Therefore, the type of the above sub-pixels can be determined according to the type of the inorganic light-emitting element 120. That is, the R inorganic light-emitting element may include the R sub-pixel 20-1, the G inorganic light-emitting element may include the G sub-pixel 20-2, and the B inorganic light-emitting element may include the B sub-pixel 20-3.

[0188] Here, the inorganic light-emitting element 120 may refer to a light-emitting element made of inorganic materials, different from an organic light-emitting diode (OLED) made of organic materials.

[0189] Specifically, according to the embodiment, the inorganic light-emitting element 120 may be a micro light-emitting diode (micro LED or μLED) having a size less than or equal to 100 micrometers (μm).

[0190] A display panel in which each sub-pixel is implemented as a micro-LED is a micro-LED display panel. The micro-LED display panel is one of the flat panel display panels and includes a plurality of inorganic light-emitting diodes (inorganic LEDs) each having a size less than or equal to 100 micrometers. Compared with a liquid crystal display (LCD) panel that requires a backlight, the micro-LED display panel can provide better contrast, response time, and energy efficiency. Both organic light-emitting diodes (OLEDs) and micro-LEDs have good energy efficiency, and micro-LEDs provide better performance than OLEDs in terms of brightness, luminous efficiency, and lifespan.

[0191] The inorganic light-emitting element 120 can represent grayscale values of different brightness levels according to the magnitude of the drive current or the pulse width of the drive current provided from the sub-pixel circuit 110. Here, the pulse width of the drive current can be referred to as the duty cycle or the duration of the drive current.

[0192] For example, the inorganic light-emitting element 120 can exhibit a brighter grayscale value as the drive current increases. Additionally, the inorganic light-emitting element 120 can exhibit a brighter grayscale value as the pulse width of the drive current increases (i.e., the duty cycle increases or the duration increases).

[0193] The sub-pixel circuit 110 provides a drive current to the inorganic light-emitting element 120. Specifically, the sub-pixel circuit 110 can provide a drive current with a controlled magnitude and duration to the inorganic light-emitting element 120 based on the data voltage (e.g., constant current generator voltage, PWM data voltage) and drive voltage (e.g., first drive voltage, second drive voltage) applied from the driver 200 and various control signals.

[0194] That is, the sub-pixel circuit 110 can control the brightness of the light emitted by the inorganic light-emitting element 120 by driving the inorganic light-emitting element 120 through pulse amplitude modulation (PAM) and / or pulse width modulation (PWM).

[0195] To this end, the sub-pixel circuit 110 can include a constant current generator circuit 112 for providing a constant current of a certain magnitude to the inorganic light-emitting element 120 based on the applied constant current generator voltage, and a PWM circuit 111 for providing the constant current provided by the constant current generator circuit 112 for a time corresponding to the applied PWM data voltage to the inorganic light-emitting element 120. Here, the constant current provided to the inorganic light-emitting element 120 becomes the above-mentioned drive current.

[0196] The various circuits of the above-described driver 200 may be implemented as integrated circuits (ICs) having micron or nanometer dimensions, and may be mounted in the direction of the mounting surface on which the inorganic light-emitting element 120 is mounted, or may be mounted in the direction of the surface opposite to the mounting surface, or may be mounted on a film-type substrate connected to the surface opposite to the mounting surface.

[0197] According to an embodiment of the present disclosure, the driver 200 may apply the same constant current generator voltage to all of the constant current generator circuits 112 of the display panel 100. Accordingly, driving currents (i.e., constant currents) of the same magnitude are supplied to the inorganic light-emitting elements 120 through the constant current generator circuits 112. Accordingly, the problem of wavelength variation of the LED according to the variation in the magnitude of the driving current may be solved.

[0198] In addition, the driver 200 may apply a PWM data voltage corresponding to the gray value of each sub-pixel to each PWM circuit 111 of the display panel 100. Accordingly, the duration of the driving current (i.e., constant current) supplied to the inorganic light-emitting element 120 of each sub-pixel may be controlled through the PWM circuit 111. Accordingly, the gray scale of the image may be represented.

[0199] Although the same constant current generator voltage is applied to one display module 300, different constant current generator voltages may be applied to different display modules 300. Accordingly, the brightness deviation or color deviation between the display modules that may occur when a plurality of display modules are connected to form a large display device may be compensated by adjusting the constant current generator voltage.

[0200] As described above, the display module 300 according to various embodiments may be applied to wearable devices, portable devices, handheld devices, and various electronic or electrical products that require a display in a single unit.

[0201] In addition, the display module 300 according to various embodiments may be applied to small display devices (such as personal computer monitors, TVs, etc.) and large display devices (such as digital signage, electronic displays, etc.) through the assembly and arrangement of a plurality of display modules 300.

[0202] Figure 11 is a configuration diagram of a sub-pixel circuit according to an embodiment. Referring to Figure 11 , the sub-pixel circuit 110 may include a PWM circuit 111, a constant current generator circuit 112, a first switching transistor T10, and a second switching transistor T15.

[0203] The constant current generator circuit 112 may include a first driving transistor T8, and based on the voltage applied between the source terminal and the gate terminal of the first driving transistor T8, provide a constant current with a certain amplitude to the inorganic light emitting element 120.

[0204] Specifically, when a constant current generator voltage is applied from the driver 200 during the data setting period, the constant current generator circuit 112 may apply a constant current generator voltage having a compensation threshold voltage of the first driving transistor T8 to the gate terminal B of the first driving transistor T8.

[0205] There may be a difference in threshold voltage between the first driving transistors T8 included in the sub-pixels of the display panel 100. In this case, even when the same constant current generator voltage is applied, the constant current generator circuit 112 of each sub-pixel provides different driving currents to the inorganic light emitting element 120, the amplitude of which is determined by the threshold voltage difference of the first driving transistor T8, and this appears as blotches on the image. Therefore, it is necessary to compensate for the threshold voltage deviation of the first driving transistors T8 included in the display panel 100.

[0206] To this end, the constant current generator circuit 112 may include an internal compensator 12. Specifically, when a constant current generator voltage is applied, the constant current generator circuit 112 may apply a first voltage to the gate terminal B of the first driving transistor T8 through the internal compensator 12 based on the constant current generator voltage and the threshold voltage of the first driving transistor T8.

[0207] Thereafter, during the light emitting period, the constant current generator circuit 112 may provide a constant current to the inorganic light emitting element 120 through the turned-on first driving transistor T8, the amplitude of which is based on the first driving voltage applied to the source terminal of the first driving transistor T8 and the first voltage applied to the gate terminal of the first driving transistor T8.

[0208] Therefore, the constant current generator circuit 112 may provide a driving current having an amplitude corresponding to the applied constant current generator voltage to the inorganic light emitting element 120 regardless of the threshold voltage of the first driving transistor T8.

[0209] As Figure 11 shown, in the first switching transistor T10, the source terminal is connected to the drain terminal of the first driving transistor T8, and the drain terminal is connected to the source terminal of the second switching transistor T15. In addition, in the second switching transistor T15, the source terminal is connected to the drain terminal of the first switching transistor T10, and the drain terminal is connected to the anode terminal of the inorganic light emitting element 120. Therefore, when the first switching transistor T10 and the second switching transistor T15 are turned on, a constant current is provided to the inorganic light emitting element 120.

[0210] The PWM circuit 111 includes a second driving transistor T3 and controls the on / off operation of the first switching transistor T10 to control the time for a constant current to flow through the inorganic light-emitting element 120.

[0211] Specifically, when a PWM data voltage is applied from the driver 200 during a data setting period, the PWM circuit 111 can apply the PWM data voltage having the compensation threshold voltage of the second driving transistor T3 to the gate terminal A of the second driving transistor T3.

[0212] Since the above problems caused by the threshold voltage deviation among the first driving transistors T8 can occur in the same way for the second driving transistor T3, the PWM circuit 111 may further include an internal compensator 11.

[0213] Therefore, when the PWM data voltage is applied, the PWM circuit 111 can apply a second voltage based on the PWM data voltage and the threshold voltage of the second driving transistor T3 to the gate terminal A of the second driving transistor T3 through the internal compensator 11.

[0214] Thereafter, during an emission period, when the second driving transistor T3 is turned on based on the second voltage applied to the gate terminal of the second driving transistor T3 and the second driving voltage applied to the source terminal of the second driving transistor T3, the PWM circuit 111 can apply the second driving voltage to the gate terminal of the first switching transistor T10 to turn off the first switching transistor T10, thereby controlling the time for a constant current to flow through the inorganic light-emitting element 120.

[0215] At this time, when the voltage between the gate terminal and the source terminal of the second driving transistor T3 becomes the threshold voltage of the second driving transistor T3, since the second voltage applied to the gate terminal of the second driving transistor T3 varies according to the sweep voltage applied to the PWM circuit 111, the second driving transistor T3 can be turned on. Here, the sweep voltage is a voltage applied from the driver 200 to linearly change the voltage of the gate terminal of the second driving transistor T3, and can be a linearly varying signal (such as a triangular wave), but is not limited thereto.

[0216] Therefore, the PWM circuit 111 can allow a constant current to flow through the inorganic light-emitting element 120 only during the time corresponding to the applied PWM data voltage, regardless of the threshold voltage of the second driving transistor T3.

[0217] The PWM circuit 111 may include a resetter 13. The resetter 13 may be configured to forcibly turn on the first switching transistor T10. As described above, in order for a constant current to flow through the inorganic light-emitting element 120 to emit light, the first switching transistor T10 must be turned on. Therefore, through the operation of the resetter 13, the first switching transistor T10 can be turned on at the start time of each light-emitting cycle among a plurality of light-emitting cycles.

[0218] The second switching transistor T15 may be turned on / off according to a control signal (Emi_PAM described later) of the driver 200. The on / off timing of the second switching transistor T15 may be related to the implementation of black gradation, and its detailed description will be given later.

[0219] The first driving voltage may be a voltage used when the constant current generator circuit 112 supplies a driving current (i.e., a constant current) to the inorganic light-emitting element 120 during a light-emitting cycle, and the second driving voltage may be a voltage used when the constant current generator circuit 112 sets a data voltage (e.g., a PWM data voltage or a constant current generator voltage) to the sub-pixel circuit 110 during a data setting cycle.

[0220] When a driving current flows through the inorganic light-emitting element 120, an IR drop occurs, and thus a voltage drop occurs in the first driving voltage. However, in order to accurately represent gradation, an accurate data voltage must be set to the sub-pixel circuit 110, and for this purpose, the driving voltage applied to the sub-pixel circuit 110 must be stable.

[0221] Therefore, according to an embodiment, during a data setting cycle, the second driving voltage without an IR drop is applied not only to the PWM circuit 111 but also to the constant current generator circuit 112 configured to provide a driving current.

[0222] Hereinafter, Figures 12 to 23 The configuration and operation of the sub-pixel circuit 110 according to an embodiment will be described in more detail.

[0223] Figure 12 is a detailed circuit diagram of the sub-pixel circuit 110 according to an embodiment. Referring to Figure 12 the sub-pixel circuit 110 includes a PWM circuit 111, a constant current generator circuit 112, a first switching transistor T10, and a second switching transistor T15. At this time, as described above in Figure 11 it can be seen that the PWM circuit 111 includes an internal compensator 11 and a resetter 13, and the constant current generator circuit 112 includes an internal compensator 12.

[0224] Transistors T17 and T18 may be included in a circuit configuration for applying a second driving voltage VDD_PWM to the constant current generator circuit 112 during a data setting period.

[0225] Transistor T13 is a circuit configuration that is turned on according to a test voltage before the inorganic light emitting element 120 is mounted on the TFT layer described later and electrically connected to the sub-pixel circuit 110, and is used to confirm whether the sub-pixel circuit 110 is abnormal.

[0226] In Figure 12 where VDD_PAM represents a first driving voltage (e.g., +10 [V]), VDD_PWM represents a second driving voltage (e.g., +10 [V]), VSS represents a ground voltage (e.g., 0 [V]), and Vset represents a low voltage (e.g., -3 [V]) for turning on the first switching transistor T10. VDD_PAM, VDD_PWM, VSS, Vset, and the test voltage can be applied from the above driving voltage supply circuit.

[0227] VST(n) represents a signal for applying a voltage to the sub-pixel circuit 110 to initialize nodes A and B.

[0228] SP(n) represents a signal for applying a data voltage to the sub-pixel circuit 110.

[0229] SET(n) represents a signal for applying to the resetter 13 of the PWM circuit 111 to turn on the first switching transistor T10.

[0230] Emi_PWM(n) represents a signal for turning on transistors T1 and T5 to apply the second driving voltage VDD_PWM to the PWM circuit 111, and turning on transistors T6 and T16 to apply the first driving voltage VDD_PAM to the constant current generator circuit 112.

[0231] Sweep(n) represents a sweep voltage. According to an embodiment, the sweep voltage may be a linearly decreasing voltage, but is not limited thereto. For example, when the transistors included in the sub-pixel circuit 110 are implemented as NMOS, a linearly increasing voltage may also be used as the sweep voltage. For each light emitting cycle, the sweep voltage may be repeatedly applied in the same form.

[0232] Emi_PAM(n) represents a signal for turning on the second switching transistor T15.

[0233] In the above signals, n represents the n-th row line. As described above, the driver 200 drives the display panel 110 for each row line (or scan line or gate line). Therefore, the above control signals VST(n), SP(n), SET(n), Emi_PWM(n), Sweep(n), and Emi_PAM(n) are applied to all sub-pixel circuits 110 included in the n-th row line in the same order as described later Figure 13 the same order as that applied to all sub-pixel circuits 110 included in the n-th row line.

[0234] Therefore, the above control signals can be referred to as scan signals or gate signals and can be applied from the above gate driver.

[0235] Vsig(m)_R / G / B represents the PWM data voltage for each of the R, G, and B sub-pixels of the pixels included in the m-th column line. Specifically, since the above gate signal is a signal for the n-th row line, Figure 12 the Vsig(m)_R / G / B shown represents the PWM data voltage for each of the R, G, and B sub-pixels of a specific pixel set at the intersection of the n-th row line and the m-th column line, which is time-division multiplexed and applied.

[0236] At this time, Vsig(m)_R / G / B can be applied from the above data driver. In addition, Vsig(m)_R / G / B can use a voltage between, for example, +10 [V] (black) and +15 [V] (full white), but is not limited thereto.

[0237] Since Figure 12 the sub-pixel circuit 110 shown corresponds to one of the R, G, and B sub-pixels (for example, the R sub-pixel), only the PWM data voltage of the R sub-pixel among the time-division multiplexed PWM data voltages is selected and applied to the sub-pixel circuit 110 through the MUX circuit.

[0238] VPAM_R / G / B represents the constant current generator voltage for each of the R, G, and B sub-pixels included in the display panel 100. As described above, the same constant current generator voltage can be applied to the display panel 100.

[0239] However, the same constant current generator voltage may mean that the same constant current generator voltage is applied to the same type of sub-pixels included in the display panel 100, but does not necessarily mean that the same constant current generator voltage is applied to all different types of sub-pixels (such as R, G, and B). This is because the R, G, and B sub-pixels have different characteristics depending on the type of sub-pixel. Therefore, the constant current generator voltage may vary according to the type of sub-pixel.

[0240] Even in such a case, the same constant current generator voltage can be applied to sub-pixels of the same type regardless of the column lines or row lines. Thus, according to an embodiment, unlike the PWM data voltage, the constant current generator voltage can be directly applied to each type of sub-pixel from the driving voltage supply circuit without using a data driver.

[0241] That is, since the same voltage needs to be applied to sub-pixels of the same type regardless of the column lines or row lines, a DC voltage can be used as the constant current generator voltage. Thus, for example, three types of DC voltages (e.g., +5.1 [V], +4.8 [V], and +5.0 [V]) corresponding to R, G, and B sub-pixels, respectively, can be directly applied to the R, G, and B sub-pixel circuits of the display panel 100 separately from the driving voltage circuit. In this case, the MUX circuit is also unnecessary.

[0242] According to an embodiment, when better characteristics are exhibited by using the same constant current generator voltage for different types of sub-pixels, the same constant current generator voltage can be applied to different types of sub-pixels.

[0243] Figure 13 is the timing diagram of the gate signal described above in Figure 12 .

[0244] In Figure 13 , VST(n) and SP(n) (①) are related to the data setting operation of the sub-pixel circuit 110, and Emi_PWM(n), SET(n), Emi_PAM(n), and Sweep(n) (②) are related to the light emitting operation of the sub-pixel circuit 110.

[0245] As described above, according to an embodiment, during one image frame period, for each row line, the data setting period is performed once, and the light emitting period is performed multiple times.

[0246] Thus, signal ① is applied to each row line of the display panel 100 once per image frame, and signal ② is applied to each row line of the display panel 100 multiple times per image frame.

[0247] Figure 14 is the timing diagram of various signals for driving the display panel 100 during one image frame period according to an embodiment. In Figure 14 , an example is shown in which the display panel 100 includes 270 row lines.

[0248] As can be seen, as shown by reference numerals 1-①, 2-① to 270-①, the gate signals VST(n) and SP(n) for data setting operations are applied to each row line once in sequence of the row lines in one frame, and as shown by reference numerals 1-②, 2-② to 270-②, the gate signals Emi_PWM(n), SET(n), Emi_PAM(n) and Sweep(n) for light emission operations are applied to each row line multiple times.

[0249] As described above, according to the embodiment, during one image frame period, some of the light emission periods (e.g., the light emission periods above the lines corresponding to the data setting periods in the connection Figure 6 in the display panel 100) are based on the data voltages applied during the one image frame period, and the remaining light emission periods (e.g., the light emission periods below the lines corresponding to the data setting periods in the connection Figure 6 in the display panel 100) are based on the data voltages applied during the previous image frame period of the one image frame period.

[0250] In this regard, it can be seen that in the Figure 14 light emission operation through the gate signal shown, the light emission operation through the gate signal of reference numeral 14 is a light emission operation based on the data voltage applied in the previous image frame period.

[0251] Hereinafter, the detailed operation of the sub-pixel circuit 110 according to the embodiment will be described with reference to Figures 15 to 23 FIG.

[0252] Figure 15 FIG. Figure 13 shows the operation of the sub-pixel circuit 110 for the signal VST(n) in the gate signal shown.

[0253] When the data setting period starts, the driver 200 may first turn on the first driving transistor T8 included in the constant current generator circuit 112 and the second driving transistor T3 included in the PWM circuit 111.

[0254] For this purpose, the driver 200 may apply a low voltage (e.g., -3 [V]) to the sub-pixel circuit 110 through the signal VST(n), as Figure 15 shown.

[0255] Accordingly, when the low voltage is applied to the gate terminal of the second driving transistor T3 (hereinafter referred to as node A) through the turned-on transistor T12, the second driving transistor T3 is turned on. Additionally, when the low voltage is applied to the gate terminal of the first driving transistor T8 (hereinafter referred to as node B) through the turned-on transistor T11, the first driving transistor T8 is turned on.

[0256] When a low voltage (e.g., -3 [V]) is applied to the sub-pixel circuit 110 through the signal VST(n), the transistor T18 can also be turned on. VDD_PWM (hereinafter referred to as the second driving voltage (e.g., +10 [V])) is applied to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the node B through the turned-on transistor T18. In this case, the second driving voltage can be a reference potential for setting the data voltage to be processed according to the signal SP(n).

[0257] Figure 16 is a diagram showing the operation of the sub-pixel circuit 110 according to Figure 13 the signal SP(n) in the gate signal shown.

[0258] In the data setting period, when the first driving transistor T8 and the second driving transistor T3 are turned on through the signal VST(n), the driver 200 inputs the data voltage to each of the node A and the node B.

[0259] For this purpose, as Figure 16 shown, the driver 200 can apply a low voltage to the sub-pixel circuit 110 through the signal SP(n).

[0260] When a low voltage is applied to the sub-pixel circuit 110 based on the signal SP(n), the transistors T2 and T4 of the PWM circuit 111 are turned on. Therefore, the PWM data voltage Vsig(m)_R / G / B can be applied to the node A through the turned-on transistor T2, the second driving transistor T3 in the on state, and the turned-on transistor T4.

[0261] At this time, the PWM data voltage applied from the driver 200 is not set to the node A as it is, but a PWM data voltage with the compensation threshold voltage of the second driving transistor T3 (i.e., a voltage obtained by summing the PWM data voltage and the threshold voltage of the second driving transistor T3) is set to the node A.

[0262] Specifically, when the transistor T2 and the transistor T4 are turned on according to the signal SP(n), the PWM data voltage applied to the source terminal of the transistor T2 is input to the internal compensator 11. At this time, since the second driving transistor T3 is in a fully on state through the signal VST(n), the input PWM data voltage starts to be input to the node A while sequentially passing through the transistor T2, the second driving transistor T3, and the transistor T4. That is, the voltage of the node A starts to rise from the low voltage.

[0263] However, the voltage of node A does not rise to the input PWM data voltage, but only rises to a voltage corresponding to the sum of the PWM data voltage and the threshold voltage of the second driving transistor T3. This is because when the PWM data voltage starts to be input to the internal compensation circuit 11, since the voltage of node A is low enough (e.g., -3 [V]), the second driving transistor T3 is fully turned on, current flows sufficiently and the voltage of node A rises smoothly. However, as the voltage of node A increases, the voltage difference between the gate terminal (node A) and the source terminal of the second driving transistor T3 decreases, and the flow of current decreases. As a result, when the voltage difference between the gate terminal and the source terminal of the second driving transistor T3 reaches the threshold voltage of the second driving transistor T3, the second driving transistor T3 is turned off and the current flow stops.

[0264] That is, since the PWM data voltage is applied to the source terminal of the second driving transistor T3 through the turned-on transistor T2, the voltage of node A only rises to the sum of the PWM data voltage and the threshold voltage of the second driving transistor T3.

[0265] When a low voltage is applied to the sub-pixel circuit 110 through the signal SP(n), the transistors T7 and T9 of the constant current generator circuit 111 are also turned on. Therefore, the constant current generator voltage VPAM_R / G / B can be applied to the B node through the turned-on transistor T7, the first driving transistor T8 in the on state, and the turned-on transistor T9.

[0266] At this time, the constant current generator voltage applied from the driver 200 is not set to the node B as it is. Instead, for the same reason as described above for node A, the PWM data voltage having the compensation threshold voltage of the first driving transistor T8 (i.e., the voltage obtained by adding the constant current generator voltage and the threshold voltage of the first driving transistor T8) is set to the node B.

[0267] When a low voltage is applied to the sub-pixel circuit 110 through the signal SP(n), the transistor T17 is also turned on. Since the second driving voltage is applied to the other end of the capacitor C through the turned-on transistor T17, the reference potential of each data voltage applied to node A and node B is maintained.

[0268] Figure 17 is a diagram showing the operation of the sub-pixel circuit 110 according to Figure 13 the signal SET(n) in the gate signal shown. Specifically, Figure 17 shows the operation of the sub-pixel circuit 110 according to the signal SET(n) in the first light emission period after the data setting period for one row line is performed.

[0269] When the setting of the respective data voltages of the constant current generator circuit 112 and the PWM circuit 111 is completed, the driver 200 first turns on the first switching transistor T10 to cause the inorganic light emitting element to emit light.

[0270] For this purpose, as Figure 17 shown, the driver 200 applies a low voltage to the sub-pixel circuit 110 (specifically, the resetter 13 of the PWM circuit 111) through the signal SET(n).

[0271] Accordingly, the voltage Vset is charged in the capacitor C3 through the turned-on transistor T14. As described above, since Vset is a low voltage (for example, -3 [V]), when the Vset voltage is charged in the capacitor C3, the low voltage is applied to the gate terminal of the first switching transistor T10 (hereinafter referred to as node C), so that the first switching transistor T10 is turned on.

[0272] Before the signal Emi_PWM(n) is applied, the resetter 13 can operate independently of the rest of the circuit configuration. Therefore, according to the embodiment, the low voltage can be applied through the signal SET(n) earlier than Figure 13 shown in the figure.

[0273] Figure 18 is a diagram showing the operation of the sub-pixel circuit 110 according to Figure 13 the signals Emi_PWM(n), Emi_PAM(n), and Sweep(n) in the gate signal shown.

[0274] When a low voltage is applied to node C based on the signal SET(n) and the first switching transistor T10 is turned on, the driver 200 can supply power to the inorganic light emitting element 120 based on the voltages set to node A and node B.

[0275] For this purpose, the driver 200 can apply a low voltage to the sub-pixel circuit 110 through the signals Emi_PWM(n) and Emi_PAM(n), and apply a sweep voltage to the sub-pixel circuit 110 through the signal Sweep(n).

[0276] First, the operation of the constant current generator circuit 112 according to the signal applied from the driver 200 will be described below.

[0277] The constant current generator circuit 112 can supply a constant current to the inorganic light emitting element 120 based on the voltage set to node B.

[0278] Specifically, since a low voltage can be applied to the gate terminal through signals Emi_PWM(n) and Emi_PAM(n), transistors T6 and the second switching transistor T15 are turned on. As described above, the first switching transistor T10 is in the on state according to the signal SET(n). Additionally, as described above, in a state where a voltage that is the sum of the constant current generator voltage (e.g., +5 [V]) and the threshold voltage of the first driving transistor T8 is applied to node B, since the voltage VDD_PAM (hereinafter referred to as the first driving voltage (e.g., +10 [V])) is applied to the source terminal of the first driving transistor T8 through the transistor T6 turned on according to the signal Emi_PWM(n), a voltage less than the threshold voltage of the first driving transistor T8 is applied between the gate terminal and the source terminal of the first driving transistor T8, and thus the first driving transistor T8 is also turned on (as a reference, in the case of a PMOSFET, the threshold voltage has a negative value, and when a voltage less than the threshold voltage is applied between the gate terminal and the source terminal, the PMOSFET is turned on, and when a voltage exceeding the threshold voltage is applied, the PMOSFET is turned off).

[0279] Accordingly, the first driving voltage can be applied to the anode terminal of the inorganic light-emitting element 120 through the turned-on transistors T6, the first driving transistor T8, the first switching transistor T10, and the second switching transistor T15, and a potential difference exceeding the forward voltage Vf is generated across the inorganic light-emitting element 120. Accordingly, a driving current (i.e., a constant current) can flow through the inorganic light-emitting element 120, and the inorganic light-emitting element 120 starts to emit light. In this regard, the amplitude of the driving current (i.e., the constant current) that causes the inorganic light-emitting element 120 to emit light can have an amplitude corresponding to the constant current generator voltage.

[0280] Since a driving current must be supplied to the inorganic light-emitting element 120 during the light-emitting period, the driving voltage applied to the constant current generator circuit 112 changes from the second driving voltage to the first driving voltage. Specifically, as Figure 18 shown, when a low voltage is applied to transistors T6 and T16 according to the signal Emi_PWM(n), the first driving voltage is applied to the other end of the capacitor C2 through the turned-on transistors T6 and T16.

[0281] At this time, as described above in the Figure 11 description, when a driving current flows through the inorganic light-emitting element 120, a voltage drop occurs in the first driving voltage due to the IR drop generated in the transistors T6 and the first driving transistor T8.

[0282] However, even if a voltage drop occurs in the first driving voltage, it is voltage-coupled by a voltage corresponding to the difference between the second driving voltage and the first driving voltage. Therefore, the voltage of node B also drops. Regardless of the amount of voltage drop (i.e., IR drop) of the first driving voltage, the voltage between the gate terminal and the source terminal of the first driving transistor T8 always remains the same. Therefore, according to the sub-pixel circuit 110 according to the embodiment, since the voltage drop of the first driving voltage is compensated, no problem can be seen.

[0283] Next, the operation of the PWM circuit 111 according to the signal applied from the driver 200 will be described as follows.

[0284] The PWM circuit 111 can control the light emission time of the inorganic light-emitting element 120 based on the voltage set to node A. Specifically, the PWM circuit 111 can control the turn-off operation of the first switching transistor T10 based on the voltage set to node A, thereby controlling the driving time of the constant current supplied to the inorganic light-emitting element 120 by the constant current generator circuit 112. Therefore, the light emission time of the inorganic light-emitting element 120 can be controlled.

[0285] As described above, when the constant current generator circuit 112 can supply a constant current to the inorganic light-emitting element 120, the inorganic light-emitting element 120 starts to emit light.

[0286] At this time, referring to Figure 18 , even if the transistors T1 and T5 are turned on according to the signal Emi_PWM(n), the second driving voltage is not applied to node C because the second driving transistor T3 is in the off state. Therefore, the first switching transistor T10 remains in the on state, and a constant current flows through the inorganic light-emitting element 120.

[0287] Specifically, when the transistor T1 is turned on according to the signal Emi_PWM(n), the second driving voltage (e.g., +10 [V]) is applied to the source terminal of the second driving transistor T3 through the transistor T1 turned on according to the signal Emi_PWM(n).

[0288] As described above, when a voltage between +10 [V] (black) and +15 [V] (full white) is used as the PWM data voltage, assuming that the threshold voltage of the second driving transistor T3 is -1 [V], since a voltage between +9 [V] (black) and +14 [V] (full white) is set to node A, a voltage of -1 [V] to +4 [V] equal to or higher than the threshold voltage -1 [V] of the second driving transistor T3 is applied between the gate terminal and the source terminal of the second driving transistor T3.

[0289] Therefore, unless the PWM data voltage corresponding to the black gray scale is set to node A, when the second driving voltage is applied to the source terminal of the second driving transistor T3 (i.e., a low voltage is applied to the sub-pixel circuit 110 according to the signal Emi_PWM(n)), the second driving transistor T3 is in the off state, and as long as the second driving transistor T3 remains in the off state, the first switching transistor T10 remains in the on state, and thus the inorganic light-emitting element 120 remains lit (in the case where the PWM data voltage corresponding to the black gray scale is set to node A, when the second driving voltage is applied to the source terminal of the second driving transistor T3, the second driving transistor T3 immediately turns on).

[0290] However, when the voltage of node A changes and a voltage equal to or less than the threshold voltage of the second driving transistor T3 - 1 [V] is applied between the gate terminal and the source terminal of the second driving transistor T3, the second driving transistor T3 is turned on, and the second driving voltage is applied to node C, and thus the first switching transistor T10 is turned off. Therefore, a constant current no longer flows through the inorganic light-emitting element 120, and the inorganic light-emitting element 120 stops emitting light.

[0291] Specifically, referring to Figure 18 , when a low voltage is applied to the sub-pixel circuit 110 according to the signal Emi_PWM(n), it can be seen that a sweep voltage is also applied through the signal Sweep(n). In this regard, the sweep voltage can be a voltage linearly decreasing from +15 [V] to +10 [V], but is not limited thereto.

[0292] Since the change in the sweep voltage is coupled to node A through the capacitor C1, the voltage of node A changes according to the change in the sweep voltage.

[0293] When the voltage of node A decreases according to the change in the sweep voltage and becomes a voltage corresponding to the sum of the second driving voltage and the threshold voltage of the second driving transistor T3 (i.e., when a voltage equal to or less than the threshold voltage of the second driving transistor T3 is applied between the gate terminal and the source terminal of the second driving transistor T3), the second driving transistor T3 is turned on.

[0294] Therefore, the second driving voltage as a high voltage is applied to node C through the turned-on first transistor T1, second driving transistor T3, and transistor T5, and thus the first switching transistor T10 is turned off.

[0295] In this way, the PWM circuit 111 can control the light-emitting time of the inorganic light-emitting element 120 based on the voltage set to node A.

[0296] Figure 19It is a diagram showing each operation of the sub-pixel circuit 110 when PWM data voltages corresponding to full white gray scale, middle gray scale, and black gray scale are set to node A.

[0297] Specifically, Figure 19 It shows the change in the voltage of node A according to the change in the sweep voltage according to an embodiment, the on / off change of the second driving transistor T3 according to the change in the voltage of node A, the change in the voltage of node C according to the on / off change of the second driving transistor T3, and the on / off change of the first switching transistor T10 according to the change in the voltage of node C.

[0298] Regarding the case where the PWM data voltage corresponding to the middle gray scale is set to node A, as described above, before the voltage of node A changes according to the sweep voltage and becomes a voltage corresponding to the sum of the second driving voltage VDD_PWM and the threshold voltage Vth of the second driving transistor T3, the second driving transistor T3 remains in the off state, and the voltage Vset is maintained in node C. Therefore, it can be seen that the first switching transistor T10 remains in the on state.

[0299] However, after the voltage of node A continuously changes according to the sweep voltage and becomes a voltage corresponding to the sum of the second driving voltage VDD_PWM and the threshold voltage Vth of the second driving transistor T3, the second driving transistor T3 is turned on and the second driving voltage VDD_PWM is applied to node C. Therefore, it can be seen that the first switching transistor T10 is turned off.

[0300] When the PWM data voltage corresponding to the full white gray scale is set to node A, even if the voltage of node A changes according to the sweep voltage, during the light emission period (specifically, when a low voltage is applied through the signal Emi_PWM(n)), the voltage of node A does not drop below the voltage corresponding to the sum of the second driving voltage VDD_PWM and the threshold voltage Vth of the second driving transistor T3.

[0301] Therefore, when the PWM data voltage corresponding to the full white gray scale is set to node A, the second driving transistor T3 remains in the off state during the entire light emission period. Therefore, the voltage Vset, which is a low voltage, is maintained in node C. Therefore, the first switching transistor T10 remains in the on state.

[0302] When the PWM data voltage corresponding to the black gray scale is set to node A, the voltage of node A starts from a voltage less than or equal to the sum of the second driving voltage VDD_PWM and the threshold voltage Vth of the second driving transistor T3, and has a value less than or equal to the voltage corresponding to the sum of the second driving voltage VDD_PWM and the threshold voltage Vth of the second driving transistor T3 throughout the light emission period.

[0303] Therefore, when the PWM data voltage corresponding to the black gradation is set to node A, the second driving voltage is applied to node C during the entire light emission period, and thus, the first switching transistor T10 remains in the off state during the entire light emission period.

[0304] When the application of the low voltage to the sub-pixel circuit 110 through the signals Emi_PWM(n) and Emi_PAM(n) is completed and the application of the sweep voltage is completed according to the Sweep(n) signal, the corresponding light emission period ends.

[0305] At this time, as Figure 18 shown by reference numeral 18 in the figure, it can be seen that when the light emission period ends (specifically, when the application of the low voltage is completed through the signal Emi_PWM(n)), the sweep voltage is restored to the voltage before the linear change.

[0306] As described above, since the change in the sweep voltage is coupled to node A through the capacitor C1, when the sweep voltage is restored as described above, the voltage of node A that changes linearly according to the sweep voltage is also restored.

[0307] Therefore, according to the embodiment, before the start of the second light emission period as the next light emission period, the voltage of node A that linearly changes according to the sweep voltage during the first light emission period is restored according to the sweep voltage.

[0308] Specifically, the voltage of node A becomes the voltage that is the sum of the PWM data voltage and the threshold voltage Vth of the second driving transistor T3 during the data setting period, linearly changes according to the change in the sweep voltage during the light emission period, and is restored to the voltage that is the sum of the PWM data voltage and the threshold voltage Vth of the second driving transistor T3 when the light emission period ends. Therefore, the same light emission operation is possible in the next light emission period.

[0309] Figure 20 It is a diagram showing the reset operation of node C in the second and subsequent light emission periods among a plurality of light emission periods of one row line.

[0310] According to the embodiment, as described above, a plurality of light emission periods are performed for each row line during one image frame. In this regard, in order for the inorganic light emitting element 120 to emit light during the light emission period, as described above in Figure 17 and 18 it is described, the first switching transistor T10 must first be in the on state.

[0311] However, as referred to above with reference to Figure 18As described above, as the light emission cycle progresses, the second driving voltage is applied to node C, so the first switching transistor T10 is in the off state. Therefore, in order to perform the next light emission cycle, it is necessary to reset the voltage of node C to a low voltage.

[0312] For this purpose, when the next light emission cycle starts, the driver 200 applies a low voltage to the resetter 13 of the PWM circuit 111 through the signal SET(n), as Figure 20 shown.

[0313] Therefore, the Vset voltage is charged in the capacitor C3 through the conducting transistor T14. As described above, since Vset is a low voltage (for example, -3 [V]), when the voltage Vset is charged in the capacitor C3, a low voltage is applied to the gate terminal of the first switching transistor T10 (hereinafter referred to as node C), so the first switching transistor T10 is turned on.

[0314] Thereafter, as referred to Figure 18 above, the driver 200 can control the light emission operation of the inorganic light emitting element 120 during the next light emission cycle.

[0315] As described above, according to the embodiment, during one image frame period, for each row line, the data setting period is performed once, and the light emission period is performed multiple times. Therefore, since the data setting period is not performed in the second and subsequent light emission cycles of a row line, in the Figure 20 timing diagram, different from Figure 17 that, the gate signals VST(n) and SP(n) for data setting are not shown.

[0316] Figure 21 is a diagram showing the gate signals applied to the sub-pixel circuit 110 included in a row line during one frame time according to the embodiment.

[0317] For example, as Figure 21 shown, assuming an embodiment in which nine light emission cycles are performed for a row line, the driver 200 applies the signals VST(n) and SP(n) once for one frame time to perform one data setting period.

[0318] Thereafter, the driver 200 drives the sub-pixel circuit 110 in the first light emission cycle as referred to above Figure 17 and Figure 18 described, and repeatedly drives the sub-pixel circuit 110 in each of the second to ninth light emission cycles as referred to above Figure 20 and Figure 18 described.

[0319] Figure 22 and Figure 23It is a diagram showing the operation of the sub-pixel circuit 110 related to the implementation of black grayscale.

[0320] Referring to Figure 22 the timing diagram, it can be seen that there is a difference between the time when a low voltage starts to be applied to the signal Emi_PWM(n) and the time when a low voltage is applied to the signal Emi_PAM(n). This is the same in the timing diagrams of the gate signals shown in Figures 13 to 18 , Figure 21 and Figure 22 .

[0321] In this way, the difference between the time when a low voltage starts to be applied to the signal Emi_PWM(n) and the time when a low voltage is applied to the signal Emi_PAM(n) lies in the implementation of black grayscale.

[0322] Specifically, when the data voltage corresponding to black grayscale is set to node A, as described above, when a low voltage is applied through the signal Emi_PAM(n) (i.e., when the second driving voltage is applied to the source terminal of the second driving transistor T3), the second driving transistor T3 is immediately turned on.

[0323] Therefore, theoretically, when a low voltage is applied through the signal Emi_PAM(n), the second driving voltage is applied to node C through the turned-on transistor T1, the second driving transistor T3, and the transistor T5. Therefore, the first switching transistor T10 needs to be immediately turned off (when the first switching transistor T10 is immediately turned off, the driving current (i.e., the constant current) does not flow through the inorganic light-emitting element 120 at all, and black grayscale is exhibited).

[0324] However, in reality, as Figure 23 shown, there is a charging time for the second driving voltage VDD_PWM required for node C. Therefore, the first switching transistor T10 is not immediately turned off. Specifically, after the second driving voltage is applied to node C and charging starts, until the voltage capable of turning off the first switching transistor T10 is charged to node C, the first switching transistor T10 remains in the on state. Therefore, a leakage of the constant current occurs in the first switching transistor T10.

[0325] As a result, when the first switching transistor T10 and the inorganic light-emitting element 120 are directly connected without the second switching transistor T15, even if the data voltage corresponding to black grayscale is set to node A, the constant current leaking in the first switching transistor T10 flows through the inorganic light-emitting element 120 for a period of time. Therefore, accurate black grayscale may not be achieved.

[0326] Therefore, according to the embodiment, the second switching transistor T15 can be disposed between the first switching transistor T10 and the inorganic light-emitting element 120. Additionally, the driver 200 can control the second switching transistor T15 to turn on after a predetermined period of time has elapsed since the time when the second driving voltage is applied to the source terminal of the second driving transistor T3. Here, the predetermined period of time can be a period of time that is equal to or greater than the period of time during which the voltage of node C is charged from the voltage Vset to a voltage capable of turning off the first switching transistor T10.

[0327] In this case, even if the data voltage corresponding to the black gradation is set at node A, the leakage current generated when the first switching transistor T10 is not immediately turned off can be blocked by the second switching transistor T15. Therefore, accurate black gradation can be achieved.

[0328] Hereinafter, various embodiments of a method for driving the display panel 100 as shown in Figures 24A to 29 will be described with reference to Figure 3B and Figure 3C .

[0329] Figure 24A FIG. shows the concept of driving the display panel 100 in the same manner during two image frame periods. In each frame of Figure 3B , the vertical axis represents the row lines and the horizontal axis represents time. Figure 24A

[0330] In Figure 24A , VST represents a control signal for the initialization operation of the sub-pixel circuit 110, PWM represents a control signal for setting the PWM data voltage, PAM represents a control signal for setting the constant current generator voltage, and Emission represents a control signal for the light-emitting operation of the inorganic light-emitting element 120 based on the set PWM data voltage and constant current generator voltage.

[0331] In Figure 24A , the "scan" described together with each control signal means that the corresponding control signal is sequentially applied in the order of the row lines.

[0332] Referring to Figure 24A , the driver 200 can drive the display panel 100 such that data voltages (PWM data voltage and constant current generator voltage) are applied to the sub-pixels included in each row line of the display panel 100 in the order of the row lines, and the sub-pixels included in each row line of the display panel 100 emit light in the order of the row lines based on the applied data voltages.

[0333] In this regard, the driver 200 may drive the display panel 100 such that data voltage setting operations for all row lines are performed during the entire image frame period. In this case, since the light emission operation of the inorganic light emitting element 120 is performed in each row line after setting the data voltage, the light emission operation of some row lines may be performed in the next image frame period, as Figure 24A shown.

[0334] Figure 24B is a block diagram of the sub-pixel circuit 110 according to an embodiment, Figure 24C is for driving Figure 24B the timing diagram of various control signals for driving the sub-pixel circuit 110 shown.

[0335] According to an embodiment, the driver 200 may drive the sub-pixel circuit 110 included in each row line as Figure 24C shown, so as to drive the display panel 100 as Figure 24A shown.

[0336] Figure 24D is a diagram showing an image displayed on the display panel 100 when driving the display panel 100 as Figure 24A shown.

[0337] Specifically, Figure 24D shows the light emission operation of the display panel 100 during the X period when a PWM data voltage corresponding to full white gray scale is set in each sub-pixel of the display panel 100.

[0338] Referring to Figure 24D , as described above, it can be seen that the sub-pixels included in each row line of the display panel 100 emit light in sequence according to the order of the row lines.

[0339] Figure 25A shows the concept of driving the display panel 100 in two image frames in the same manner as Figure 3C . In each frame of Figure 25A , the vertical axis represents the row lines and the horizontal axis represents time.

[0340] In Figure 25A , different from the driving method shown in Figure 24A , it can be seen that the control signal VST and the control signal PAM are not applied to the display panel 100 in sequence according to the order of the row lines, but are applied jointly and simultaneously. Therefore, the expression "scanning" is not described either.

[0341] That is to say, according to the driving method shown in Figure 25A , the initialization operation and the constant current generator voltage setting operation are performed jointly and simultaneously in all sub-pixel circuits 110 of the display panel 100.

[0342] Similar toFigure 24A As shown, the PWM data voltage setting operation and the light emitting operation are sequentially performed in the order of the row lines. Therefore, in Figure 25A the example shown, the driver 200 can drive the display panel 100 such that the PWM data voltage is applied to the sub-pixels included in each row line of the display panel 100 in the order of the row lines, and the sub-pixels included in each row line of the display panel 100 emit light in the order of the row lines based on the applied data voltage.

[0343] In this regard, the driver 200 can drive the display panel 100 such that the data voltage setting operation and the light emitting operation for all row lines are completed during one image frame time. In this case, as Figure 25A shown, the light emitting operations for all row lines are completed within the corresponding image frame time.

[0344] Figure 25B is a block diagram of the sub-pixel circuit 110 according to an embodiment, Figure 25C is for driving Figure 25B the various control signals for the sub-pixel circuit 110 shown in

[0345] Referring to Figure 25B and Figure 25C , different from Figure 24B and Figure 24C , it can be seen that the signal VST and the signal CCG_Scan are globally input. As Figure 25C shown, the driver 200 can drive the display panel 100 shown in Figure 25A by driving the sub-pixel circuits 110 included in each row line.

[0346] Figure 25D is a diagram showing an image displayed on the display panel 100 when driving the display panel 100 as Figure 25A shown.

[0347] Specifically, Figure 25D shows the light emitting operation of the display panel 100 during the X period when the PWM data voltage corresponding to the full white gray level is set to each sub-pixel of the display panel 100.

[0348] Referring to Figure 25D , as described above, it can be seen that the sub-pixels included in each row line of the display panel 100 emit light in sequence in the order of the row lines. However, in Figure 25A the case of the driving method shown, since the light emitting operations for all row lines are completed within the corresponding image frame time, different from Figure 24D , the light emitting operation based on the data voltage applied in one image frame period does not extend to the next image frame period.

[0349] Referring to Figure 24BAnd Figure 25B , the sub-pixel circuit 110 includes a sweep gating transistor Tr, and it can be seen that while the sweep gating transistor is turned on according to the control signal Emi(n), a PWM sweep signal is applied to the PWM circuit 111.

[0350] At this time, as Figure 24C and Figure 25C shown, the PWM sweep signal (PWM sweep) is a periodic signal, in which a sweep voltage linearly varying between two voltages is repeated in the periodic signal.

[0351] Therefore, according to the embodiment, when the sweep gating transistor is turned on according to the signal Emi(n), a plurality of consecutive sweep voltages gated in the PWM sweep signal are applied to the PWM circuit 111. Figure 26 This sweep gating operation is shown.

[0352] According to an embodiment of the present disclosure, since during the light emission period of each row line (i.e., when a low voltage is applied through the signal Emi(n)), each sweep voltage performs a light emission operation of the inorganic light emitting element 120 based on the data voltage, it can be seen that the inorganic light emitting elements 120 included in the corresponding row line emit light multiple times.

[0353] Figure 27A And Figure 27B are detailed circuit diagrams of the sub-pixel circuit 110 according to various embodiments.

[0354] The above-mentioned sweep gating method can be implemented by designing a gating circuit inside the sub-pixel circuit 110, or can be implemented to receive a sweep signal gated by an externally separated sweep gate driver circuit.

[0355] Figure 27A Shows an embodiment of the sub-pixel circuit 110 including a sweep gating circuit, and Figure 27B shows an embodiment of the sub-pixel circuit 110 configured to receive a sweep signal gated according to the light emission period from a sweep gate driver.

[0356] When a plurality of display modules 300 are combined to implement a large display device, image distortion may problematically occur at the boundary portion between the upper display module and the lower display module.

[0357] Figure 28A Is a diagram showing image distortion occurring at the boundary portion between the upper display module and the lower display module and its solution method in the driving method of Figure 24A .

[0358] As Figure 28A shown on the left side of Figure 28AWhen driving the upper display module and the lower display module 300 as shown, image distortion may occur at the boundary portion of the modules.

[0359] Therefore, according to an embodiment, as Figure 28A shown on the right side, the driver 200 drives the lower display module 300 by reversing the scanning direction of the lower display module 300, thereby preventing the image distortion phenomenon occurring at the boundary portion of the modules.

[0360] In this regard, the scanning direction can also be reversed by changing the driving order of the row lines (specifically, by driving the gate driver in reverse). Therefore, for example, when the display module 300 includes 270 row lines, the driver 200 drives the upper display module 300 sequentially from the first row line to the 270th row line, and drives the lower display module 300 sequentially from the 270th row line to the first row line, thereby preventing the image distortion phenomenon occurring at the boundary portion of the modules.

[0361] Since the same row lines are driven simultaneously at the boundary portion between the left display module and the right display module, image distortion does not occur.

[0362] Figure 28B is a diagram showing image distortion occurring at the boundary portion between the upper display module and the lower display module in the driving method of Figure 25A and its solution. Since the principle is the same as that of Figure 28A , redundant descriptions are omitted.

[0363] Figure 29 is a diagram showing a method of driving the display panel 100 using multiple sweep signals according to an embodiment.

[0364] According to an embodiment, as described above, instead of using a single sweep signal (PWMSweep) through gating in all sub-pixel circuits, multiple sweep signals having a time difference in the linearly varying period are gated and used. Figure 29 shows an example of using five sweep signals having a time difference in the linearly varying period.

[0365] Figure 30A is a cross-sectional view of a display module according to an embodiment. In Figure 30A , for ease of explanation, only one pixel included in the display module 300 is shown.

[0366] According to ​ , the display module 300 includes a glass substrate 80, a TFT layer 70, and inorganic light-emitting elements R 120-R, G 120-G, and B 120-B. In this regard, the above-mentioned sub-pixel circuit 110 is implemented as a thin-film transistor (TFT) and can be included in the TFT layer 70 above the glass substrate 80.

[0367] Each of the inorganic light-emitting elements R 120-R, G 120-G, and B 120-B is mounted in the TFT layer 70 so as to be electrically connected to the corresponding sub-pixel circuit 110 to construct the above-described sub-pixel.

[0368] Although not shown in the drawings, for each of the inorganic light-emitting elements 120-R, 120-G, and 120-B, there is a sub-pixel circuit 110 in the TFT layer 70 that supplies a driving current to the inorganic light-emitting elements 120-R, 120-G, and 120-B, and each of the inorganic light-emitting elements 120-R, 120-G, and 120-B can be mounted or disposed in the TFT layer 70 to be electrically connected to the corresponding sub-pixel circuit 110.

[0369] ​ Examples are shown in which the inorganic light-emitting elements R 120-R, G 120-G, and B 120-B are flip-chip type micro LEDs. However, the embodiments are not limited thereto, and the inorganic light-emitting elements R 120-R, G 120-G, and B 120-B may be horizontal or vertical type micro LEDs according to the embodiments.

[0370] ​ is a cross-sectional view of a display module according to another embodiment of the present disclosure.

[0371] Referring to ​ , the display module 300 includes a TFT layer 70 formed on one surface of a glass substrate 80, inorganic light-emitting elements R 120-R, G 120-G, and B 120-B mounted on the TFT layer 70, a driver 200, and connection wirings 90 for electrically connecting the sub-pixel circuit 110 formed in the TFT layer 70 and the driver 200.

[0372] As described above in ​ , according to an embodiment, at least some of the various circuits of the driver 200 may be implemented in the form of a separate chip to be disposed on the rear surface of the glass substrate 80, and may be connected to the sub-pixel circuit 110 formed in the TFT layer 70 through the connection wirings 90.

[0373] In this regard, referring to ​ , it can be seen that the sub-pixel circuit 110 included in the TFT layer 70 can be electrically connected to the driver 200 through the connection wirings 90 formed at the edge (or side surface) of the TFT panel (hereinafter, the TFT layer 70 and the glass substrate 80 are collectively referred to as the TFT panel).

[0374] In this way, the reason for forming the connection wiring 90 in the edge region of the display panel 100 and connecting the sub-pixel circuit 110 included in the TFT layer 70 and the driver 200 is that when forming holes penetrating the glass substrate 80 to connect the sub-pixel circuit 110 and the driver 200, there may be problems such as cracks occurring in the glass substrate 80 due to the temperature difference between the manufacturing process of the TFT panel 70 and 80 and the process of filling the holes with a conductive material.

[0375] As described above in ​ According to another embodiment, at least some of the various circuits of the driver 200 may be formed together with the sub-pixel circuits in the TFT layer formed in the display panel 100 and connected to the sub-pixel circuits. ​ This embodiment is shown.

[0376] ​ is a plan view of the TFT layer 70 according to an embodiment. Referring to ​ it can be seen that in the TFT layer 70, in addition to the region occupied by one pixel 10 (in this region, there are sub-pixel circuits 110 corresponding to the R, G, and B sub-pixels included in the pixel 10), there is also the remaining region 11.

[0377] As described above, since the remaining region 11 exists in the TFT layer 70, some of the various circuits of the driver 200 described above can be formed in the remaining region 11.

[0378] ​ An example of implementing the gate driver circuit 230 in the remaining region 11 of the TFT layer 70 is shown. In this way, the structure in which the gate driver circuit 230 is formed in the TFT layer 70 can be called a gate in panel (GIP) structure, but the name is not limited to this.

[0379] ​ This is only an example, and the circuits that can be included in the remaining region 11 of the TFT layer 70 are not limited to the gate driver circuit 230. According to an embodiment, the TFT layer 70 may further include a MUX circuit for selecting R, G, and B sub-pixels, an electrostatic discharge (ESD) protection circuit for protecting the sub-pixel circuit 110 from static electricity, a sweep voltage providing circuit, etc.

[0380] ​ is a diagram showing the GIP structure according to various embodiments.

[0381] ​ Shows the formation in the TFT layer 70 for providing ​An example of a gate driver for various gate signals shown. As shown, in the case where the display panel 100 includes 270 row lines, 542 gate driver circuits for three gate signals VST(n), CCG_Scan(n), and PWM_Scan(n) related to data setting and 270 gate driver circuits for a gate signal Emi(n) related to a light-emitting operation can be formed or provided on the TFT layer 70.

[0382] At this time, the reason for requiring 542 gate driver circuits to generate three gate signals related to data setting is that, as ​ shown, the signal PWM_Scan(n) is used as the signal VST(n) for the next row line, and two additional gate drivers are required to generate the signal VST(1) and the last reset signal.

[0383] ​ An example of a gate driver for various gate signals shown is formed in the TFT layer 70 to provide ​ An example of a gate driver for various gate signals shown. In the ​ case of the driving method shown, as described above, the signal VST and the signal CCG_scan are global inputs.

[0384] Therefore, as shown, in the case where the display panel 100 includes 270 row lines, 271 gate driver circuits (including one gate driver circuit for generating the last reset signal) for generating a gate signal PWM_Scan(n) related to PWM data setting and 270 gate driver circuits for a gate signal Emi(n) related to a light-emitting operation can be formed or provided in the TFT layer 70.

[0385] ​ An example of a gate driver for various gate signals shown is formed in the TFT layer 70 to provide ​ An example of a gate driver for various gate signals shown.

[0386] According to an embodiment, as ​ shown, gate driver circuits for gate signals VST(n) and SP(n) related to data setting operations and gate driver circuits for gate signals Emi_PWM(n), SET(n), Emi_PAM(n), and Sweep(n) related to light-emitting operations can be formed or provided in the TFT layer 70.

[0387] Referring to ​ , it can be seen that the same gate driver circuits are sequentially provided in a left-right symmetric manner. This is called double feeding, and through this double feeding, the RC delay value generated when the gate signal is sent to each area of the display panel 100 can be minimized, and the uniformity of the RC delay in each area can be increased.

[0388] The number of the above-described gate driver circuits is merely an example, and the implementation example is not limited to the above number. That is, depending on how the gate driver circuit is designed or how the gate signals output from the gate driver circuit are connected between the row lines, different implementations are possible.

[0389] ​ is a configuration diagram of the display device 1000 according to an embodiment.

[0390] Referring to ​ , the display device 1000 includes a display panel 100, a driver 200, and a processor 900.

[0391] The display panel 100 includes a plurality of pixels, and each pixel includes a plurality of sub-pixels.

[0392] Specifically, the display panel 100 may be formed in a matrix form such that gate lines G1 to Gx and data lines D1 to Dy cross each other, and each pixel may be formed in an area provided at the intersection.

[0393] At this time, each pixel may include three sub-pixels (such as R, G, and B), and as described above, each sub-pixel included in the display panel 100 may include an inorganic light-emitting element 120 and a sub-pixel circuit 110 of a corresponding color.

[0394] Here, the data lines D1 to Dy are lines for applying a data voltage (specifically, a PWM data voltage) to each sub-pixel included in the display panel 100, and the gate lines G1 to Gx are lines for selecting pixels (or sub-pixels) included in the display panel 100 for each line. Therefore, the data voltage applied through the data lines D1 to Dy may be applied to the pixels (or sub-pixels) of the selected row line through a gate signal.

[0395] In this regard, according to an embodiment, the data voltage to be applied to the pixels connected to each data line may be applied to each of the data lines D1 to Dy. At this time, since one pixel includes a plurality of sub-pixels (for example, R, G, and B sub-pixels), the data voltages to be respectively applied to the R, G, and B sub-pixels included in one pixel (that is, the R data voltage, the G data voltage, and the B data voltage) may be time-division multiplexed and applied to the respective sub-pixels through one data line. The data voltage time-division multiplexed and applied through one data line as described above may be applied to the respective sub-pixels through a MUX circuit.

[0396] According to an embodiment, separate data lines may be provided for each of the R, G, and B sub-pixels. In this case, the R data voltage, G data voltage, and B data voltage do not need to be time-division multiplexed and applied, and the corresponding data voltages can be simultaneously applied to the corresponding sub-pixels through each data line.

[0397] In ​ for ease of explanation, only one set of gate lines (such as G1 to Gx) is shown. However, the actual number of gate lines may vary according to the driving method of the sub-pixel circuit 110 included in the display panel 100. For example, as ​ shown, six gate lines VST, SP, Emi_PWM, Emi_PAM, Sweep, and SET may be provided for one row line.

[0398] The driver 200 drives the display panel 100 under the control of the processor 900 and may include a timing controller 210, a data driver 220, a scan driver 230, and the like.

[0399] The timing controller 210 may receive an input signal IS, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a main clock signal MCLK from the outside, generate an image data signal, a scan control signal, a data control signal, a light emission control signal, etc., and provide them to the display panel 100, the source driver 220, the gate driver 230, and the like.

[0400] In addition, the timing controller 210 may apply a control signal (i.e., a MUX signal) for selecting each of the R, G, and B sub-pixels to a MUX circuit (not shown). Therefore, a plurality of sub-pixels included in the pixels of the display panel 100 can be selected through the MUX circuit (not shown).

[0401] The data driver 220 (or source driver) is a means for generating a data signal (specifically, a PWM data voltage), and generates a data signal by receiving the R / G / B component image data from the processor 900. In addition, the data driver 220 may apply the generated data signal to each sub-pixel circuit 110 of the display panel 100 through the data lines D1 to Dy.

[0402] The gate driver 230 (or scan driver) may select pixels arranged in a matrix in units of row lines to generate various gate signals (e.g., VST, SP, Emi_PWM, Emi_PAM, Sweep, SET, etc.) for driving the selected pixels, and apply the generated gate signals to the display panel 100 through the gate lines G1 to Gx. Specifically, according to an embodiment of the present disclosure, the gate driver 230 may sequentially apply the generated gate signals in the order of the row lines.

[0403] Although not shown in the drawings, the driver 200 may further include a driving voltage providing circuit for providing various driving voltages (e.g., a first driving voltage VDD_PAM, a second driving voltage VDD_PWM, a ground voltage VSS, a reset voltage Vset, a test voltage TEST, a constant current generator voltage VPAM_R / G / B, etc.) to the sub-pixel circuits 110 included in the display panel 100, a clock signal providing circuit for providing a clock signal to the gate driver circuit 230 or the data driver circuit 220, a MUX circuit, a sweep voltage providing circuit, an ESD protection circuit, and the like.

[0404] The processor 900 controls the overall operation of the display device 1000. Specifically, the processor 900 may drive the display panel 100 by controlling the driver 200.

[0405] To this end, the processor 900 may be implemented as at least one of a central processing unit (CPU), a microcontroller, an application processor (AP), a communication processor (CP), or an ARM processor.

[0406] In ​ the processor 900 and the timing controller 210 are described as separate components, but according to an embodiment, there may be an embodiment in which only one of the two components is included in the display device 1000 and the included component even performs the function of the other component.

[0407] ​ is a flowchart of a driving method of the display module 300 according to an embodiment.

[0408] Here, the display module 300 may include a display panel 100, in which a plurality of pixels are disposed on a plurality of row lines, and each pixel includes a plurality of sub-pixels.

[0409] In this regard, as ​ shown, the display module 300 may apply a PWM data voltage to the sub-pixels included in each row line of the display panel 100 in the order of the row lines, and drive the display panel 100 such that the sub-pixels included in at least some consecutive row lines among the plurality of row lines emit light for a time corresponding to the applied PWM data voltage (S3300).

[0410] Specifically, the display module 300 may apply a PWM data voltage to the sub-pixels included in each row line during the data setting period of each row line, and drive the display panel 100 such that the sub-pixels included in the at least some consecutive row lines emit light for a time corresponding to the applied PWM data voltage during a plurality of light emitting periods of each row line.

[0411] Here, a first light emission period among a plurality of light emission periods is temporally continuous with a data setting period, and each of the plurality of light emission periods may have a predetermined time interval.

[0412] Multiple row lines of the display panel 100 may be divided into a plurality of groups, and each group includes consecutive row lines. In this regard, the display module 300 may apply a first PWM data voltage to sub-pixels included in each row line in order from a first row line to a last row line among the multiple row lines during a first image frame period, and drive the display panel 100 such that during the first image frame period, sub-pixels included in one group among the plurality of groups emit light in order of the row lines, and then sub-pixels included in each of at least two consecutive groups emit light in order of the row lines based on the applied first PWM data voltage. At this time, the at least two consecutive groups include the one group.

[0413] In addition, the display module 300 may apply a second PWM data voltage to sub-pixels included in each row line in order from a first row line to a last row line among the multiple row lines during a second image frame period preceding the first image frame period, and drive the display panel 100 such that during the first image frame period, sub-pixels included in each of the remaining groups among the plurality of groups other than at least one group driven based on the first PWM data voltage emit light in order of the row lines based on the second PWM data voltage.

[0414] In addition, the display module 300 may drive the display panel 100 such that during the first image frame period, sub-pixels in each row line included in each of the plurality of groups emit light multiple times in a plurality of light emission periods of each row line based on at least one of the first PWM data voltage or the second PWM data voltage.

[0415] According to various embodiments, it is possible to prevent the wavelength of light emitted by the inorganic light emitting element from changing according to the gray scale.

[0416] In addition, it is possible to easily correct spots or colors that may appear in an image displayed on the display panel due to deviations between sub-pixel circuits. Specifically, even when a module-type display panel is combined to form a large-area display panel, it is possible to more easily correct brightness or color differences between display panel modules.

[0417] In addition, a more optimized driving circuit can be designed, and the inorganic light emitting element can be stably and effectively driven. Specifically, the power consumption of an image displayed on the display panel can be reduced.

[0418] In addition, it can contribute to the miniaturization and weight reduction of the display panel.

[0419] In the above, an example in which the sub-pixel circuit 110 is implemented as a P-type TFT is shown, but the above various embodiments can be applied to an N-type TFT.

[0420] In addition, in various embodiments, the TFTs constituting the TFT layer (or TFT panel) are not limited to a specific structure or type. That is to say, the TFTs cited in various examples of the present disclosure are low-temperature polycrystalline silicon (LTPS) TFTs, and can also be implemented as oxide TFTs, polycrystalline silicon or single-crystalline silicon (a-silicon) TFTs, organic TFTs, graphene TFTs, etc., and P-type (or N-type) MOSFETs can be manufactured and applied only in the Si wafer CMOS process.

[0421] In addition, examples of implementing the sub-pixel circuit 110 using the TFT layer are described above. However, the embodiments are not limited thereto. That is to say, according to another embodiment of the present disclosure, the sub-pixel circuit 110 can be implemented in the form of a micro IC without using the TFT layer. In this regard, the micro IC can be implemented in the sub-pixel unit or the pixel unit, and can be mounted on the substrate together with the inorganic light-emitting element 120. In addition, the position where the micro IC is mounted can be, for example, around the corresponding inorganic light-emitting element 120, but is not limited thereto.

[0422] Various embodiments of the present disclosure can be implemented as software including instructions stored in a machine-readable storage medium (e.g., a computer). A machine is a device capable of calling the stored instructions from the storage medium and operating according to the called instructions, and can include an electronic device (e.g., the display device 1000) according to the embodiment.

[0423] When a command is executed by a processor, the processor can directly or by using other components under the control of the processor execute the function corresponding to the command. The command can include code generated or executed by a compiler or an interpreter. The machine-readable storage medium can be provided in the form of a non-transitory storage medium. Here, "non-transitory" only means that the storage medium does not include signals and is tangible, but does not distinguish between semi-permanent storage or temporary storage of data in the storage medium.

[0424] According to an embodiment, a method according to various embodiments can be provided by being included in a computer program product. The computer program product can be traded between a seller and a buyer as a commodity. The computer program product can be released in the form of a machine-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)) or can be released online through an application store (e.g., PlayStoreTM). In the case of online release, at least a part of the computer program product can be temporarily stored or temporarily generated in a storage medium (such as the memory of a manufacturer's server, an application store's server, or a forwarding server).

[0425] Each element (e.g., module or program) in the elements according to various embodiments may include a single entity or multiple entities, and some of the above sub-elements are omitted, or other sub-elements may also be included in various embodiments. Optionally or additionally, some elements (e.g., modules or programs) may be integrated into a single entity to perform the functions performed by each corresponding element before integration identically or similarly. The operations performed by modules, programs, or other elements according to various embodiments may be executed sequentially, in parallel, repeatedly, or heuristically, or at least some operations may be executed in a different order or omitted, or other operations may be added.

[0426] The above description is only for explaining the technical concept of the present disclosure, and those of ordinary skill in the art to which the present disclosure pertains will be able to make various modifications and variations without departing from the basic features of the present disclosure. In addition, the example embodiments discussed in the present disclosure are not intended to limit but to explain the technical concept of the present disclosure, and the scope of the technical concept of the present disclosure is not limited by these embodiments. Therefore, the protection scope of the present disclosure should be interpreted by the claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included within the scope of the present disclosure.

Claims

1. A display module, comprising: A display panel including a plurality of pixels, wherein each pixel includes a plurality of sub-pixels, and the plurality of pixels are disposed on a plurality of row lines of the display panel; and A driver configured to: Apply a pulse width modulation (PWM) data voltage to the sub-pixels in each of the row lines included in the row lines of the display panel in the order of the row lines; and Drive the display panel such that the sub-pixels in at least two consecutive row lines among the plurality of row lines emit light for a time corresponding to the applied PWM data voltage in the order of the row lines, Wherein each of the plurality of sub-pixels includes an inorganic light-emitting element and a sub-pixel circuit, Wherein the sub-pixel circuit includes: a constant current generator circuit configured to provide a constant current to the inorganic light-emitting element based on an applied constant current generator voltage, Wherein the constant current generator circuit includes a first driving transistor, and based on the application of the constant current generator voltage, the constant current generator circuit is configured to apply a first voltage based on the applied constant current generator voltage and the threshold voltage of the first driving transistor to the gate terminal of the first driving transistor, Wherein the constant current generator circuit further includes: A first transistor connected between the drain terminal and the gate terminal of the first driving transistor; and A second transistor including a drain terminal connected to the source terminal of the first driving transistor and a gate terminal connected to the gate terminal of the first transistor, and Wherein during a state in which the constant current generator voltage is applied through the source terminal of the second transistor when the first transistor and the second transistor are turned on, the constant current generator circuit is further configured to: apply the first voltage to the gate terminal of the first driving transistor through the turned-on first driving transistor.

2. The display module according to claim 1, wherein, The driver is further configured to: During a data setting period for each of the row lines, apply the PWM data voltage to the sub-pixels in each of the row lines included in the row lines; And Drive the display panel such that the sub-pixels in each of the at least two consecutive row lines emit light for a time corresponding to the applied PWM data voltage during a plurality of light-emitting periods for each of the row lines.

3. The display module according to claim 2, wherein, A first light-emitting period among the plurality of light-emitting periods is continuous in time with the data setting period, and Wherein each of the plurality of light-emitting periods has a predetermined time interval.

4. The display module according to claim 2, wherein, The plurality of row lines are divided into a plurality of groups, each group including consecutive row lines, Wherein the driver is further configured to: During a second image frame period, apply a second PWM data voltage to the sub-pixels in each of the row lines included in the row lines from a first row line to a last row line among the plurality of row lines in the order of the row lines; and Drive the display panel such that during the second image frame period, the sub-pixels included in the first group among the multiple groups emit light in the order of the row lines, and then the sub-pixels included in each of the multiple consecutive groups emit light in the order of the row lines based on the applied second PWM data voltage, and wherein the multiple consecutive groups include the first group.

5. The display module according to claim 4, wherein, The driver is further configured to: During a first image frame period before the second image frame period, apply a first PWM data voltage to the sub-pixels included in each of the row lines among the multiple row lines in the order of the row lines from the first row line to the last row line; And Drive the display panel such that during the second image frame period, except for at least one group driven based on the second PWM data voltage among the multiple groups, the sub-pixels included in each of the multiple groups emit light in the order of the row lines based on the first PWM data voltage.

6. The display module according to claim 5, wherein, The driver is further configured to: drive the display panel such that during the second image frame period, the sub-pixels included in each row line among the row lines of each of the multiple groups emit light multiple times during the multiple light emission periods for each row line among the row lines based on one or more of the first PWM data voltage and the second PWM data voltage.

7. The display module according to claim 2, wherein, The sub-pixel circuit is configured to control the light emission time of the inorganic light emitting element during each of the multiple light emission periods according to the driving of the driver, and wherein the sub-pixel circuit further includes: A PWM circuit configured to provide a constant current to the inorganic light emitting element for a time corresponding to the applied PWM data voltage.

8. The display module according to claim 7, wherein, The PWM circuit includes a second driving transistor, and based on the application of the PWM data voltage, the PWM circuit is configured to apply a second voltage based on the applied PWM data voltage and the threshold voltage of the second driving transistor to the gate terminal of the second driving transistor.

9. The display module according to claim 8, wherein, The PWM circuit further includes: A third transistor connected between the drain terminal and the gate terminal of the second driving transistor; and A fourth transistor having a drain terminal connected to the source terminal of the second driving transistor and a gate terminal connected to the gate terminal of the third transistor, and wherein during a state in which the PWM data voltage is applied through the source terminal of the fourth transistor when the third transistor and the fourth transistor are turned on, the PWM circuit is further configured to: apply the second voltage to the gate terminal of the second driving transistor through the turned-on second driving transistor.

10. The display module according to claim 8, wherein, The constant current generator circuit is further configured to: provide the constant current to the inorganic light emitting element, the constant current having an amplitude based on a first driving voltage applied to the source terminal of the first driving transistor and the first voltage applied to the gate terminal of the first driving transistor.

11. The display module according to claim 8, wherein, The sub-pixel circuit further includes: a first switching transistor having a gate terminal connected to the drain terminal of the second driving transistor and a source terminal connected to the drain terminal of the first driving transistor, wherein the constant current generator circuit is further configured to: during a state in which a first driving voltage is applied to the source terminal of the first switching transistor through the first driving transistor, supply the constant current to the inorganic light-emitting element through the turned-on first switching transistor, and wherein the PWM circuit is further configured to: during a state in which the second driving transistor is turned on based on the second voltage applied to the gate terminal of the second driving transistor and the second driving voltage applied to the source terminal of the second driving transistor, apply the second driving voltage to the gate terminal of the first switching transistor to turn off the first switching transistor.

12. The display module according to claim 11, wherein, The second driving transistor is configured to be turned on once the second voltage applied to the gate terminal of the second driving transistor changes according to the sweep voltage applied to the PWM circuit and the voltage between the gate terminal and the source terminal of the second driving transistor becomes the threshold voltage of the second driving transistor.

13. The display module according to claim 11, wherein, The sub-pixel circuit further includes: a second switching transistor having a source terminal connected to the drain terminal of the first switching transistor and a drain terminal connected to the anode terminal of the inorganic light-emitting element, and wherein the second switching transistor is configured to be turned on once a predetermined time has elapsed since the second driving voltage was applied to the source terminal of the second driving transistor.

14. The display module according to claim 11, wherein, The PWM circuit further includes: a resetter configured to turn on the first switching transistor before the first driving voltage is applied to the source terminal of the first switching transistor through the first driving transistor.

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