Display substrate and crack detection method thereof, and display device

Abstract

A display substrate and a crack detection method and a display device thereof. The display substrate comprises: a base substrate (1), comprising a display area (1A) and a peripheral area (1B) surrounding the display area (1A); a first crack detection line (2), located in the peripheral area (1B) and surrounding the display area (1A); a second crack detection line (3), located in the peripheral area (1B) and surrounding the display area (1A); at least one first electrostatic discharge circuit (4), located in the peripheral area (1B), each first electrostatic discharge circuit (4) comprising at least one first thin film transistor (40), the at least one first thin film transistor (40) comprising a first gate (41); and at least one second electrostatic discharge circuit (5), located in the peripheral area (1B) and electrically connected to the second crack detection line (3), each second electrostatic discharge circuit (5) comprising at least one second thin film transistor (50), the at least one second thin film transistor (50) comprising a second gate (51), wherein the second gate (51) and the first gate (41) are electrically connected.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a crack detection method thereof, and a display device. Background Art

[0002] With the continuous improvement of OLED (Organic Light-Emitting Diode) technology, higher requirements are placed on the reliability of OLED product screens. GDS (Gate Data Shot) defects caused by film cracks are one of the main defects of OLED products. Summary of the invention

[0003] According to some embodiments of the present disclosure, there is provided a display substrate, including:

[0004] A substrate, comprising a display area and a peripheral area surrounding the display area;

[0005] A first crack detection line, located in the peripheral area and surrounding the display area;

[0006] a second crack detection line located in the peripheral area and surrounding the display area;

[0007] at least one first electrostatic discharge circuit located in the peripheral area, each first electrostatic discharge circuit comprising at least one first thin film transistor, and the at least one first thin film transistor comprising a first gate; and

[0008] At least one second electrostatic release circuit is located in the peripheral area and electrically connected to the second crack detection line, each second electrostatic release circuit includes at least one second thin film transistor, and the at least one second thin film transistor includes a second gate, wherein the second gate is electrically connected to the first gate.

[0009] In some embodiments, the display area further includes:

[0010] A plurality of sub-pixels located in the display area, including test sub-pixels and non-test sub-pixels; and

[0011] The unit test circuit is located in the peripheral area and is electrically connected to the plurality of sub-pixels, the first crack detection line and the second crack detection line respectively.

[0012] In some embodiments, the first crack detection line includes a first end and a second end, the first end of the first crack detection line is configured to input a first electrical signal detection signal, the second end is configured to output a second electrical signal detection signal, and the at least one first electrostatic release circuit is electrically insulated from the first crack detection line.

[0013] In some embodiments, the unit test circuit includes at least one test thin film transistor, each test thin film transistor includes a source, a drain and a gate, the at least one test thin film transistor includes a first group of test thin film transistors, and the source or drain of the first group of test thin film transistors is electrically connected to the test sub-pixel;

[0014] The second crack detection line includes a first end and a second end, the first end of the second crack detection line is configured to input a bright line detection signal, and the second end is electrically connected to a drain or a source of the first group of test thin film transistors.

[0015] In some embodiments, the at least one test thin film transistor further includes a second group of test thin film transistors, and sources or drains of the second group of test thin film transistors are electrically connected to the non-test sub-pixels.

[0016] In some embodiments, the at least one test thin film transistor is a P-type thin film transistor.

[0017] In some embodiments, at least a portion of the second crack detection line surrounds at least a portion of the first crack detection line.

[0018] In some embodiments, the first crack detection line includes a first crack detection line section and a second crack detection line section that are mirror-symmetrical, and the second crack detection line includes a first crack detection line section and a second crack detection line section that are mirror-symmetrical.

[0019] In some embodiments, the display substrate further includes: a common electrode located in the peripheral area and surrounding the display area, wherein the second gate and the first gate are electrically connected to the common electrode respectively.

[0020] In some embodiments, the first gate and the second gate are an integral structure.

[0021] In some embodiments, the at least one first thin film transistor includes an active layer, a first gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, and the source and the drain of the at least one first thin film transistor are electrically insulated from the crack detection line; the at least one second thin film transistor includes an active layer, a second gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, and the source and the drain of the at least one second thin film transistor are electrically connected to the crack detection line.

[0022] In some embodiments, the first electrostatic discharge circuit and the second electrostatic discharge circuit are respectively located on two sides of the unit test circuit and are mirror-symmetrical.

[0023] In some embodiments, the display area includes a first boundary, a second boundary, a third boundary and a fourth boundary; the peripheral area includes a first peripheral region located outside the first boundary, a second peripheral region located outside the second boundary, a third peripheral region located outside the third boundary and a fourth peripheral region located outside the fourth boundary; the common electrode includes a first part located in the first peripheral region and a second part located in the second peripheral region, the third peripheral region and the fourth peripheral region, and the first gate of the at least one first thin film transistor and the second gate of the at least one second thin film transistor are electrically connected to the first part of the common electrode, respectively.

[0024] In some embodiments, at least a portion of the second crack detection line located in the first peripheral region is located in the same layer and made of the same material as the source and drain of the at least one second thin film transistor, and at least a portion of the second crack detection line located in the second peripheral region, the third peripheral region, and the fourth peripheral region is located in the same layer and made of the same material as the gate of the at least one second thin film transistor.

[0025] In some embodiments, a portion of the first crack detection line or the second crack detection line located in the first peripheral region is U-shaped or L-shaped, and a bent portion of the U-shape or L-shape has a cut angle.

[0026] In some embodiments, the source and drain of the at least one first thin film transistor are short-circuited by a metal layer, and the source and drain of the at least one first thin film transistor are located in the same layer as the metal layer and are made of the same material;

[0027] The source and drain of the at least one second thin film transistor are short-circuited by a metal layer, and the source and drain of the at least one second thin film transistor are located in the same layer as the metal layer and are made of the same material.

[0028] According to some other embodiments of the present disclosure, a method for detecting cracks in a display substrate is provided, the display substrate comprising:

[0029] A substrate, comprising a display area and a peripheral area surrounding the display area;

[0030] a first crack detection line, located in the peripheral area and surrounding the display area, the first crack detection line comprising a first end and a second end;

[0031] a second crack detection line located in the peripheral area and surrounding the display area;

[0032] at least one first electrostatic discharge circuit, located in the peripheral area and electrically insulated from the first crack detection line, each first electrostatic discharge circuit comprising at least one first thin film transistor, the at least one first thin film transistor comprising a first gate; and

[0033] at least one second electrostatic discharge circuit, located in the peripheral area and electrically connected to the second crack detection line, each second electrostatic discharge circuit includes at least one second thin film transistor, the at least one second thin film transistor includes a second gate, wherein the second gate is electrically connected to the first gate,

[0034] The crack detection method comprises:

[0035] Inputting a first electrical signal detection signal to a first end portion of the first crack detection line;

[0036] receiving a second electrical signal detection signal from a second end of the first crack detection line; and

[0037] Whether there is a crack in the display substrate is determined according to the first electrical signal detection signal and the second electrical signal detection signal.

[0038] In some embodiments, judging whether there is a crack in the display substrate according to the first electrical signal detection signal and the second electrical signal detection signal includes:

[0039] determining a resistance value between a first end of the first crack detection line and a second end of the first crack detection line according to the first electrical signal detection signal and the second electrical signal detection signal; and

[0040] According to the comparison result between the resistance value and the resistance threshold, it is determined whether there is a crack in the display substrate.

[0041] In some embodiments, the crack detection method further includes disconnecting the electrical connection between the at least one first electrostatic discharge circuit and the first crack detection line.

[0042] In some embodiments, the display substrate further comprises:

[0043] A plurality of sub-pixels located in the display area, including test sub-pixels and non-test sub-pixels; and

[0044] a unit test circuit, located in the peripheral area and electrically connected to the plurality of sub-pixels, the first crack detection line and the second crack detection line, respectively, the unit test circuit comprising at least one test thin film transistor, each test thin film transistor comprising a source, a drain and a gate, the at least one test thin film transistor comprising a first group of test thin film transistors, a source or a drain of the first group of test thin film transistors being electrically connected to the test sub-pixel;

[0045] The second crack detection line includes a first end and a second end, the first end of the second crack detection line is configured to input a bright line detection signal, and the second end is electrically connected to a drain or a source of the first group of test thin film transistors,

[0046] The crack detection method further comprises:

[0047] A level signal for turning off the at least one test thin film transistor is input to the at least one test thin film transistor.

[0048] According to some further embodiments of the present disclosure, a method for detecting cracks in a display substrate is provided, the display substrate comprising:

[0049] A substrate, comprising a display area and a peripheral area surrounding the display area;

[0050] A plurality of sub-pixels, located in the display area, including test sub-pixels and non-test sub-pixels;

[0051] a unit test circuit, located in the peripheral area and electrically connected to the plurality of sub-pixels, the unit test circuit comprising at least one test thin film transistor, each test thin film transistor comprising a source, a drain and a gate, the at least one test thin film transistor comprising a first group of test thin film transistors, a source or a drain of the first group of test thin film transistors being electrically connected to the test sub-pixels;

[0052] a first crack detection line, located in the peripheral area and surrounding the display area, and electrically connected to the unit test circuit;

[0053] a second crack detection line, located in the peripheral area and surrounding the display area, the second crack detection line comprising a first end and a second end, the first end of the second crack detection line being configured to input a bright line detection signal, and the second end being electrically connected to a drain or a source of the first group of test thin film transistors;

[0054] at least one first electrostatic discharge circuit located in the peripheral area, each first electrostatic discharge circuit comprising at least one first thin film transistor, and the at least one first thin film transistor comprising a first gate; and

[0055] at least one second electrostatic discharge circuit, located in the peripheral area and electrically connected to the second crack detection line, each second electrostatic discharge circuit includes at least one second thin film transistor, the at least one second thin film transistor includes a second gate, wherein the second gate is electrically connected to the first gate,

[0056] The crack detection method comprises:

[0057] A first level signal is input to the gates of the first group of test thin film transistors to turn on the first group of test thin film transistors, and a bright line detection signal is input to the first end of the first crack detection line to detect the light emitting state of the test sub-pixel.

[0058] In some embodiments, the bright line detection signal is a constant voltage signal, and a voltage value of the constant voltage signal is greater than a voltage threshold.

[0059] In some embodiments, the at least one test thin film transistor further comprises a second group of test thin film transistors, sources or drains of the second group of test thin film transistors are electrically connected to the non-test sub-pixels,

[0060] The crack detection method further comprises:

[0061] A first level signal is input to the gate of the second group of test thin film transistors to turn on the second group of test thin film transistors, and a second level signal is input to the drain or source of the second group of test thin film transistors to make the non-test sub-pixels present a dark state.

[0062] According to some further embodiments of the present disclosure, a display device is provided, comprising the display substrate described in any of the aforementioned embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0064] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings.

[0065] in:

[0066] Figure 1 is a schematic diagram of the regional distribution of a display substrate according to an embodiment of the present disclosure;

[0067] Figure 2 A crack detection method for a display substrate according to an embodiment of the present disclosure;

[0068] Figure 3 is a crack detection method for a display substrate according to another embodiment of the present disclosure;

[0069] Figure 4A is a schematic diagram of the design of a first electrostatic discharge circuit and a second electrostatic discharge circuit of a display substrate according to an embodiment of the present disclosure;

[0070] Figure 4B is a schematic diagram of a principle of an electrostatic discharge circuit in a display substrate according to an embodiment of the present disclosure;

[0071] Figure 5A yes Figure 4A An enlarged schematic diagram of the middle circle A;

[0072] Figure 5B yes Figure 5A Structural diagram of the middle BB section;

[0073] Figure 6 It is a schematic flow chart of a method for manufacturing a display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0075] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprise" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0076] In the present disclosure, when a specific device is described as being located between a first device and a second device, there may or may not be an intermediate device between the specific device and the first device or the second device. When a specific device is described as being connected to other devices, the specific device may be directly connected to the other device without an intermediate device, or may not be directly connected to the other device but have an intermediate device.

[0077] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries, such as general dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.

[0078] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0079] At present, PCD (Panel Crack Detection) is mostly used for film crack detection. There are two main ways to detect PCD: one is electrical signal detection, usually resistance detection, such as detecting the resistance at both ends of the peripheral metal winding. When cracks appear in the PCD, the resistance value will deviate from the reference value; the other is bright line detection, also known as voltage detection, that is, connecting the peripheral metal winding to the data line of the display area. When cracks appear in the PCD, bright lines will appear on the screen. The PCD line of the OLED display is relatively long, and static electricity is easily accumulated during the process. If these accumulated static electricity cannot be discharged in time, the static electricity may break through the driving thin film transistor (Thin Film Transistor, abbreviated as TFT) or the TFT of the scanning unit in the panel adjacent to the PCD line, resulting in the failure of individual pixel light emission or the failure of the entire panel.

[0080] However, the inventors have found through research that the breakdown effect of ESD will affect the detection results of PCD, for example, causing PCD signal disturbance, which can easily cause PCD to over-detect, thereby reducing the accuracy of crack detection.

[0081] In view of this, the embodiments of the present disclosure provide a display substrate and a manufacturing method thereof, a crack detection method, a display panel and a display device, which can realize multiple PCD detection methods and can effectively improve the accuracy of PCD.

[0082] Figure 1 Schematic diagram of the regional distribution of a display substrate according to an embodiment of the present disclosure.

[0083] refer to Figure 1 In some embodiments, the display substrate includes a base substrate 1, a first crack detection line 2, a second crack detection line 3, at least one first electrostatic discharge circuit 4 and at least one second electrostatic discharge circuit 5.

[0084] The material of the base substrate 1 may be glass, ceramic, polyimide, etc. The base substrate 1 includes a display area 1A and a peripheral area 1B surrounding the display area 1A.

[0085] exist Figure 1 In the figure, the display area 1A includes: a first boundary 1a, a second boundary 1b, a third boundary 1c and a fourth boundary 1d. The first boundary 1a is opposite to the third boundary 1c, and the second boundary 1b is opposite to the fourth boundary 1d. The peripheral area 1B is located outside the display area 1A (i.e., on the side away from the display area 1A), and belongs to the non-display area. The peripheral area 1B includes a first peripheral area located outside the first boundary 1a, a second peripheral area located outside the second boundary 1b, a third peripheral area located outside the third boundary 1c, and a fourth peripheral area located outside the fourth boundary 1d. For example, Figure 1 As shown, the first peripheral area is the peripheral area located below the first border 1a, the second peripheral area is the peripheral area located on the left side of the second border 1b, the third peripheral area is the peripheral area located above the third border 1c, and the fourth peripheral area is the peripheral area located on the right side of the fourth border 1d.

[0086] The first crack detection line 2 is located in the peripheral area 1B and surrounds the display area 1A. Figure 1 As shown, the first crack detection line 2 includes a first crack detection line section 21 and a second crack detection line section 22 which are mirror-symmetrical.

[0087] like Figure 1 As shown, the first section crack detection line 21 of the first crack detection line 2 is located in the first part of the first peripheral area (e.g., the left half of the first peripheral area), the second peripheral area and the first part of the third peripheral area (e.g., the left half of the third peripheral area). The second section crack detection line 22 is located in the second part of the first peripheral area (e.g., the right half of the first peripheral area), the fourth peripheral area and the second part of the third peripheral area (e.g., the right half of the third peripheral area).

[0088] The first crack detection line 2 includes a first end and a second end. When an electrical signal is used to detect cracks, the first end of the first crack detection line 2 is configured to input a first electrical signal detection signal, and the second end is configured to output a second electrical signal detection signal.

[0089] The second crack detection line 3 is located in the peripheral area 1B and surrounds the display area 1A. Similar to the first crack detection line 2, the second crack detection line 3 may also include a first crack detection line 31 and a second crack detection line 32 that are mirror-symmetrical.

[0090] Similar to the first crack detection line 2, the first section crack detection line 31 of the second crack detection line 3 is located in the first part of the first peripheral area, the second peripheral area and the first part of the third peripheral area. The second section crack detection line 32 is located in the second part of the first peripheral area, the fourth peripheral area and the second part of the third peripheral area.

[0091] like Figure 1 As shown, the second crack detection line 3 includes a first end and a second end. When bright line detection is used, the first end of the second crack detection line 3 is configured to input a bright line detection signal for determining whether there is a crack in the film layer.

[0092] In some implementations, at least a portion of the second crack detection line 3 surrounds at least a portion of the first crack detection line 2 .

[0093] Next, the electrostatic discharge circuit used in conjunction with the crack detection line is described.

[0094] like Figure 1 As shown, at least one first electrostatic discharge circuit 4 is located in the peripheral area 1B and is electrically insulated from the first crack detection line 2, and is used to realize the electrostatic discharge of the first crack detection line 2. Figure 1 In the embodiment, two first electrostatic discharge circuits 4 located at different positions are electrically connected to the first crack detection line 2 respectively. It should be understood that the first electrostatic discharge circuit 4 can also be arranged at other positions electrically connected to the first crack detection line 2. Each first electrostatic discharge circuit 4 includes at least one first thin film transistor. The at least one first thin film transistor includes a first gate, where the first gate can be formed by electrically connecting the gates of each first thin film transistor in the at least one first thin film transistor.

[0095] In some embodiments, the at least one first thin film transistor includes an active layer, a first gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, and the source and the drain of the at least one first thin film transistor are electrically insulated from the crack detection line. The source and the drain of the at least one first thin film transistor are short-circuited by a metal layer, and the source and the drain of the at least one first thin film transistor are located in the same layer as the metal layer and are made of the same material.

[0096] like Figure 1As shown, at least one second electrostatic discharge circuit 5 is located in the peripheral area 1B and is electrically connected to the second crack detection line 3, so as to realize the electrostatic discharge of the second crack detection line 3. Similarly, each second electrostatic discharge circuit 5 can also be set at any position electrically connected to the second crack detection line 3. Each second electrostatic discharge circuit 5 includes at least one second thin film transistor. In some embodiments, the at least one second thin film transistor includes an active layer, a second gate located on the side of the active layer away from the substrate, and a source and a drain located on the side of the second gate away from the substrate, the source and the drain of the at least one second thin film transistor are electrically connected to the crack detection line, and the second gate is electrically connected to the first gate. For example, the second gate of a second electrostatic discharge circuit 5 can be electrically connected to the first gate of a first electrostatic discharge circuit 4 adjacent to the second electrostatic discharge circuit 5. Here, the second gate can be formed by electrically connecting the gates of each second thin film transistor in at least one second thin film transistor. The common gate structure of the first electrostatic discharge circuit 4 and the second electrostatic discharge circuit 5 will be described in detail later in conjunction with FIG. 4.

[0097] In some embodiments, the source and drain of the at least one second thin film transistor are short-circuited by a metal layer, and the source and drain of the at least one second thin film transistor are located in the same layer and made of the same material as the metal layer. In some embodiments, at least part of the second crack detection line located in the first peripheral region is located in the same layer and made of the same material as the source and drain of the at least one second thin film transistor, and at least part of the second crack detection line located in the second peripheral region, the third peripheral region, and the fourth peripheral region is located in the same layer and made of the same material as the gate of the at least one second thin film transistor.

[0098] like Figure 1 As shown, the display substrate further includes a common electrode 8, which is located in the peripheral area 1B and surrounds the display area 1A. In some embodiments, the first electrostatic discharge circuit 4 (first gate) and the second electrostatic discharge circuit 5 (second gate) are electrically connected to the common electrode 8, respectively. The common electrode 8 includes a first portion 81 located in the first peripheral area and a second portion 82 located in the second peripheral area, the third peripheral area, and the fourth peripheral area, wherein the first electrostatic discharge circuit 4 and the second thin film transistor 5 are electrically connected to the first portion 81 of the common electrode 8, respectively.

[0099] like Figure 1 As shown, part of the first crack detection line or the second crack detection line located in the first peripheral area is U-shaped or L-shaped, and the bending part of the U-shape or L-shape may have a cut angle.

[0100] In the above embodiment, the display substrate includes a first crack detection line 2, a second crack detection line 3, at least one first electrostatic discharge circuit 4 electrically connected to the first crack detection line 2, and at least one second electrostatic discharge circuit 5 electrically connected to the second crack detection line 3, and the gate of the first thin film transistor in the first electrostatic discharge circuit 4 is electrically connected to the gate of the second thin film transistor in the second electrostatic discharge circuit 5. The first electrostatic discharge circuit 4 and the second electrostatic discharge circuit 5 electrically connected to the gate can protect each other, improve the stability and reliability of the electrostatic discharge circuit, reduce the impact of the breakdown of ESD on the PCD result, and reduce the possibility of PCD over-detection, thereby further improving the accuracy of film crack detection.

[0101] like Figure 1 As shown, in some embodiments, the display substrate may further include a plurality of sub-pixels 6 and a unit test circuit CT located in the display area 1A. In some embodiments, the first electrostatic discharge circuit 4 and the second electrostatic discharge circuit 5 are located on both sides of the unit test circuit CT, respectively, and are mirror-symmetrical.

[0102] The plurality of sub-pixels 6 include a test sub-pixel 61 and a non-test sub-pixel 62. Each sub-pixel can display any one of red, green and blue colors, so that the display substrate can present a picture.

[0103] The unit test circuit CT is located in the peripheral area 1B and is electrically connected to the plurality of sub-pixels 6, the first crack detection line 2 and the second crack detection line 3 respectively. The unit test circuit CT includes at least one test thin film transistor (TFT) 7. The at least one test thin film transistor 7 may be a P-type thin film transistor or an N-type thin film transistor. Each test thin film transistor 7 includes a source, a drain and a gate. Figure 1 As shown, the gates of the test thin film transistors 7 are all connected to the switch signal line SWd. At least one test thin film transistor includes a first group of test thin film transistors 71. One electrode of the source or drain of the first group of test thin film transistors 71 is electrically connected to the test sub-pixel 61, and the other electrode is electrically connected to the signal lines (also called control voltage lines) D1 and D2, respectively. In some embodiments, at least one test thin film transistor 7 also includes a second group of test thin film transistors 72. One electrode of the source or drain of the second group of test thin film transistors 72 is electrically connected to the non-test sub-pixel 62.

[0104] In the case where the source of the first group of test thin film transistors 71 is electrically connected to the test sub-pixel 61, the second end 3b of the second crack detection line 3 is electrically connected to the drain of the first group of test thin film transistors 71. Alternatively, in the case where the drain of the first group of test thin film transistors 71 is electrically connected to the test sub-pixel 61, the second end 3b of the second crack detection line 3 is electrically connected to the source of the first group of test thin film transistors 71. In other words, the test sub-pixel 61 is electrically connected to the second end 3b of the second crack detection line 3 via the first group of test thin film transistors 71.

[0105] In the above embodiment, the two crack detection lines can use different PCD detection methods to detect film cracks respectively, thereby combining multiple crack detection results to improve the accuracy of film crack identification.

[0106] The following takes the first crack detection line using electrical signal detection as an example. Figure 1 and Figure 2 A crack detection method for a display substrate is described.

[0107] Figure 2 A crack detection method for a display substrate according to an embodiment of the present disclosure is provided. Figure 2 As shown, the crack detection method of this embodiment includes the following steps 202-206.

[0108] Step 202: input a first electrical signal detection signal to the first end of the first crack detection line 2. For example, the first electrical signal detection signal is a voltage signal of +2.5V.

[0109] Step 204: Receive a second electrical signal detection signal from the second end of the first crack detection line 2. Step 206: Determine whether there is a crack in the display substrate according to the first electrical signal detection signal and the second electrical signal detection signal.

[0110] In some embodiments, first, the resistance value between the first end of the first crack detection line 2 and the second end of the first crack detection line 2 is determined based on the first electrical signal detection signal and the second electrical signal detection signal; next, based on the comparison result of the resistance value and the resistance threshold, it is determined whether there is a crack in the display substrate.

[0111] For example, a multimeter can be used to determine the resistance value between the first end of the first crack detection line 2 and the second end of the first crack detection line 2; when the measured resistance value (for example, 1KΩ (kilo-ohm)) is less than a resistance threshold value (for example, 100KΩ), it is judged that there is no crack in the display substrate, and when the measured resistance value (for example, 150KΩ) is greater than the resistance threshold value (for example, 100KΩ), it is judged that there is a crack in the display substrate.

[0112] In some embodiments, the crack detection method further includes: disconnecting the electrical connection between at least one first electrostatic discharge circuit 4 and the first crack detection line 2. This can reduce the impact of ESD breakdown on the PCD detection signal and further improve the accuracy of PCD.

[0113] In some other embodiments, the crack detection method based on electrical signals further includes: inputting a level signal to at least one test thin film transistor 7 to turn off at least one test thin film transistor 7. For example, in the case where at least one test thin film transistor 7 is a P-type thin film transistor, by inputting a level signal V GH (e.g. +7V) to turn off at least one test thin film transistor 7. The signal line connected to the second crack detection line 3 can be configured to be in a high impedance state. This can reduce the influence of other crack detection structural components on the detection result of the crack detection method, and further improve the result accuracy of the above crack detection method.

[0114] It should be noted here that the second crack detection line can also adopt the structure of the above-mentioned first crack detection line and adopt the crack detection method based on electrical signals to perform crack detection, which will not be described in detail here.

[0115] As mentioned above, PCD detection methods include bright line detection in addition to electrical signal detection. Figure 1 and Figure 3 Another crack detection method for display substrates is described.

[0116] Figure 3 A crack detection method for a display substrate according to another embodiment of the present disclosure is disclosed.

[0117] like Figure 3 As shown, the crack detection method of this embodiment includes steps 302-304.

[0118] Step 302 : Input a first level signal to the gates of the first group of test thin film transistors 71 to turn on the first group of test thin film transistors 71 .

[0119] Step 304, input a bright line detection signal to the first end of the second crack detection line 3 to detect the light emitting state of the test sub-pixel 61. In some embodiments, the bright line detection signal is a constant voltage signal, and the voltage value of the constant voltage signal is greater than the voltage threshold (for example, +6V). In this way, after the second electrostatic discharge circuit 5 is connected, the breakdown effect of the second electrostatic discharge circuit 5 will not affect the normal operation of the bright line detection, that is, it will not cause the PCD to be over-detected, thereby further improving the result accuracy of the above crack detection method.

[0120] For example, first, when at least one test thin film transistor 7 is a P-type thin film transistor, a level signal V GL (For example, -7V) is used to turn on at least one test thin film transistor 7. Next, by inputting a bright line detection signal (for example, +7V) to the signal line, the bright line detection signal is input from the first end of the second crack detection line 3, passes through the second crack detection line 3, and is then transmitted to the test sub-pixel 61 by the second crack detection line 3. In the bright line detection, the signal is input through the data line of the IC, so that the screen appears in a dark state. When there is no crack on the display substrate or the crack is small, the second crack detection line 3 is not broken, and the test sub-pixels 71 in the display area are all in a dark state. If there is a large crack in the display substrate, causing the second crack detection line 3 to be broken, the test sub-pixel 71 in the display area emits light, which is reflected in the bright line in the dark state picture in the display area, thereby determining that the display substrate has cracks.

[0121] In some embodiments, the crack detection method further includes: inputting a first level signal to the gate of the second group of test thin film transistors 72 to turn on the second group of test thin film transistors 72, and inputting a second level signal to the other electrode of the drain or source of the second group of test thin film transistors 72 to make the non-test sub-pixel 62 present a dark state. For example, through the signal line D 1 and D 2 A second level signal (for example, +7V) is input, and the second level signal is transmitted to the non-test sub-pixel 62 through the second group of test thin film transistors 72, so that the non-test sub-pixels 62 are all in a dark state, which is more conducive to displaying the detection results of the test sub-pixel, and thus more conveniently implementing the above-mentioned crack detection method.

[0122] In the above embodiment, since the second electrostatic discharge circuit 5 is protected by the first electrostatic discharge circuit 4 sharing the same gate with the second electrostatic discharge circuit 5 , the working stability and reliability of the second electrostatic discharge circuit 5 are improved, thereby improving the accuracy of the PCD.

[0123] Of course, the first crack detection line may also adopt the structure of the second crack detection line and adopt a bright line detection method to perform crack detection, which will not be described in detail here.

[0124] It should be understood that the embodiments of the present disclosure may respectively adopt the above two crack detection methods to perform crack detection, and then combine the detection results of the two crack detection methods to improve the accuracy of the product screen PCD.

[0125] Combine the following Figure 4A and 4B The electrostatic discharge circuit is further described.

[0126] Figure 4A1 is a schematic diagram of the design of a first electrostatic discharge circuit and a second electrostatic discharge circuit of a display substrate according to an embodiment of the present disclosure.

[0127] Combine the following Figure 4A To explain the common gate structure (ie, the connection structure between the first gate 41 and the second gate 51 ) of a first electrostatic discharge circuit 4 in at least one first electrostatic discharge circuit 4 and a second electrostatic discharge circuit 5 adjacent to the first electrostatic discharge circuit 4 .

[0128] refer to Figure 4A The first electrostatic discharge circuit 4 includes two rows of first thin film transistors 40 arranged in parallel. The first thin film transistors 40 in each row of first thin film transistors 40 are arranged along the extension direction of the first crack detection line 2. The source and drain of the first thin film transistors 40 in each row of first thin film transistors 40 are electrically insulated from the first crack detection line 2. The gates of the first thin film transistors 40 in each row of first thin film transistors 40 are sequentially connected along the arrangement direction of the row of first thin film transistors 40, and the gates of the first thin film transistors 40 in each row are connected to each other on both sides along the extension direction of the first crack detection line 2. The gates of the two rows of first thin film transistors 40 are electrically connected to form a first gate 41.

[0129] The specific arrangement of the second electrostatic discharge circuit 5 is different from that of the first electrostatic discharge circuit 4 in that the crack detection line electrically connected to the second electrostatic discharge circuit 5 is the second crack detection line 3 and the source and drain of the second thin film transistors 50 in each row of the second thin film transistors 50 are electrically connected to the second crack detection line 3, and the rest is similar and will not be repeated here. The gates of the two rows of second thin film transistors 50 are electrically connected to form a second gate 51. The second gate 51 and the first gate 41 are connected to each other on both sides along the extension direction of the crack detection line.

[0130] Figure 4B FIG. 1 is a schematic diagram of the principle of an electrostatic discharge circuit in a display substrate according to an embodiment of the present disclosure. Figure 4A The second electrostatic discharge circuit 5 shown is taken as an example for explanation.

[0131] As shown in FIG5 , the source and drain of the second thin film transistor 50 in the second electrostatic discharge circuit 5 are electrically connected. The source and drain of the second thin film transistor 50 are electrically connected to the second crack detection line. And the second gate 51 of the second thin film transistor 50 can be set to a negative constant voltage. For example, the access voltage Vss of the first gate 41 and the second gate 51 is -3V to -4V.

[0132] By using the above connection method, the second thin film transistor 50 of the second electrostatic discharge circuit 5 is equivalent to a capacitor, wherein the source and drain of the second thin film transistor 50 are equivalent to one plate of the capacitor, and the gate of the second thin film transistor 50 is equivalent to the other plate of the capacitor. By making the second gate 51 and the first gate 41 continuously at a low potential, when the crack detection line generates static charge, the static charge can be released through the first thin film transistor 40 and the second thin film transistor 50. In the embodiment of the present disclosure, by designing a dual electrostatic discharge circuit with a common gate structure, it is possible to ensure that the access voltages of the first gate 41 and the second gate 51 are uniform and stable, thereby achieving normal operation of the electrostatic discharge circuit.

[0133] Figure 5A yes Figure 4A Enlarged schematic diagram of circle A in the middle. Figure 5B yes Figure 5A Schematic diagram of the structure of the BB section.

[0134] refer to Figures 4A-5B In some embodiments, at least one electrostatic discharge circuit 5 includes at least one TFT 50. Figure 5B As shown, the TFT 50 includes an active layer 52, a gate 51 located on a side of the active layer 52 away from the substrate 1, and a source 55 and a drain 56 located on a side of the gate 51 away from the substrate 1. The source 55 and the drain 56 of the TFT 50 are electrically connected to the second crack detection line 3 and to the active layer 52. The gate 51 of the TFT 50 is electrically connected to the common electrode 8. The active layer 52 can be made of polysilicon material. Figure 4A In the embodiment, part of the second crack detection line 3 is bent into a U-shape in the first peripheral area, and the TFT 50 in the electrostatic discharge circuit 5 is located in the bottom area of ​​the U-shape. The bent part of the U-shape can be provided with a cut angle to reduce the risk of tip discharge.

[0135] refer to Figure 5A-5BIn some embodiments, the source 55 and the drain 56 of the TFT 50 are short-circuited by the metal layer 57, and the source 55 and the drain 56 are located in the same layer and made of the same material as the metal layer 57. For example, the source 55 and the drain 56 of the TFT 50 and the metal layer 57 are made of conductive materials such as molybdenum, copper, aluminum, gold, silver or titanium. In this way, the source 55 and the drain 56 and the metal layer 57 can be formed by the same patterning process to simplify the processing steps. Here and in the following, the same layer and the same material can be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask template to pattern the film layer through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0136] refer to Figure 5B In some embodiments, while using an electrostatic discharge circuit to release the PCD line, a PCD line routing layer change technology is used. That is, at least part of the second crack detection line 3 located in the first peripheral area is located in the same layer and made of the same material as the source 55 and drain 56 of at least one TFT 50, so that at least part of the second crack detection line 3 in this area can be formed by the same patterning process as the source 55 and drain 56 of at least one TFT 50, so as to simplify the processing procedures. In addition, at least part of the second crack detection line 3 located in the second peripheral area, the third peripheral area, and the fourth peripheral area is located in the same layer and made of the same material as the gate 51 of the at least one TFT 50, so that the conductor area with antenna effect is reduced by the jumper of the second crack detection line 3 between layers, and the static electricity accumulated on the second crack detection line 3 is released to the TFT 50.

[0137] exist Figure 4A In the embodiment, the gate electrodes 51 of each row of TFTs 50 may be sequentially connected along the arrangement direction of the row of TFTs 50. The gate electrodes 51 of each row of TFTs 50 are connected to each other at both sides along the arrangement direction of the row of TFTs 50. For an electrostatic discharge circuit having two rows of TFTs 50, the gate electrodes 51 of the two rows of TFTs 50 may be in a ring shape and led outwards so as to be electrically connected to the common electrode 8.

[0138] refer to Figure 5BIn some embodiments, the display substrate 1 further includes: a first gate insulating layer 12, a second gate insulating layer 13 and an interlayer insulating layer 14. The first gate insulating layer 12 is located on a side of the base substrate 1 adjacent to the gate 51 of the at least one TFT 50, and covers the active layer 52 of the at least one TFT 50. The second gate insulating layer 13 is located on a side of the first gate insulating layer 12 away from the base substrate, and covers the gate 51 of the at least one TFT 50. The interlayer insulating layer 14 is located on a side of the second gate insulating layer 13 away from the base substrate 1. Figure 5B In the embodiment, the buffer layer 11 may be disposed on the base substrate 1, and the active layer 52 may be disposed on the surface of the buffer layer 11. In other embodiments, the active layer 52 may be directly disposed on the surface of the base substrate 1.

[0139] like Figure 5B As shown, the source electrode 55 and the drain electrode 56 are arranged on the side of the interlayer insulating layer 14 away from the substrate 1, and are electrically connected to the active layer 52 through at least one first via hole 59 penetrating the interlayer insulating layer 14, the second gate insulating layer 13 and the first gate insulating layer 12. Figure 5A In the embodiment, the source 55 and the drain 56 of the TFT 50 are electrically connected to the active layer 52 through three first via holes 59. The display substrate 1 further includes a planarization layer 15 located on a side of the interlayer insulating layer 14 away from the substrate 1, and the planarization layer 15 covers the source 55 and the drain 56 of at least one TFT 50.

[0140] According to another aspect of the present disclosure, a method for manufacturing a display substrate is provided. Figure 6 Provide explanation.

[0141] Figure 6 It is a schematic flow chart of a method for manufacturing a display substrate according to an embodiment of the present disclosure.

[0142] like Figure 6 As shown, the method for manufacturing a display substrate includes steps 602-610.

[0143] Step 602: Provide a base substrate. The base substrate includes a display area and a peripheral area surrounding the display area.

[0144] Step 604: forming a first crack detection line on the base substrate. The first crack detection line is located in the peripheral area and surrounds the display area.

[0145] Step 606: forming a second crack detection line on the base substrate. The second crack detection line is located in the peripheral area and surrounds the display area.

[0146] Step 608, forming at least one first electrostatic discharge circuit on the substrate. The at least one first electrostatic discharge circuit is located in the peripheral area. Each first electrostatic discharge circuit includes at least one first thin film transistor. The at least one first thin film transistor includes a first gate.

[0147] Step 610, forming at least one second electrostatic discharge circuit on the substrate. The at least one second electrostatic discharge circuit is located in the peripheral area and is electrically connected to the second crack detection line. Each second electrostatic discharge circuit includes at least one second thin film transistor. The at least one second thin film transistor includes a second gate. The second gate is electrically connected to the first gate.

[0148] It should be understood that the execution order of steps 604-610 in the above embodiment is only an exemplary description and cannot limit the scope of the present disclosure. For example, the above manufacturing method can also execute step 608 first and then execute step 606.

[0149] In the above embodiment, the design of the first electrostatic discharge circuit and the common gate structure of the first electrostatic discharge circuit can ensure the etching uniformity and stability when the display substrate is manufactured using the backplane process.

[0150] In some embodiments, at least a portion of the first crack detection line and at least a portion of the second crack detection line are formed in the same process film layer. For example, at least a portion of the first crack detection line and at least a portion of the second crack detection line can be formed in the same film layer using a backplane process. Of course, at least a portion of the first crack detection line and at least a portion of the second crack detection line can also be formed in different film layers. For example, for FMLOC (Flexible Multiple Layer OnCell, flexible multi-layer integrated touch) products, the first crack detection line and the second crack detection line can be respectively set in different film layers.

[0151] The above display substrate embodiments of the present disclosure can be applied to various display panels and display devices. Therefore, the present disclosure also provides a display panel, such as an AMOLED display panel, which includes the above display substrate. The present disclosure also provides a display device, including the above display panel. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0152] So far, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution disclosed here.

[0153] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a peripheral area surrounding the display area; A first crack detection line, located in the peripheral area and surrounding the display area; a second crack detection line located in the peripheral area and surrounding the display area; At least one first electrostatic discharge circuit is located in the peripheral area, each first electrostatic discharge circuit includes at least one first thin film transistor, and the at least one first thin film transistor includes a first gate; and At least one second electrostatic release circuit is located in the peripheral area and electrically connected to the second crack detection line, each second electrostatic release circuit includes at least one second thin film transistor, and the at least one second thin film transistor includes a second gate, wherein the second gate is electrically connected to the first gate.

2. The display substrate according to claim 1, wherein: The first crack detection line includes a first end and a second end, the first end of the first crack detection line is configured to input a first electrical signal detection signal, the second end is configured to output a second electrical signal detection signal, and the at least one first electrostatic release circuit is electrically insulated from the first crack detection line.

3. The display substrate according to claim 1, further comprising: A plurality of sub-pixels, located in the display area, including test sub-pixels and non-test sub-pixels; and The unit test circuit is located in the peripheral area and is electrically connected to the plurality of sub-pixels and to at least one of the first crack detection line and the second crack detection line.

4. The display substrate according to claim 3, wherein: The unit test circuit comprises at least one test thin film transistor, each test thin film transistor comprises a source, a drain and a gate, the at least one test thin film transistor comprises a first group of test thin film transistors, and the source or drain of the first group of test thin film transistors is electrically connected to the test sub-pixel; The second crack detection line includes a first end and a second end, the first end of the second crack detection line is configured to input a bright line detection signal, and the second end is electrically connected to a drain or a source of the first group of test thin film transistors.

5. The display substrate according to claim 4, wherein: The at least one test thin film transistor further includes a second group of test thin film transistors, and sources or drains of the second group of test thin film transistors are electrically connected to the non-test sub-pixels.

6. The display substrate according to claim 4, wherein: The at least one test thin film transistor is a P-type thin film transistor.

7. The display substrate according to claim 1, wherein: At least a portion of the second crack detection line surrounds at least a portion of the first crack detection line.

8. The display substrate according to any one of claims 1 to 7, wherein: The first crack detection line includes a first crack detection line section and a second crack detection line section that are mirror-symmetrical, and the second crack detection line includes a first crack detection line section and a second crack detection line section that are mirror-symmetrical.

9. The display substrate according to claim 1, further comprising: A common electrode is located in the peripheral area and surrounds the display area, wherein the second gate and the first gate are electrically connected to the common electrode respectively.

10. The display substrate according to claim 1, wherein: The first gate and the second gate are an integrated structure.

11. The display substrate according to claim 9, wherein: The at least one first thin film transistor comprises an active layer, a first gate located at a side of the active layer away from the substrate, and a source and a drain located at a side of the gate away from the substrate, wherein the source and the drain of the at least one first thin film transistor are electrically insulated from the crack detection line; The at least one second thin film transistor includes an active layer, a second gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, and the source and the drain of the at least one second thin film transistor are electrically connected to the crack detection line.

12. The display substrate according to claim 3, wherein: The first electrostatic discharge circuit and the second electrostatic discharge circuit are respectively located on two sides of the unit test circuit and are mirror-symmetrical.

13. The display substrate according to claim 9, wherein: The display area includes a first boundary, a second boundary, a third boundary and a fourth boundary; The peripheral region includes a first peripheral area located outside the first boundary, a second peripheral area located outside the second boundary, a third peripheral area located outside the third boundary, and a fourth peripheral area located outside the fourth boundary; The common electrode includes a first portion located in the first peripheral area and a second portion located in the second peripheral area, the third peripheral area and the fourth peripheral area, and the first gate of the at least one first thin film transistor and the second gate of the at least one second thin film transistor are electrically connected to the first portion of the common electrode, respectively.

14. The display substrate according to claim 13, wherein: At least part of the second crack detection line located in the first peripheral area is located in the same layer and has the same material as the source and drain of the at least one second thin film transistor, and at least part of the second crack detection line located in the second peripheral area, the third peripheral area and the fourth peripheral area is located in the same layer and has the same material as the gate of the at least one second thin film transistor.

15. The display substrate according to claim 14, wherein: A portion of the first crack detection line or the second crack detection line located in the first peripheral area is U-shaped or L-shaped, and a bent portion of the U-shape or L-shape has a cut angle.

16. The display substrate according to claim 1, wherein: The source and drain of the at least one first thin film transistor are short-circuited by a metal layer, and the source and drain of the at least one first thin film transistor are located in the same layer as the metal layer and are made of the same material; The source and drain of the at least one second thin film transistor are short-circuited by a metal layer, and the source and drain of the at least one second thin film transistor are located in the same layer as the metal layer and are made of the same material.

17. A method for detecting cracks in a display substrate, the display substrate comprising: A substrate, comprising a display area and a peripheral area surrounding the display area; a first crack detection line, located in the peripheral area and surrounding the display area, the first crack detection line comprising a first end and a second end; a second crack detection line located in the peripheral area and surrounding the display area; at least one first electrostatic discharge circuit, located in the peripheral area and electrically insulated from the first crack detection line, each first electrostatic discharge circuit comprising at least one first thin film transistor, and the at least one first thin film transistor comprising a first gate; and at least one second electrostatic discharge circuit, located in the peripheral area and electrically connected to the second crack detection line, each second electrostatic discharge circuit includes at least one second thin film transistor, the at least one second thin film transistor includes a second gate, wherein the second gate is electrically connected to the first gate, The crack detection method comprises: Inputting a first electrical signal detection signal to a first end portion of the first crack detection line; receiving a second electrical signal detection signal from a second end of the first crack detection line; and Whether there is a crack in the display substrate is determined according to the first electrical signal detection signal and the second electrical signal detection signal.

18. The crack detection method according to claim 17, wherein: Judging whether there is a crack in the display substrate according to the first electrical signal detection signal and the second electrical signal detection signal includes: determining a resistance value between a first end of the first crack detection line and a second end of the first crack detection line according to the first electrical signal detection signal and the second electrical signal detection signal; and According to the comparison result between the resistance value and the resistance threshold, it is determined whether there is a crack in the display substrate.

19. The crack detection method according to claim 17, wherein: The display substrate further comprises: A plurality of sub-pixels located in the display area, including test sub-pixels and non-test sub-pixels; and a unit test circuit, located in the peripheral area and electrically connected to the plurality of sub-pixels, the first crack detection line and the second crack detection line, respectively, the unit test circuit comprising at least one test thin film transistor, each test thin film transistor comprising a source, a drain and a gate, the at least one test thin film transistor comprising a first group of test thin film transistors, a source or a drain of the first group of test thin film transistors being electrically connected to the test sub-pixel; The second crack detection line includes a first end and a second end, the first end of the second crack detection line is configured to input a bright line detection signal, and the second end is electrically connected to a drain or a source of the first group of test thin film transistors, The crack detection method further comprises: A level signal for turning off the at least one test thin film transistor is input to the at least one test thin film transistor.

20. A method for detecting cracks in a display substrate, the display substrate comprising: A substrate, comprising a display area and a peripheral area surrounding the display area; A plurality of sub-pixels, located in the display area, including test sub-pixels and non-test sub-pixels; a unit test circuit, located in the peripheral area and electrically connected to the plurality of sub-pixels, the unit test circuit comprising at least one test thin film transistor, each test thin film transistor comprising a source, a drain and a gate, the at least one test thin film transistor comprising a first group of test thin film transistors, a source or a drain of the first group of test thin film transistors being electrically connected to the test sub-pixels; a first crack detection line, located in the peripheral area and surrounding the display area, and electrically connected to the unit test circuit; a second crack detection line, located in the peripheral area and surrounding the display area, the second crack detection line comprising a first end and a second end, the first end of the second crack detection line being configured to input a bright line detection signal, and the second end being electrically connected to a drain or a source of the first group of test thin film transistors; At least one first electrostatic discharge circuit is located in the peripheral area, each first electrostatic discharge circuit includes at least one first thin film transistor, and the at least one first thin film transistor includes a first gate; and at least one second electrostatic discharge circuit, located in the peripheral area and electrically connected to the second crack detection line, each second electrostatic discharge circuit includes at least one second thin film transistor, the at least one second thin film transistor includes a second gate, wherein the second gate is electrically connected to the first gate, The crack detection method comprises: Inputting a first level signal to the gate of the first group of test thin film transistors to turn on the first group of test thin film transistors; A bright line detection signal is input to a first end portion of the first crack detection line to detect a light emitting state of the test sub-pixel.

21. The crack detection method according to claim 20, wherein: The bright line detection signal is a constant voltage signal, and a voltage value of the constant voltage signal is greater than a voltage threshold.

22. The crack detection method according to claim 21, wherein: The at least one test thin film transistor further comprises a second group of test thin film transistors, wherein source electrodes or drain electrodes of the second group of test thin film transistors are electrically connected to the non-test sub-pixels, The crack detection method further comprises: A first level signal is input to the gate of the second group of test thin film transistors to turn on the second group of test thin film transistors, and a second level signal is input to the drain or source of the second group of test thin film transistors to make the non-test sub-pixels present a dark state.

23. A display device comprising the display substrate according to any one of claims 1 to 16.

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