A hybrid probability logic calculation method and device

Abstract

The present application discloses a method and device for calculating mixed probability logic (probability and binary logic). The method realizes the integration of binary logic coding function on the basis of traditional probability calculation (Stochastic Computing), thereby realizing the probability-binary mixed calculation technology, including its mathematical logic basis, the basic four arithmetic operations of addition, subtraction, multiplication and division of mixed calculation, probability-binary conversion structure and complex polynomial fitting calculation method and device. The present application scheme solves the problems of large calculation delay, no precise calculation and low calculation efficiency of traditional probability calculation. The probability-binary mixed calculation method achieves the calculation efficiency, accuracy and function equivalent to binary digital logic and circuit.

Description

Technical Field

[0001] The present invention relates to the fields of digital logic, artificial intelligence and integrated circuits, and in particular to a digital logic calculation method and processing device that mixes probability calculation and binary logic. Background Art

[0002] Binary numbers or Boolean logic are the mathematical basis of modern digital circuits, signal systems, etc. Each function of binary logic uses a logic algorithm to calculate the output value based on one or more inputs. The algorithm determines whether the output is true or false (1 true, 0 false, or vice versa) based on the combination of true and false inputs. Probabilistic (or "random") logic is implemented based on probability number representation, that is, the probability of a logic high level turning on (or "firing") when the pulse time is accumulated. It is a pseudo-analog quantity calculation method performed in the digital domain.

[0003] Probabilistic computing is a digital computing method that is widely used in numerical computing, digital circuits, digital communications and other fields. Compared with traditional binary number addition, subtraction, multiplication, division, square and other operations, probabilistic number computing has huge advantages in on-chip hardware resource consumption. The multipliers and adders required in high-bit binary number calculations require a large circuit area overhead. However, when using probability numbers instead of binary numbers for addition and multiplication operations, only one selector or logic gate is often required to realize the probabilistic pulse train addition and multiplication operations, which greatly reduces the on-chip logic resources required for the operation. Therefore, it is very suitable for brain-like computing engineering application fields with high computational overhead and stringent power consumption requirements.

[0004] In the traditional probability calculation method, the probability number multiplier only needs an AND gate (unipolar probability number) or an XOR gate (bipolar probability number) to be implemented. Although this implementation method is accurate for the calculation of the probability number pulse string itself (when the input sequences are unrelated), the probability number pulse string generated by the classic random number generator (SNG: stochastic number generator) is essentially a Bernoulli sequence that satisfies the binomial distribution. There will be an error between the binary number converted by the counter method and the original binary number. To achieve more accurate calculations, a longer sequence length is required to support it, and for every 1-bit increase in the binary number, the length of the probability number pulse string needs to be doubled to ensure the same accuracy, which greatly increases the number of cycles required for the calculation, that is, the calculation time is extended. Summary of the invention

[0005] The present invention proposes a hybrid probability logic calculation method and device, which integrates binary logic coding function based on the pulse train of traditional probability (random) calculation, thereby realizing probability-binary hybrid calculation.

[0006] The technology of probability-binary hybrid calculation includes its mathematical logic basis, the basic four arithmetic operations of addition, subtraction, multiplication and division of hybrid calculation, probability-binary conversion structure and method and device for complex polynomial fitting calculation.

[0007] The present invention proposes the following technical solutions:

[0008] On the one hand, the present application proposes a hybrid probability logic calculation method, comprising the following steps:

[0009] Decompose the value of the binary number d to be encoded with a bit width of n into a power series of 2, and use M binary numbers d0, d1, ..., d M-1 The value of is the coefficient, that is: d = 2 0 d 0+ 2 1 d1+...+2 M-1 d M-1 ;

[0010] The M binary numbers with a bit width less than n are compared with the random number sequence respectively to obtain M probability pulse trains s0(i), s1(i), ..., s M-1 (i), where i is the probability pulse number;

[0011] The M probability pulse strings are arranged from large to small according to the corresponding powers to form an M-bit parallel output probability pulse string combination, i.e., a mixed stream, as the code of the binary number d to be encoded;

[0012] Each parallel M-bit probability pulse represents a multi-bit binary number, and the average of multiple multi-bit binary numbers is used as the average of the mixed stream to represent the value of the binary number d to be encoded.

[0013] Furthermore, the two binary numbers a and b are encoded into independent mixed streams s a (i), s b (i);

[0014] Let the multi-bit binary numbers with the same sequence number of probability pulses in the two mixed streams be multiplied one by one to obtain a new mixed stream s c (i) = s a (i)s b (i); using the mean of the new mixed stream to represent the product of two binary numbers a and b;

[0015] Alternatively, the multi-bit binary numbers with the same sequence number of probability pulses in the two mixed streams are added one by one to obtain a new mixed stream s d (i) = s a (i)+s b(i); using the mean of the new mixed stream to represent the sum of two binary numbers a and b;

[0016] Alternatively, let the multi-bit binary numbers with the same sequence number of probability pulses in the two mixed streams be divided one by one to obtain a new mixed stream s c (i) = s a (i) / s b (i); Using the mean of the new mixed stream to represent the result of dividing two binary numbers a and b.

[0017] In a second aspect, the present application further proposes a hybrid probability logic device (A-type converter) for implementing the method described in the first aspect of the present application, comprising an input terminal, a random number generator, a comparator, and an output terminal;

[0018] Input terminal, used to decompose the binary number d to be encoded with a bit width of n into M binary numbers d0, d1, ..., d with a bit width less than n M-1 , satisfying d = 2 0 d 0+ 2 1 d1+...+2 M-1 d M-1 ;

[0019] A random number generator, used to generate M random number sequences;

[0020] A comparator is used to compare the M binary numbers with a bit width less than n with the random number sequence to obtain M probability pulse strings s0(i), s1(i), ..., s M-1 (i), where i is the probability pulse number;

[0021] The output end is used to arrange the M probability pulse strings from large to small according to the corresponding powers into an M-bit parallel output probability pulse string combination, that is, a mixed stream, as the code of the binary number d to be encoded.

[0022] Preferably, the M binary numbers with a bit width less than n have the same bit width; or, the binary numbers d0, d1, ..., d M-1 At least 2 of them have different bit widths.

[0023] Preferably, the comparator comprises a single-bit comparator for binary numbers with a bit width of 1; the single-bit comparator is composed of an inverter and a NOR gate, one input signal is connected to the input binary data, and the other input signal is connected to the random number generator.

[0024] In a third aspect, the present application also proposes a calculation method for mixed probability logic, comprising the following steps:

[0025] A first binary number A to be encoded with a bit width of M and a second binary number F to be encoded with a bit width of n are used to compare the second binary number F to be encoded with an n-bit random number sequence to generate a probability pulse string f(i); each bit in the probability pulse string f(i) is weighted by the first binary number A to be encoded to obtain M probability pulse strings, namely s0(i), s1(i), s2(i) and s M-1 (i); where i is the probability pulse number;

[0026] The M probability pulse trains are arranged in the bit order of the corresponding first binary number A to be encoded into an M-bit parallel output probability pulse train combination, i.e., a mixed stream, as a mixed code of the first binary number A to be encoded and the second binary number to be encoded;

[0027] Each parallel M-bit probability pulse represents a multi-bit binary number, and the average of multiple multi-bit binary numbers is used as the average of the mixed stream, which is used to represent the product of the first binary number A to be encoded and the second binary number F to be encoded.

[0028] In a fourth aspect, the present application further proposes a hybrid probability logic device (B-type converter) for implementing the method described in the third aspect of the present application, comprising a first input terminal, a second input terminal, a comparator, a weighter, and an output terminal;

[0029] A first input terminal, used for inputting a first to-be-encoded binary number A with a bit width of M;

[0030] A second input terminal, used for inputting a second binary number F to be encoded with a bit width of n;

[0031] A comparator, used for comparing the second binary number F to be encoded with an n-bit random number sequence to generate a probability pulse train f(i);

[0032] A weighter, used for the first binary number A to be encoded to weight each bit in the probability pulse string f(i) to obtain M probability pulse strings, namely s0(i), s1(i), s2(i) and s M-1 (i); where i is the probability pulse number;

[0033] The output end is used to arrange the M probability pulse strings into an M-bit parallel output probability pulse string combination according to the bit sequence of the corresponding first binary number A to be encoded, that is, a mixed stream, as a mixed code of the first binary number A to be encoded and the second binary number to be encoded.

[0034] Preferably, the n-bit random number sequence uses a linear pseudo-random sequence generator LFSR with a length of 2 n , and [0,2 n-1] each number appears once in the random number sequence.

[0035] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects:

[0036] The invention realizes the integration of binary logic coding function on the basis of traditional probabilistic (stochastic) computing (Stochastic Computing), thereby realizing probabilistic-binary hybrid computing (hybrid SC logic). The purpose of the invention is to solve the problems of long delay and inaccurate calculation in traditional probabilistic (stochastic) computing. The method realizes a low-delay, high-speed and high-precision probabilistic computing implementation method, completely improves the traditional probabilistic computing method, and solves the contradiction between high-precision and high-speed computing in probabilistic computing.

[0037] By using the A-type converter, the length of binary numbers encoded as a mixed stream is reduced to 1 / 2 compared to encoding them as a probability pulse train. M-1 , see attached for details Figure 1 ~5; At the same time, the type B converter of the probability calculation also has the function of an accurate multiplier calculation circuit. The multiplier calculation time extension is proportional to the binary bit width. For a parallel M-bit pulse stream, the accuracy of the calculation result is increased to 1 / 2 compared with the traditional probability calculation. M The calculation delay is as follows. Figures 6 to 8 As shown;

[0038] The probabilistic mixed logic calculation method proposed in the present invention is applicable to various numerical logic calculations, digital circuits and digital coding, including but not limited to polynomial fitting, matrix calculation, neural network, deep learning and communication coding, image, signal processing, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0040] Figure 1 Encoding process for mixed streams;

[0041] Figure 2(a) shows the operation flow of the mixed probability calculation multiplication unit, taking a 2-bit mixed stream input as an example;

[0042] FIG2( b ) is an embodiment 1 of the mixed probability calculation multiplication unit, taking a 2-bit mixed stream input as an example;

[0043] FIG2( c ) is an embodiment 2 of the mixed probability calculation multiplication unit, taking a 2-bit mixed stream input as an example;

[0044] Figure 3 A logic gate combination method for adding two multi-bit pulse streams;

[0045] Figure 4 A logic gate combination method for dividing two multi-bit pulse streams;

[0046] FIG5(a) is an A-type mixed probability calculation coding unit embodiment 1, parallel 2-bit mixed stream

[0047] FIG5(b) is a diagram of a type A mixed probability calculation coding unit embodiment 2, parallel 3-bit mixed stream

[0048] FIG5(c) is a diagram of a type A mixed probability calculation coding unit embodiment 3, parallel 5-bit mixed stream

[0049] Figure 6 An embodiment of a B-type mixing probability calculation coding unit;

[0050] Figure 7 To construct polynomial calculations using type B;

[0051] Figure 8 An example of the precise multiplier calculation process for probabilistic-binary mixed logic calculation is given. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present invention more clear, the specific implementation of the present invention will be described in detail below with reference to the accompanying drawings, wherein the formula structure and the device are shown in the form of a block diagram rather than in detail to avoid blurring the present invention.

[0053] The hybrid probability logic proposed in the present invention refers to the hybrid logic of probability and binary, involving a computing mechanism and system that mixes probability (random) logic and binary calculation, and more specifically, involves integrating binary logic encoding functions based on pulse trains based on traditional probability (random) calculations, thereby realizing probability-binary hybrid calculations. The technical solution includes its mathematical logic basis, the basic four arithmetic operations of addition, subtraction, multiplication and division of hybrid calculations, probability-binary conversion structure and complex polynomial fitting calculations, etc.

[0054] The calculation in this application refers to signal processing; the calculation method refers to a signal processing method. For example, the mixed probability logic calculation method refers to a mixed probability logic processing method implemented by a circuit or a computer program.

[0055] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0056] Boolean digital logic calculation is the foundation of the current hardware computing system. Whether it is digital circuits, signal processing or computer architecture, digital calculations are based on this. However, probabilistic (random) logic calculations are completely different from the above binary Boolean logic calculations. The specific details are as follows:

[0057] like Figure 1 As shown, the present application proposes a hybrid probability logic calculation method, comprising the following steps:

[0058] Step 101: Decompose the value of the binary number d to be encoded into M short-bit-width binary numbers d0, d1, ..., d M-1 The power series of 2 with coefficients, the binary numbers before and after decomposition satisfy the following relationship, d = 2 0 d 0+ 2 1 d1+...+2 M-1 d M-1 .

[0059] Step 102: Encode the M short-bit-width binary numbers into M probability pulse trains s0(i), s1(i), ..., s M-1 (i)

[0060] When M short-bit-width binary numbers are encoded into M probability pulse trains, an example is to compare the M short-bit-width binary numbers with the k-bit random number sequence to obtain M probability pulse trains s0(i), s1(i), ..., s M-1 (i), where k is greater than or equal to d0~d M-1 The maximum bit width.

[0061] Step 103: Arrange the M probability pulse trains in order according to the power sizes corresponding to them to obtain an M-bit parallel output probability pulse train combination, wherein each parallel M-bit probability pulse represents an M-bit binary number.

[0062] Multiple probability pulse trains are combined in parallel, where each parallel multi-bit probability pulse represents a binary number (referred to as a multi-bit binary number in this application), and this new data representation form is called a hybrid stream.

[0063] Step 104: Taking the average of the plurality of multi-bit binary numbers as the average of the mixed stream, representing the value of the binary number d to be encoded.

[0064] For example, for a mixed stream composed of M parallel probability pulse trains, if each M-bit binary number in the mixed stream is recorded and their mean is calculated, the obtained mean is approximately proportional to the binary number d to be encoded, that is, the expected value of the mixed stream is proportional to the binary number d. Similar to a single probability pulse train, when a mixed stream is used to represent a binary number d, the longer the length of the mixed stream, the higher the representation accuracy.

[0065] It should also be noted that, since the mixed flow of the present application is physically a group of pulse signals representing data, the mixed probability logic calculation method of the present application is applied in a digital circuit to form a mixed flow generation method for probability pulse calculation. The mixed probability logic device of the present application is a mixed flow generation device for realizing probability pulse calculation.

[0066] Figure 1 The hybrid stream coding and probabilistic pulse string coding generation methods are also compared. The prior art probabilistic pulse string generation method compares the n-bit binary number d with the n-bit uniformly distributed random number sequence one by one. If the binary number is greater than the random number, 1 is output, otherwise 0 is output. According to the comparison result, a probabilistic pulse string (Stochastic Bitstream) S consisting of 0 or 1 can be obtained respectively. The probability of the high level "1" of the probabilistic pulse string is P(S) = d / 2 n It can be seen that the hybrid stream coding significantly shortens the processing time length (1 / 2) compared with the probability pulse train coding through parallel output. M-1 ), thus significantly reducing circuit processing time.

[0067] Figures 2(a) to (c) include an embodiment and logic expression of the multiplication operation of two multi-bit pulse streams. When processing the multiplication operation of two binary numbers a and b, they are encoded into independent mixed streams, and each number in the two mixed streams is multiplied one by one. The product of the two mixed streams is realized by combining logic gates. The operation process can be described by s c (i) = s a (i) s b (i), (i = 1, 2, ..., N) means that each number in the mixed stream is subjected to a binary logic multiplication operation to obtain a new mixed stream output. During this operation, the mixed stream will follow the expected product law in probability statistics theory, E[S c ]=E[S a S b ]=E[S a ]E[S b ], realizing the multiplication operation of the expected value of the mixed stream. Figure 2 shows the specific process and two circuit structure examples of probability multiplication calculation when the mixed stream is a 2-bit stream. aThe mean value is equal to 16 / 8, S b The mean value is 11 / 8, and its two-bit product S c The mean is 22 / 8 = E[S a ]E[S b ], which is consistent with the expected theoretical value. To simplify the representation, the 2-bit mixed stream multiplier used in Figure 2(a) has two 2-bit mixed streams S a , S b ; Output is a 4-bit mixed stream S c To simplify the representation, each multi-bit binary number in the input and output mixed streams is represented by a decimal value. When a 2-bit multiplier is implemented using a gate circuit, the structure is shown in Figures 2(b) to (c); the expression of the multiplication logic relationship of the 2-bit mixed stream is also shown in Figures 2(b) to (c).

[0068] Figure 3 It is a logic gate combination method for adding two multi-bit pulse streams. When processing the addition operation of two binary numbers a and b, they are first encoded into a mixed stream, and each number in the two mixed streams is added one by one. The output mixed stream follows the expected addition relationship, E[S d ]=E[S a +S b ]=E[S a ]+E[S b ], that is, the addition operation of the mixed stream is completed. Similar to the multiplier, when the pulse string of the random variable is a multi-bit pulse stream, the addition of the two pulse streams is achieved through a composite logic gate. Figure 3 The mixing probability calculation addition unit in is taken as an example of 2-bit mixed stream input. Here, the 2-bit stream S a The mean value is equal to 15 / 8, S b The mean of the two bit streams is 13 / 8, and the result of the addition of the two bit streams is S d The mean is 28 / 8 = E[S a ]+E[S b ], which is consistent with the calculated theoretical value of mathematical expectation.

[0069] Figure 4 The logic gate combination method for dividing two multi-bit pulse streams is presented. When processing the division operation of two binary numbers a and b, they are first encoded into a mixed stream. The division operation of two mixed streams is the inverse operation of multiplication. The output mixed stream follows the expected operation relationship, E[S c ]E[S b ]=E[S a ], that is, E[S c ]=E[S a ] / E[S b], completing the division operation of the mixed stream. The circuit structure includes a multiplier and an accumulative counter, and its calculation accuracy is positively correlated with the accumulated length of the pulse string.

[0070] The coding circuit that converts an n-bit binary number into an M-bit mixed stream is called an A-type coding unit. The decomposed short-bit width binary number is compared with the random number generator (RNG) to generate M probability pulse trains, namely s0(i), s1(i), ..., s M-1 (i). For an n-bit binary number x, it is converted into a mixed stream, that is, based on the attached Figure 1 In order to implement the hybrid stream coding method, we provide some implementation examples of type A coding units, as shown in Figures 5(a) to (c).

[0071] A hybrid probability logic device as a type A coding unit, used to generate a hybrid stream, comprising:

[0072] Input terminal, used to decompose the binary number d to be encoded with a bit width of n into M binary numbers d0, d1, ..., d with a bit width less than n M-1 , satisfying d = 2 0 d 0+ 2 1 d1+...+2 M-1 d M-1 ;

[0073] A random number generator, used to generate M random number sequences;

[0074] A comparator is used to compare the M binary numbers with a bit width less than n with the random number sequence to obtain M probability pulse strings s0(i), s1(i), ..., s M-1 (i), where i is the probability pulse number;

[0075] The output end is used to arrange the M probability pulse strings from large to small according to the corresponding powers into an M-bit parallel output probability pulse string combination, that is, a mixed stream, as the code of the binary number d to be encoded.

[0076] Preferably, the M binary numbers with a bit width less than n have the same bit width; or, the binary numbers d0, d1, ..., d M-1 At least 2 of them have different bit widths.

[0077] As an embodiment of the A-type encoding unit, if there are continuous 0s in the low bits of the short bit width number, the bit widths of the random number and the short bit width number can be reduced synchronously, according to the number of continuous 0s in the low bits. For example, the comparison between (1000) and a 4-bit random number can be reduced to the comparison between (1) and a 1-bit random number. The specific circuit structure is shown in FIG5(a). The low (n-1)-bit of the binary number x, x0~x n-2Compare with (n-1)-bit random number generator (RNG) to generate 2 0 Weighted probability pulse train s0(i), the most significant bit x n-1 Compare with 1-bit RNG to generate 2 1 Weighted probability pulse train s1(i). ;

[0078] The single-bit comparator is composed of an inverter and a NOR gate. One input signal is connected to the input binary data, and the other input signal is connected to the random number generator. In addition, we also give the circuit structure of two other grouping methods, which encodes the 6-bit binary number into a 3-bit and 5-bit mixed stream. See the attached Figure 5(b) , 5(c) .

[0079] As a second embodiment of the A-type coding unit, FIG. 5(b) decomposes a 5-bit binary number x into three 4-bit binary numbers weighted by a power series of 2, x = [x500x2]22 2 +[x400x1]22 1 +[x300x0]22 0 , respectively compared with the 4-bit RNG to obtain a 3-bit mixed stream, E[S] = x / 2 4 , E[S] represents the expected value of the mixed flow.

[0080] As a third embodiment of the A-type coding unit, FIG. 5(c) decomposes a 5-bit binary number x into three 2-bit binary numbers weighted by a power series of 2, x = [x5x4]22 4 +0×2 3 +[x3x2]22 2 +0×2 1 +[x1x0]22 0 , respectively compared with the 2-bit RNG to obtain a 5-bit mixed stream, where s3(i)=s1(i)=0, E[S]=x / 2 2 .

[0081] On the other hand, in order to realize the multiplication operation, the present application also proposes another mixed probability logic calculation method, which performs mixed encoding on a first binary number A to be encoded with a bit width of M and a second binary number F to be encoded with a bit width of n, comprising the following steps:

[0082] Step 201, compare the second binary number to be encoded F with an n-bit random number sequence to generate a probability pulse train f(i);

[0083] Step 202: Use the first binary number A to be encoded to weight each bit in the probability pulse string f(i) to obtain M probability pulse strings, namely s0(i), s1(i), s2(i) and s M-1 (i); where i is the probability pulse number;

[0084] Step 203, the M probability pulse strings are arranged in the order of the bits of the corresponding first binary number A to be encoded into an M-bit parallel output probability pulse string combination, i.e., a mixed stream, as a mixed code of the first binary number A to be encoded and the second binary number F to be encoded;

[0085] Step 204: each parallel M-bit probability pulse in the mixed stream represents a multi-bit binary number, and the average of multiple multi-bit binary numbers is used as the average of the mixed stream to represent the product of the first binary number A to be encoded and the second binary number F to be encoded.

[0086] To implement the method of steps 201 to 204, we provide another encoding circuit unit, called a B-type encoding unit, such as Figure 6 As shown, a circuit for converting two binary numbers (n-bit and M-bit, respectively) into a multi-bit probability pulse stream is realized. A hybrid probability logic device is used to generate a hybrid stream, comprising two modules, a probability pulse train encoding circuit and a weighting circuit, which are connected to each other. The expectation of outputting the hybrid stream follows the basic mathematical relationship, E[S] = A·E[F] = A·F / 2 n ; wherein the probability pulse string encoding circuit includes a first input terminal, a second input terminal, and a comparator; the weighting circuit includes a weighter and an output terminal.

[0087] A first input terminal, used for inputting a first to-be-encoded binary number A with a bit width of M;

[0088] A second input terminal, used for inputting a second binary number F to be encoded with a bit width of n;

[0089] A comparator, used for comparing the second binary number F to be encoded with an n-bit random number sequence to generate a probability pulse train f(i);

[0090] A weighter, used for the first binary number A to be encoded to weight each bit in the probability pulse string f(i) to obtain M probability pulse strings, namely s0(i), s1(i), s2(i) and s M-1 (i); where i is the probability pulse number;

[0091] The output end is used to arrange the M probability pulse strings into an M-bit parallel output probability pulse string combination according to the bit sequence of the corresponding first binary number A to be encoded, that is, a mixed stream, as a mixed code of the first binary number A to be encoded and the second binary number to be encoded.

[0092] For the expectation of binary numbers E[A]=y, the expectation of the mixed flow follows the basic mathematical relationship:

[0093] like Figure 7 , based on the quadratic polynomial calculation of mixed probability calculation, in this method, the polynomial uses z = x 2 +y 2 -2x+xy to meet different calculation conditions such as multiplication accumulation and self-multiplication. When the B-type coding unit completes the mixed probability stream coding, it also completes a multiplication operation at the same time. Therefore, when implementing the first multiplication of the polynomial, BN-SB (B-type) can be used as a multiplier that uses two binary inputs to output a probability stream. The advantage of this special usage is more prominent when operating quadratic polynomials, because quadratic polynomials have only one multiplication in each monomial. When processing Figure 7 When the quadratic polynomial is shown, z = x 2 +y 2 -2x+xy, x and y are M-bit data. Binary operations require four M-bit multipliers and three 2 M The mixed probability calculation circuit of this scheme only needs four BN-SB converters and three M-bit adders to realize its multiplication and accumulation calculation. It can be understood that when used to calculate x 2 When two x are input into the first input and the second input respectively; when used to calculate y 2 When calculating xy, input x and y into the first input terminal and the second input terminal respectively; when calculating 2x, input 2 and x into the first input terminal and the second input terminal respectively. Finally, add the output data of multiple converters.

[0094] In order to achieve the same calculation accuracy, the pulse stream length of hybrid logic calculation is lower than that of traditional single-bit stream. When converting the n-bit binary number x into an (M+1)-bit probability pulse stream, each bit stream in the (M+1) bit stream has an accuracy of (nM) bits, that is, the pulse string length is N=2 n-M -1 is sufficient to represent x. However, for conventional SC, a single-bit probability pulse stream of N = 2 is required n -1 length.

[0095] For the proposed hybrid logic pulse flow, when M = 0, the hybrid logic flow is the classic probability calculation. This is an extreme case with the lowest hardware occupancy but the longest delay. When M = n-1, the hybrid logic flow is converted to binary numbers. This is another extreme case with the best delay and maximum hardware occupancy. With this hybrid logic, latency and hardware occupancy can be traded off instead of choosing two extreme cases.

[0096] At the same time, the accurate multiplier calculation circuit structure of the mixed probability calculation, that is, the multiplication operation is realized by using type B, and its characteristic is that the multiplier calculation delay is negatively correlated with the mixed stream bit width. For the M-bit pulse stream, the delay required to obtain the accurate calculation result is reduced to 1 / 2 of the traditional probability calculation. M . Type B converter, the value corresponding to the output multi-bit mixed stream is the product of the two input binary numbers A and F. In the conversion process, the error only comes from the encoding of the probability pulse string f(i), and the weighting of the probability pulse string by another binary number A does not produce errors. In the encoding process of f(i), if an n-bit pseudo-random number sequence is used, such as LFSR, its period is equal to 2 n , and [0,2 n -1] will appear once in the random number sequence. So when the length of f(i) is 2 n When , there is no error in the encoding of f(i), the type B converter will output an accurate mixed stream, that is, it can achieve accurate probability calculation multiplication function. Figure 8 An example of applying a type B coding circuit to perform precise multiplication operations, where both input data are 3-bit binary data. In the encoding process of f(i), a 3-bit pseudo-random number sequence is used, whose period is equal to 8, and each number in [0,7] appears once in the random number sequence. Therefore, when the length of f(i) is 8, there is no error in the encoding of f(i), and the value (5 / 8) can be accurately represented. At this time, the type B converter will output an accurate multi-bit pulse stream, representing the product of the two inputs (15 / 8), that is, an accurate probability calculation multiplication function is realized.

[0097] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity or device including the element.

[0098] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A method for calculating mixed probabilistic logic, characterized in that: The following steps are involved: The input end decomposes the value of the binary number d to be encoded with a bit width of n into a power series of 2, with M binary numbers d0, d1, ..., d M-1 The value of is the coefficient, that is: d = 2 0 d 0+ 2 1 d1+...+2 M-1 d M-1 ; The comparator compares the M binary numbers with a bit width less than n with the random number sequence respectively to obtain M probability pulse trains s0(i), s1(i), ..., s M-1 (i), where i is the probability pulse number; The output end arranges the M probability pulse strings from large to small according to the corresponding powers into an M-bit parallel output probability pulse string combination, that is, a mixed stream, as the code of the binary number d to be encoded; Each parallel M-bit probability pulse represents a multi-bit binary number, and the average of multiple multi-bit binary numbers is used as the average of the mixed stream to represent the value of the binary number d to be encoded.

2. A mixed probability logic calculation method as claimed in claim 1, characterized in that: The following steps are involved: Encode two binary numbers a and b into independent mixed streams s a (i), s b (i); Let the multi-bit binary numbers with the same sequence number of probability pulses in the two mixed streams be multiplied one by one to obtain a new mixed stream s c (i) = s a (i)s b (i); The product of two binary numbers a and b is represented by the mean value of the new mixed stream.

3. A mixed probability logic calculation method as claimed in claim 1, characterized in that: The following steps are involved: Encode two binary numbers a and b into independent mixed streams s a (i), s b (i); Let the multi-bit binary numbers with the same sequence number of probability pulses in the two mixed streams be added one by one to obtain a new mixed stream s d (i) = s a (i)+s b (i); The sum of two binary numbers a and b is represented by the mean value of the new mixed stream.

4. A mixed probability logic calculation method as claimed in claim 1, characterized in that: Encode two binary numbers a and b into independent mixed streams s a (i), s b (i); Divide the multi-bit binary numbers with the same sequence number of probability pulses in the two mixed streams one by one to obtain a new mixed stream s c (i) = s a (i) / s b (i); The result of dividing two binary numbers a and b is represented by the mean value of the new mixed stream.

5. A hybrid probabilistic logic device, used to implement the method of claim 1, characterized in that: It includes input terminal, random number generator, comparator and output terminal; Input terminal, used to decompose the binary number d to be encoded with a bit width of n into M binary numbers d0, d1, ..., d with a bit width less than n M-1 , satisfying d = 2 0 d 0+ 2 1 d1+...+2 M-1 d M-1 ; A random number generator, used to generate M random number sequences; A comparator is used to compare the M binary numbers with a bit width less than n with the random number sequence to obtain M probability pulse strings s0(i), s1(i), ..., s M-1 (i), where i is the probability pulse number; The output end is used to arrange the M probability pulse strings from large to small according to the corresponding powers into an M-bit parallel output probability pulse string combination, that is, a mixed stream, as the code of the binary number d to be encoded.

6. The hybrid probabilistic logic device according to claim 5, characterized in that: The M binary numbers whose bit width is smaller than n have the same bit width; or, The binary numbers d0, d1, ..., d M-1 At least 2 of them have different bit widths.

7. The hybrid probabilistic logic device according to claim 6, characterized in that: The comparator comprises a single-bit comparator for a binary number with a bit width of 1; The single-bit comparator is composed of an inverter and a NOR gate, one input signal is connected to the input binary data, and the other input signal is connected to the random number generator.

8. A method for calculating mixed probability logic, characterized in that: The following steps are involved: A first binary number A to be encoded with a bit width of M at the first input terminal and a second binary number F to be encoded with a bit width of n at the second input terminal are used, and a comparator compares the second binary number F to be encoded with an n-bit random number sequence to generate a probability pulse string f(i); a weighter uses the first binary number A to be encoded to weight each bit in the probability pulse string f(i) to obtain M probability pulse strings, namely s0(i), s1(i), s2(i) and s M-1 (i); Where i is the probability pulse number; The output end arranges the M probability pulse strings according to the bit sequence of the corresponding first binary number A to be encoded into an M-bit parallel output probability pulse string combination, that is, a mixed stream, as a mixed code of the first binary number A to be encoded and the second binary number to be encoded; Each parallel M-bit probability pulse represents a multi-bit binary number, and the average of multiple multi-bit binary numbers is used as the average of the mixed stream, which is used to represent the product of the first binary number A to be encoded and the second binary number F to be encoded.

9. A hybrid probabilistic logic device, used to implement the method of claim 8, characterized in that: It comprises a first input terminal, a second input terminal, a comparator, a weighter, and an output terminal; A first input terminal, used for inputting a first to-be-encoded binary number A with a bit width of M; A second input terminal, used for inputting a second binary number F to be encoded with a bit width of n; A comparator, used for comparing the second binary number F to be encoded with an n-bit random number sequence to generate a probability pulse train f(i); A weighter, used for the first binary number A to be encoded to weight each bit in the probability pulse string f(i) to obtain M probability pulse strings, namely s0(i), s1(i), s2(i) and s M-1 (i); Where i is the probability pulse number; The output end is used to arrange the M probability pulse strings into an M-bit parallel output probability pulse string combination according to the bit sequence of the corresponding first binary number A to be encoded, that is, a mixed stream, as a mixed code of the first binary number A to be encoded and the second binary number to be encoded.

10. The hybrid probabilistic logic device according to claim 9, characterized in that: The n-bit random number sequence uses a linear pseudo-random sequence generator LFSR with a length of 2 n , and [0,2 n -1] each number appears once in the random number sequence.

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