A superconducting binary neural network acceleration method and accelerator
Through the use of superconducting RSFQ logic and new two -value representation methods in the BNN accelerator, the high performance and low energy consumption computing of BNN is realized, and the performance and energy efficiency restrictions implemented by the existing CMOS are solved.
Patent Information
- Application Number
- CN202210513312.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-11
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2042-05-11
AI Technical Summary
The BNN inference accelerator implemented by existing CMOS has limitations in terms of performance and energy efficiency, and it is difficult to meet the needs of high-performance computing.
Adopting a BNN accelerator design based on superconducting RSFQ logic, a new binary representation method is proposed, so that the first layer of BNN can also perform binary calculations, and the popcount operation is implemented through pure combination accumulation parallel units to avoid feedback loops and storage circuit.
It has significantly improved the performance and energy efficiency of the superconducting BNN, which has increased by 3 orders of magnitude compared to traditional CMOS.
Smart Images
Figure CN114841102B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of superconducting fast single flux quantum RSFQ and neural network calculation, and in particular to a superconducting binary neural network acceleration method and an accelerator. Background Art
[0002] Superconducting single flux quantum (SFQ) circuit technology is listed by ITRS as a promising next-generation integrated circuit technology. Superconducting RSFQ circuit is a type of SFQ circuit with ultra-high speed and ultra-low power consumption. Research has confirmed that simple RSFQ circuits made with submicron Josephson junction technology can operate at a maximum frequency of 770GHz, a high speed that is difficult to achieve with semiconductor integrated circuits. Under the same process conditions, the logic gate delay and bit operation power consumption in the RSFQ circuit are two orders of magnitude lower than those of the corresponding semiconductor circuits.
[0003] The most basic device in the RSFQ circuit is a superconducting ring composed of a Josephson junction (JJ), which is a switching element. Unlike CMOS circuits, the storage component of the RSFQ circuit is an inductor rather than a capacitor. The magnetic flux in the superconducting ring is quantized as Φ = n * Φ0, where Φ0 = 2.07 × 10 -15 Wb. Information is stored in the form of flux quanta and transmitted in the form of SFQ voltage pulses. The presence of the pulse represents a logical "1", and the absence represents a logical "0". Unlike CMOS circuits, in RSFQ logic, almost all logic gates require clock signals to propagate the stored flux quanta to the output. Since an RSFQ logic gate can be regarded as a first-level pipeline, the RSFQ circuit is a fully gate-level pipeline circuit. Logic depth refers to the number of levels of clocked logic gates.
[0004] Binarized Neural Network (BNN) is a neural network that is quantized to the extreme and can be deployed on devices with limited resources. In BNN, both activation and weight are represented by 1 bit, which greatly saves storage capacity and computation. In order to quantize the real-valued weight or activation variable x to 1 bit, the Sign(x) function is often used to achieve binarization:
[0005]
[0006] Among them, x b Is the binary value corresponding to the real-valued weight or activation variable x. The nonlinear activation function f in the full-precision convolutional neural network can be expressed as:
[0007]
[0008] In BNN, except for the first layer, the activations and weights of neurons in the remaining layers have only two possible values, namely -1 or +1. Therefore, the product and sum between weights and activations in equation (2) can be replaced by logical exclusive-OR (XNOR) operations and popcount operations. The function of the popcount operation is to count the number of 1s in a data vector. Moreover, the final result can be obtained by comparing popcount with a trained threshold μ, and the threshold μ is obtained through training, so the threshold μ of each layer is not necessarily the same. Therefore, for a BNN, equation (2) becomes:
[0009]
[0010] In formula 2, w and x are float32 floating point numbers (decimal numbers), and w in formula 3 is b and x b Represents w and x after binarization, that is, w b and x b They are all 1-bit numbers (0 or 1), and b stands for binarized.
[0011] In order to implement BNN using hardware, many studies have proposed BNN reasoning accelerators based on FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit). However, these designs are all based on traditional CMOS implementation, and the maximum performance and energy efficiency that can be achieved are limited. Summary of the invention
[0012] In view of the shortcomings of the prior art, the present invention proposes a BNN inference accelerator design based on superconducting RSFQ logic, and proposes a new binary representation method, so that the first layer in the BNN can also perform binary calculations without losing accuracy; the present invention also proposes to use a pure combinatorial accumulative parallel counter (APC) based on superconducting unique logic units to implement popcount operations, avoiding the feedback loop and storage circuit in the traditional popcount design, which can effectively improve the performance and energy efficiency of superconducting BNNs.
[0013] Specifically, the present invention proposes a superconducting binary neural network acceleration method, comprising:
[0014] Step 1: Obtain all real-valued weights and real-valued activations of the first layer of the neural network to be run as current weights and current activations, respectively, and binarize the current weights and current activations to obtain binary weights and binary activations;
[0015] Step 2: input the data pairs consisting of all the binary weights and their corresponding binary activations into a plurality of XNOR gates in the neural processing unit to perform multiplication operations on each data pair;
[0016] Step 3: All multiplication results are accumulated through a pure combination accumulation parallel unit, and the accumulated result and the preset threshold are input to the comparator, and the comparison result is used as the binary activation of the next layer;
[0017] Step 4: Obtain the real-valued weight of the next layer as the current weight, binarize the current weight, and use the binary activation obtained in step 3 as the current activation, and execute step 3 until the comparison result of the last layer of the superconducting binary neural network is obtained as the operation result of the superconducting binary neural network.
[0018] The superconducting binary neural network acceleration method, wherein the binarization process is completed by the following formula:
[0019]
[0020] where x b is the binary value corresponding to the real-valued weight or activation variable x.
[0021] The superconducting binary neural network acceleration method, wherein the pure combination accumulation parallel unit includes a superconducting approximation unit and a superconducting parallel counter;
[0022] The superconducting approximation unit is composed of a column of superconducting OR-AND gate pairs to reduce the input data bit width; the superconducting parallel counter is composed of cascaded superconducting full adders, and the superconducting full adder includes a T1 trigger, a CB3 unit, a D trigger and a separation unit.
[0023] The superconducting binary neural network acceleration method, wherein the input of the superconducting full adder is the value to be summed A, the value to be summed B, the carry C and the clock CLK, and the output is the sum result Sum and the carry Carry; CLK is connected to the rd port of the T1 trigger and the clock port of the D trigger through the separation unit; A, B, C are logically OR-operated through the CB3 unit, the output result is connected to the data input end of the T1 trigger, the output of the T1 trigger is connected to the data input end of the D trigger, and finally the carry Carry of the full adder is obtained from the output end of the D trigger, and the sum result Sum of the full adder is obtained from the sum end of the T1 trigger.
[0024] The present invention also proposes a superconducting binary neural network accelerator, which includes:
[0025] The initial module is used to obtain all the real-valued weights and real-valued activations of the first layer of the neural network to be run as the current weights and current activations, respectively, and binarize the current weights and current activations to obtain binary weights and binary activations;
[0026] An XNOR module, used for inputting data pairs consisting of all the binary weights and their corresponding binary activations into a plurality of XNOR gates in the neural processing unit to perform a multiplication operation on each data pair;
[0027] An accumulation module, used for accumulating all multiplication results through a pure combinational accumulation parallel unit, inputting the accumulation result and a preset threshold into a comparator, and using the comparison result as a binary activation of the next layer;
[0028] The loop module is used to obtain the real-valued weight of the next layer as the current weight, binarize the current weight, and use the binary activation obtained in step 3 as the current activation, and call the accumulation module again until the comparison result of the last layer of the superconducting binary neural network is obtained as the operation result of the superconducting binary neural network.
[0029] The superconducting binary neural network accelerator, wherein the binarization process is completed by the following formula:
[0030]
[0031] where x b is the binary value corresponding to the real-valued weight or activation variable x.
[0032] The superconducting binary neural network accelerator, wherein the pure combination accumulation parallel unit includes a superconducting approximation unit and a superconducting parallel counter;
[0033] The superconducting approximation unit is composed of a column of superconducting OR-AND gate pairs to reduce the input data bit width; the superconducting parallel counter is composed of cascaded superconducting full adders, and the superconducting full adder includes a T1 trigger, a CB3 unit, a D trigger and a separation unit.
[0034] The superconducting binary neural network accelerator, wherein the input of the superconducting full adder is a value to be summed A, a value to be summed B, a carry C and a clock CLK, and the output is a sum result Sum and a carry Carry; CLK is connected to the rd port of the T1 trigger and the clock port of the D trigger through the separation unit; A, B, and C are logically OR-operated through the CB3 unit, and the output result is connected to the data input end of the T1 trigger, and the output of the T1 trigger is connected to the data input end of the D trigger, and finally the carry Carry of the full adder is obtained from the output end of the D trigger, and the sum result Sum of the full adder is obtained from the sum end of the T1 trigger.
[0035] The present invention also proposes a storage medium for storing a program for executing any one of the superconducting binary neural network acceleration methods.
[0036] The present invention also proposes a client for use with any of the superconducting binary neural network accelerators.
[0037] It can be seen from the above scheme that the advantages of the present invention are:
[0038] The superconducting BNN accelerator design proposed in this invention can improve the performance and energy efficiency by three orders of magnitude compared to traditional CMOS BNN accelerators. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 This is a structural diagram of the superconducting RSFQ BNN accelerator proposed in the present invention;
[0040] Figure 2 This is a structural diagram of the 16-bit RSFQAPC that satisfies path balance proposed by the present invention. DETAILED DESCRIPTION
[0041] In order to implement an efficient BNN accelerator using RSFQ logic, several specific challenges need to be overcome. One challenge is how to design an accumulator using superconducting logic, because RSFQ logic has ultra-deep pipeline characteristics, and the accumulator requires a feedback loop to implement the accumulation operation, which can lead to significant performance degradation. Because the next clock pulse needs to wait for a long data transmission delay through the feedback path. In addition, superconducting memory has weak driving capability and poor scalability, so it is also difficult to implement on-chip storage using superconducting RSFQ logic. Specifically, the present invention includes the following key technical points:
[0042] Key point 1: New binary representation method. Based on the traditional use of functions for binarization, a new binarization function is proposed. Under this representation, the first layer of BNN can also use binary values for reasoning without losing accuracy.
[0043] Key point 2, superconducting RSFQ binary neural network accelerator structure. A purely combinatorial BNN accelerator architecture is designed based on superconducting RSFQ logic. This architecture uses the gate-level pipeline characteristics of superconducting RSFQ logic and has a pipelined neural processing unit without the need to include feedback loops and storage units.
[0044] Key point 3, the implementation method of popcount operation based on superconducting RSFQ logic. First, the superconducting full adder (FA) is implemented based on the T1 gate, CB3 gate, Splitter gate and trigger unique to superconducting RSFQ logic. Then, a divide-and-conquer strategy is adopted to merge low-bit-width APCs into high-bit-width APCs. The subtraction and binarization operations of the accumulated result and the training threshold are implemented through the comparator.
[0045] Key point 4, the analytical formula for the number of pipeline stages and JJ numbers of APC. The number of pipeline stages and JJ numbers of APCs with different bit widths can be directly calculated based on the formula.
[0046] In order to make the above features and effects of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.
[0047] 1. New binary representation method
[0048] The BNN model uses binary weights and activations, so its multiplication and addition calculations are transformed into binary multiplication and addition operations that can be implemented in a highly hardware-friendly manner. The multiplication operation can be implemented through an XNOR gate, and the addition operation can be implemented through a popcount operation. The binary method of the traditional BNN is shown in equation (1). Based on it, the new representation method (denoted as SN) proposed in the present invention is as follows:
[0049]
[0050] As shown in Table 1, under the SN representation method, binary multiplication operations can still be implemented using XNOR gates. For addition operations:
[0051]
[0052] Table 1 Multiplication under SN representation (⊙ in the table represents XOR operation)
[0053]
[0054]
[0055] If x is a decimal greater than or equal to 0, the results of Formula 4 and Formula 1 are the same, both are x b = 1. If x is a decimal less than 0, in formula 1, the value x after x is binarized is b =-1, the result x after binarization in formula 4 b=0. After binarization using Formula 4, the first layer of BNN can also be calculated using the binarized activations and weights. If binarization is performed using Formula 1, in order to ensure the accuracy of the network, the first layer of BNN must be calculated using floating-point activations and weights. However, the area overhead of floating-point multiplication implemented in hardware is very large, so the methods before the present invention all put the second and subsequent layers of BNN on the accelerator to run, and the first layer is still run on the CPU, that is, the first layer is not accelerated.
[0056] 2. Superconducting BNN Accelerator Architecture Design
[0057] The ultra-high frequency characteristics of superconducting RSFQ circuits give them considerable advantages in tasks with high computational requirements. Considering the storage limitations of RSFQ circuits, the present invention combines the high frequency characteristics of RSFQ circuits and the low storage requirements of BNNs to propose a BNN accelerator architecture based on superconducting RSFQ logic, such as Figure 1 shown.
[0058] First, the weight w and neuron activation x need to be binarized by equation (4), so that all operations of the entire network are calculated bit by bit, avoiding the extra computational cost caused by the non-binarized calculation of the first layer in the traditional BNN. Then, the binarized weights and activation values are alternately input into the neural processing unit, such as Figure 1 As shown in the figure, the activation value x[i] and the weight w[i] (1≤i≤n) enter the network alternately. Then the neural processing unit completes the multiplication operation through a column of XNOR gates, implements the accumulation operation through APC, and implements the subtraction and binarization operation of the training threshold through the comparator. The output of the current layer is the input of the next layer, and the output of the current layer is already a binary value, which is directly used as the activation input of the next layer.
[0059] 3. Implementation method of popcount operation based on superconducting RSFQ logic
[0060] The present invention uses the basic logic unit in the SFQ circuit to implement the popcount operation based on APC. In order to ensure the path balance requirement of the superconducting RSFQ circuit, a superconducting trigger is inserted into the APC circuit. The RSFQAPC that can calculate the number of 1s in the input 16-bit binary number that satisfies the path balance is as follows: Figure 2 It consists of a layer of superconducting approximate units (AU) and a superconducting parallel counter (PC). One layer of AU is composed of a column of superconducting OR-AND gate pairs, which can reduce the input data bit width by half, as shown in Figure 1. Figure 2As shown in Figure 1, the superconducting PC is composed of cascaded superconducting full adders FA. However, if the full adder design of CMOS logic is directly implemented using the functionally equivalent RSFQ logic gates, the efficiency is low. This is because in CMOS logic, a full adder requires at least five gates to implement.
[0061] Therefore, the present invention proposes to implement a full adder based on a unit unique to RSFQ logic. Specifically, the RSFQ full adder is implemented using four RSFQ gates: a T1 flip flop, a CB3 gate (Confluence Buffer 3), a D flip flop, and a splitter gate, such as Figure 2 As shown. For the sake of clarity, the full adder symbol in the figure omits the clock port (CLK). The full adder has three data input ports, namely A, B, and C (indicating carry), one clock input port CLK; two output ports Sum and Carry, Sum represents sum, and Carry represents carry. The clock signal CLK passes through a separation unit ( Figure 2 The SPL in the D flip-flop is connected to the rd port of T1 and the clock port of the D flip-flop. The three data inputs A, B, and C of the full adder are logically ORed through the CB3 unit, and the output result is connected to the data input terminal (t) of the T1 flip-flop. The output (out) of the T1 flip-flop is connected to the data input terminal (data) of the D flip-flop. Finally, the carry output (Carry) of the full adder is obtained from the output terminal (out) of the D flip-flop, and the sum (Sum) of the full adder is obtained from the sum terminal of the T1 flip-flop.
[0062] 4. APC pipeline series analytical formula
[0063] In a superconducting RSFQ circuit, almost all logic gates are driven by a clock, so the RSFQ circuit is also called a gate-level pipeline circuit. The number of pipeline stages in the APC determines the effective frequency of the RSFQ BNN. In order to calculate the number of pipeline stages of the APC, first calculate the number of full adders f(V) required for the APC with N-bit input.
[0064] For N-bit input, RSFQAPC of V-bit output (N=2 V ), the number of full adders is:
[0065]
[0066] The PC in RSFQAPC is designed based on a divide-and-conquer strategy: given 2 l-input PCs, the (2l+1)-input PC can utilize the 2 l-input PCs and Similarly, the 2 (2l+1) input PC and The PC with (4l+3) inputs can be realized by using ripple carry adders. This process is repeated until the PC input is ≥ N-1. For example, when l=3, only one FA is needed, so the number of pipeline stages is 1; when l=7, the number of ripple carry adder stages required is Therefore, a total of 3 pipeline stages are required; when l = 15, a total of The number of pipeline stages.
[0067] In summary, the number of pipeline stages s(l) contained in a PC with l inputs is:
[0068]
[0069] Where l = 2 V -1. In the proposed N-input RSFQAPC, N / 2 superconducting OR gates and AND gates, f(V) full adders are included, where N=2 V By replacing the (l+1) term in equation (7) with N / 2, the number of pipeline stages included in RSFQAPC replaces S(N) as:
[0070]
[0071] The last term “+1” in equation (8) is because the first layer of the APC is an AU consisting of superconducting OR gates and AND gates.
[0072] 5. Area analytic formula for superconducting BNN accelerator
[0073] The area of the RSFQ circuit is usually expressed in JJ complexity. JJ complexity indicates the number of JJs required for a logic block. Although a logic block consists of logic gates and transmission lines, the present invention evaluates the system-level JJ complexity by only calculating the JJ complexity of the gates. This is because passive transmission lines (PTLs) without JJs are widely used in the wiring of RSFQ circuits, so the JJ complexity of the transmission lines can be ignored.
[0074] The JJ complexity of the gate GATE ) is equal to the JJ complexity of AU (JJ AU ), the JJ complexity of the full adder (JJ FA ), and the JJ complexity of DFF for path balancing (JJ PB_DFF ), as shown below:
[0075] JJ GATE =JJ AU +JJ FA +JJ PB_DFF (9)
[0076] If the JJ complexity of each gate in the superconducting process library is known, JJ AU and JJ FA It is easy to calculate. Therefore, the following will focus on JJ PB_DFF The calculation method of .
[0077] As mentioned above, RSFQAPC is designed based on the divide-and-conquer strategy. For a PC with l inputs, the number of path-balanced DFFs d(l) that need to be inserted is:
[0078]
[0079] Substituting equation (7) into equation (10), d(l) can be expressed as:
[0080]
[0081] Therefore, the number of DFFs D(N) that need to be inserted in the entire APC can be calculated using the following recursive formula:
[0082]
[0083] If the superconducting open source library MIT-LL SFQ is used, the JJ complexity of each gate is shown in Table 1, and the JJ complexity of the gate is:
[0084]
[0085] Table 1 JJ complexity of logic units in MIT-LL RSFQ library
[0086]
[0087] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiment.
[0088] The present invention also proposes a superconducting binary neural network accelerator, which includes:
[0089] The initial module is used to obtain all the real-valued weights and real-valued activations of the first layer of the neural network to be run as the current weights and current activations, respectively, and binarize the current weights and current activations to obtain binary weights and binary activations;
[0090] An XNOR module, used for inputting data pairs consisting of all the binary weights and their corresponding binary activations into a plurality of XNOR gates in the neural processing unit to perform a multiplication operation on each data pair;
[0091] An accumulation module, used for accumulating all multiplication results through a pure combinational accumulation parallel unit, inputting the accumulation result and a preset threshold into a comparator, and using the comparison result as a binary activation of the next layer;
[0092] The loop module is used to obtain the real-valued weight of the next layer as the current weight, binarize the current weight, and use the binary activation obtained in step 3 as the current activation, and call the accumulation module again until the comparison result of the last layer of the superconducting binary neural network is obtained as the operation result of the superconducting binary neural network.
[0093] The superconducting binary neural network accelerator, wherein the binarization process is completed by the following formula:
[0094]
[0095] where x b is the binary value corresponding to the real-valued weight or activation variable x.
[0096] The superconducting binary neural network accelerator, wherein the pure combination accumulation parallel unit includes a superconducting approximation unit and a superconducting parallel counter;
[0097] The superconducting approximation unit is composed of a column of superconducting OR-AND gate pairs to reduce the input data bit width; the superconducting parallel counter is composed of cascaded superconducting full adders, and the superconducting full adder includes a T1 trigger, a CB3 unit, a D trigger and a separation unit.
[0098] The superconducting binary neural network accelerator, wherein the input of the superconducting full adder is a value to be summed A, a value to be summed B, a carry C and a clock CLK, and the output is a sum result Sum and a carry Carry; CLK is connected to the rd port of the T1 trigger and the clock port of the D trigger through the separation unit; A, B, and C are logically OR-operated through the CB3 unit, and the output result is connected to the data input end of the T1 trigger, and the output of the T1 trigger is connected to the data input end of the D trigger, and finally the carry Carry of the full adder is obtained from the output end of the D trigger, and the sum result Sum of the full adder is obtained from the sum end of the T1 trigger.
[0099] The present invention also proposes a storage medium for storing a program for executing any one of the superconducting binary neural network acceleration methods.
[0100] The present invention also proposes a client for use with any of the superconducting binary neural network accelerators.
Claims
1. A superconducting binary neural network acceleration method, characterized in that: include: Step 1: Obtain all real-valued weights and real-valued activations of the first layer of the neural network to be run as current weights and current activations, respectively, and binarize the current weights and current activations to obtain binary weights and binary activations; Step 2: input the data pairs consisting of all the binary weights and their corresponding binary activations into a plurality of XNOR gates in the neural processing unit to perform multiplication operations on each data pair; Step 3: All multiplication results are accumulated through a pure combination accumulation parallel unit, and the accumulated result and the preset threshold are input to the comparator, and the comparison result is used as the binary activation of the next layer; Step 4, obtaining the real-valued weight of the next layer as the current weight, binarizing the current weight, and using the binary activation obtained in step 3 as the current activation, and executing step 3 until the comparison result of the last layer of the superconducting binary neural network is obtained as the operation result of the superconducting binary neural network; The binarization process is completed by the following formula: in x b are real-valued weights or activation variables x The corresponding binary value; And the pure combination accumulation parallel unit includes a superconducting approximation unit and a superconducting parallel counter; The superconducting approximation unit is composed of a column of superconducting OR-AND gate pairs to reduce the input data bit width; the superconducting parallel counter is composed of cascaded superconducting full adders, and the superconducting full adder includes a T1 trigger, a CB3 unit, a D trigger and a separation unit.
2. The superconducting binary neural network acceleration method according to claim 1, characterized in that: The input of the superconducting full adder is a value to be summed A, a value to be summed B, a carry C and a clock CLK, and the output is a summation result Sum and a carry Carry; CLK is connected to the rd port of the T1 trigger and the clock port of the D trigger through the separation unit; A, B, and C are logically OR-operated through the CB3 unit, and the output result is connected to the data input end of the T1 trigger, and the output of the T1 trigger is connected to the data input end of the D trigger, and finally the carry Carry of the full adder is obtained from the output end of the D trigger, and the summation result Sum of the full adder is obtained from the sum end of the T1 trigger.
3. A superconducting binary neural network accelerator, characterized in that: include: The initial module is used to obtain all the real-valued weights and real-valued activations of the first layer of the neural network to be run as the current weights and current activations, respectively, and binarize the current weights and current activations to obtain binary weights and binary activations; An XNOR module, used for inputting data pairs consisting of all the binary weights and their corresponding binary activations into a plurality of XNOR gates in the neural processing unit to perform a multiplication operation on each data pair; An accumulation module, used for accumulating all multiplication results through a pure combinational accumulation parallel unit, inputting the accumulation result and a preset threshold into a comparator, and using the comparison result as a binary activation of the next layer; A loop module is used to obtain the real-valued weight of the next layer as the current weight, binarize the current weight, and use the binary activation obtained in step 3 as the current activation, and call the accumulation module again until the comparison result of the last layer of the superconducting binary neural network is obtained as the operation result of the superconducting binary neural network; The binarization process is completed by the following formula: where x b is the binary value corresponding to the real-valued weight or activation variable x; And the pure combination accumulation parallel unit includes a superconducting approximation unit and a superconducting parallel counter; The superconducting approximation unit is composed of a column of superconducting OR-AND gate pairs to reduce the input data bit width; the superconducting parallel counter is composed of cascaded superconducting full adders, and the superconducting full adder includes a T1 trigger, a CB3 unit, a D trigger and a separation unit.
4. The superconducting binary neural network accelerator according to claim 3, characterized in that: The input of the superconducting full adder is a value to be summed A, a value to be summed B, a carry C and a clock CLK, and the output is a summation result Sum and a carry Carry; CLK is connected to the rd port of the T1 trigger and the clock port of the D trigger through the separation unit; A, B, and C are logically OR-operated through the CB3 unit, and the output result is connected to the data input end of the T1 trigger, and the output of the T1 trigger is connected to the data input end of the D trigger, and finally the carry Carry of the full adder is obtained from the output end of the D trigger, and the summation result Sum of the full adder is obtained from the sum end of the T1 trigger.
5. A storage medium for storing a program for executing the superconducting binary neural network acceleration method as described in claim 1 or 2.
6. A client for use with the superconducting binary neural network accelerator described in claim 3 or 4.