Computer-implemented method for voltage rule checking on a design automation platform

Abstract

The present invention proposes a computer-implemented method for performing voltage rule checking on a design automation platform, comprising inserting a virtual component and its model with a safe operating area setting in a netlist generated by an electronic design automation platform or a circuit diagram of a process design kit, setting parameters of the virtual component and the model so that the virtual component does not affect the original circuit of the netlist or the circuit diagram, performing a safe operating area check on the netlist or the circuit diagram on the electronic design automation platform, and checking a warning message that violates the safe operating area setting triggered by the virtual component and the model during the safe operating area check to obtain a layout position that violates the safe operating area setting.

Description

Technical Field

[0001] The present invention generally relates to a computer-implemented method for performing voltage rule checking, and more particularly, to a computer-implemented method for performing specific voltage rule checking by inserting a pseudo component model with a safe operating area (SOA) setting set in the component model. Background Art

[0002] Metal oxide semiconductor (MOS) integrated circuits must ensure that their design does not violate specific electrical design rules. For example, for MOS devices, if the voltage across the gate oxide exceeds the value that the gate oxide can withstand, its charge transfer behavior will cause the gate oxide to break, causing the device to fail or become unreliable. This phenomenon is called gate oxide collapse. Similar voltage collapse phenomena are also seen in wires between high and low voltage domains, where the voltage difference of the insulation layer has an upper limit on the withstand voltage.

[0003] Similarly, if the voltage from source to drain or drain to source is too large for a MOS device channel to carry, the excessive current may break through the channel, causing circuit failure or even damage the device due to overheating. This is particularly prone to occur in device designs with small channel lengths and high voltages. Another possible failure occurs when the source voltage or drain voltage of a MOS device is too large relative to its substrate voltage, at which point the junction from the source or drain to the substrate collapses, causing unexpected circuit performance errors.

[0004] These types of problems mentioned above can be avoided by developing and following specific high-voltage electrical design rules. As the size of integrated circuits continues to shrink and transistor density continues to increase, circuit designers have turned to automated design tools, layout tools, and verification tools to handle a large amount of this tedious and error-prone work. Circuit designers typically use commercially available circuit simulator software, such as SPICE (Simulation Program with Integrated Circuit Emphasis), to perform operations called design rule checks (DRC) or electrical rule checks (ERC) in an attempt to develop circuits that follow electrical design specifications and improve their circuit performance. In order to ensure that the designed circuits follow electrical design rules, the industry hopes to be able to detect whether violations of high-voltage design specifications occur in such simulations.

[0005] However, current simulator software of this type cannot intuitively implement voltage rule checking between back-end layout routings, nor can it easily mark metal lines belonging to different voltage domains. Since the voltage and current of each node in the netlist are both the output and input values ​​of the circuit simulator to solve the Kirchhoff voltage and current law (KVL and KCL) equations, this iteration process cannot check the voltage at the beginning of the circuit simulation, nor can it check the voltage cross-voltage value between multiple components or metal routings. As a result, users must carefully monitor each node of the transistor to verify that there will be no problems under various circumstances. This disadvantage is more obvious in circuits with a large number of high-voltage nodes or flash memory architectures.

[0006] From the above discussion, it can be seen that the industry still needs to improve the voltage rule checking of the existing circuit simulator to provide more complete detection to meet the actual design requirements. Summary of the invention

[0007] In view of the deficiencies of the above-mentioned known technologies, the present invention hereby proposes a novel voltage rule checking method, which is characterized in that pseudo components and their models with safe operating area (SOA) settings are inserted into a netlist or circuit diagram that can be checked, so as to achieve the effect of checking the voltage rules of a specific circuit segment, thereby overcoming the problem that the known technology cannot mark or check the cross-voltage between the back-end layout routing or between different voltage domains or circuit blocks.

[0008] The purpose of the present invention is to propose a computer-implemented method for performing voltage rule checking on an electronic design automation platform, which includes inserting a virtual component with a safe operating area setting and a model of the virtual component in a netlist generated by the electronic design automation platform or a circuit diagram of a process design kit, and setting parameters of the virtual component and the model so that the virtual component will not affect the original circuit of the netlist or the circuit diagram, performing a safe operating area check on the netlist or the circuit diagram on the electronic design automation platform, and checking the warning message of violating the safe operating area setting triggered by the virtual component and the model during the safe operating area check to obtain the layout position that violates the safe operating area setting.

[0009] These and other objects of the present invention will become more apparent to those skilled in the art after reading the following detailed description of the preferred embodiment which is described in various diagrams and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] This specification contains drawings and constitutes a part of this specification, so that those skilled in the art can further understand the embodiments of the present invention. These drawings depict some embodiments of the present invention and illustrate their principles together with the description herein. In these drawings:

[0011] Figure 1 A general purpose computer architecture for executing the computer-implemented method of the present invention is depicted;

[0012] Figure 2 for An example of a netlist on the program interface;

[0013] Figure 3 This is an example of a data graph of a safe operating area (SOA);

[0014] Figure 4 for Output data message of a safe operation area check of five virtual components on the program interface;

[0015] Figure 5 An example of inserting a pseudo device into a netlist according to an embodiment of the present invention;

[0016] Figure 6 An example of inserting a virtual component in a circuit diagram according to an embodiment of the present invention;

[0017] Figure 7 FIG. 4 is another example of inserting a virtual component in a circuit diagram according to an embodiment of the present invention.

[0018] Figure 8 and Fig. 9 According to the embodiment of the present invention SOA syntax and circuit symbol types exist in several virtual components and their models;

[0019] Figures 10 to 12 Inserting virtual components between physical components in a circuit diagram and a netlist according to an embodiment of the present invention and triggering a warning message after performing an SOA check are respectively described;

[0020] Figures 13 to 15 Inserting virtual components between different voltage domains in a circuit diagram and a netlist according to an embodiment of the present invention and triggering warning messages after performing SOA checks;

[0021] Fig.16 A flow chart of a computer-implemented method for performing voltage rule checking on an electronic design automation platform according to an embodiment of the present invention; and

[0022] Fig.17FIG. 4 is a system block diagram of executing the voltage rule checking method of the present invention at the hardware layer and the software layer according to an embodiment of the present invention.

[0023] Please note that all illustrations in this manual are of a legend nature. For the sake of clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the same reference symbols in the figures will be used to indicate corresponding or similar component features after modification or in different embodiments.

[0024]

Explanation of symbols

[0025] 101 Processor

[0026] 102 DRAM

[0027] 103 Disk Drive

[0028] 104 User Interface

[0029] 105 Input / output devices

[0030] 501, 502 Executable

[0031] 901 Model File

[0032] 1001 Inverter

[0033] 1101 Virtual Component Model

[0034] 1201 Warning Message

[0035] 1401 Virtual Component Model

[0036] 1501 Warning Message

[0037] 1601-1611 Steps

[0038] 1700 Hardware Layer

[0039] 1702 Processor

[0040] 1704 DRAM

[0041] 1706 User Interface

[0042] 1708 Output Device

[0043] 1710 Disk Drive

[0044] 1720 Software Layer

[0045] 1722 Circuit Simulator

[0046] 1724 Voltage Rules

[0047] 1726 Model File

[0048] 1728 Virtual Components

[0049] 1730 Execution Iteration

[0050] 1732 Warning judgment result

[0051] 1734 LOG file

[0052] 1736 Test Report

[0053] 1738 Circuit Modification

[0054] 1740 Circuit Database

[0055] Cvrc1, Cvrc2 virtual capacitor model DETAILED DESCRIPTION

[0056] One or more embodiments of the present invention are a method for checking an integrated circuit (IC) design in the form of a digital computer file that depicts multiple features and their locations on a mask layer. This checking operation determines whether such IC design complies with design rules related to manufacturing technology (for example, determining a predetermined spacing relationship between features) or whether such IC design complies with electrical rules (for example, detecting potential misalignment between IC layout levels or exceeding a safe operating area). Preferably, one or more such embodiments of the present invention are implemented on a computer-implemented design rule check or electrical rule check program or circuit simulation program. Many specific details will be presented in the following description to allow those skilled in the art to have a more comprehensive understanding of the present invention. However, it should be understood that for those skilled in the art, some embodiments of the present invention can be implemented without some or all of such specific details of the present invention. In other examples, known process operations will not be described in detail to avoid blurring the focus of the present invention.

[0057] Figure 1 A general purpose computer architecture 100 for executing the computer-implemented method of the present invention is depicted. A user enters instructions for executing the computer-implemented method of the present invention through a user interface 104 including a display, keyboard, mouse, etc. A processor 101 reads computer-readable code and data from a dynamic random access memory (DRAM) 102 and performs operations and processing on the code and data. A high capacity storage device, such as a disk drive 103, can provide program code and data related to the computer-implemented method of the present invention to be loaded into the DRAM 102. An input / output device 105 can provide data connections to transmit data to other devices, such as a network, a modem, a printer, etc.

[0058] The computer-implemented method of the present invention is generally implemented by using an electronic design automation (EDA) platform installed on the computer architecture 100, for example, including Company or Company or Company It should be noted that for the present invention, in the circuit design process, as long as there is a circuit simulation tool, layout tool or verification tool based on a device model as input, such as a circuit design program that can use a netlist or schematic file or format to perform calculations, modifications or processing, the voltage rule checking method proposed by the present invention can be applied, and is not limited to the above-mentioned commercial software.

[0059] In some embodiments of the present invention, a netlist is used to illustrate the specific implementation of the present invention. Figure 2 As shown, it is The program interface is used as an example of a ring oscillator netlist example. Generally, when performing related operations of circuit simulation design, the simulated circuit diagram must be entered first. The circuit simulator provides component models such as transistors, ICs, capacitors, diodes, resistors, inductors, etc. The user selects the corresponding parts and connects them to form a circuit. In the actual simulation, the created circuit diagram will be converted into a file called a "netlist" (also called a serial file) by the electronic design automation platform. It describes the interconnection relationship between different components, nodes, or blocks in the circuit diagram and the condition settings to be simulated or checked in text and digital format, so that the circuit simulator can read, calculate, process and other actions. There will be multiple lines of description consisting of text and numbers in the netlist. Basically, each line of description defines a specific physical component. For example, C2_9112 in the figure represents a specific physical capacitor in the circuit layout. In addition, the text in the line may also describe the action and path to be performed. Generally speaking, netlists can be divided into pre-layout netlists and post-layout netlists according to the stages of the circuit design process. The voltage rule checking method of the present invention can be applied to these two types of netlists.

[0060] On the other hand, the voltage rule checking method of the present invention needs to be implemented with the function of safe operating area (SOA). The safe operating area referred to here refers to the range of voltage-current and other conditions under which power semiconductor components, such as bipolar transistors, field effect transistors, gate electrodes and insulated gate bipolar transistors, can perform expected normal operations without causing damage. Figure 3 FIG. 1 is an example of a safe operating area (SOA) data graph, which details the drain-to-source voltage (V) at which a transistor device reaches failure or thermal runaway under transient operating conditions with different pulse times (100 μs to 1 ms). DS ) for the drain-to-source current (I DS ) relationship diagram, which includes the drain-to-source on-resistance (R DS (on)) limit, current limit, maximum power limit, drain to source voltage (BV DSS ) limit, and thermal instability limit curves. The range of the safe operating area is the area surrounded by these curves and the coordinate axes in the figure. This range combines the operating limitations of the component in terms of maximum voltage, maximum current, maximum power dissipation, etc. The specifications of the safe operating area are generally defined by voltage, current or frequency, and can also be set as a more complex function, depending on the needs of the user and inspection. For example, the voltage limit (Vmax) of a metal line or a node on it may be a function of the spacing between the metal lines, and the lower limit of the voltage limit may be the minimum spacing between the metal lines.

[0061] For the current circuit simulators in the industry, as mentioned above or In commercial circuit simulation programs such as , when the terminal voltage of individual circuit components exceeds the safe operating area set by the user, the system can issue a warning message to the component to remind the user to pay attention. This is a built-in safe operating area check function. The output results of the simulation analysis are usually saved in the form of binary or text files. Figure 4 As shown, it is The program interface is an example of an output data message of a safe operating area check, which shows a warning message that the voltage of a specific physical component or node exceeds its set maximum voltage limit (model parameter, such as Bv_max) during simulation.

[0062] Although the current commercial circuit simulation software can provide a safe operating area check function, its check is limited to whether the parameter value (such as voltage) of a single component in the netlist or circuit diagram exceeds the safe operating area, and it is unable to implement cross-voltage checks between multiple components or metal windings, and it is also unable to mark metal wires belonging to different voltage domains. In this regard, the present invention intends to implement a voltage rule check between multiple components, voltage domains, or metal wires with high degree of freedom, wide coverage, and user-definable by adding virtual components and their models to the safe operating area check of the above-mentioned electronic design automation platform.

[0063] The pseudo device referred to in the present invention is a dummy object, which does not correspond to any physical component of an integrated circuit, but the model of the pseudo device with parameter settings related to the safe operating area (SOA) can perform the voltage rule check (VRC) required by the present invention. The above-mentioned object can be composed of netlist text, circuit symbols (schematic symbols) or layouts, and the various settings of the safe operating area are parameterized in the model of the virtual device in the form of an abstraction layer. Multiple identical virtual devices can share a model. In particular, if it is a layout object, it is represented by a non-physical drawing layer layout.

[0064] Now please refer to Figure 5 , which is an example of inserting a pseudodevice model into a netlist according to an embodiment of the present invention. Figure 5 The example netlist shown is in A post-layout netlist on the program interface, in which each row represents a different physical component, node or block in the circuit diagram, such as C2_9112 represents a specific physical capacitor in the circuit layout. Figure 5 The netlist shown is basically the same as Figure 2 The difference is that Figure 5Two lines of execution formulas 501 and 502 are inserted into the netlist, which respectively represent two virtual capacitor elements Cvrc100 and Cvrc200 in the embodiment of the present invention. Some pin texts (pin texts, which can also be called "characters") or labels in the execution formulas 501 and 502, such as Cvrc100 VDDCORE EN and Cvrc200 VSSCORE EN, can be identified by the program to perform the check of the virtual element model when checking the safe operating area (here "bv_max = 2" is set to 2 volts), and trigger a warning message when the safe operating area setting is violated, and the layout position or netlist section that violates the safe operating area setting can be known through these pin texts or labels. The identified pin text or label can also belong to different subnets, which can be used to find voltage warnings between subcircuits or functional blocks (for example, between two different voltage domains of 1.8V and 6V). According to this embodiment, a virtual capacitor model is inserted between nodes that are to be checked in the netlist (e.g., between two wires), and the voltage difference between the nodes can be checked in the safe operating area check. When the voltage difference exceeds the safe operating area setting defined by the user for these virtual component models, for example, the voltage difference exceeds 2V (bv_max=2), this check will list a warning message in the subsequent output data.

[0065] The virtual components and their models proposed in the present invention may include a variety of different components that can be input through a circuit simulator, including virtual capacitors, virtual resistors, virtual metal oxide semiconductor transistors, virtual bipolar junction transistors or virtual diodes. To insert a virtual component model into a netlist, the desired virtual component model can be set in a model file (model card) in advance. The model file is a collection of multiple models. These virtual component models can be inserted into specific positions between run decks in the netlist by directly calling the model file, or by feeding instance parameters from the netlist through the program's preset SOA interface, or by manually modifying the netlist through the program interface to add virtual components with safe operating area settings.

[0066] On the other hand, in addition to the netlist, the virtual component model of the present invention can also be inserted in the circuit diagram environment. Figure 6, which is an example of inserting a virtual component model into a circuit diagram according to an embodiment of the present invention. In the above netlist example, the virtual component model exists in the netlist in an executable form consisting of pin text and numbers and is implemented. In this embodiment, the virtual component model is directly inserted into the circuit diagram to be checked in the form of a circuit symbol, especially a circuit symbol compatible with a process design kit (PDK). For example, in Figure 6 In the example, through the process design kit, the user can directly see the layout circuit diagram on the user interface, such as the physical components such as NAND1, INV2, INV3, INV4, INV5, etc. connected in series as shown in the figure. The user can also insert a virtual component model on a specific node or between nodes in the circuit diagram by directly calling the safe operating area symbol in the process design kit. For example, taking the virtual capacitor model Cvrc1 as an example, it is inserted into the position between node out2 and node out5 in the circuit diagram through the process design kit, so that when performing the safe operating area check, it can be checked whether the voltage difference between the two nodes out2 and out5 exceeds the specification. Similarly, please refer to Figure 7 , taking the virtual capacitor model Cvrc2 as an example, it is inserted into the node V in the circuit diagram through the process design kit. DD With node V SS between the V DD With V SS Whether the voltage difference between them exceeds the specification.

[0067] In the present invention, the virtual components and their models that can be inserted in the safe operating area check are not limited to the virtual capacitors and their models shown in the above embodiments, but can also include virtual resistors, virtual metal oxide semiconductor field effect transistors (MOSFETs), virtual bipolar transistors (BJTs), and virtual diodes. Figure 8 , which uses the SOA syntax of HSPICE and circuit symbol types to illustrate several virtual component models of the present invention.

[0068] For the virtual capacitor model, it is considered open when calculating the DC operating point, and the capacitance value C can be set very small (such as 1*10 -20 F), so that the insertion of this virtual capacitor model will not affect the electrical properties of the original circuit. In SOA inspection, the voltage limit of the two ends of the virtual capacitor model can be preset to a value, such as 16V (Bv_max=16V). This voltage limit can also be a function of a set of instance parameters. For example, the voltage limit is equal to the metal line spacing multiplied by a proportional constant k. The SOA limit can be calculated and set through the input parameters of the interface of the netlist.

[0069] For virtual resistors and their models, there are two types of connection: series connection and parallel connection. For the series virtual resistor model, its resistance value R can be set very small (such as 1*10 -20 ohm), while for the parallel virtual resistance model, the resistance value R can be set very large (such as 1*10 20 ohm), so that the insertion of this virtual resistance model will not significantly affect the DC electrical properties of the original circuit regardless of series or parallel connection. In SOA inspection, the voltage limit of the two ends of the virtual resistance model can be preset to a value, such as 16V (Bv_max=16V), and this voltage limit can also be a function of a set of instance parameters.

[0070] For virtual MOSFET and its model, MOSFET is a four-terminal component, which has six terminal voltages, namely Vgs, Vgd, Vgb, Vbd, Vbs, and Vds, available for monitoring and inspection. Fig. 9 As shown, the safe operating area settings of the six terminal voltages can be inserted into the run decks in the netlist by manually modifying or calling the model card 901 of the simulated MOSFET. The maximum values ​​of the six terminal voltages set in the figure are all set to 1V. The critical voltage Vth of the virtual MOSFET element can be set very large (such as 100V) to prevent the virtual element from being turned on and interfering with the original circuit. The terminal voltages of virtual elements such as virtual bipolar transistors and virtual diodes, such as Veb, Vec, Vbc, etc., can also be set in the netlist or circuit diagram in the same way to achieve the effect of SOA inspection.

[0071] Now please refer to Figures 10 to 12 The actual method and result of inserting the virtual component and its model of the present invention to perform SOA inspection will be explained by taking the physical component of the first-stage inverter as an example. Fig.10 , which shows a circuit diagram of a ring oscillator composed of several inverters 1001 connected in series. A virtual capacitor element Cvcr is inserted between the input and output ends of each inverter 1001 to detect the output / input voltage difference of each stage of the ring oscillator, and the maximum voltage limit is set to 1V (bv_max=1V). When the given power supply voltage is 1.2V, the cross-voltage between the output end and the output end (1.2V) will exceed the set voltage limit (1V). In this way, when performing the SOA check, it will pop up an SOA warning message. Fig.11 In FIG. 1 , it can be seen that a virtual component model 1101 corresponding to the virtual capacitor Cvcr with SOA setting (bv_max=1) is inserted in the execution iteration of the netlist. Fig.12In FIG. 1 , it can be seen that the warning message 1201 triggered by the virtual component model 1101 appears in the output result of the SOA check. By checking the warning message 1201 triggered by the virtual component model 1101 in the SOA check, the layout position that violates the safe operating area setting, that is, the position of the inserted virtual capacitor Cvcr, can be known.

[0072] Now please refer to Figures 13 to 15 , which is the actual practice and result of using the virtual components and their models proposed by the present invention to perform SOA checks between different voltage domains. First, Fig.13 In the figure, a circuit diagram including three different voltage domains of 0-1.1V, 0-8V and 0-32V is shown, wherein a virtual capacitor Cvcr1 is inserted between the voltage domain 0-1.1V and the voltage domain 0-8V, and a virtual capacitor Cvcr2 is inserted between the voltage domain 0-8V and the voltage domain 0-32V by the above method of the present invention, so as to detect the voltage difference between these voltage domains, wherein the maximum voltage limits set by the two virtual capacitors Cvcr1 and Cvcr2 are 7V (bv_max=7V) and 24V (bv_max=24V), respectively, and the capacitance values ​​are all set to 1*10 - 20 F, will not significantly affect the performance of the original circuit. Fig.14 In FIG. 1 , it can be seen that virtual component models 1401 corresponding to virtual capacitors Cvcr1 and Cvcr2 with SOA settings (bv_max=7 and bv_max=24) are inserted into the execution iteration of the netlist. Fig.15 In FIG. 1 , it can be seen that the warning message 1501 triggered by the virtual component model 1401 appears in the simulation result of the SOA check.

[0073] In addition to the aforementioned pre-layout netlist, post-layout netlist, and process design kit (PDK) circuit diagram environments, the action of inserting virtual components and their models in the present invention can also be performed in the layout stage, for example, by using the automatic place and route tool (APR) used in the layout stage to insert virtual components into the layout pattern, and can exist in the form of text or labels in the GDS (Graphics Data System) file.

[0074] Now please refer to Fig.16 Based on the above embodiments, Fig.16The summary depicts the flow of a computer-implemented method for performing voltage rule checking on an electronic design automation platform according to an embodiment of the present invention. First, in step 1601, a voltage rule check is performed on an electronic design automation platform, which can be implemented by the safe operating area function of the platform. Then, in step 1602, the user builds the required virtual components and their models according to the voltage rule check to be performed, which can include features such as netlist text, circuit symbols or layout, and the corresponding various settings of the safe operating area are parameterized and assigned to the model of the virtual component. Then, in step 1603, the built virtual components and their models with safe operating area parameter settings are inserted into the netlist or circuit diagram using a circuit simulator, and the voltage rule checking loop is entered at this time (1604). This voltage rule checking loop can be performed in various circuit design stages, including inserting in the netlist before layout (1605), inserting in the circuit diagram (1606), inserting in the GDS file (1607), or inserting in the netlist after layout (1608). Then, in step 1609, a safe operating area check is performed through the circuit simulator, and the voltage rule check specially set above is also performed during the process. If the voltage rule check is passed, the circuit design process continues (1610). If the voltage rule check is not passed, the warning message of violation of the safe operating area setting triggered by the virtual component and the model is checked to find out the layout position that violates the safe operating area setting, and modify its circuit design (1611).

[0075] Now please refer to Fig.17 , which is a system block diagram of the voltage rule checking method of the present invention on the hardware layer and the software layer according to an embodiment of the present invention. Among them, the hardware layer 1700 represents all the physical components used to execute the computer-implemented method of the present invention, and its components are roughly the same as Figure 1 The general purpose computer architecture 100 is the same as that described above. The software layer 1720 is a non-physical component that is stored in a computer-readable medium in the form of data or data and allows the computer to perform operations and processing on it. First, the entire voltage rule checking method is run based on a circuit simulator 1722. The circuit simulator 1722 can be various SPICE-type commercial circuit simulator software available on the market, which can perform analog or mixed signal circuit simulation. The various instructions and data output by the circuit simulator 1722 will be transmitted to the hardware layer 1700 and will be calculated and processed by the processor 1702. The dynamic random access memory (DRAM) 1704 of the hardware layer 1700 can temporarily store the data or data to be processed and can be stored by the system during the method.

[0076] Refer to Fig.17The voltage rule 1724 to be executed in the method is implemented in the circuit simulator 1722 by inputting a model card 1726 having the aforementioned voltage rule check (VRC) parameters. The circuit simulator 1722 first inputs the file of the circuit design to be simulated, which may include a netlist derived from the circuit diagram and / or layout. The model file 1726 or the file of the process design kit (PDK) describes the characteristics of the individual physical components to be integrated into the circuit design. The desired virtual component 1728 model is pre-set in the model file, and these virtual component models can be input or inserted into specific positions between the run decks 1730 in the netlist by directly calling the model file. The above-mentioned input model file and input run deck actions can be completed through the user interface 1706 of the hardware layer 1700, such as input devices such as keyboards and mice, and program operation interfaces, and the desired voltage rule check is performed. In the method, the warning determination result 1732 of the voltage rule check will be transmitted and displayed through the output device 1708, such as a display, network, modem, printer, etc. At this time, the LOG file 1734 can store the error message of the violation of the voltage rule check in text form. If the voltage rule check is passed, the entire test report 1736 will be generated by the system and displayed through the output device 1708, which can also include a file in a compatible comma separated value (CSV) format. If the voltage rule check fails, the warning message of the violation of the voltage rule check triggered by the virtual component and the model can be viewed through the output device 1708 to find out the layout location that violates the safe operating area setting, and then perform circuit modification 1738 on the location. The modified circuit data will be input into the circuit database 1740 and stored in the high-capacity storage device of the hardware layer 1700, such as the disk drive 1710. The disk drive 1710 can provide program code and data related to the computer-implemented method of the present invention to be loaded into the DRAM 1704 during the entire method execution stage and provided for the system to perform related operations and processing.

[0077] According to the above-mentioned embodiments, the voltage rule checking method proposed in the present invention can freely check the voltage effect of specific circuit sections such as each node, between multiple nodes, or between voltage domains in the safe operating area check by inserting virtual components and their models with safe operating area settings in the netlist and circuit diagram. This can overcome the problem that the known technology cannot mark or check the cross-voltage between the back-end layout routing or between different voltage domains or circuit blocks, and its scope can cover but is not limited to between routings, between components, between layers, or between functional blocks, and can be used to perform design optimization and other actions with external tools of the circuit simulator.

[0078] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A computer-implemented method for performing voltage rule checking on an electronic design automation platform, comprising: Inserting a virtual component with a safe operating region setting and a model of the virtual component in a netlist generated by an electronic design automation platform or a circuit diagram of a process design kit, wherein the virtual component does not correspond to any physical component in an original circuit of the netlist or the circuit diagram, and wherein the safe operating region setting includes a user-defined terminal voltage limit of the virtual component; Setting parameters of the virtual component and the model so that the virtual component does not affect the original circuit; Performing a safe operating area check on the netlist or the circuit diagram on the electronic design automation platform; and The warning message of violation of the safe operating area setting triggered by the virtual component and the model in the safe operating area check is checked to obtain the layout position violating the safe operating area setting.

2. The computer-implemented method of claim 1, wherein the virtual component and the model are set in the model file in the form of pin text, label or subnet list name, and the step of inserting the virtual component and the model with the safe operation area setting includes calling the model file to insert the virtual component and the model in the model file between the execution iterations in the netlist. 3 . The computer-implemented method of claim 2 , wherein the netlist is a pre-layout circuit simulation netlist or a post-layout circuit simulation netlist.

4. The computer-implemented method of claim 1 , wherein the step of inserting the virtual component with the safe operating area setting and the model comprises calling the symbol of the virtual component in the process design kit to insert the symbol of the virtual component between the circuits to be checked in the circuit diagram. 5 . The computer-implemented method of claim 1 , wherein the dummy component is inserted into the exported GDS file by an automatic place-and-route tool during a layout stage. 6 . The computer-implemented method of claim 1 , wherein the virtual elements include virtual capacitors, virtual resistors, virtual metal oxide semiconductor transistors, virtual bipolar junction transistors, or virtual diodes.

7. The computer-implemented method of claim 1, wherein the electronic design automation platform is a circuit simulator, wherein the circuit simulator is or or 8. The computer-implemented method of claim 7, wherein the virtual element is a virtual capacitor.

9. The computer-implemented method of claim 7, wherein the virtual element is a virtual series resistor.

10. The computer-implemented method of claim 7, wherein the virtual element is a virtual parallel resistor.

11. The computer-implemented method of claim 7, wherein the dummy element is a dummy MOSFET.

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